Packaging method of hall current sensor chip and chip structure

Abstract

The application discloses a packaging method and a chip structure of a Hall current sensor, and meets the requirements of low resistance, a large range, high reliability, small size and a large number of function pins; the packaging method comprises a FPC isolation device structure with an electromagnetic shielding function, which is arranged between a lead frame base island and a die, and a Hall point of the die corresponds to a slot opening position of the FPC isolation device structure, so that eddy current formed by a metal film under a high-frequency magnetic field can be avoided, and the normal work of a Hall sensing point of a sensor silicon chip is not interfered, the bandwidth of a differential Hall sensor is reduced, and the isolation voltage requirement is met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and specifically to a packaging method and chip structure for a Hall current sensor chip. Background Technology

[0002] Hall effect sensor chips are manufactured by integrating Hall effect sensing elements, amplifiers, compensation circuits, and other electronic circuits onto a single die using integrated circuit technology. They offer advantages such as small size, long lifespan, simple structure, and high frequency, and are widely used not only in traditional power electronics, home appliances, computers, and automobiles, but also in defense industries such as aerospace and shipbuilding. However, to meet the requirements of small package size, low resistance, large detection range, and high isolation withstand voltage for Hall effect current sensor chips, new packaging methods need to be developed to achieve market application.

[0003] Traditional surface mount packaging, widely used for power transistors and voltage regulator chips, features a lead frame base island connected to the center pin. However, for Hall effect current sensor chips, the heatsink serves as the current input circuit, while the die output is wire-bonded to the pin. Therefore, the internal lead frame base island cannot be connected to the pin, resulting in high on-resistance, a small current range, and a thinner molded enclosure, leading to poor reliability when large currents are applied. Summary of the Invention

[0004] Firstly, the present invention aims to provide a packaging method for a Hall current sensor chip, so as to obtain a Hall current sensor chip with small size and convenient manufacturing process while satisfying the requirements of low resistance and large range.

[0005] Secondly, the present invention aims to provide a chip structure for a Hall current sensor, which has the advantages of low resistance and large range, and reduces its overall size by semi-enclosing the heat sink and base island with a plastic package.

[0006] This invention is achieved through the following technical solution:

[0007] A method for packaging a Hall current sensor chip, comprising:

[0008] Fabricate a lead frame, comprising at least two lead frames, each lead frame having a base island; the lead frames are arranged in a single row and spaced apart;

[0009] Heat sinks are placed on the lead frame to fill in the area outside the base island;

[0010] Fabricate an FPC isolation device structure, which includes two metal layers and an intermediate layer sandwiched between the two metal layers; slot the metal layers so that the slots correspond to the Hall points of the die;

[0011] The FPC isolation device structure is arranged on the base island, and the other side of the FPC isolation device structure is used to lay the die.

[0012] The die, FPC isolation device structure, and base island are sequentially fixed and connected by baking bonding; then any metal layer is grounded.

[0013] Alternatively, each adjacent lead frame can be connected by a link along the extension direction of the lead frame.

[0014] As an alternative approach, a stamping operation on the base island is also included, the stamping operation comprising the following steps:

[0015] The two opposite sides of the base island are stamped to form a first step and a second step, with the stamping depth of the first step and the second step being equal; then, a dovetail groove is formed by stamping on the side with the first step, and multiple nail holes are formed by stamping in other unstamped areas on the other side of the base island at preset intervals.

[0016] As an optional method, the stamping depth of both the first step and the second step is 0.3mm, and the stamping depth of the dovetail groove is also 0.3mm; the first step and the second step are used to form a snap-fit ​​with the heat sink.

[0017] As an alternative, the metal layer is made of electrolytic copper, and the middle layer is a PI film; the PI film is bonded to the two metal layers respectively by TPI method.

[0018] As an alternative, the metal layer is stamped to form a slot, so that the slot corresponds to the Hall point of the core.

[0019] As an alternative approach, DAF films are provided on both sides of the FPC isolation device structure. After the DAF films are bonded to both sides of the FPC isolation device structure, they are brought close to the lead frame and the die, respectively. The DAF films on both sides of the FPC isolation device structure are baked at high temperature to cure them. Then, the FPC isolation device structure is bonded to the lead frame and the die, respectively.

[0020] As an alternative approach, in the direction from the die to the base island, the projected area of ​​the die on the plane where the base island is located is smaller than the projected area of ​​the FPC isolation device structure; one edge of the FPC isolation device structure extends beyond the plane where the base island is located.

[0021] As an alternative, the heat sink includes a current sensing input surface, a current sensing output surface, and a current sensing flow surface, with the current sensing input surface and the current sensing output surface soldered onto PCB board pads; the width of the current sensing flow surface is such that the current sensing can reach a preset value.

[0022] On the other hand, the present invention also provides a structure for a Hall current sensor chip, which is fabricated using the above-described Hall current sensor chip packaging method, and includes:

[0023] The lead frame and the base island disposed on the lead frame, the base island including a first surface and a second surface disposed opposite to each other; an FPC isolation device structure is attached to the first surface; a die is laid on the FPC isolation device structure, the die is used to form a connection with the pins of the lead frame through bonding leads; a plurality of base island pin holes are arranged at predetermined positions on the first surface of the base island; V-grooves are also formed on the pins of the lead frame.

[0024] The base island also includes a first stamping step and a second stamping step arranged opposite to each other; a dovetail groove is also formed on the first side of the base island; and

[0025] The molding compound is hollow and has a cavity for housing the base island to form an enclosing structure. A chip heat sink is also provided on the side of the molding compound that contacts the second surface of the base island. The chip heat sink is attached to the base island through a first stamping step and a second stamping step.

[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0027] Based on meeting the requirements of low resistance, large range, high reliability, small size, and many functional pins, the present invention provides a packaging method that includes encapsulating an FPC isolation device structure with electromagnetic shielding function. The structure is positioned between the lead frame base island and the die, and the Hall point of the die corresponds to the slot of the FPC isolation device structure. This can prevent the metal film from forming eddy currents under high-frequency magnetic fields, thereby interfering with the normal operation of the Hall sensing point of the sensor silicon chip, reducing the bandwidth of the differential Hall sensor, and meeting the isolation withstand voltage requirements. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This is a schematic diagram of the single-row lead frame structure provided in Embodiment 2 of the present invention;

[0030] Figure 2 This is a partially enlarged schematic diagram of the single-row lead frame provided in Embodiment 2 of the present invention;

[0031] Figure 3 This is a top view of the internal structure of the packaged chip provided in Embodiment 2 of the present invention;

[0032] Figure 4 This is a front view schematic diagram of the internal structure of the packaged chip provided in Embodiment 2 of the present invention;

[0033] Figure 5 This is a three-dimensional schematic diagram of the internal structure of the packaged chip provided in Embodiment 2 of the present invention;

[0034] Figure 6 This is a three-dimensional schematic diagram of the external structure of the packaged chip provided in Embodiment 2 of the present invention;

[0035] Figure 7 This is a front view schematic diagram of the encapsulated FPC isolation device structure provided in Embodiment 2 of the present invention;

[0036] Figure 8 This is a top view schematic diagram of the encapsulated FPC isolation device structure provided in Embodiment 2 of the present invention;

[0037] Figure 9 This is a flowchart of the novel packaging technology method provided in Embodiment 1 of the present invention.

[0038] The attached diagram shows the markings and corresponding component names:

[0039] 1-Connecting rod, 2-Lead frame base island, 3-Lead frame pin, 4-Stamped step on the back of the base island, 5-Stamped step on the front of the base island, 6-Dovetail groove of the base island, 7-Pin hole of the base island, 8-V-groove of the pin, 9-FPC isolation device structure, 10-Die, 11-Bonding lead, 12-DAF film, 13-Molding body, 14-Chip heat sink, 15-Electrolytic copper shielding layer, 16-PI film, 17-Slotted opening of the shielding layer. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0041] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments provided in this invention without inventive effort are within the scope of protection of this invention.

[0042] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0043] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this invention based on the specific circumstances.

[0045] Example 1

[0046] Please see Figure 9 This embodiment provides a packaging method for a Hall current sensor chip. Based on the TO263-7 method, it features an improved lead frame design, resulting in lower resistance and a wider current detection range. Furthermore, by encapsulating an FPC isolation device structure, the chip's electromagnetic shielding function is enhanced, while simultaneously improving its isolation withstand voltage performance. This embodiment is implemented as follows:

[0047] The packaging method of this embodiment comprises the following steps: lead frame design – lead frame preparation – FPC isolation device structure encapsulation – first optical inspection – wafer preparation – wafer grinding – wafer dicing – wafer cleaning – second optical inspection – die bonding – wire bonding – third optical inspection – injection molding – high-temperature curing – overflow removal / electroplating – laser marking – lead trimming / forming – fourth optical inspection. The proprietary lead frame design method and the addition of an FPC isolation device structure encapsulation method in this process represent a creative invention compared to the traditional TO263-7 package. The lead frame design includes the following sub-steps:

[0048] S1: Leadframe Link Design: The design of the leadframe link needs to ensure that it meets the structural strength requirements and molding process requirements. Traditional TO263-7 package leadframes do not have links at the connection points between adjacent base islands; the base islands are connected to the intermediate pins to support the leadframe and meet structural strength requirements. However, due to functional requirements, the new TO263-7 package's leadframe base islands cannot be connected to the pins. Therefore, to meet structural strength requirements, a spacing needs to be increased between adjacent base islands, and a link needs to be added for support. The link width is 3.3mm. The leadframe is designed with a single-row structure, with 16 leadframe units per row. The leadframe length is 258.4mm and the width is 32mm.

[0049] S2: Design of the lead frame base island shape: First, two upper and lower slots are stamped on the base island. The slots are semi-circular in shape with a diameter of 1.3mm, and their positions correspond to the two Hall effect points (PADs) of the die. Second, a step is stamped on the back of the base island. The unstamped part is the external heat sink. The stamped part is placed inside the molding compound, and a slot is opened in the stamped step. This treatment can improve the magnetic sensitivity to 1.7GS and help improve the bonding strength between the frame and the molding compound. Finally, the external heat sink area of ​​the base island is horizontally completed. The two sides of the base island are 0.542mm from the edge of the molding compound. Under the premise of meeting the process requirements, the on-resistance is greatly reduced. According to simulation and sample measurement results, the on-resistance can be as low as below 30uΩ.

[0050] S3: Design of the lead frame heatsink dimensions: The dimensions of the lead frame heatsink should meet three requirements. First, the heatsink is divided into a current sensing input surface, a current sensing output surface, and a current sensing path area. The input and output surfaces are soldered to the PCB board pads. To effectively prevent solder creep defects, the width of the current sensing path area is designed to be 1.3mm. Second, to meet the requirement that the maximum current sensing current is 300A, the area of ​​the input and output surfaces should be greater than 16mm². 2 The design area is 17.72mm. 2 Finally, to meet the isolation withstand voltage requirements and achieve an electrical insulation capability of 4800V, the ramp distance from the lower edge of the heat sink to the pin should be greater than 8mm, and the designed ramp distance is 8.24mm.

[0051] S4: Lead Frame Anti-Delamination Design: The lead frame anti-delamination design mainly involves surface treatment of the frame, including stamping steps on the front and back of the lead frame base island, opening dovetail grooves and pin holes on the surface, and opening V-shaped holes at the leads to enhance the bonding strength between the lead frame and the molding compound. The stamping depth of the front step, back step, and dovetail groove is 0.3mm, and the stamping depth of the pin holes and V-shaped holes is 0.05mm, effectively preventing delamination and cracking.

[0052] In addition, this embodiment incorporates a method for encapsulating an FPC isolation device structure after receiving the lead frame and before the first optical inspection and wafer preparation. The sub-steps are as follows:

[0053] S1: Receiving Lead Frames: Prepare the new TO263-7 lead frames that have been fabricated according to the design requirements. The frame material is selected as 19210 copper alloy, and the frame thickness is 1.27mm. Design the bonding positions of the FPC isolation device structure on the lead frame base island. After receiving the lead frames, inspect the incoming materials. Return any abnormal ones to the supplier, and prepare the normal ones for wafer mounting.

[0054] S2: DAF film bonding isolation device structure: Receive an FPC isolation device structure with a thickness of 99um and prepare a DAF film with a thickness of 10um. Use a fully automatic wafer bonding machine to bond the DAF film to the back of the FPC isolation device structure, and wait for the next step.

[0055] S3: Cutting the isolation device structure: According to the design scheme, the FPC isolation device structure with the DAF film bonded is cut into a regular shape of 4.6mm*3.4mm as required. After the cutting is completed, Nikon performs an appearance inspection. After passing the quality inspection, the subsequent wafer mounting process continues.

[0056] S4: Isolation device structure mounting: After quality inspection, the qualified FPC isolation device structure, which has been cut to the required size, is placed in the position required by the design of the lead frame base island through the DB machine. The lower edge of the FPC isolation device structure is 0.3mm longer than the lower edge of the base island to meet the requirement of covering the lead frame base island in the area through which the lead lines pass.

[0057] S5: Baking and Bonding of Isolator Structure: After the FPC isolator structure is mounted, the mounted lead frame and FPC isolator structure are baked at high temperature on a Bake machine. The baking process parameters are 180℃ and 24h, so that the DAF film between the lead frame of the FPC isolator structure is cured, and the bonding between the FPC isolator structure and the lead frame base island is completed.

[0058] As an alternative approach, based on the above steps and methods, to reduce on-resistance, the lead frame material is selected from 19210 copper alloy, which has lower resistivity and lower resistance under the same size and shape conditions. To meet the isolation withstand voltage requirements, the FPC isolation device structure size should be larger than the die size, and it should also cover the internal frame area through which the subsequent wire bonding process passes. The selected FPC isolation device structure consists of an electrolytic copper metal layer + a PI layer + an electrolytic copper metal layer, where the PI layer thickness is 30um-150um. The metal layer has upper and lower slots to prevent the metal film from forming eddy currents under high-frequency magnetic fields, which would interfere with the normal operation of the Hall sensing point of the sensor silicon chip, reduce the bandwidth of the differential Hall sensor, and play an electromagnetic shielding role. In addition, the shielding layer of the FPC isolation device structure can be connected to ground by wire bonding to reduce the impact of electromagnetic interference on the sensor chip.

[0059] The novel TO263-7 packaged Hall current sensor chip prepared by the above embodiments of the present invention has lower on-resistance and a larger current detection range, which is superior to the traditional SOW16 and SOP8 packages. It also has the advantages of small size and more functional pins, which is significantly better than Allegro's CB package. In addition, this novel TO263-7 package also incorporates an FPC isolation device structure with electromagnetic shielding function, which can not only avoid the generation of eddy currents inside and cancel the response of magnetic fields, but also increase the isolation withstand voltage function, which can meet the isolation withstand voltage requirement of more than 5KV.

[0060] Example 2

[0061] Please see Figures 1-8 This embodiment fabricates a Hall current sensor chip based on the chip packaging method described in the above embodiment. Please refer to [the previous document] again. Figure 1 and Figure 2 The leadframe of the package has a single-row structure with 16 leadframe units in one row. Link 1 is used to meet the strength requirements of the entire leadframe structure. For the traditional TO263-7 package leadframe, there is no link 1 structure, but it is connected at the base island and the middle pin to meet the structural requirements.

[0062] Please refer to it again. Figures 3-5 The first and second steps are the back and front stamping steps of the base island, respectively. The stamping depth of the back stamping step 4 is 0.3mm. This design improves the magnetic sensitivity of the chip's current detection while enhancing the bonding strength between the molding compound and the frame. The stamping depth of the front stamping step 5 is 0.3mm. The stamping depth of the dovetail groove 6 is 0.3mm. The stamping depth of the pin hole 7 is 0.05mm, and the stamping depth of the lead V-groove 8 is 0.05mm. All four of these designs enhance the bonding strength between the molding compound and the frame.

[0063] As an optional embodiment, the FPC isolator structure 9 measures 4.6mm * 3.4mm * 0.099mm, with a DAF film 12 bonded to it via baking and bonding. The die 10 has a thickness of 140µm, with the DAF film 12 bonded to it via baking and bonding. The bonding position of the leads in the isolator structure should cover the area of ​​the lead frame base island 2 to better provide isolation and withstand voltage. The DAF film 12 is used for insulation. The encapsulator 13 uses an epoxy resin encapsulant.

[0064] Please refer to it again. Figure 6 In this embodiment, the area of ​​the current-sensing inlet and outlet surfaces of the heat sink is 17.72 mm², the width of the current-sensing path area is 1.3 mm, and the ramp distance from the lower edge of the heat sink to the pin along the plastic encapsulation 13 is 8.24 mm, satisfying the requirements of heat dissipation, prevention of solder creep, and isolation withstand voltage. Please refer again. Figure 7 and Figure 8 The FPC isolation device structure 9 in this embodiment consists of an electrolytic copper metal layer, an intermediate PI layer, and another electrolytic copper metal layer. The top and bottom electrolytic copper metal layers are 12µm thick and provide electromagnetic shielding. The intermediate PI layer is 75µm thick. The intermediate PI layer and the top and bottom electrolytic copper shielding layers are bonded together using a TPI method. Furthermore, slots 17 are cut into the top and bottom shielding layers to ensure that the Hall effect points of the die 10 correspond to the slot positions, thus preventing eddy currents from being generated internally, which could interfere with the normal operation of the Hall effect sensing points of the sensor silicon chip and reduce the bandwidth of the differential Hall effect sensor.

[0065] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A packaging method for a Hall current sensor chip structure, characterized in that, The Hall current sensor chip structure includes: a lead frame and a base island disposed on the lead frame. The base island includes a first surface and a second surface disposed opposite to each other. An FPC isolation device structure is attached to the first surface. A die is laid on the FPC isolation device structure, and the die is connected to the pins of the lead frame through bonding leads. Multiple base island pin holes are arranged at preset positions on the first surface of the base island. V-grooves are also formed on the pins of the lead frame. A first stamping step is provided on the first surface of the base island, and a second stamping step is provided on the second surface; a dovetail groove is also formed on the first surface of the base island; and The molding compound is hollow and has a cavity for housing the base island to form an enclosing structure. A chip heat sink is also provided on the side of the molding compound that contacts the second surface of the base island. The chip heat sink is attached to the base island through a first stamping step and a second stamping step. The chip heat sink includes a current input surface, a current output surface, and a current flow surface. The current input surface and the current output surface are soldered onto the PCB board pads. The width of the current flow surface is sufficient to allow the current to flow in to reach a preset value. The ramp distance from the lower edge of the chip heat sink to the pin is greater than 8mm. Encapsulation methods include: A lead frame is fabricated, comprising at least two lead frames, each of which has a base island; the lead frames are arranged in a single row and spaced apart; adjacent lead frames are connected by a connecting rod along the extending direction of the lead frames. Heat sinks are placed on the lead frame to fill in the area outside the base island; Fabricating an FPC isolation device structure, the FPC isolation device structure comprising two metal layers and an intermediate layer sandwiched between the two metal layers, the intermediate layer being a PI film; The metal layer is slotted so that the slots in the metal layer correspond to the Hall points of the die. The FPC isolation device structure is arranged on the base island, and the other side of the FPC isolation device structure away from the base island is used to lay the core. The die, FPC isolation device structure, and base island are sequentially fixed and connected by baking bonding; then any of the metal layers is grounded. Both sides of the FPC isolation device structure are provided with DAF films; after the DAF films are bonded to both sides of the FPC isolation device structure, the two sides of the FPC isolation device structure are respectively close to the lead frame and the die; after the DAF films on both sides of the FPC isolation device structure are baked at high temperature to cure them, the two sides of the FPC isolation device structure are respectively bonded to the lead frame and the die.

2. The packaging method for a Hall current sensor chip structure according to claim 1, characterized in that, It also includes a stamping operation on the base island, the stamping operation comprising the following steps: A first stamping step is formed on the first surface of the base island, and a second stamping step is formed on the second surface of the base island. The stamping depths of the first stamping step and the second stamping step are equal. Then, a dovetail groove is formed on the side with the first stamping step. In other unstamped areas on the first surface of the base island, multiple nail holes are formed at preset intervals.

3. The packaging method for a Hall current sensor chip structure according to claim 2, characterized in that, The stamping depth of the first stamping step and the second stamping step is 0.3 mm, and the stamping depth of the dovetail groove is also 0.3 mm; the first stamping step and the second stamping step are used to form a snap-fit ​​with the heat sink.

4. The packaging method for a Hall current sensor chip structure according to claim 1, characterized in that, The metal layer is made of electrolytic copper; the PI film is bonded to the two metal layers respectively by TPI method.

5. The packaging method for a Hall current sensor chip structure according to claim 4, characterized in that, The metal layer is punched to form an opening, such that the opening corresponds to the Hall point of the core.

6. The packaging method for a Hall current sensor chip structure according to claim 1, characterized in that, In the direction from the die to the base island, the projected area of ​​the die on the plane where the base island is located is smaller than the projected area of ​​the FPC isolation device structure; one edge of the FPC isolation device structure extends beyond the plane where the base island is located.

Images