Substrate structure in semiconductor devices and semiconductor devices

Abstract

The application provides a substrate structure in a semiconductor device and the semiconductor device. The substrate structure in the semiconductor device comprises a substrate, a top layer of silicon and a plurality of shallow trench isolation structures, wherein the substrate comprises a plurality of cavities arranged at intervals in a predetermined direction, the top layer of silicon is located on a surface of the substrate, the top layer of silicon comprises a plurality of top layer of silicon parts, thicknesses of the plurality of top layer of silicon parts are different, one top layer of silicon part and at least a corresponding cavity form a base region, and the plurality of shallow trench isolation structures are located between any two adjacent base regions. In the substrate structure, the thicknesses of the top layer of silicon parts are different, the voltage requirements of different semiconductor devices can be met, and thus the problem that, in the prior art, because the thickness of the top layer of silicon on the same wafer is the same, the thickness of the top layer of silicon of a semiconductor device with a smaller voltage requirement is too large to cause the parasitic capacitance of the semiconductor device to be too large is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a substrate structure and a semiconductor device. Background Technology

[0002] Currently, all traditional and patterned wafers are designed for manufacturing only one type of device, such as... Figure 1 As shown, the wafer includes a silicon layer 102, a silicon oxide layer 101, and a silicon substrate layer 100 stacked sequentially. Therefore, the wafer cannot meet the requirement of manufacturing devices with different operating voltages on the same wafer.

[0003] Therefore, in the prior art, devices with different operating voltages cannot be fabricated on the same wafer.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a substrate structure and a semiconductor device to solve the problem that devices with different operating voltages cannot be fabricated on the same wafer in the prior art.

[0006] According to one aspect of the present invention, a substrate structure for a semiconductor device is provided, comprising: a substrate including a plurality of spaced cavities, the plurality of cavities being spaced apart in a predetermined direction, the predetermined direction being a direction perpendicular to the thickness of the substrate; a top silicon layer located on the surface of the substrate, the top silicon layer including a plurality of top silicon portions, the top silicon portions being correspondingly disposed on the substrate on both sides of the cavities and located on the cavities, and the thickness of the top silicon portions on any two cavities being different, one top silicon portion and at least one corresponding cavity forming a base region, and devices formed on any two base regions being different; and a plurality of shallow trench isolation structures located between any two adjacent base regions.

[0007] Optionally, the substrate further includes: a first insulating dielectric layer located on the inner surface of the cavity; a first trap-rich layer located on the surface of the first insulating dielectric layer away from the cavity, wherein a substrate region is formed by a top silicon portion, a corresponding cavity, and the first insulating dielectric layer and the first trap-rich layer within the cavity.

[0008] Optionally, the substrate further includes: a second insulating dielectric layer located on the surface of the first trap-rich layer away from the first insulating dielectric layer, wherein a substrate region is formed by a top silicon portion, a corresponding cavity, and the first insulating dielectric layer, the first trap-rich layer, and the second insulating dielectric layer within the cavity.

[0009] Optionally, the second insulating dielectric layer includes: a first insulating portion having a cavity; and a second insulating portion located within the cavity and used to support the portion of the first insulating portion that contacts the top silicon portion, wherein the second insulating portion divides the cavity into two sub-cavities.

[0010] Optionally, the thickness of the first insulating dielectric layer is between 0.5 nm and 10 nm.

[0011] Optionally, the thickness of the first trap-rich layer is between 3nm and 200nm.

[0012] Optionally, the material of the first trap-rich layer includes at least one of polycrystalline silicon, SiC, and SiGe.

[0013] Optionally, the shallow trench isolation structure includes: a second trap-rich layer; and a third insulating dielectric layer surrounding the outer periphery of the second trap-rich layer.

[0014] Optionally, the depth of the cavity is between 200 nm and 2 μm.

[0015] According to another aspect of the present invention, a semiconductor device is also provided, including a substrate structure and a device portion, wherein the substrate structure is any of the substrate structures in the semiconductor device described herein, and the device portions are disposed one-to-one on the substrate region, and the devices of any two device portions are different.

[0016] In this embodiment of the invention, the substrate structure in the semiconductor device includes a substrate, a top silicon layer, and multiple shallow trench isolation structures. The substrate includes multiple cavities spaced apart in a predetermined direction. The top silicon layer is located on the surface of the substrate and includes multiple top silicon portions of varying thicknesses. Each top silicon portion and its corresponding at least one cavity form a base region. Multiple shallow trench isolation structures are located between any two adjacent base regions. In this substrate structure, the varying thickness of the top silicon portions allows for thicker top silicon layers for semiconductor devices with higher voltage requirements and thinner top silicon layers for semiconductor devices with lower voltage requirements. This satisfies the voltage requirements of different semiconductor devices, solving the problem in the prior art where devices with different operating voltages cannot be fabricated on the same wafer, thereby improving the electrical performance of the semiconductor device. Furthermore, the cavities in this substrate structure further reduce the parasitic capacitance of the semiconductor device, and the multiple shallow trench isolation structures suppress interference between different semiconductor devices, further enhancing the electrical performance of the semiconductor device. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A planar cross-sectional view of a wafer in the prior art is shown;

[0019] Figure 2 A schematic diagram of a substrate structure in a semiconductor device according to an embodiment of this application is shown;

[0020] Figures 3 to 8 The diagrams show the semiconductor structures formed after each process step in the fabrication method of the cavity in the prior art.

[0021] Figures 9 to 10 A schematic diagram of the substrate structure formed after each process step of etching the top silicon according to an embodiment of this application is shown.

[0022] Figure 11 A schematic diagram of a substrate structure having a first trap-rich layer according to an embodiment of this application is shown;

[0023] Figure 12 A schematic diagram of a substrate structure having a second insulating dielectric layer according to an embodiment of this application is shown;

[0024] Figure 13 A schematic diagram of a substrate structure having two sub-cavities according to an embodiment of this application is shown;

[0025] Figure 14A schematic diagram of a substrate structure having a second trap-rich layer according to an embodiment of this application is shown;

[0026] Figure 15 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0027] The above figures include the following reference numerals:

[0028] 100. Silicon substrate layer; 101. Silicon oxide layer; 102. Silicon layer; 103. Substrate; 104. Cavity; 105. Top silicon layer; 106. Base region; 107. Shallow trench isolation structure; 108. First oxide layer; 109. Second oxide layer; 110. Silicon nitride layer; 111. First insulating dielectric layer; 112. First trap-rich layer; 113. Second insulating dielectric layer; 114. First insulating portion; 115. Second insulating portion; 116. Third trap-rich layer; 117. Third insulating dielectric layer; 200. First back gate; 201. First source; 202. First gate; 203. First drain; 300. Second back gate; 301. Second source; 302. Second gate; 303. Second drain. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0033] As mentioned in the background section, devices with different operating voltages cannot be fabricated on the same wafer in the prior art. In order to solve the above problem, in a typical embodiment of this application, a substrate structure and a semiconductor device are provided.

[0034] According to an embodiment of this application, a substrate structure in a semiconductor device is provided. Figure 2 This is a schematic diagram of a substrate structure in a semiconductor device according to an embodiment of this application, such as... Figure 2 As shown, the substrate 103 structure includes a substrate 103, a top silicon layer 105, and a plurality of shallow trench isolation structures 107. The substrate 103 includes a plurality of spaced cavities 104, which are spaced apart in a predetermined direction perpendicular to the thickness of the substrate 103. The top silicon layer 105 is located on the surface of the substrate 103 and includes a plurality of top silicon layer 105 portions. The top silicon layer 105 portions are correspondingly disposed on the substrate 103 on both sides of the cavities 104 and located on the cavities 104. The thickness of the top silicon layer 105 portions on any two cavities 104 is different. One top silicon layer 105 portion and the corresponding at least one cavity 104 form a base region 106. The devices formed on any two base regions 106 are different. The plurality of shallow trench isolation structures 107 are located between any two adjacent base regions 106.

[0035] The aforementioned substrate structure includes a substrate, a top silicon layer, and multiple shallow trench isolation structures. The substrate includes multiple cavities spaced apart in a predetermined direction. The top silicon layer is located on the surface of the substrate and comprises multiple top silicon portions of varying thicknesses. Each top silicon portion and its corresponding at least one cavity form a base region. Multiple shallow trench isolation structures are located between any two adjacent base regions. In this substrate structure, the varying thickness of the top silicon portions allows for thicker top silicon layers for semiconductor devices with higher voltage requirements and thinner top silicon layers for semiconductor devices with lower voltage requirements. This satisfies the voltage requirements of different semiconductor devices, solving the problem in the prior art where devices with different operating voltages cannot be fabricated on the same wafer, thereby improving the electrical performance of the semiconductor devices. Furthermore, the cavities in this substrate structure further reduce the parasitic capacitance of the semiconductor devices, and the multiple shallow trench isolation structures suppress interference between different semiconductor devices, further enhancing the electrical performance of the semiconductor devices.

[0036] In one specific embodiment of this application, the materials of the substrate and the top silicon layer can be silicon or silicon carbide. Of course, in actual applications, they are not limited to silicon or silicon carbide and can also be other materials.

[0037] In another specific embodiment, the substrate can be a high-resistivity substrate, which can reduce parasitic power loss and minimize harmonic disturbances in high-frequency applications. It can also be a low-resistivity substrate. Of course, it is not limited to high-resistivity and low-resistivity substrates, and can also be other substrates.

[0038] Specifically, the locations of the multiple cavities are determined according to the needs of the actual device or circuit. Photoresist is deposited and developed in these areas, and then etched to form the cavities. The etching method can be dry etching, wet etching, or a combination of dry and wet etching. After forming the cavities, the substrate is bonded to the top silicon layer via wafer bonding to obtain the substrate structure.

[0039] Figures 3 to 8 The diagrams show the semiconductor structure formed after each process step in the fabrication method of the cavity in the prior art. The formation process of the cavity 104 includes the following steps: Figure 3 As shown, a substrate 103 is provided; a first oxide layer 108 is formed on the surface of the substrate 103 by thermal oxidation, forming as shown in the figure. Figure 4 The structure shown is as follows: photoresist is deposited and developed in the area to be etched, and then the first oxide layer 108 is etched to form a structure as shown. Figure 5 The structure shown; as Figure 6 As shown, substrate 103 is etched to form cavity 104; top silicon 105 is bonded to the surface of the first oxide layer 108 away from substrate 103 to form, as shown. Figure 7The structure shown; the thickness of the top silicon 105 is reduced to form a structure as shown. Figure 8 The structure shown.

[0040] In one specific embodiment of this application, such as Figure 9 As shown, to prevent damage to the substrate during the etching of the top silicon layer 105, which could lead to poor electrical performance of the semiconductor device, a second oxide layer 109 is first formed on the surface of the top silicon layer 105 away from the substrate. Then, a silicon nitride layer 110 is formed on the surface of the second oxide layer 109 away from the top silicon layer 105. The thickness of the silicon nitride is between 3 nm and 5 nm. Due to the high hardness of silicon nitride, damage to the substrate structure can be avoided in subsequent processes. Furthermore, the second oxide layer can alleviate excessive stress generated during the etching of the silicon nitride layer.

[0041] In practical applications, the above-mentioned method for forming the top silicon layer includes: etching the silicon nitride layer 110 and the second oxide layer 109 where etching is required, exposing the top silicon layer 105, and forming a structure as described above. Figure 10 The structure is shown. The desired top silicon thickness can be achieved by etching away a portion of the top silicon, or by first oxidizing the top silicon to consume a portion of its thickness, leaving a layer thinner than the target thickness. Then, the silicon nitride layer and the oxide layer on the top silicon surface are etched away, and the top silicon is regrown to the target thickness. This method allows for a flatter top silicon growth. The target thickness needs to be determined based on the device's operating voltage.

[0042] The method for forming the aforementioned shallow trench isolation structure includes: etching a shallow trench between any two adjacent substrate regions, and filling the shallow trench with silicon dioxide to form a shallow trench isolation structure. The presence of the shallow trench isolation structure can suppress signal crosstalk between devices and achieve better electrical isolation.

[0043] In one embodiment of this application, such as Figure 11As shown, the substrate 103 further includes a first insulating dielectric layer 111 and a first rich trap layer 112. The first insulating dielectric layer 111 is located on the inner surface of the cavity; the first rich trap layer 112 is located on the surface of the first insulating dielectric layer 111 away from the cavity. A substrate region 106 is formed by a top silicon portion, a corresponding cavity, and the first insulating dielectric layer 111 and the first rich trap layer 112 within the cavity 104. In this embodiment, the inner surface of the cavity has a first insulating dielectric layer, and the surface of the first insulating dielectric layer away from the cavity has a first rich trap layer. The rich trap layer has a large number of interface states, which act as carrier traps. These interface states can trap carriers, thereby preventing these carriers from generating substrate crosstalk. Furthermore, the first insulating dielectric layer separates the first rich trap layer from the substrate, preventing the recrystallization of the first rich trap layer at high temperatures. The recrystallized rich trap layer will lose its ability to trap induced mobile charges, thereby further improving the electrical performance of the semiconductor device.

[0044] To further improve the electrical performance of semiconductor devices, such as Figure 12 As shown, in another embodiment of this application, the substrate 103 further includes a second insulating dielectric layer 113, wherein the second insulating dielectric layer 113 is located on the surface of the first trap-rich layer 112 away from the first insulating dielectric layer 111. A substrate region 106 is formed by a top silicon layer, a corresponding cavity, and the first insulating dielectric layer 111, the first trap-rich layer 112, and the second insulating dielectric layer 113 within the cavity. In this embodiment, a second insulating dielectric layer is present on the surface of the first trap-rich layer away from the first insulating dielectric layer, and the second insulating dielectric layer fills the cavity, further preventing crosstalk.

[0045] Specifically, the materials of the first insulating dielectric layer and the second insulating dielectric layer can be silicon dioxide. In practical applications, they are not limited to silicon dioxide and can also be other materials. Those skilled in the art can choose according to the actual situation.

[0046] In another embodiment of this application, such as Figure 13 As shown, the second insulating dielectric layer includes a first insulating portion 114 and a second insulating portion 115. The first insulating portion 114 has a cavity; the second insulating portion 115 is located within the cavity and supports the portion of the first insulating portion 114 that contacts the top silicon layer. The second insulating portion 115 divides the cavity into two sub-cavities. In this embodiment, the second insulating portion divides the cavity in the first insulating portion into two sub-cavities, and also supports the portion of the first insulating portion that contacts the top silicon layer, thereby further improving the stability of the cavity structure and thus further improving the electrical performance of the semiconductor device.

[0047] In one specific embodiment of this application, the material of the second insulating dielectric layer is silicon dioxide. Since the dielectric constant of silicon dioxide is smaller than that of silicon, and the dielectric constant of vacuum is smaller than that of silicon dioxide, this substrate structure can reduce the parasitic capacitance of semiconductor devices.

[0048] In another specific embodiment, the second insulating part can not only divide the cavity into two sub-cavities, but also divide the cavity into multiple sub-cavities. A second insulating part is provided between any two adjacent sub-cavities. Those skilled in the art can select the number of sub-cavities according to the actual situation.

[0049] In another embodiment of this application, the thickness of the first insulating dielectric layer is between 0.5 nm and 10 nm. In this embodiment, the thickness of the first insulating dielectric layer is between 0.5 nm and 10 nm, allowing induced charges to cross the first insulating dielectric layer and be captured by the first trap-rich layer, further reducing interference caused by induced charges and thus further improving the electrical performance of the semiconductor device. Of course, in practical applications, the thickness of the first insulating dielectric layer is not limited to this range and can be other ranges.

[0050] To further improve the electrical performance of the semiconductor device, in another embodiment of this application, the thickness of the first trap-rich layer is between 3 nm and 200 nm. Similarly, in practical applications, the thickness of the first trap-rich layer can also be other values.

[0051] In another embodiment of this application, the material of the first trap-rich layer includes at least one of polysilicon, SiC, and SiGe. In this embodiment, using at least one of polysilicon, SiC, and SiGe as the material of the first trap-rich layer ensures better trapping performance, thereby further improving the electrical performance of the semiconductor device. Of course, the material of the first trap-rich layer can also be other materials, which can be selected by those skilled in the art according to the actual situation.

[0052] In another embodiment of this application, such as Figure 14 As shown, the shallow trench isolation structure includes a second trap-rich layer and a third insulating dielectric layer, wherein the third insulating dielectric layer surrounds the outer periphery of the second trap-rich layer. Since the trapped charges present in the third insulating dielectric layer can also induce a weak mobile charge accumulation region in the shallow region of the interface with silicon, causing device loss and signal crosstalk between devices, in this embodiment, the shallow trench isolation structure includes a second trap-rich layer and a third insulating dielectric layer. The second trap-rich layer can suppress the formation of the weak mobile charge accumulation region, reduce signal crosstalk, and thereby further improve the electrical performance of the semiconductor device.

[0053] In one specific embodiment of this application, the material of the second trap-rich layer includes at least one of polycrystalline silicon, SiC, and SiGe, and the material of the third insulating dielectric layer is silicon dioxide. In practical applications, the second trap-rich layer and the third insulating dielectric layer can also be other materials, which can be selected by those skilled in the art according to the actual situation.

[0054] In another specific embodiment, the formation process of the second trap-rich layer is as follows: an isolation trench is etched in the shallow trench isolation structure, then an oxide layer is formed on the inner wall of the isolation trench by high-temperature thermal oxidation, and then a polycrystalline silicon trap-rich layer is filled in it. The thickness of the oxide layer is between 2nm and 5nm, which allows induced charges to pass through the oxide layer and be trapped by the trap-rich layer. The shallow trench isolation structure with the trap-rich layer can form a larger silicon region while ensuring better device isolation, thereby achieving better heat dissipation.

[0055] In another embodiment of this application, the depth of the cavity is between 200 nm and 2 μm. In this embodiment, the cavity depth is between 200 nm and 2 μm, which further ensures a small parasitic capacitance of the entire bonding structure, thereby further improving the electrical performance of the semiconductor device. Of course, the depth of the cavity is not limited to the above numerical range; those skilled in the art can design cavities with even greater depths to further reduce parasitic capacitance.

[0056] According to an embodiment of this application, a semiconductor device is also provided, including a substrate structure and a device portion. The substrate structure is any of the substrate structures in the above-mentioned semiconductor devices, and the device portions are disposed one-to-one on the substrate region. The devices of any two of the device portions are different.

[0057] The aforementioned semiconductor device includes a substrate structure and device sections. The substrate structure can be any of the aforementioned semiconductor device substrate structures. The device sections are correspondingly disposed on the substrate region, and the devices in any two device sections are different. In the aforementioned substrate structure, the thickness of the top silicon layer varies. Semiconductor devices with higher voltage requirements have a thicker top silicon layer, while semiconductor devices with lower voltage requirements have a thinner top silicon layer. Therefore, the voltage requirements of different semiconductor devices can be met, thereby solving the problem in the prior art that devices with different operating voltages cannot be fabricated on the same wafer, thus improving the electrical performance of the semiconductor device. In addition, the cavity in this substrate structure further reduces the parasitic capacitance of the semiconductor device, and the multiple shallow trench isolation structures can suppress interference between different semiconductor devices, further improving the electrical performance of the semiconductor device. Therefore, since the semiconductor device uses the aforementioned substrate structure, multiple semiconductor devices with different operating voltages can be integrated on this semiconductor device, further improving the electrical performance of the semiconductor device.

[0058] In one specific embodiment, such as Figure 15 As shown, the aforementioned semiconductor structure includes a semiconductor device operating at 12V, a semiconductor device operating at 5V, and a substrate structure. The first device portion of the 12V semiconductor device includes a first back gate 200, a first source 201, a first gate 202, and a first drain 203, with the cavity 104 located below the first device portion. The second device portion of the 5V semiconductor device includes a second back gate 300, a second source 301, a second gate 302, and a second drain 303, with the cavity 104 located below the second device portion. This semiconductor device includes two semiconductor devices operating at different voltages, further improving the electrical performance of the semiconductor device.

[0059] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0060] 1) The substrate structure of this application includes a substrate, a top silicon layer, and multiple shallow trench isolation structures. The substrate includes multiple cavities spaced apart in a predetermined direction. The top silicon layer is located on the surface of the substrate and includes multiple top silicon portions of varying thicknesses. Each top silicon portion and its corresponding at least one cavity form a base region. Multiple shallow trench isolation structures are located between any two adjacent base regions. In this substrate structure, the different thicknesses of the top silicon portions allow for greater thickness in semiconductor devices with higher voltage requirements and less thickness in semiconductor devices with lower voltage requirements. Therefore, the voltage requirements of different semiconductor devices can be met, solving the problem in the prior art where devices with different operating voltages cannot be fabricated on the same wafer, thereby improving the electrical performance of the semiconductor devices. Furthermore, the cavities in this substrate structure further reduce the parasitic capacitance of the semiconductor devices, and the multiple shallow trench isolation structures can suppress interference between different semiconductor devices, further improving the electrical performance of the semiconductor devices.

[0061] 2) The semiconductor device of this application includes a substrate structure and device portions. The substrate structure can be any of the aforementioned semiconductor device substrate structures. The device portions are disposed one-to-one on the substrate region, and the devices in any two device portions are different. In the aforementioned substrate structure, the thickness of the top silicon layer varies. The top silicon layer of semiconductor devices with higher voltage requirements is thicker, while the top silicon layer of semiconductor devices with lower voltage requirements is thinner. Therefore, the voltage requirements of different semiconductor devices can be met, thereby solving the problem in the prior art that devices with different operating voltages cannot be fabricated on the same wafer, and thus improving the electrical performance of the semiconductor device. In addition, the cavity in this substrate structure further reduces the parasitic capacitance of the semiconductor device, and the multiple shallow trench isolation structures can suppress interference between different semiconductor devices, further improving the electrical performance of the semiconductor device. Therefore, since the semiconductor device adopts the aforementioned substrate structure, multiple semiconductor devices with different operating voltages can be integrated on the semiconductor device, further improving the electrical performance of the semiconductor device.

[0062] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A substrate structure in a semiconductor device, characterized by, include: A substrate includes a plurality of spaced cavities, the plurality of cavities being spaced apart in a predetermined direction, the predetermined direction being a direction perpendicular to the thickness of the substrate; The top silicon layer is located on the surface of the substrate. The top silicon layer includes multiple top silicon layers, which are correspondingly disposed on the substrate on both sides of the cavity and located on the cavity. The thickness of the top silicon layer on any two cavities is different. One top silicon layer and at least one corresponding cavity form a base region. The devices formed on any two base regions are different. Multiple shallow trench isolation structures are located between any two adjacent base regions; The substrate further includes: a first insulating dielectric layer located on the inner surface of the cavity; A first trap-rich layer is located on the surface of the first insulating dielectric layer away from the cavity. A substrate region is formed by a top silicon portion, a corresponding cavity, and the first insulating dielectric layer and the first trap-rich layer within the cavity.

2. The substrate structure of claim 1, wherein The substrate further includes: The second insulating dielectric layer is located on the surface of the first trap-rich layer away from the first insulating dielectric layer. A substrate region is formed by a top silicon portion, a corresponding cavity, and the first insulating dielectric layer, the first trap-rich layer, and the second insulating dielectric layer within the cavity.

3. The substrate structure of claim 2, wherein, The second insulating dielectric layer includes: The first insulating part has a cavity; The second insulating portion, located within the cavity and used to support the portion of the first insulating portion that contacts the top silicon portion, divides the cavity into two sub-cavities.

4. The substrate structure of claim 1, wherein The thickness of the first insulating dielectric layer is between 0.5 nm and 10 nm.

5. The substrate structure of claim 1, wherein The thickness of the first trap-rich layer is between 3nm and 200nm.

6. The substrate structure according to claim 1, characterized in that, The material of the first trap-rich layer includes at least one of polycrystalline silicon, SiC, and SiGe.

7. The substrate structure according to claim 1, characterized in that, The shallow trench isolation structure includes: The second rich trap layer; A third insulating dielectric layer is disposed around the outer periphery of the second trap-rich layer.

8. The substrate structure according to any one of claims 1 to 7, characterized in that, The depth of the cavity is between 200 nm and 2 μm.

9. A semiconductor device, characterized in that, It includes a substrate structure and a device section, wherein the substrate structure is the substrate structure of the semiconductor device according to any one of claims 1 to 8, and the device sections are disposed one-to-one on the substrate region, and the devices of any two device sections are different.

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