Power supply system and chip

Abstract

The application provides a power supply system and a chip, which can utilize a first power tube and a first overcurrent detection module to form a power supply protection branch for supplying power to a first circuit in the chip and detecting overcurrent, utilize a second power tube and a second overcurrent detection module to form another power supply protection branch for supplying power to a second circuit in the chip and detecting overcurrent, thereby realizing overcurrent detection and protection of the first circuit and the second circuit in the chip supplied by the same power supply signal, overcurrent protection when overcurrent occurs in the power supply branch in which any one of the first circuit and the second circuit is located, and reduction of the misjudgment rate of overcurrent protection of the chip. When the technical scheme of the application is applied to a fingerprint chip (especially a side fingerprint chip), the problem that the fingerprint chip is overheated and the temperature is too high to endanger the safety of a user due to a long time and a large short-circuit current can be avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a power supply system and chip. Background Technology

[0002] Chip technology is closely related to people's daily lives. From manufacturing to reaching consumers, chips undergo multiple logistics transfers, which can easily cause irreparable hardware damage due to unforeseen external forces. This can lead to short circuits in some nodes of the chip's internal circuitry, with short-circuit currents reaching hundreds of milliamps. Prolonged exposure to large short-circuit currents can cause the chip to overheat, further damaging the internal circuitry and even endangering user safety. This is especially true in fingerprint chip modules. Because the fingerprint chip in a fingerprint module needs to directly contact the outside world or the human body, its packaging differs from ordinary chips (for example, side-mounted fingerprint modules often only use epoxy molding compound EMC and fingerprint coating to achieve thinness). Therefore, if some nodes of the fingerprint chip's internal circuitry short-circuit, the resulting short-circuit current can reach hundreds of milliamps. Prolonged exposure to large short-circuit currents can cause the fingerprint chip to overheat, endangering user safety.

[0003] Therefore, how to design a power supply system and a chip with such a power supply system to effectively power, detect current, and protect overcurrent circuits within the chip has become one of the key technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a power supply system and chip that can effectively supply power and detect current in the first and second circuits inside the chip, so as to provide timely overcurrent protection when an overcurrent occurs in either the first or second circuit.

[0005] To achieve the above objectives, the present invention provides a power supply system for supplying power to a first circuit and a second circuit of a chip respectively via the same power signal, the power supply system comprising:

[0006] The first power transistor is coupled between the power signal and the power supply terminal of the first circuit.

[0007] The first overcurrent detection module is connected to the control terminal of the first power transistor and is used to detect the first power supply current provided by the first power transistor to the first circuit. When the first power supply current exceeds the first current limit value, the first power transistor is turned off to stop the power supply signal from supplying power to the power terminal of the first circuit.

[0008] The second power transistor is coupled between the power signal and the power supply terminal of the second circuit.

[0009] The second overcurrent detection module is connected to the control terminal of the second power transistor. It is used to detect the second power supply current provided by the second power transistor to the second circuit, and to turn off the second power transistor when the second power supply current exceeds the second current limit value, so as to stop the power supply signal from supplying power to the power terminal of the second circuit.

[0010] Optionally, the power supply system further includes a first OR logic, wherein the two input terminals of the first OR logic are respectively connected to the output terminals of the first overcurrent detection module and the second overcurrent detection module, and the output terminal of the first OR logic is connected to the interrupt pin of a control unit; the first OR logic is used to send an interrupt signal to the control unit through the interrupt pin when the first power supply current exceeds the first current limit value or the second power supply current exceeds the second current limit value, and further enables the control unit to control the first power transistor or the second power transistor to turn on again after detecting the interrupt signal for a period of time.

[0011] Optionally, the first circuit has a low-power module, and the power supply system has a signal input / output module and an interrupt module. The power supply terminal of the low-power module is directly connected to the power signal. The signal input / output module is connected between the output terminal of the low-power module and the input / output pin of the control unit. The interrupt module is connected to the output terminal of the first OR logic, the interrupt pin of the control unit, and the output terminal of the low-power module. The low-power module is used to supply power to the signal input / output module and the interrupt module when the first power transistor is turned off, so that the signals output by the signal input / output module and the signals output by the interrupt module can be effectively sent to the control unit.

[0012] Optionally, the first overcurrent detection module has a first comparator and a first reference circuit. One input terminal of the first comparator is connected to the connection node between the first power transistor and the power supply terminal of the first circuit, and the other input terminal of the first comparator is connected to the output terminal of the first reference circuit.

[0013] The second overcurrent detection module has a second comparator and a second reference circuit. One input terminal of the second comparator is connected to the connection node between the second power transistor and the power supply terminal of the second circuit, and the other input terminal of the second comparator is connected to the output terminal of the second reference circuit.

[0014] Wherein, the first reference circuit and the second reference circuit are two electrically separated circuits. The first reference circuit is used to generate a first reference voltage according to the first current limit value, and the second reference circuit is used to generate a second reference voltage according to the second current limit value; or, the first reference circuit and the second reference circuit are the same reference circuit, and the same reference circuit generates a reference voltage according to the first current limit value and the second current limit value.

[0015] Optionally, the first reference circuit, the second reference circuit, or the same reference circuit each include a coupled reference switch and a tail load, and the control terminal of the reference switch and the other end of the tail load are both grounded.

[0016] Optionally, the tail load is a tail current source or a tail resistor.

[0017] Optionally, the first power transistor, the second power transistor, and the reference switch transistor constitute a current mirror structure. The first current limiting value of the first overcurrent detection module is determined by the size ratio of the first power transistor and the reference switch transistor, and the second current limiting value of the second overcurrent detection module is determined by the size ratio of the second power transistor and the reference switch transistor.

[0018] Optionally, when the first overcurrent detection module and the second overcurrent detection module share the same reference circuit, the size ratio of the first power transistor and the reference switch transistor is such that when the drain current of the first power transistor is equal to the first current limiting value, the drain voltage of the first power transistor and the reference switch transistor are equal to and equal to the reference voltage; the size ratio of the second power transistor and the reference switch transistor is such that when the drain current of the second power transistor is equal to the second current limiting value, the drain voltage of the second power transistor and the reference switch transistor are equal to and equal to the reference voltage; wherein the drain current of the first power transistor is the first supply current, and the drain current of the second power transistor is the second supply current.

[0019] Optionally, the first overcurrent detection module further includes a first delay circuit, which is coupled between the output terminal of the first comparator and the control terminal of the first power transistor, and is used to keep the voltage at the control terminal of the first power transistor unchanged when the first supply current is greater than the first current limit value but does not exceed the first preset duration.

[0020] And / or, the second overcurrent detection module further includes a second delay circuit, which is coupled between the output terminal of the second comparator and the control terminal of the second power transistor, for maintaining the voltage at the control terminal of the second power transistor unchanged when the second supply current is greater than the second current limit value but does not exceed the second preset duration.

[0021] Optionally, the first delay circuit is an RC delay circuit, and / or the second delay circuit is an RC delay circuit.

[0022] Optionally, the first overcurrent detection module further includes a second OR logic, one input of the second OR logic is connected to the output of the first delay circuit, and the other input of the second OR logic is connected to the start / stop control signal issued by the control unit. The second OR logic is used to control the first power transistor to be turned on or off according to the start / stop control signal or the output of the first delay circuit.

[0023] And / or, the second overcurrent detection module further includes a third OR logic, one input of which is connected to the output of the second delay circuit, and the other input of which is connected to the start / stop control signal. The third OR logic is used to control the second power transistor to turn on or off according to the start / stop control signal or the output of the second delay circuit.

[0024] Optionally, the power supply system further includes a first resistor, one end of which is connected to the power signal, and the other end of which is connected to the power supply terminal of the first overcurrent detection module.

[0025] And / or, the power supply system further includes a second resistor, one end of which is connected to the power signal, and the other end of which is connected to the power supply terminal of the second overcurrent detection module.

[0026] Based on the same inventive concept, the present invention also provides a chip, which includes a first circuit, a second circuit, and a power supply system as described in the present invention. The power supply system supplies power to the first circuit and the second circuit respectively through the same power signal, and the power supply system provides a first power supply current to the first circuit and a second power supply current to the second circuit.

[0027] Optionally, the first circuit, the second circuit, and the power supply system are all coupled to the control unit. When the first power supply current exceeds the first current limit or the second power supply current exceeds the second current limit, the power supply system sends an interrupt signal to the control unit. After a period of time, the power supply system receives a start-stop control signal from the control unit and further controls the corresponding first power transistor or second power transistor to turn on again. If the interrupt signal received at a fixed time interval exceeds a threshold, the control unit will not send the start-stop control signal.

[0028] Optionally, the chip is a fingerprint chip, and the first circuit includes a fingerprint pixel array, a fingerprint signal acquisition circuit, a signal amplification circuit, and an analog-to-digital converter connected in sequence; the second circuit includes a filtering circuit and a digital signal processing circuit, and the digital signal processing circuit is used to output the image of the fingerprint acquired by the first circuit.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] 1. A power supply protection branch is formed by using a first power transistor and a first overcurrent detection module to supply power and detect overcurrent in the first circuit within the chip. A second power transistor and a second overcurrent detection module are formed to form another power supply protection branch to supply power and detect overcurrent in the second circuit within the chip. This enables the first circuit and the second circuit within the chip, which are powered by the same power signal, to perform overcurrent detection and protection separately. Overcurrent protection can be performed when an overcurrent occurs in the power supply branch of either the first circuit or the second circuit, reducing the false alarm rate of the chip's overcurrent protection.

[0031] 2. The power supply system of the present invention allows two power supply branches to share the same external power signal, thus having fewer constraints on the power supply voltage and being applicable to chips in various voltage domains.

[0032] 3. The power supply system of this invention can be added to the original internal circuit of the chip without causing a loss of voltage margin to the chip.

[0033] 4. When the first overcurrent detection module and the second overcurrent detection module share the same reference circuit, the first power transistor, the second power transistor, and the reference switch in the same reference circuit can form a current mirror structure. By reasonably setting the size ratio of the first power transistor, the second power transistor, and the reference switch in the same reference circuit, a balance can be achieved between circuit power consumption and overcurrent protection speed, thereby further reducing power consumption and allowing the chip's operating voltage range to reach a lower level.

[0034] 5. The first circuit of the chip is equipped with a low-power module, which can be directly connected to an external power supply signal to supply power to the interrupt module and signal input / output module of the power supply system after the first power transistor is turned off. Thus, when the chip enters the overcurrent protection state, some corresponding signals can still be effectively sent to the corresponding control unit by the interrupt module and signal input / output module (the control unit can be an external controller chip or an internal control unit of the chip).

[0035] 6. When the technical solution of the present invention is applied to fingerprint chips (especially side fingerprint chips), it can avoid the problem of fingerprint chips overheating and exceeding the temperature due to long-term large short-circuit current, which could endanger the safety of users. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the circuit architecture design of a power supply system according to an embodiment of the present invention.

[0037] Figure 2 yes Figure 1 The diagram shows the connection between the power supply system and the external control unit.

[0038] Figure 3 yes Figure 2 The diagram shows an example of the circuit architecture design of the first overcurrent detection module and the second overcurrent detection module in the power supply system shown.

[0039] Figure 4 yes Figure 2 This is another example of the circuit architecture design of the first overcurrent detection module and the second overcurrent detection module in the power supply system shown.

[0040] Figure 5 yes Figure 2 and Figure 4 The diagram shows specific circuit design examples of the various reference circuits in the diagram.

[0041] Figure 6 yes Figure 4 The diagram shows a specific circuit connection in a particular circuit architecture design example.

[0042] Figure 7 yes Figure 6 The diagram shows the curves of the second supply current and the DOCP signal changing with the actual situation in the specific circuit shown.

[0043] Figure 8 This is a schematic diagram of the structure of a chip according to an embodiment of the present invention. Detailed Implementation

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. Although the terms first, second, third, etc., may be used to describe various elements, components, and / or portions, these elements, components, and / or portions should not be limited by these terms. These terms are used merely to distinguish one element, component, or portion from another element, component, or portion. Therefore, without departing from the teachings of the invention, the first element, component, or portion discussed below may be referred to as the second element, component, or portion. When used herein, the singular forms of "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0045] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] Please refer to Figure 1An embodiment of the present invention provides a power supply system 1, which is used to supply power to a first circuit 3 and a second circuit 2 of a chip via the same external power signal AVDD. The power supply system 1 includes: a first power transistor M1, a first overcurrent detection module OCP_A, a second power transistor M2, and a second overcurrent detection module OCP_D. The first power transistor M1 is coupled between the power signal AVDD and the power supply terminal (not shown) of the first circuit 3, and the second power transistor M2 is coupled between the power signal AVDD and the power supply terminal (not shown) of the second circuit 2. The first overcurrent detection module OCP_A is connected to the control terminal of the first power transistor M1, and the second overcurrent detection module OCP_D is connected to the control terminal of the second power transistor M2. When M1 and M2 are MOSFETs, their control terminals are the gates of the MOSFETs; when M1 and M2 are transistors, their control terminals are the bases of the transistors. The first overcurrent detection module OCP_A is used to detect the first supply current I1 provided by the first power transistor M1 to the power supply terminal (not shown) of the first circuit 3, and when the first supply current I1 exceeds the first current limit value (not shown), it turns off the first power transistor M1 (i.e., turns off M1) to stop the power supply signal AVDD from supplying power to the power supply terminal of the first circuit 3; the second overcurrent detection module OCP_D is used to detect the second supply current I2 provided by the second power transistor M2 to the second circuit 2, and when the second supply current I2 exceeds the second current limit value (not shown), it turns off the second power transistor M2 (i.e., turns off M2) to stop the power supply signal AVDD from supplying power to the power supply terminal (not shown) of the second circuit 2.

[0047] Optionally, the power supply system 1 may have a power input terminal VDD PAD (which can be a circuit formed by connecting multiple electronic components, or a wiring structure such as pads, terminals, or pins). The power signal AVDD is connected to the first power transistor M1, the first overcurrent detection module OCP_A, the second power transistor M2, and the second overcurrent detection module OCP_D through the power input terminal VDD. It is worth noting that in many practical applications of chips, multiple voltage domain power supplies cannot be provided to the chip externally. The power terminals (not shown) of the first circuit 3 and the second circuit 2 of the chip are both coupled to the external power signal AVDD. However, the power signal AVDD can be powered internally by a low-dropout regulator (LDO) to output different voltages to power the first circuit 3 and the second circuit 2 respectively. The operating currents of the first circuit 3 and the second circuit 2 are significantly different, so the first power transistor M1 and the second power transistor M2 need to be powered separately for overcurrent detection. The first circuit 3 is, for example, an analog circuit, and the second circuit 2 is, for example, a digital circuit.

[0048] Alternatively, please refer to Figure 2 The power supply system also includes a first OR logic OR1. The two inputs of the first OR logic OR1 are respectively connected to the outputs of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D. The output of the first OR logic OR1 is connected to the interrupt pin INT of a control unit 4. The first OR logic OR1 is used to send an interrupt signal INT to the control unit 4 through the interrupt pin INT when the first supply current I1 exceeds the first current limit value (not shown) set for the first circuit 3, or when the second supply current I2 exceeds the second current limit value (not shown) set for the second circuit 2. Furthermore, the control unit 4 controls the first power transistor M1 or the second power transistor M2 to turn on again (also known as M1 or M2 turning on) after detecting the interrupt signal INT for a period of time.

[0049] Optionally, the first circuit 3 includes a low-power module 30 directly powered by the power signal AVDD. This power supply system includes a signal input / output module (I / O PAD) and an interrupt module (IRQ PAD). The power supply terminal of the low-power module 30 is directly connected to the power signal AVDD. The signal input / output module (I / O PAD) is connected between the output terminal of the low-power module 30 and the input / output pins (I / O) of the control unit 4. The interrupt module (IRQ PAD) is connected to the output terminal of the first OR logic (OR1), the interrupt pin (INT) of the control unit 4, and the output terminal of the low-power module 30. The low-power module 30 supplies power to the signal input / output module (I / O PAD) and the interrupt module (IRQ PAD) when the first power transistor M1 is turned off, ensuring that the signals output by both the signal input / output module (I / O PAD) and the interrupt module (IRQ PAD) are effectively transmitted to the control unit 4.

[0050] As an example, the low-power module 30 may consist of interconnected subthreshold transistors BG and low-dropout regulators LDO.

[0051] It should be understood that the control unit 4 can be a controller chip (e.g., an MCU chip) that is independent of the chip having the power supply system 1, the first circuit 3 and the second circuit 2, or it can be a control circuit that is integrated into the same chip as the power supply system 1, the first circuit 3 and the second circuit 2 as needed.

[0052] In this embodiment, the power supply system 1 also has a start / stop control terminal Shutdn PAD that connects to the control unit 4, the first overcurrent detection module OCP_A, and the second overcurrent detection module OCP_D. The control unit 4 provides a start / stop control signal Shutdn to the start / stop control terminal Shutdn PAD of the power supply system 1. Under the control of the start / stop control signal Shutdn, the first overcurrent detection module OCP_A can control the first power transistor M1 to turn on or off, and the second overcurrent detection module OCP_D can control the second power transistor M2 to turn on or off under the control of the start / stop control signal Shutdn.

[0053] When both the first power transistor M1 and the second power transistor M2 are PMOS transistors (of course, this invention is not limited to this, and they can also be NMOS transistors, NPN transistors, or PNP transistors, etc.), Figure 2 The specific operation control process of the power supply system shown includes:

[0054] First, the control unit 4 outputs a start control signal to the start / stop control terminal Shutdn PAD of the power supply system 1 to control the output of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D. When the first overcurrent detection module OCP_A outputs a low level to the gate of the first power transistor M1 and the second overcurrent detection module OCP_D outputs a low level to the gate of the second power transistor M2, the first power transistor M1 and the second power transistor M2 are turned on (i.e. turned on). The power supply signal AVDD supplies power to the first circuit 3 and the second circuit 2 in the chip. At this time, the first power transistor M1 and the second power transistor M2 are working in the deep linear region and have a very small voltage drop.

[0055] When the first circuit 3 and the second circuit 2 of the chip are working, the first overcurrent detection module OCP_A starts to detect the drain current of the first power transistor M1 (i.e., the first supply current I1), and the second overcurrent detection module OCP_D starts to detect the drain current of the second power transistor M2 (i.e., the second supply current I2). Under normal operating conditions, both I1 and I2 are small. The output of the first overcurrent detection module OCP_A keeps the first power transistor M1 continuously conducting, and the second overcurrent detection module OCP_D keeps the second power transistor M2 continuously conducting. The outputs of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D together make the first logic OR1 continuously output a low level to the interrupt module IRQ PAD. The interrupt pin INT of the control unit 4 will not be pulled up, and the control unit 4 detects that the chip's operating current is normal.

[0056] When I1 remains consistently high (mainly when I1 continuously exceeds the set first current limit value and the duration exceeds the set first preset time, indicating a fault such as a short circuit to ground in the first circuit 3), the first overcurrent detection module OCP_A outputs a high level to the gate of the first power transistor M1 to turn off the first power transistor M1, thereby turning off the power supply signal AVDD to the first circuit 3 (so that most or all of the electronic components of the first circuit 3 stop working) to achieve the purpose of overcurrent protection of the chip. At the same time, the output of the corresponding output terminal of the first overcurrent detection module OCP_A also causes the first logic OR1 to continuously output a high-level signal to the interrupt module IRQ PAD, thereby pulling up the interrupt pin INT of the control unit 4 (or, in other words, the interrupt module IRQ PAD sends an interrupt signal INT to the control unit 4), thereby enabling the control unit 4 to detect the overcurrent protection status of the chip. After a certain period of time, the control unit 4 sends a start-stop control signal Shutdn through the start-stop control terminal Shutdn PAD, which controls the output of the first overcurrent detection module OCP_A to flip, so as to turn on the first power transistor M1 again, so that the power signal AVDD can supply power to the first circuit 3 again, thereby restoring the operation of the first circuit 3.

[0057] Similarly, when I2 remains consistently high (mainly when I2 continuously exceeds the second current limit value and the duration exceeds the second preset time, indicating a fault such as a short circuit to ground in the second circuit 3), the second overcurrent detection module OCP_D outputs a high level to the gate of the second power transistor M2 to turn off the second power transistor M2, thereby turning off the power supply signal AVDD to the second circuit 2 (so that most or all of the electronic components of the second circuit 2 stop working) to achieve the purpose of overcurrent protection of the chip. At the same time, the output of the corresponding output terminal of the second overcurrent detection module OCP_D also causes the first logic OR1 to continuously output a high level signal to the interrupt module IRQ PAD, thereby pulling up the interrupt pin INT of the control unit 4 (or, in other words, the interrupt module IRQ PAD sends an interrupt signal INT to the control unit 4), thus enabling the control unit 4 to detect the overcurrent protection status of the chip. After a certain period of time, the control unit 4 sends a start-stop control signal Shutdn through the start-stop control terminal ShutdnPAD to control the output of the second overcurrent detection module OCP_D to flip, so as to turn on the second power transistor M2 again, so that the power signal AVDD can supply power to the second circuit 2 again, thereby restoring the operation of the second circuit 2.

[0058] It should be understood that since the interrupt module IRQ PAD is connected to the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D through the first logic OR1, as long as either of the two supply currents I1 and I2 is continuously large as described above, the first logic OR1 can continuously output a high-level signal to the interrupt module IRQ PAD, thereby pulling up the interrupt pin INT of the control unit 4, thus enabling the control unit 4 to detect the current protection status of the chip.

[0059] Furthermore, when the first circuit 3 has a low-power module 30 that is directly powered by the power signal AVDD, the output of the low-power module 30 can power the input / output module I / O PAD and the interrupt module IRQ PAD. This ensures that when the first power transistor M1 is turned off, the corresponding signals generated by the interrupt module IRQ PAD and the input / output module I / O PAD due to the continuous operation of the second power transistor M2 and the continuous output of the second circuit 2 can still be effectively sent to the control unit 4.

[0060] Furthermore, when the power supply system is integrated into the same chip as the first circuit 3 and the second circuit 2, the interrupt module IRGPAD, the input / output module I / O PAD, the start / stop control terminal Shutdn PAD, and the power input terminal VDD PAD are all used to form the corresponding pins of the chip to output or connect to the corresponding external signals.

[0061] Furthermore, the circuit architecture design and specific circuit connection of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D can adopt any suitable design known to those skilled in the art, and the present invention does not impose any specific limitations on them.

[0062] As an example, please refer to Figure 3The first overcurrent detection module OCP_A includes a first comparator COMP1, a first delay circuit 11, a first reference circuit 12, and a second logic OR 2. The first reference circuit 12 is directly powered by the power supply signal AVDD and is used to generate a first current limiting value based on the power supply signal AVDD. One input terminal of the first comparator COMP1 is connected to the connection node between the first power transistor M1 and the power supply terminal of the first circuit 3 to acquire the first supply current I1 provided by the first power transistor M1 to the first circuit 3; the other input terminal of the first comparator COMP1 is connected to the output terminal of the first reference circuit 12 to acquire the first current limiting value generated by the first reference circuit 12. Thus, the first comparator COMP1 can compare the magnitude of I1 and the first current limiting value and output a corresponding high or low level according to the comparison result. The first delay circuit 11 is coupled between the output of the first comparator COMP1 and the control terminal of the first power transistor M1 (via the second OR logic OR2). It is used to maintain the voltage at the control terminal of the first power transistor M1 unchanged when the first supply current I1 is greater than the first current limit value generated by the first reference circuit 12, but the duration of this excess does not exceed a first preset duration. One input of the second OR logic OR2 is connected to the output of the first delay circuit 11, and the other input is connected to the start / stop control terminal Shutdn PAD to receive the start / stop control signal Shutdn issued by the control unit 4. The second OR logic OR2 is used to control the first power transistor M1 to turn on or off according to the start / stop control signal Shutdn issued by the control unit 4 or the output AOCP of the first delay circuit 11.

[0063] The second overcurrent detection module OCP_D includes a second comparator COMP2, a second delay circuit 13, a second reference circuit 14, and a third logic OR 3. The second reference circuit 14 is directly powered by the power supply signal AVDD. The second reference circuit 14 generates a second current limit value based on the power supply signal AVDD. This second current limit value can be the same as or different from the first current limit value generated by the first reference circuit 12. One input terminal of the second comparator COMP2 is connected to the connection node between the second power transistor M2 and the power supply terminal of the second circuit 2 to acquire the second supply current I2 provided by the second power transistor M2 to the second circuit 2. The other input terminal of the second comparator COMP2 is connected to the output terminal of the second reference circuit 14 to acquire the second current limit value generated by the second reference circuit 14. Thus, the second comparator COMP2 can compare the magnitudes of I2 and the second current limit value and output a corresponding high or low level based on the comparison result. The second delay circuit 13 is coupled between the output of the second comparator COMP2 and the control terminal of the second power transistor M2 (via the third OR logic OR3). It is used to maintain the voltage at the control terminal of the second power transistor M2 unchanged when the second supply current I2 is greater than the second current limit value generated by the second reference circuit 14, but the duration of this excess does not exceed the second preset duration. One input of the third OR logic OR3 is connected to the output of the second delay circuit 13, and the other input is connected to the start / stop control terminal Shutdn PAD to receive the start / stop control signal Shutdn issued by the control unit 4. The third OR logic OR3 is used to control the second power transistor M2 to turn on or off according to the start / stop control signal Shutdn issued by the control unit 4 or the output DOCP of the second delay circuit 13.

[0064] The configuration of the first delay circuit 11 and the second delay circuit 13 can prevent damage to the chip caused by a large current in a short period of time, and also prevent the output of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D from flipping due to a large current in a short period of time.

[0065] In the above example, the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D use two electrically separated reference circuits (i.e., the first reference circuit 12 and the second reference circuit 14) to obtain their respective required current limiting values, which can meet the different overcurrent protection threshold requirements of different circuits within the chip. However, the technical solution of the present invention is not limited to this. Please refer to... Figure 4 In other examples of this embodiment, the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D can share the same reference circuit 10. This same reference circuit 10 can also provide different current limiting values ​​to the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D, which is equivalent to... Figure 3 The first reference circuit 12 and the second reference circuit 14 in the circuit are the same reference circuit. This same reference circuit can still provide different first and second current limiting values, depending on the size ratio between the first power transistor M1, the second power transistor M2, and the reference switch transistor Ms in the reference circuit 10. Since the size ratio between the first power transistor M1 and the reference switch transistor Ms in the reference circuit 10 is different from the size ratio between the second power transistor M2 and the reference switch transistor Ms in the reference circuit 10, the first and second current limiting values ​​are different. This achieves the technical effect of reducing circuit area.

[0066] It should be understood that in the above examples, each reference circuit 10 / 12 / 14 can provide the required current limiting value for the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D. Each reference circuit 10 / 12 / 14 can generate a corresponding reference voltage according to the first current limiting value and the second current limiting value. The first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D compare the detection voltage corresponding to the first supply current I1 (i.e., the drain voltage of the first power transistor M1) and the detection voltage corresponding to the second supply current I2 (i.e., the drain voltage of the second power transistor M2) with the corresponding reference voltage. Specifically, the same reference circuit 10 or the first reference circuit 12 can generate a corresponding first reference voltage according to the first current limit value, and the first overcurrent detection module OCP_A can compare the drain voltage of the first power transistor M1 with the first reference voltage to output a high level or a low level according to the comparison result; the same reference circuit 10 or the second reference circuit 14 can generate a corresponding second reference voltage according to the second current limit value, and the second overcurrent detection module OCP_D can compare the drain voltage of the second power transistor M2 with the second reference voltage to output a high level or a low level according to the comparison result.

[0067] Alternatively, please refer to Figures 3-5 The first reference circuit 12, the second reference circuit 14, or the same reference circuit 10 may each include a coupled reference switch Ms and a tail load Rs. The control terminal of the reference switch Ms (i.e., the gate of the MOS transistor) and the other end of the tail load Rs are both grounded. The other end of the reference switch Ms is connected to the power supply signal AVDD. The tail load Rs can be a tail current source or a tail resistor. The tail load Rs ensures that the drain current of Ms is constant and provides a stable switching point voltage for the first comparator COMP1 and the second comparator COMP2, thereby improving the accuracy and reliability of the comparison results of the first comparator COMP1 and the second comparator COMP2.

[0068] Please refer to Figure 6 The following example illustrates the circuit design principle and logic timing of the power supply system in this embodiment, using the example of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D sharing the same reference circuit 10, where the reference circuit 10 consists of a reference switch Ms and a tail load Rs, the first delay circuit 11 consists of a delay resistor R3 and a delay capacitor C1, the second delay circuit 13 consists of a delay resistor R4 and a delay capacitor C2, and the reference switch Ms, the first power transistor M1, and the second power transistor M2 are all PMOS transistors forming a current mirror.

[0069] In this power supply system, the power signal AVDD is directly connected to the source of the reference switch Ms, the source of the first power transistor M1, and the source of the second power transistor M2. The drain of the first power transistor M1 is connected to the power supply terminal of the first circuit 3, and the drain of the second power transistor M2 is connected to the power supply terminal of the second circuit 2. This satisfies the different operating current requirements of the first circuit 3 and the second circuit 2 within the chip, while reducing the adverse effects of the second circuit 2 on the first circuit 3. One end of the delay resistor R3 and the delay capacitor C1 are connected to form the output terminal of the first delay circuit 11, and are connected to one end of the second logic OR2 and one input terminal of the first logic OR1. The other end of the delay resistor R3 is connected to the output terminal of the first comparator COMP1, and the other end of the delay capacitor C1 is grounded. One end of the delay resistor R4 and the delay capacitor C2 are connected to form the output terminal of the second delay circuit 13, and are connected to one end of the third logic OR3 and another input terminal of the first logic OR1. The other end of the delay resistor R4 is connected to the output terminal of the second comparator COMP2, and the other end of the delay capacitor C2 is grounded. The gate of the reference switching transistor Ms is directly grounded. The gate of the first power transistor M1 is connected to the output of the second logic OR2, and the gate of the second power transistor M2 is connected to the output of the third logic OR3. Therefore, the first power transistor M1 is indirectly controlled by the output of the first delay circuit 11, and the second power transistor M2 is indirectly controlled by the output of the second delay circuit 13.

[0070] Under normal operating conditions, the first comparator COMP1 and the second comparator COMP2 output zero node voltages (via the first delay circuit 11 and the second delay circuit 13, respectively). Therefore, the gate-source voltages of transistors M1, M2, and Ms are equal, forming a current mirror structure. The first comparator COMP1 detects the magnitude of the drain node voltages of transistors M1 and Ms, using the voltage-current formula of a MOS transistor. It can be seen that by setting appropriate aspect ratios for both M1 and Ms, that is, by setting the size ratio between M1 and Ms appropriately, the drain voltages of M1 and Ms will be the same (i.e., both are the reference reference voltages generated by the reference reference circuit 10) when the first supply current I1 is exactly the first current limit value (e.g., 50mA), that is, when the drain current of M1 equals the first current limit value. The drain voltage of Ms at this time will then be used as the switching voltage of comparator COMP1. For example, by selecting the value of Rs such that the operating current flowing through Ms (i.e., the first supply current I1, or the drain current of Ms) is 10μA, and simultaneously, the drain voltages of M1 and Ms are... S With a transistor size ratio of 5000:1, when the operating current of transistor M1 is less than 50mA, the drain voltage of transistor M1 is less than the drain voltage of transistor Ms, and the output of the first comparator COMP1 does not flip. When the operating current of transistor M1 is greater than 50mA, the output of the first comparator COMP1 flips, the gate voltage of transistor M1 goes high, transistor M1 is turned off, and the power supply to the first circuit 3 within the chip is cut off. During the operation of the internal circuitry, multiple signals may flip simultaneously, resulting in a momentary large current in the circuit, but the chip circuit is still operating normally. To shield the adverse effects of such or other momentary large current pulses on the operating logic of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D, the first delay circuit 11 connected to the output of the first comparator COMP1 ensures that the momentary large current does not cause a change in the gate voltage of transistor M1. Similarly, by adjusting the size ratio of transistors M2 and Ms, when the second supply current I2 is exactly at the second current limit value (e.g., 50mA), that is, when the drain current of transistor M2 equals the second current limit value, the drain voltages of transistors M2 and Ms are the same (i.e., both are the reference reference voltage generated by the reference reference circuit 10). This also controls the magnitude of the operating current of transistor M2 (i.e., the second current limit value) when the output of the second comparator COMP2 flips, using the drain voltage of transistor Ms at this time as the flip voltage of comparator COMP2. The second delay circuit 13 connected to the output of the second comparator COMP2 ensures that a large instantaneous current will not cause a change in the gate voltage of transistor M2.

[0071] In other words, the first power transistor M1, the second power transistor M2, and the reference switch transistor Ms constitute a current mirror structure. The first current limit value required by the first overcurrent detection module OCP_A is determined by the size ratio of the first power transistor M1 and the reference switch transistor Ms, and the second current limit value required by the second overcurrent detection module OCP_D is determined by the size ratio of the second power transistor M2 and the reference switch transistor Ms. Figure 6In the illustrated embodiment, the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D share the same reference circuit (composed of the reference switching tube Ms and the tail load Rs). The toggle voltages of the two comparators COMP1 and COMP2 can both be the drain voltage of Ms (that is, the same reference voltage). However, by setting different size ratios of the first power tube M1 and the second power tube M2 to the reference switching tube Ms respectively, different first and second current limiting values can be achieved. For example: when the drain current of the first power tube M1 (the first supply current I1) is normal, the drain voltage of M1 > the drain voltage of Ms; when the drain current of the first power tube M1 (the first supply current) is overcurrent (greater than the first current limiting value), the drain voltage of M1 is pulled down < the drain voltage of Ms, and the comparator COMP1 toggles accordingly. When the drain current of the second power tube M2 (the second supply current I2) is normal, the drain voltage of M2 > the drain voltage of Ms; when the drain current of the second power tube M2 (the second supply current I2) is overcurrent (greater than the second current limiting value), the drain voltage of M2 is pulled down < the drain voltage of Ms, and the comparator COMP2 toggles accordingly.

[0072] The first and second delay circuits 11 and 13 are detailed here. As mentioned above, the first delay circuit 11 in the first overcurrent detection module OCP_A includes a resistor R3 and a capacitor C1, which is configured to keep the output signal AOCP of the first overcurrent detection module OCP_A unchanged when the first supply current I1 is greater than the first current limiting value but does not exceed the first preset duration, that is, keep the gate voltage of the first power tube M1 unchanged. Specifically, when COMP1 toggles to pull high, since the resistor R3 and the capacitor C1 can slow down the voltage climbing speed of the output signal AOCP, the voltage of the output signal AOCP has not reached the threshold for the second OR logic OR1 to toggle, and the load current I1 recovers to be less than the first current limiting value, so that the comparator COMP1 toggles again to pull low. As a result, neither the output signal AOCP nor the second OR logic OR2 toggles. The second delay circuit 13 in the second overcurrent detection module OCP_D includes a resistor R4 and a capacitor C2, which is configured to keep the output signal DOCP of the second overcurrent detection module OCP_D unchanged when the second supply current I2 is greater than the second current limiting value but does not exceed the second preset duration, that is, keep the gate voltage of the second power tube M2 unchanged. Specifically, when COMP2 toggles to pull high, since the resistor R4 and the capacitor C2 can slow down the voltage climbing speed of the output signal DOCP, the voltage of the output signal DOCP has not reached the threshold for the third OR logic OR3 to toggle, and the load current I2 recovers to be less than the second current limiting value, so that the comparator COMP2 toggles again to pull low. As a result, it can be considered that neither the output signal DOCP nor the third OR logic OR3 toggles. In summary, one or both of the first delay circuit 11 and the second delay circuit 13 can be RC delay circuits. The following Figure 7The second delay circuit 13 is used as an example for illustration.

[0073] Figure 7 This is the timing diagram of the second circuit 2 in the power supply system of this embodiment. Please refer to... Figures 2 to 7 As shown, when a short-term pulse current occurs in the second power supply current I2 provided by the second power transistor M2, the second overcurrent detection module OCP_D internally uses the second delay circuit 13 to shield the influence of the instantaneous large current pulse on the working logic of the second overcurrent detection module OCP_D. That is, it can maintain the DOCP output of the second overcurrent detection module OCP_D at low, so that the short-term pulse large current will not cause a change in the gate voltage of the second power transistor M2. When the current recovers, the circuit state returns to its original state, and the interrupt module IRQ PAD will not pull up the interrupt pin INT of the control unit 4. When the second power supply current I2 experiences a large current exceeding the second preset duration (greater than the second current limit value), the DOCP output of the second overcurrent detection module OCP_D goes high, which will pull up the gate voltage of the second power transistor M2, turn off the M2 transistor, disconnect the power supply to the second circuit 3, and the interrupt module IRQ PAD will pull up the interrupt pin INT of the control unit 4, so that the control unit 4 detects the overcurrent protection state of the chip.

[0074] It should be understood that the above Figure 6 The circuit design and data examples described above are merely illustrative of the present invention. In other embodiments of the present invention, different design values ​​(e.g., different first current limiting values) can be achieved by adjusting the device parameters of the electronic components in the circuit, and the input polarity of the first comparator and the second comparator can also be interchanged. Furthermore, Figures 1 to 6 The diagram only shows the most important circuit components of power supply system 1, but this does not mean that the power supply system of the present invention only has these circuits. In other embodiments of the present invention, the circuits of the power supply system can be added or removed according to actual needs. For example, in another embodiment of the power supply system of the present invention, the first delay circuit 11 and / or the second delay circuit 13 are omitted; or, for example, please refer to... Figure 8In another embodiment of the power supply system of the present invention, a first resistor R1 and / or a second resistor R2 are added. One end of the first resistor R1 is connected to the power signal AVDD, and the other end of the first resistor R1 is connected to the power supply terminal of the first overcurrent detection module OCP_A. One end of the second resistor R2 is connected to the power signal AVDD, and the other end of the second resistor R2 is connected to the power supply terminal of the second overcurrent detection module OCP_D. This prevents static electricity from damaging the first circuit 3 and the second circuit 2 through the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D, respectively. On the other hand, the power supplies of the first overcurrent detection module OCP_A and the second overcurrent detection module OCP_D are also independent. This ensures that when the first power transistor M1 is turned off, the first overcurrent detection module OCP_A continues to operate. Moreover, since the first supply current I1 is 0, the first comparator COMP1 in the first overcurrent detection module OCP_A will not flip back to turn on the first power transistor M1 again when the control unit 4 does not send the start / stop control signal shutdown. Similarly, when the second power transistor M2 is turned off, the second overcurrent detection module OCP_D continues to operate. However, since the second supply current I2 is 0, the second comparator COMP2 in the second overcurrent detection module OCP_D will not flip back to turn on the second power transistor M2 again when the control unit 4 does not send the start / stop control signal shutdown.

[0075] Based on the same inventive concept, please refer to Figures 1 to 8 The present invention also provides a chip, which includes a first circuit 3, a second circuit 2 and a power supply system 1 as described in the present invention. The power supply system 1 supplies power to the first circuit 3 and the second circuit 2 respectively through the same power signal AVDD, and the power supply system 1 provides a first power supply current I1 to the first circuit 3 and a second power supply current I2 to the second circuit 2.

[0076] Optionally, the first circuit 3, the second circuit 2, and the power supply system 1 are all coupled to the control unit 4. When the first supply current I1 exceeds the first current limit or the second supply current I2 exceeds the second current limit, the power supply system 1 sends an interrupt signal INT to the control unit 4. After a certain period of time (the length of which is determined by the control unit 4), the power supply system 1 receives the start / stop control signal shutdown from the control unit 4 and further controls the first power transistor M1 or the second power transistor M2 to turn on again. If the overcurrent still occurs, the overcurrent protection is triggered again to turn off the first power transistor M1 or the second power transistor M2, and the power supply system 1 will send the interrupt signal INT to the control unit 4 again. If the interrupt signal received by the control unit 4 at a fixed time interval exceeds the threshold, the control unit 4 considers the chip to be faulty and will not send the start / stop control signal shutdown.

[0077] Optionally, the chip is a functional chip such as a fingerprint chip, and the control unit 4 is a controller chip independent of the fingerprint chip. In other embodiments of the present invention, the control unit 4 may be a control circuit integrated within the chip.

[0078] Optionally, the chip is a fingerprint chip (e.g., a side fingerprint chip). The first circuit 3 includes a fingerprint pixel array 31, a fingerprint signal acquisition circuit 32, a signal amplification circuit (e.g., PGA) 33, and an analog-to-digital converter 34 connected in sequence. The second circuit 2 includes a filter circuit 21 and a digital signal processing circuit 22. The digital signal processing circuit 22 is used to process the fingerprint information acquired by the first circuit 3 and output a fingerprint image. It can be seen that the analog circuit part (first circuit 3) and the digital circuit part (second circuit 2) in the fingerprint chip 1 of this embodiment can be powered by the same power supply signal AVDD. Different operating voltages can be achieved through internal components such as a low dropout linear regulator (LDO) (not shown), and power supply and overcurrent protection (OCP) are respectively achieved through the first power transistor M1 and the second power transistor M2.

[0079] In summary, the power supply system and chip provided by this invention do not cause voltage margin loss to the chip. Furthermore, it utilizes a first power transistor and a first overcurrent detection module to form a power supply protection branch for powering and detecting overcurrent in the first circuit within the chip, and a second power transistor and a second overcurrent detection module to form another power supply protection branch for powering and detecting overcurrent in the second circuit within the chip. This achieves separate overcurrent detection and protection for the first and second circuits within the chip, which are powered by the same power signal. Overcurrent protection can be provided when an overcurrent occurs in either the first or second circuit's power supply branch, reducing the false alarm rate of the chip's overcurrent protection. Simultaneously, since the two power supply branches share the same external power signal, there are fewer constraints on the power supply voltage, making it applicable to chips operating in various voltage domains. Furthermore, when the first overcurrent detection module and the second overcurrent detection module share the same reference circuit, the first power transistor, the second power transistor, and the reference switch in the same reference circuit can form a current mirror structure. By rationally setting the size ratio of the first power transistor, the second power transistor, and the reference switch in the same reference circuit, a balance can be achieved between circuit power consumption and overcurrent protection speed, further reducing power consumption and allowing the chip's operating voltage range to reach a lower level. When the technical solution of this invention is applied to fingerprint chips (especially side-mounted fingerprint chips), it can avoid the problem of the fingerprint chip overheating and exceeding its temperature due to prolonged large short-circuit current, thus protecting user safety.

[0080] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A power supply system, characterized in that, The power supply system is used to supply power to a first circuit and a second circuit of a chip respectively via the same power signal, the power supply system comprising: The first power transistor is coupled between the power signal and the power supply terminal of the first circuit. The first overcurrent detection module is connected to the control terminal of the first power transistor and is used to detect the first power supply current provided by the first power transistor to the first circuit. When the first power supply current exceeds the first current limit value, the first power transistor is turned off to stop the power supply signal from supplying power to the power terminal of the first circuit. The second power transistor is coupled between the power signal and the power supply terminal of the second circuit. The second overcurrent detection module is connected to the control terminal of the second power transistor and is used to detect the second power supply current provided by the second power transistor to the second circuit. When the second power supply current exceeds the second current limit value, the second power transistor is turned off to stop the power supply signal from supplying power to the power terminal of the second circuit. The first OR logic has two input terminals connected one-to-one to the output terminals of the first overcurrent detection module and the second overcurrent detection module, respectively, and the output terminal of the first OR logic is connected to the interrupt pin of the control unit. The first OR logic is used to send an interrupt signal to the control unit through the interrupt pin when the first power supply current exceeds the first current limit value or the second power supply current exceeds the second current limit value, and further enables the control unit to control the first power transistor or the second power transistor to turn on again after detecting the interrupt signal for a period of time. The first circuit has a low-power module, and the power supply system has an interrupt module. The power supply terminal of the low-power module is directly connected to the power signal. The interrupt module is connected to the output terminal of the first OR logic, the interrupt pin of the control unit, and the output terminal of the low-power module. The low-power module is used to supply power to the interrupt module when the first power transistor is turned off, so that the signal output by the interrupt module can be effectively sent to the control unit.

2. The power supply system as described in claim 1, characterized in that, The power supply system also has a signal input / output module, which is connected between the output terminal of the low-power module and the input / output pin of the control unit. The low-power module is also used to supply power to the signal input / output module when the first power transistor is turned off, so that the signal output by the signal input / output module can be effectively sent to the control unit.

3. The power supply system as described in claim 1, characterized in that, The first overcurrent detection module has a first comparator and a first reference circuit. One input terminal of the first comparator is connected to the connection node between the first power transistor and the power supply terminal of the first circuit, and the other input terminal of the first comparator is connected to the output terminal of the first reference circuit. The second overcurrent detection module has a second comparator and a second reference circuit. One input terminal of the second comparator is connected to the connection node between the second power transistor and the power supply terminal of the second circuit, and the other input terminal of the second comparator is connected to the output terminal of the second reference circuit. Wherein, the first reference circuit and the second reference circuit are two electrically separated circuits. The first reference circuit is used to generate a first reference voltage according to the first current limit value, and the second reference circuit is used to generate a second reference voltage according to the second current limit value; or, the first reference circuit and the second reference circuit are the same reference circuit, and the same reference circuit generates a reference voltage according to the first current limit value and the second current limit value.

4. The power supply system as described in claim 3, characterized in that, The first reference circuit, the second reference circuit, or the same reference circuit each include a coupled reference switch and a tail load, and the control terminal of the reference switch and the other end of the tail load are both grounded.

5. The power supply system as described in claim 4, characterized in that, The tail load is either a tail current source or a tail resistor.

6. The power supply system as described in claim 4, characterized in that, The first power transistor, the second power transistor, and the reference switch transistor constitute a current mirror structure. The first current limiting value of the first overcurrent detection module is determined by the size ratio of the first power transistor and the reference switch transistor, and the second current limiting value of the second overcurrent detection module is determined by the size ratio of the second power transistor and the reference switch transistor.

7. The power supply system as described in claim 6, characterized in that, When the first overcurrent detection module and the second overcurrent detection module share the same reference circuit, the size ratio of the first power transistor and the reference switch transistor is such that when the drain current of the first power transistor is equal to the first current limit value, the drain voltage of the first power transistor and the reference switch transistor are equal to and equal to the reference voltage. The size ratio of the second power transistor and the reference switch transistor is such that when the drain current of the second power transistor is equal to the second current limit value, the drain voltage of the second power transistor and the reference switch transistor are equal to and equal to the reference voltage. Here, the drain current of the first power transistor is the first supply current, and the drain current of the second power transistor is the second supply current.

8. The power supply system as described in any one of claims 3-7, characterized in that, The first overcurrent detection module further includes a first delay circuit, which is coupled between the output terminal of the first comparator and the control terminal of the first power transistor, and is used to keep the voltage at the control terminal of the first power transistor unchanged when the first supply current is greater than the first current limit value but does not exceed the first preset duration. And / or, the second overcurrent detection module further includes a second delay circuit, which is coupled between the output terminal of the second comparator and the control terminal of the second power transistor, for maintaining the voltage at the control terminal of the second power transistor unchanged when the second supply current is greater than the second current limit value but does not exceed the second preset duration.

9. The power supply system as described in claim 8, characterized in that, The first delay circuit is an RC delay circuit, and / or the second delay circuit is an RC delay circuit.

10. The power supply system as described in claim 8, characterized in that, The first overcurrent detection module further includes a second OR logic. One input of the second OR logic is connected to the output of the first delay circuit, and the other input of the second OR logic is connected to the start / stop control signal issued by the control unit. The second OR logic is used to control the first power transistor to turn on or off according to the start / stop control signal or the output of the first delay circuit. And / or, the second overcurrent detection module further includes a third OR logic, one input of which is connected to the output of the second delay circuit, and the other input of which is connected to the start / stop control signal. The third OR logic is used to control the second power transistor to turn on or off according to the start / stop control signal or the output of the second delay circuit.

11. The power supply system as described in any one of claims 1-7, characterized in that, The power supply system also has a first resistor, one end of which is connected to the power signal, and the other end of which is connected to the power supply terminal of the first overcurrent detection module. And / or, the power supply system further includes a second resistor, one end of which is connected to the power signal, and the other end of which is connected to the power supply terminal of the second overcurrent detection module.

12. A chip, characterized in that, The system includes a first circuit, a second circuit, and a power supply system as described in any one of claims 1 to 11, wherein the power supply system supplies power to the first circuit and the second circuit respectively through the same power signal, and the power supply system provides a first power supply current to the first circuit and a second power supply current to the second circuit.

13. The chip as described in claim 12, characterized in that, The first circuit, the second circuit, and the power supply system are all coupled to the control unit. When the first power supply current exceeds the first current limit or the second power supply current exceeds the second current limit, the power supply system sends an interrupt signal to the control unit. After a period of time, the power supply system receives a start-stop control signal from the control unit and further controls the corresponding first power transistor or second power transistor to turn on again. If the interrupt signal received at a fixed time interval exceeds a threshold, the control unit will not send the start-stop control signal.

14. The chip as described in claim 12 or 13, characterized in that, The chip is a fingerprint chip. The first circuit includes a fingerprint pixel array, a fingerprint signal acquisition circuit, a signal amplification circuit, and an analog-to-digital converter connected in sequence. The second circuit includes a filtering circuit and a digital signal processing circuit. The digital signal processing circuit is used to output the image of the fingerprint acquired by the first circuit.

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