Periodic reverse current limiting in acf converters

Abstract

The present disclosure relates to cycle-by-cycle reverse current limiting in ACF converters. In one embodiment, a method for operating an ACF converter includes turning on a low-side transistor coupled between a primary winding of a transformer and a reference terminal to cause forward current into the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor coupled between the primary winding and a clamp capacitor to cause reverse current to flow through the primary winding; and after turning on the high-side transistor, keeping the high-side transistor on for a first time period when overcurrent of the reverse current is not detected, and turning off the high-side transistor after the first time period, and turning off the high-side transistor without keeping the high-side transistor on for the first time period when overcurrent of the reverse current is detected.

Description

Technical Field

[0001] This disclosure generally relates to an electronic system and method, and in specific embodiments relates to cycle-by-cycle reverse current limiting in an active clamp flyback (ACF) converter. Background Technology

[0002] Switching converters have various topologies, including buck, boost, buck-boost, and flyback converters. Figure 1 A schematic diagram of an exemplary flyback converter 100 is shown. The flyback converter 100 includes a transformer 112, a resistor 104, capacitors 106 and 114, diodes 108 and 116, a transistor 102, and a primary controller 110.

[0003] During normal operation, the primary controller 110 turns transistor 102 on and off in a known manner to allow a primary current Ip to flow through the primary winding 112a. The primary current Ip induces a secondary current Is to flow through the secondary winding 112b. Diode 116 cooperates with output capacitor 114 to operate as a rectifier, such that the output voltage Vout is a DC voltage (e.g., with superimposed ripple).

[0004] The topology of flyback converter 100 is also referred to as an RCD-clamped flyback converter because converter 100 includes an RCD clamping circuit (formed by components 104, 106, and 108). The purpose of this RCD clamping circuit is to dissipate the energy taken from the input source and stored in the primary winding during each switching cycle, which is not transferred to the secondary winding due to imperfect coupling between them. This unused energy is often referred to as "leakage inductance energy" because it is assumed to be stored in a portion of the primary inductance, which is not coupled to the secondary inductance, called the leakage inductance. RCD-clamped flyback converters are generally simple and inexpensive circuits.

[0005] Figure 2 A schematic diagram of an exemplary flyback converter 200 is shown. The flyback converter 200 operates in a similar manner to the flyback converter 100. However, the flyback converter 200 replaces the RCD clamp of the converter 100 with an active clamp formed by transistor 208 and capacitor 106. Therefore, the topology of the flyback converter 200 is also referred to as an active clamp flyback (ACF) converter.

[0006] The advantages of ACF converters include the recycling of leakage inductor energy to achieve soft switching (ZVS) of transistors 208 and 102, high efficiency (e.g., greater than 93%) that can be achieved with high switching frequencies (e.g., above 200 kHz), and smooth waveforms that result in low EMI. Summary of the Invention

[0007] According to one embodiment, a method for operating an active clamp flyback (ACF) converter includes: turning on a low-side transistor coupled between a first terminal and a reference terminal of a primary winding of a transformer, such that a forward current enters the primary winding via a second terminal and exits the primary winding via the first terminal; turning off the low-side transistor after turning it on; turning on a high-side transistor coupled between the first terminal of the primary winding and a first terminal of a clamping capacitor after turning off the low-side transistor, such that a reverse current flows through the primary winding, wherein a second terminal of the clamping capacitor is coupled to a second terminal of the primary winding, and wherein the reverse current has a direction opposite to the forward current; and after turning on the high-side transistor, keeping the high-side transistor on for a first time period when no overcurrent of reverse current is detected, and turning off the high-side transistor after the first time period, and turning off the high-side transistor without keeping it on for the first time period when an overcurrent of reverse current is detected.

[0008] According to one embodiment, an active clamp flyback (ACF) converter includes: a transformer including a primary winding and a secondary winding; a low-side transistor having a current path coupled between a first terminal and a reference terminal of the primary winding; a clamping capacitor coupled to a second terminal of the primary winding; a high-side transistor having a current path coupled between the first terminal of the primary winding and the clamping capacitor; a current sensor configured to sense a reverse current flowing through the clamping capacitor, the reverse current having a direction from the clamping capacitor to the first terminal of the primary winding; and a primary controller configured to: turn on the low-side transistor to allow forward current to flow through the primary winding. The second terminal of the winding enters the primary winding and exits the primary winding via the first terminal of the primary winding. After the low-side transistor is turned on, the low-side transistor is turned off. After the low-side transistor is turned off, the high-side transistor is turned on, allowing reverse current to flow through the primary winding. After the high-side transistor is turned on, the presence of reverse current overcurrent is detected based on the output of the current sensor. When no reverse current overcurrent is detected, the high-side transistor is kept on for a first time period and then turned off after the first time period. When reverse current overcurrent is detected, the high-side transistor is turned off without keeping it on for the first time period.

[0009] According to one embodiment, an integrated circuit includes: a reference terminal configured to receive a reference voltage; a voltage sensing terminal configured to be coupled to a clamping capacitor via a sensing capacitor and to the reference terminal via a sensing resistor; a first control terminal configured to be coupled to a control terminal of a high-side transistor having a current path coupled between the voltage sensing terminal and a first terminal of a primary winding of a transformer; a second control terminal configured to be coupled to a control terminal of a low-side transistor having a first current path terminal coupled to the current path of the high-side transistor; a comparator having a first input configured to receive a threshold voltage, a second input coupled to the voltage sensing terminal, and an output configured to provide an overcurrent detection signal; and a primary control... The device is configured to: turn on the low-side transistor to allow forward current to enter the primary winding via the second terminal of the primary winding and exit the primary winding via the first terminal of the primary winding; turn off the low-side transistor after turning on the low-side transistor; turn on the high-side transistor after turning off the low-side transistor to allow reverse current to flow through the primary winding, the reverse current having the opposite direction to the forward current; and after turning on the high-side transistor, detect the presence of overcurrent based on an overcurrent detection signal; when the overcurrent detection signal is deasserted, keep the high-side transistor on for a first time period, and turn off the high-side transistor after the first time period; and when the overcurrent detection signal is asserted, turn off the high-side transistor without keeping it on for the first time period. Attached Figure Description

[0010] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 and Figure 2 A schematic diagram of an exemplary flyback converter is shown;

[0012] Figure 3A and Figure 3B It shows the relationship with Figure 2 The flyback converter operation is an example waveform associated with the complementary ACF converter;

[0013] Figure 4A and Figure 4B It shows the relationship with Figure 2 The flyback converter operation is an example waveform associated with a non-complementary ACF converter;

[0014] Figure 5A A schematic diagram of an exemplary ACF converter that can be driven as a non-complementary ACF converter is shown.

[0015] Figure 5B The operation is shown Figure 5AA flowchart of an exemplary method for an ACF converter;

[0016] Figure 5C It shows the relationship with during steady state. Figure 5A An example waveform associated with the ACF converter;

[0017] Figure 5D It shows the interaction with during startup. Figure 5A An example waveform associated with the ACF converter;

[0018] Figure 5E It shows Figure 5A A schematic diagram of an ACF converter, which shows Figure 5A A model of the ACF converter;

[0019] Figure 5F and Figure 5G The following are shown respectively during short-circuit conditions and negative output transition. Figure 5A The waveform associated with the ACF converter;

[0020] Figure 6 A flowchart of an embodiment of a method for operating a non-complementary ACF converter according to an embodiment of the present invention is shown;

[0021] Figure 7 An ACF converter according to an embodiment of the present invention is shown;

[0022] Figure 8 An embodiment of the invention is shown with Figure 7 The waveform associated with ACF;

[0023] Figure 9A , Figure 9B and Figure 10 An embodiment of the invention is shown, and its implementation is illustrated. Figure 6 The method Figure 7 The waveform associated with the ACF converter;

[0024] Figure 11 A flowchart illustrating an embodiment of a method for operating a non-complementary ACF converter according to an embodiment of the present invention is shown; and

[0025] Figure 12 An ACF converter according to an embodiment of the present invention is shown.

[0026] Unless otherwise stated, the numbers and symbols corresponding in the different figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Detailed Implementation

[0027] The manufacture and use of the disclosed embodiments will now be discussed in detail. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0028] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. Embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer precisely to the same embodiment. Furthermore, in one or more embodiments, specific constructions, structures, or features may be combined in any suitable manner.

[0029] Embodiments of the invention will be described in a specific context, such as an ACF converter operating as a non-complementary ACF converter with cycle-by-cycle reverse current limiting, for applications such as USB-PD Type-C. Embodiments of the invention can be used in other types of applications.

[0030] In one embodiment of the invention, when an overcurrent event is detected in such a reverse current, the reverse current flowing through the high-side transistor of the ACF converter, which operates as a non-complementary ACF converter, is limited on a cycle-by-cycle basis. In some embodiments, the reverse current is limited by early turn-off of the high-side transistor of the ACF converter. In some embodiments, when the high-side transistor is turned off early, the typical dead time between turning off the high-side transistor and turning on the low-side transistor is shortened (e.g., to a minimum dead time) to limit the drain-source voltage of the low-side transistor when it is turned on.

[0031] In some embodiments, overcurrent events in the reverse current are detected by monitoring the current flowing through the high-side transistor of the ACF converter. In some embodiments, the current sensor includes a sensing capacitor dynamically connected in parallel with the clamping capacitor of the ACF converter.

[0032] In some embodiments, overcurrent events in the reverse current are caused by a short-circuit condition or by a negative output transition of the ACF converter. In some embodiments, during an overcurrent event caused by a short-circuit condition, a soft-start function is activated to limit the current peak when the low-side transistor is turned on.

[0033] The ACF converter 200 can operate as a complementary ACF converter or as a non-complementary ACF converter. Figure 3A and Figure 3B An exemplary waveform is shown that is associated with the operating converter 200 as a complementary ACF converter.

[0034] like Figure 3A As shown, the signals V that drive transistors 102 and 108 respectively G_102 and V G_208 They are turned on and off in a complementary manner. Therefore, when transistor 208 is off, transistor 102 is on, and vice versa. Figure 3B As shown, when voltage V1 is high (when transistor 102 is off and transistor 208 is on), the primary current Ip and secondary current Is have a sinusoidal shape. When voltage V1 is low (when low-side transistor 102 is on and high-side transistor 208 is off), the primary current Ip has a linear shape, while the secondary current Is is zero.

[0035] Figure 4A and Figure 4B An exemplary waveform is shown associated with the operating converter 200 as a non-complementary ACF converter. For example... Figure 4A and Figure 4B As shown, after the secondary current has been demagnetized for a period of time, transistor 208 turns on to allow the primary current Ip to increase sufficiently to achieve soft switching. Therefore, the primary and secondary sides of the ACF converter 200 are simultaneously turned on.

[0036] In a non-complementary manner (e.g., as Figure 4A and Figure 4B Some advantages of embodiments of the ACF converter (e.g., 200) shown include lower RMS current in the primary-side cycle, lower power loss, higher efficiency, and a wide, easily manageable input voltage V. in and wide output voltage V out This range of applications could be particularly advantageous for applications such as USB Power Delivery (USB-PD).

[0037] like Figure 4B As shown, in time period t B During the current bump period (also known as the current bump time period), the secondary current Is is conducting with a positive current, while the primary current Ip is conducting with a reverse (negative) current. Although Figure 4 shows the secondary current Ip as the current bump time period t... B The current is a straight line during the period, but the current Is may have other shapes, such as during the current bump time period t. B The parabolic or sine shape during the period.

[0038] Figure 5AA schematic diagram of an exemplary ACF converter 500 is shown. The ACF 500 includes a transformer 512, a feedback circuit 530, a clamping capacitor 506, a transistor 502, a primary controller 510, a current sensor 526, and an error amplifier 528. The feedback circuit 530 includes a primary section 530a and a secondary section 530b. The ACF converter 500 can operate as a non-complementary ACF converter.

[0039] The feedback circuit 530 can be implemented in any manner known in the art, for example by using an optocoupler.

[0040] Error amplifier 528 can be implemented in any manner known in the art and may include, for example, frequency compensation and an amplification gain that may be greater than, equal to, or less than 1. Although error amplifier 528 is shown on the primary side, it can be implemented on the secondary side. For example, a portion 530b of feedback circuit 530 may include error amplifier 528, and the error signal V err For example, an optical coupler can be used to transmit data to the primary controller 510.

[0041] The load 532 can be, for example, a switch or a linear voltage or current regulator; other loads are also possible.

[0042] The current sensor 526 is configured to sense the current I flowing through the transistor 502. 502 The current sensor 526 can be implemented in any manner known in the art. For example, in some embodiments, the current sensor 526 may be based on the drain-source voltage V. DS_502 Determine the current I 502 Other implementations are also possible.

[0043] Transistors 502 and 508 can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Other transistor types, such as GaN transistors, can also be used.

[0044] During non-complementary operation, the primary controller 510 is configured to operate based on the error voltage V. err Transistors 502 and 508 are turned on and off to regulate the output voltage V. out For example, in some embodiments, the time that transistor 502 remains on can be based on the error voltage V. err .

[0045] The primary controller 510 is also configured to introduce a dead time t between the turn-off of transistor 508 and the turn-on of transistor 502. d So that the drain-source voltage V of transistor 502 is increased. DS_502Swinging down to zero achieves zero-voltage switching (ZVS), also known as soft-switching. Dead time t d It can be, for example, 300ns. Other values ​​can also be used.

[0046] Figure 5B A flowchart of an exemplary method 550 for operating an ACF converter 500 is shown. Figure 5C An exemplary waveform associated with the ACF converter 500 during steady state is shown. Method 550 can be implemented by the primary controller 510. Figure 5B and Figure 5C We can understand them together.

[0047] During step 552, the primary controller 510 turns on the low-side transistor 502 to charge the primary current Ip (to cause an increase in the primary current Ip), as... Figure 5C The time period t charge As shown.

[0048] Once the primary current Ip reaches a predetermined threshold, the primary controller 510 turns off the low-side transistor during step 554 to cause an increase in the secondary current Is. Therefore, the secondary current increases for a period of time and then begins to decrease. Once it is determined that the secondary current Is has decreased to 0A (step 556), the primary controller 510 turns on the high-side transistor 508 (during step 558) to allow reverse current (-Ip). clamp ) flows through the primary winding 512a (in time period t) B The beginning, such as Figure 5C (As shown).

[0049] During step 560, the high-side transistor 508 remains on to allow the reverse current to increase, such as Figure 5C Current bump time period t B As shown. Once the reverse current has increased sufficiently (e.g., reached a predetermined threshold, or by directly controlling the on-time of the high-side transistor 508), the high-side transistor 508 is turned off during step 562. In some embodiments, for example when the voltage V in or V out When the change occurs, the time period during which the high-side transistor 508 remains on changes during step 560.

[0050] During step 564, controller 510 waits for the dead time period t. d To allow the current Ip to cause the voltage V DS_502 The descent allows for ZVS. During the dead time t d After the sequence has passed, during step 552, the low-side transistor 502 is turned on again, and the sequence is repeated.

[0051] like Figure 5C As shown, during steady-state conditions (e.g., when power is supplied to a load), a dead time t is introduced between the turn-off of transistor 508 and the turn-on of transistor 502. d For example Figure 5C As shown, when transistor 502 is turned on, the voltage V DS_502 It is already at or essentially at 0V.

[0052] The primary controller 510 can also be configured to perform a soft start during the startup of the ACF converter 500. For example, during startup, capacitor 114 can be fully discharged, and initial stresses can be induced, such as those similar to a short-circuit condition. Under these conditions, the ACF converter 500 can provide maximum current to generate the output voltage V. out To prevent high spikes in the secondary current Is that could cause corresponding spikes in the primary current Ip, the power capability of the ACF converter 500 is initially limited and gradually increased from a predefined minimum to its full range. This power limiting function, also known as the soft-start function, results in a decrease in the output voltage V. out Increases slowly, for example, linearly. Figure 5D An exemplary waveform associated with the ACF converter 500 during startup is shown.

[0053] like Figure 5D As shown, the output voltage V out It increases slowly during startup. As the output voltage V... out Increase the overcurrent limit I used to limit the current flowing through transistor 502. OCP_502 For example, it can be increased in a step-by-step manner.

[0054] Error voltage V err It can be the maximum voltage V err_max and minimum voltage V err_min The voltage between. The primary controller 510 can use the error voltage V. err To determine when to turn off the low-side transistor 502 (e.g., to turn off the output voltage V). out Adjust to the target output voltage). As a non-limiting example, the voltage V err_max and V err_min These can be, for example, 3V and 1V respectively.

[0055] like Figure 5D As shown, the error voltage V err Initially, it is saturated (e.g., high) because the output voltage is significantly lower than the target output voltage (20V in the example shown). At time t1, once the output voltage V... out Approximate target output voltage, error voltage V errExit saturation and the primary controller 510 enters adjustment mode.

[0056] Figure 5E A schematic diagram of an ACF converter 500 is shown, illustrating, for example, the current bump time period t. B The model used during this period was for transformer 512. For example... Figure 5E As shown, transformer 512 can be modeled using leakage inductance 512c, magnetizing inductance 512d, and an ideal n:1 transformer (including ideal windings 512e and 512b).

[0057] like Figure 5E As shown, the secondary current Is can be given by the following formula.

[0058] I s (t)=-n·I 512e =-n·[I p -I m (1)

[0059] Where n is the turns ratio of transformer 512, I 512e (Also known as the positive component of the primary current Ip) represents the current flowing through the ideal winding 512e, and the magnetizing current Im represents the current flowing through the magnetizing inductor 512d. The magnetizing current Im may be responsible for enabling ZVS, for example, as... Figure 5C As shown.

[0060] During the current bump time period t B During this period, transistor 508 is turned on, transistor 502 is turned off, transformer 512 operates in forward mode as the actual transformer, and diode 116 is turned on, resulting in voltage V 512d For example, it can be fixed, and the voltage can be given by the following formula.

[0061] V 512d =-V out ·n (2)

[0062] Therefore, during the current bump time period t B During this period, the magnetizing current Im can be given by the following formula.

[0063]

[0064] Where L 512d It is the inductance of the magnetizing inductor 512d (also called the magnetizing inductance of transformer 512). As shown in Equation 3, the magnetizing current Im can be a linear ramp.

[0065] During the current bump time period t B During this period, the primary current Ip can be given by the following formula.

[0066]

[0067] Where V clamp_0 This represents the voltage V across capacitor 506 at the beginning of each switching cycle (e.g., at the instant the high-side transistor 508 is turned on). clamp w 512 The frequency of the sinusoidal component of the primary current Ip can be given by the following formula.

[0068]

[0069] Z 512 The characteristic impedance of the system can be expressed by the following formula.

[0070]

[0071] As shown in Equation 4, during the current bump time period, the primary current Ip has a linear component (Im) and a sinusoidal component (Im). 512e ), and so on Figure 5C As shown.

[0072] As shown in Equations 5 and 6, capacitor 506 resonates with leakage inductor 512c. As shown in Equations 5 and 6, due to voltage V... 512 During the current bump time period t B The period is fixed, so inductor 512d may not function in resonance. For example, windings 512e and 512b can be understood as a coupled circuit, where the voltage across 512 is equal to the voltage across 512e divided by n, and the current flowing through 512b is equal to the current flowing through 512e multiplied by n.

[0073] As a non-limiting example, typical value ranges for components of the ACF converter 500 include inductance L in the low μH range (e.g., 1 μH to 10 μH). 512c And capacitance C in the range of tens or hundreds of nF (e.g., 10 nF to 470 nF). 506 This could result in an impedance Z in the range of several Ω. 512 .

[0074] As shown in Equations 1 and 4, during the current bump time period, the current I 512e The maximum amplitude of Is can be compared with V 506_0 -V 512d Proportional. Under steady-state conditions, the voltage V... clamp_o It may be only slightly higher than the voltage V. 512d Therefore, during steady-state conditions, the positive component I of the primary current Ip... 512e (And the corresponding current bumps in the secondary current Is) can be relatively restricted.

[0075] The inventors recognized that during a short circuit, the output voltage V out The voltage V drops, which causes the voltage V to decrease. 512d The corresponding decrease (e.g., to 0V or essentially 0V) results in a difference V. clamp_0 -V 512d (And equivalently, the difference:) The increase in voltage V leads to a substantial increase in the primary current Ip. This is because during short-circuit conditions, the voltage V... 512d The voltage drops significantly (e.g., to 0V or essentially 0V), so the magnetizing current Im also drops significantly (e.g., to 0A), causing the magnitude of the secondary current Is to exhibit a larger current increase than the primary current Ip (because the term Im becomes negligible or very small in Equation 1). During short-circuit conditions, the peak values ​​of currents Ip and Is can be significantly higher than during steady-state conditions, for example, 8 to 10 times higher.

[0076] The inventors also realized that in ACF converters with variable output voltages (e.g., for USB-PD), negative output transitions (e.g., from 20V to 5V) can also cause current spikes in the primary current Ip and secondary current Is. For example, during a negative output transition (e.g., changing the target output voltage from 20V to 5V), the ACF converter 500 can stop switching until the output voltage V... out The target output voltage is reached. When the switch of transistor 508 is restarted, the voltage V... clamp It can be compared to voltage V 512d Much higher (because the voltage V is higher when the switch is restarted). 512d It has a value corresponding to the new output voltage (e.g., 5V), and the voltage V clamp (It has a value corresponding to the previous higher voltage (e.g., 20V). Although less noticeable than during short-circuit conditions, current spikes in the primary and secondary currents (Ip and Is) may occur when the switch is restarted after a negative output transition.

[0077] Figure 5F and Figure 5G The waveforms associated with the ACF converter 500 during short-circuit conditions and negative output transitions are shown respectively.

[0078] like Figure 5F As shown, a short-circuit condition is applied at time t2. After the short-circuit condition is applied at time t2, the peak current amplitudes of the primary current Ip and the secondary current Is increase until they reach their maximum values ​​of approximately -15A and approximately 60A, respectively, at time t3 (compared to approximately -3.5A and approximately 10A during the steady state period).

[0079] like Figure 5GAs shown, a negative output transition from 20V to 5V is applied at time t4. For example, this negative output transition might occur as a result of unplugging a laptop computer from a USB connector implementing USB-PD (e.g., while charging at 20V). When the laptop computer is disconnected, a discharge circuit (not shown) causes the output voltage V to... out Discharge (e.g., within 100 milliseconds). In such a discharge time t... discharge During this period, transistors 502 and 508 do not switch (or essentially do not switch). This is because during discharge time t... discharge There was little or no switching during the period, so the voltage V clamp At discharge time t discharge During this period, its voltage is maintained or substantially maintained. Therefore, when the switch is restarted at time t5, the difference... (Equivalently, the difference: V) clamp_0 -V 512d The current spikes in the primary and secondary currents Ip and Is are higher than during the steady-state period, resulting in current spikes, such as... Figure 5F As shown. For example, as Figure 5F As shown, current spikes of approximately -18A and 88A may occur in currents Ip and Is, respectively.

[0080] This higher current peak (e.g., as in...) Figure 5F and Figure 5G The short-circuit condition or the resulting negative output transition shown may increase stress on the components of the ACF converter 500.

[0081] Current bump time period t B The duration of this can be inversely proportional to the output voltage. Therefore, the output voltage V out A drop (e.g., during a short-circuit condition or negative output transition) can cause a current bump time t B The duration increases. For example, such as Figure 5F and Figure 5G As shown, the current bump time t after the output voltage drops (e.g., after time t2) B During this period, the duration of the current peak is longer than that during the steady-state condition (e.g., before time t2).

[0082] The inventors recognized that the bump time t could be limited by turning off transistor 508. B The current spikes generated during this period. For example, in some embodiments, the current I flowing through transistor 508. clamp It can be done at current bump time t B The period is monitored (e.g., in a cycle-by-cycle manner). If the current I... clamp Exceeding (e.g., during a switching cycle) a predetermined threshold I OCP_508Then transistor 508 will turn off (e.g., immediately) (e.g., for the remainder of the switching cycle). For example, Figure 6 A flowchart of an embodiment method 600 for operating a non-complementary ACF converter according to an embodiment of the present invention is shown. Method 600 includes steps 552, 554, 556, 558, 560, 562, 564, 602, 604, and 606. In some embodiments, steps 552, 554, 556, 558, 560, 562, and 564 may be performed in a manner similar to that in method 550.

[0083] Figure 7 An ACF converter 700 according to an embodiment of the present invention is shown. The ACF converter 700 includes a primary controller 710, transistors 502 and 508, capacitors 506 and 114, a feedback circuit 530, a transformer 512, current sensors 526 and 702, and an error amplifier 528. The primary controller 710 can implement method 600. Figure 6 and Figure 7 We can understand them together.

[0084] In some embodiments, the current sensor 702 can be implemented using a current transformer. As will be described in more detail below, in some embodiments, the current sensor 702 can be implemented using a sensing capacitor.

[0085] In some embodiments, diode 116 may be replaced in a known manner with a synchronous rectifier (SR) transistor and an SR controller for performing synchronous rectification. By using an SR transistor and an SR controller, some embodiments can advantageously achieve reduced power losses and increased efficiency.

[0086] In some embodiments, the primary controller 710 may be implemented using a general-purpose or custom microcontroller or processor, for example, coupled to memory and configured to execute instructions stored in such memory. Other implementations, such as those including a hard-coded finite state machine (FSM), are also possible.

[0087] like Figure 6 As shown, the clamping current I is measured during step 602 after the high-side transistor is turned on (step 558) (e.g., immediately). clamp and compare it with the predetermined threshold I OCP_508 A comparison is made. If the magnitude of the reverse current does not exceed a predetermined threshold (I... OCP_508 If the magnitude of the reverse current exceeds a predetermined threshold (I0), then steps 560, 562, and 564 are performed, for example, in a manner similar to that described with respect to method 550. OCP_508If the high-side transistor 508 is turned off during step 604 (e.g., immediately), the reverse current is advantageously limited because the reverse current is blocked by the body diode of the high-side transistor 508.

[0088] The inventors recognized that if the controller 710 waits for the normal dead time t after turning off the high-side transistor 508, d Then the voltage V DS_502 It might bounce back (because the reverse current is blocked by the body diode of the high-side transistor 508, and the reverse current may not grow enough to allow ZVS), and the low-side transistor 502 might be turned on via hard switching. For example, Figure 8 An embodiment of the invention is shown, in which a dead time t is waited after the high-side transistor 508 is turned off during step 604. d The waveform associated with ACF 700 when transistor 502 is turned on.

[0089] like Figure 8 As shown, after the transistor 508 is turned off, a dead time t elapses. d Subsequently, before the time transistor 502 is turned on during time t6, the voltage V DS_502 Above 200V. Therefore, in some embodiments, such as Figure 6 As shown, after the high-side transistor 508 is turned off (during step 604), during the minimum dead time t d_min After (step 606), the low-side transistor 502 is turned on (step 552), where t d_min <t d In some embodiments, the minimum dead time t d_min Basically less than the normal dead time t d For example, in some embodiments, the minimum dead time t d_min This refers to, for example, the minimum dead time to avoid cross-conduction between the high-side transistor 508 and the low-side transistor 502. For example, in some embodiments, t d_min than t d At least half the length (e.g., one-third, one-quarter, or less). For example, in some embodiments, the minimum dead time t d_min (Step 606) is 80 ns, while the normal dead time t d (Step 564) is 300 ns. Other values ​​can also be used.

[0090] As will be referred to below Figure 11 In more detail, some embodiments may implement additional auxiliary functions during step 608.

[0091] By turning on the low-side transistor 502 shortly after turning off the high-side transistor 508, some embodiments advantageously achieve ZVS or exceed the normal dead time t. d Transistor 502 turns on at a lower voltage.

[0092] Figure 9A The diagram illustrates a waveform associated with an ACF converter 700 implementing method 600 under a short-circuit condition, according to an embodiment of the invention.

[0093] like Figure 9A As shown, a short circuit condition is applied at time t7. Therefore, the output voltage V out Decrease, difference (Equivalently, the difference: V) clamp_0 -V 512 ) increases. However, because transistor 508 detects (step 602) I clamp Shortly after the overcurrent (in a cycle-by-cycle manner), the current is turned off (step 604), and the peak currents of the primary current Ip and the secondary current Is are limited. For example, as Figure 9A As shown, using method 600, the peak current amplitudes of currents Ip and Is are advantageously limited to approximately -7A and approximately 24A, respectively (compared to...). Figure 5F (Compared to approximately -18A and 88A in the example).

[0094] like Figure 9A As shown, using method 600, the current bump time period t B It is also shorter because the turn-off of transistor 508 (step 604) and the shorter dead time (step 606) result in a shorter time interval t. B Compare Figure 5F Example of current bump time period t B (Usage method 550) is shorter.

[0095] Figure 9B An embodiment according to the present invention is shown. Figure 9A The waveform is magnified at time t8. For example... Figure 9B As shown, the low-side transistor 502 is turned on at time t9 (step 552), which is immediately following the minimum dead time t. d_min This occurs after (step 606).

[0096] like Figure 9B As shown, the drain-source voltage V at time t9 DS_502 Approximately 100V, which is longer than the normal dead time t. d When it is advantageous to be small (e.g., less than) Figure 8 (as shown, greater than 200V).

[0097] Figure 10The waveforms associated with the ACF converter 700 implementing method 600 during the negative output transition are shown according to an embodiment of the present invention. Figure 10 The negative output transition shown is from 20V to 5V. Negative output transitions from different starting voltages (e.g., 25V, 20V, 18V, 15V, 12V, 10V, 9V, or others) and / or to different lower ending voltages (e.g., 20V, 18V, 15V, 12V, 10V, 9V, or others) are also possible. For example, in embodiments implemented in USB-compatible systems (which specify possible output voltages of 20V, 15V, 9V, and 5V), negative output transitions may occur from 20V to 15V, 9V, or 5V, from 15V to 9V, or from 9V to 5V.

[0098] like Figure 10 As shown, the negative output transition from 20V to 5V occurs from time t. 10 Begin. At time t 11 When restarting the switch, use method 550 (e.g., as...). Figure 5G Compared to -18A and 88A (as shown), the current spikes associated with the primary current Ip and secondary current Is reach approximately -7A and approximately 32A, respectively.

[0099] like Figure 9A and Figure 10 As shown (and) Figure 5F and Figure 5G In contrast, in some embodiments, when implementing method 600, after a short-circuit condition or after restarting switching following a negative output transition, the discharge voltage V clamp The time required is longer than that of method 550. However, when method 600 is implemented, for example, compared to method 550, the risk of exceeding the safe operating area (SOA) of transistors 502 and 508 can be advantageously reduced.

[0100] By current bump time period t B During this period, the amplitude of current spikes in the primary current Ip and secondary current Is is limited, and the current bump time t is reduced. B During the duration of the event (e.g., during short-circuit conditions or negative output transitions), some embodiments advantageously reduce the stress on one or more components of the ACF converter (e.g., 502, 508, 116), which can advantageously extend the life of the ACF converter.

[0101] like Figure 5F As shown, during a short-circuit condition, the stress on the components of the ACF converter (e.g., 502, 508, 116) may be caused by reverse current (during the current bump time t). B The current spikes in currents Ip and Is during the period (t) are caused by the current spikes, as well as by the (positive) primary current (during the time period t).A The increase in current Ip and current Is during the period is caused by peak values. Therefore, once an overcurrent condition is detected in the high-side transistor 508 (output "Yes" from step 602), some embodiments advantageously activate a soft-start function to limit the current during the time period t. A The current flowing through the low-side transistor 502 during this period (e.g., in a manner similar to that about) Figure 5D (The manner described).

[0102] In some embodiments, the soft-start function is activated during short-circuit conditions but not during negative output transitions. For example, the inventors realized that, for instance, as... Figure 9A As shown, the error voltage V during the overcurrent event caused by the reverse current due to a short circuit is... err Saturated in a state (e.g., high), while... Figure 9B As shown, the error voltage V during the overcurrent event caused by the negative output transition. err Saturates in the opposite state (e.g., low). Therefore, some embodiments determine whether the ACF converter 700 is in a short-circuit condition or a negative output transition based on the state of the error voltage when an overcurrent event of reverse current is detected, and activate the soft-start function only when a short-circuit condition is determined to exist. For example, in some embodiments, during the current bump time period t B During this period, the error voltage V during the overcurrent event of reverse current. err When saturation is high, the soft-start function is activated; otherwise, the soft-start function is not activated.

[0103] Figure 11 A flowchart of an embodiment method 1100 for operating a non-complementary ACF converter according to an embodiment of the present invention is shown. Figure 11 A possible implementation of step 608 is shown. Method 1100 includes steps 552, 554, 556, 558, 560, 562, 564, 602, 604, 606, 1102, and 1104. In some embodiments, steps 552, 554, 556, 558, 560, 562, 564, 602, 604, and 606 may be performed in a similar manner to that in method 600. The primary controller 710 may implement method 1100.

[0104] After detecting an overcurrent event of reverse current (during step 602), the error voltage V is determined during step 1102. err The state. If the error voltage V err If saturation is high during an overcurrent event, then the soft-start function is activated during step 1104, for example, during time period t. A Limit current spikes during the period.

[0105] In some embodiments, when the voltage V during step 1102 err When saturation is high, a short-circuit condition signal is asserted to indicate that a short-circuit condition has been detected. In some embodiments, during step 1102, the voltage V... err When saturation is low, an assertion signal for a negative output transition is given to indicate that a negative output transition has been detected.

[0106] In some embodiments, step 608 may be performed before, after, or simultaneously with steps 604 and / or 606.

[0107] Figure 9A and Figure 9B The waveform shown is consistent with implementation method 600 and is implemented simultaneously as follows: Figure 11 The ACF converter 700 associated with step 608 shown (i.e., Figure 9A and Figure 9B The waveform of implementation method 1100 of ACF converter 700 is shown. Figure 9A As shown, due to the error voltage V err The transistor 508 saturates high during an overcurrent event, therefore the soft-start function is active at time t. 12 Activated, with method 550 (e.g.) Figure 5F Compared to (as shown), this advantageously limits the time period t. A The peaks of currents Ip and Is during this period.

[0108] like Figure 9B As shown, due to the error voltage V err During the overcurrent event of transistor 508, it does not saturate to high (it saturates to low), therefore the soft-start function is not activated during the negative output transition, and at time t... 11 During the switching restart, the power capability of the ACF converter 700 is advantageously unaffected.

[0109] By using soft start during startup and short-circuit conditions, some embodiments can advantageously reduce the stress on the components of the ACF converter, which can advantageously extend the life of the ACF converter.

[0110] Figure 12An ACF converter 1200 according to an embodiment of the present invention is shown. The ACF converter 1200 illustrates a possible implementation of a current sensor 702. The ACF converter includes a primary controller 1210, transistors 502 and 508, capacitors 506 and 114, a rectifier diode 116 (or an SR transistor), a feedback circuit 530, a transformer 512, current sensors 526 and 702, an error amplifier 528, and a comparator circuit 1220. The comparator circuit 1220 includes a comparator 1206 and resistors 1208, 1212, 1214, and 1216. The current sensor 702 includes a sensing capacitor 1202 and a sensing resistor 1204. In some embodiments, the comparator circuit 1220 is part of the primary controller 1210.

[0111] like Figure 12 As shown, due to the sensing resistance R CS The capacitors 506 and 1202 are relatively small. They are dynamically connected in parallel to form a dynamic capacitor divider, the ratio of which can be given by the following formula.

[0112]

[0113] Where C s This indicates the capacitance of capacitor 1202, C. 506 This represents the capacitance of capacitor 506. In some embodiments, k equals 1000. Other values ​​of k may also be used, such as those higher than 1000 (e.g., 1010, 2000 or higher) or lower than 1000 (e.g., 980, 900 or lower). In some embodiments, k is at least 100.

[0114] During the current bump time period t B During this period, the reverse current I REV The current flows through capacitor 506 in positive parallel, and the current k·I REV The current flows through resistor 1204. Therefore, during the current bump time t... B During this period, voltage V sense Negative (e.g., as) Figure 8 , Figure 9A , Figure 9B and Figure 10 (As shown).

[0115] In some embodiments, due to the sensing voltage V sense During the sensing time period (t) B The period is negative, therefore a comparator circuit such as comparator circuit 1220 can be used to convert this sensed voltage V. sense With threshold V th Comparison. For example, in Figure 12 In the embodiment shown, the threshold voltage V th It can be given by the following formula

[0116]

[0117] Where R represents the resistance of each of resistors 1208, 1212 and 1216, and R1 represents the resistance of resistor 1214.

[0118] In some embodiments, the OCP threshold I OCP_508 (For example, the one used during step 602) can be given by the following formula.

[0119]

[0120] As a non-restrictive example, in Figure 9A and Figure 10 In the embodiment shown, the threshold voltage V th It was set to -500mV.

[0121] When V sense The amplitude exceeds the threshold V th At that time, signal OCP 508 Assertioned (e.g., high). Signal OCP 508 The assertion corresponds to the output "Yes" in step 602.

[0122] like Figure 12 As shown, in some embodiments, the cycle-by-cycle execution signal OCP is performed. 508 The generation (e.g., step 602). Therefore, in some embodiments, based on the reverse current I REV The amplitude during the current bump time period t B During this period, the decision to turn off the high-side transistor 604 in advance is executed cycle by cycle (step 604).

[0123] In some embodiments, R, R1, R CS C s C 506 V th The value is selected to have a suitable threshold V th To detect reverse current I REV This addresses overcurrent events while avoiding introducing significant delays in measurements. For example, in some embodiments, the time constant R... CS ·C s Keep the time short (e.g., in tens of ns, such as between 10 ns and 50 ns) to avoid reverse current I. REV A significant delay is introduced after comparison with a threshold (e.g., step 602) (e.g., because it may be desirable to take action quickly (e.g., step 606)).

[0124] In some embodiments, the current I to be sensedREV It can be tens of amperes, capacitor C 506 It is several hundred nF, capacitor C s It is several hundred pF, and the resistance R CS For resistors less than or equal to 100Ω, resistors R and R1 can be in the range of tens of kΩ, reference voltage Vref2 can be in the range of several volts (e.g., less than 10V), and threshold voltage V... th It can be in the range of several hundred mV (e.g., less than 1V).

[0125] By using a sensing capacitor (e.g., 1202) at a reference ground to sense the reverse current flowing through the high-side transistor 508, some embodiments advantageously enable sensing during the current bump time t. B During this period, current spikes are limited without using a current transformer (which can be expensive and bulky).

[0126] In some embodiments, the primary controller 1210 may be implemented in an integrated circuit. For example, in one embodiment, the integrated circuit includes elements 1206, 1208, 1210, 1212, 1214, and 1216, while other elements are implemented externally to the integrated circuit. For example, in some embodiments, elements 530 and 528 may be housed in the same package. Other implementations are also possible. For example, in some embodiments, the integrated circuit further includes transistors 502 and 508.

[0127] This document summarizes exemplary embodiments of the invention. Other embodiments can also be understood from the entirety of the description and claims submitted herein.

[0128] Example 1. A method for operating an active clamp flyback (ACF) converter, the method comprising: turning on a low-side transistor coupled between a first terminal and a reference terminal of a primary winding of a transformer, such that a forward current enters the primary winding via a second terminal of the primary winding and exits the primary winding via a first terminal of the primary winding; turning off the low-side transistor after turning it on; turning on a high-side transistor coupled between the first terminal of the primary winding and a first terminal of a clamping capacitor after turning off the low-side transistor, such that a reverse current flows through the primary winding, wherein a second terminal of the clamping capacitor is coupled to a second terminal of the primary winding, and wherein the reverse current has a direction opposite to the forward current; and after turning on the high-side transistor, maintaining the high-side transistor on for a first time period when no overcurrent of reverse current is detected, and turning off the high-side transistor after the first time period, and turning off the high-side transistor without maintaining the high-side transistor on for the first time period when an overcurrent of reverse current is detected.

[0129] Example 2. The method according to Example 1 further includes: when no overcurrent of reverse current is detected, turning on the low-side transistor after a first dead time following the turn-off of the high-side transistor; and when an overcurrent of reverse current is detected, turning on the low-side transistor after a second dead time following the turn-off of the high-side transistor, wherein the second dead time is shorter than the first dead time.

[0130] Example 3. Based on one of Examples 1 and 2, where the second dead time is at least three times shorter than the first dead time.

[0131] Example 4. The method according to any one of Embodiments 1 to 3, wherein the second dead time corresponds to a minimum dead time sufficient to prevent cross-conduction between the high-side transistor and the low-side transistor.

[0132] Example 5. According to one of Examples 1 to 4, turning on the high-side transistor includes turning on the high-side transistor when the secondary current flowing through the secondary winding of the transformer drops to about 0A.

[0133] Example 6. The method according to any one of Examples 1 to 5 further includes: determining the error voltage based on the output voltage at the output terminal coupled to the secondary winding of the transformer; and determining a short-circuit condition when the error voltage saturates to a first voltage when an overcurrent of reverse current is detected.

[0134] Example 7. The method according to any one of Examples 1 to 6 further includes: when an overcurrent of reverse current is detected, determining a negative output transition when the error voltage saturates to a second voltage; and asserting a negative output transition signal in response to determining the negative output transition.

[0135] Example 8. The method according to one of Examples 1 to 7 further includes adjusting the output voltage based on the error voltage.

[0136] Example 9. According to one of Examples 1 to 8, the method further includes activating a soft-start function to limit the power of the ACF converter when a short-circuit condition is determined.

[0137] Example 10. The method according to one of Examples 1 to 9 further includes performing synchronous rectification using a synchronous rectifier coupled to the secondary winding of the transformer.

[0138] Example 11. The method according to any one of Examples 1 to 10 further includes: sensing a sense voltage at the first terminal of the clamping capacitor using a sensing capacitor coupled between the first terminal and a reference terminal of the clamping capacitor; asserting an overcurrent signal using a comparator circuit having an input for receiving the sense voltage; and detecting an overcurrent of reverse current when the overcurrent signal is asserted.

[0139] Example 12. An active clamp flyback (ACF) converter, comprising: a transformer including a primary winding and a secondary winding; a low-side transistor having a current path coupled between a first terminal and a reference terminal of the primary winding; a clamping capacitor coupled to a second terminal of the primary winding; a high-side transistor having a current path coupled between the first terminal of the primary winding and the clamping capacitor; a current sensor configured to sense a reverse current flowing through the clamping capacitor, the reverse current having a direction from the clamping capacitor to the first terminal of the primary winding; and a primary controller configured to: turn on the low-side transistor to allow forward current to flow through the primary winding. The second terminal enters the primary winding and exits the primary winding via the first terminal of the primary winding. After the low-side transistor is turned on, the low-side transistor is turned off. After the low-side transistor is turned off, the high-side transistor is turned on, allowing reverse current to flow through the primary winding. After the high-side transistor is turned on, the presence of reverse current overcurrent is detected based on the output of the current sensor. When no reverse current overcurrent is detected, the high-side transistor is kept on for a first time period and then turned off after the first time period. When reverse current overcurrent is detected, the high-side transistor is turned off without keeping it on for the first time period.

[0140] Example 13. An ACF converter according to Example 12, wherein the current sensor includes: a sensing capacitor coupled to an intermediate node, the intermediate node being coupled between a clamping capacitor and a current path of a high-side transistor; and a sensing resistor coupled between the sensing capacitor and a reference terminal.

[0141] Example 14. An ACF converter according to one of Examples 12 or 13 further includes a comparator having a first input configured to receive a threshold voltage, a second input coupled to a sensing capacitor, and an output configured to provide an overcurrent detection signal.

[0142] Example 15. An ACF converter according to one of Examples 12 to 14, wherein the primary controller is configured to detect the presence of an overcurrent in reverse current based on an overcurrent detection signal.

[0143] Example 16. An ACF converter according to one of Examples 12 to 15, wherein the sensing capacitor is at least 100 times smaller than the clamping capacitor.

[0144] Example 17. An ACF converter according to one of Examples 12 to 16, wherein the time constants associated with the sensing capacitor and the sensing resistor are between 10 ns and 50 ns.

[0145] Example 18. An ACF converter according to one of Examples 12 to 17 also includes a rectifier diode coupled to the secondary winding.

[0146] Example 19. An ACF converter according to one of Examples 12 to 18 also includes a synchronous rectifier (SR) transistor coupled to the secondary winding.

[0147] Example 20. An ACF converter according to one of Examples 12 to 19 further includes a feedback circuit coupled to the secondary winding, the feedback circuit being configured to provide an error voltage, wherein the primary controller is configured to activate a soft-start function when the error voltage saturates to a first voltage upon detecting an overcurrent of reverse current.

[0148] Example 21. An ACF converter according to one of Examples 12 to 20, wherein the main controller is further configured to: turn on the low-side transistor after a first dead time following the turn-off of the high-side transistor when no overcurrent of reverse current is detected; and turn on the low-side transistor after a second dead time following the turn-off of the high-side transistor when an overcurrent of reverse current is detected, wherein the second dead time is shorter than the first dead time.

[0149] Example 22. An ACF converter according to one of embodiments 12 to 21, wherein the low-side transistor and the high-side transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs) or GaN transistors.

[0150] Example 23. An integrated circuit comprising: a reference terminal configured to receive a reference voltage; a voltage sensing terminal configured to be coupled to a clamping capacitor via a sensing capacitor and to the reference terminal via a sensing resistor; a first control terminal configured to be coupled to a control terminal of a high-side transistor having a current path coupled between the voltage sensing terminal and a first terminal of a primary winding of a transformer; a second control terminal configured to be coupled to a control terminal of a low-side transistor having a first current path terminal coupled to the current path of the high-side transistor; a comparator having a first input configured to receive a threshold voltage, a second input coupled to the voltage sensing terminal, and an output configured to provide an overcurrent detection signal; and The primary controller is configured to: turn on the low-side transistor to allow forward current to enter the primary winding via the second terminal of the primary winding and exit the primary winding via the first terminal of the primary winding; turn off the low-side transistor after turning it on; turn on the high-side transistor after turning off the low-side transistor to allow reverse current to flow through the primary winding, the reverse current having the opposite direction to the forward current; and after turning on the high-side transistor, detect the presence of overcurrent based on an overcurrent detection signal; when the overcurrent detection signal is deasserted, keep the high-side transistor on for a first time period; and turn off the high-side transistor after the first time period; and when the overcurrent detection signal is asserted, turn off the high-side transistor without keeping it on for the first time period.

[0151] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon referring to the specification. Therefore, the appended claims cover any such modifications or embodiments.

Claims

1. A method for operating an active clamp flyback ACF converter, the method comprising: The low-side transistor coupled between the reference terminal and the first terminal of the primary winding of the transformer is turned on so that forward current enters the primary winding via the second terminal of the primary winding and exits the primary winding via the first terminal of the primary winding. After the low-side transistor is turned on, the low-side transistor is turned off; After the low-side transistor is turned off, the high-side transistor coupled between the first terminal of the primary winding and the first terminal of the clamping capacitor is turned on to allow reverse current to flow through the primary winding, wherein the second terminal of the clamping capacitor is coupled to the second terminal of the primary winding, and wherein the reverse current has the opposite direction to the forward current. as well as After the high-side transistor is turned on When the overcurrent of the reverse current is not detected, the high-side transistor remains on for a first time period, and after the first time period, the high-side transistor is turned off. When an overcurrent of the reverse current is detected, the high-side transistor is turned off without keeping it on for the first time period.

2. The method according to claim 1, further comprising: When the overcurrent of the reverse current is not detected, the low-side transistor is turned on during the first dead time after the high-side transistor is turned off. as well as When the overcurrent of the reverse current is detected, the low-side transistor is turned on during a second dead time after the high-side transistor is turned off, wherein the second dead time is shorter than the first dead time.

3. The method of claim 2, wherein the second dead time is at least three times shorter than the first dead time.

4. The method of claim 2, wherein the second dead time corresponds to a minimum dead time sufficient to prevent cross-conduction between the high-side transistor and the low-side transistor.

5. The method of claim 1, wherein turning on the high-side transistor comprises turning on the high-side transistor when the secondary current flowing through the secondary winding of the transformer drops to about 0A.

6. The method according to claim 1, further comprising: The error voltage is determined based on the output voltage at the output terminal coupled to the secondary winding of the transformer; as well as When an overcurrent of the reverse current is detected, a short circuit condition is determined when the error voltage saturates to a first voltage.

7. The method according to claim 6, further comprising: When the overcurrent of the reverse current is detected, and when the error voltage saturates to the second voltage, a negative output transition is determined; as well as In response to determining the negative output transition, assert the negative output transition signal.

8. The method of claim 6, further comprising adjusting the output voltage based on the error voltage.

9. The method of claim 6 further includes activating a soft-start function to limit the power of the ACF converter when the short-circuit condition is determined.

10. The method of claim 1, further comprising performing synchronous rectification using a synchronous rectifier coupled to the secondary winding of the transformer.

11. The method according to claim 1, further comprising: The sensing voltage at the first terminal of the clamping capacitor is sensed using a sensing capacitor coupled between the reference terminal and the first terminal of the clamping capacitor; A comparator circuit is used to assert the overcurrent signal, the comparator circuit having an input that receives the sensed voltage; as well as When the overcurrent signal is asserted, the overcurrent of the reverse current is detected.

12. An active clamp flyback ACF converter, comprising: A transformer consists of a primary winding and a secondary winding; The low-side transistor has a current path coupled between a reference terminal and a first terminal of the primary winding; A clamping capacitor is coupled to the second terminal of the primary winding; A high-side transistor having a current path coupled between the first terminal of the primary winding and the clamping capacitor; A current sensor is configured to sense a reverse current flowing through the clamping capacitor, the reverse current having a direction from the clamping capacitor to the first terminal of the primary winding; as well as The primary controller is configured as follows: The low-side transistor is turned on so that forward current enters the primary winding via the second terminal of the primary winding and exits the primary winding via the first terminal of the primary winding. After turning on the low-side transistor, turn off the low-side transistor. After the low-side transistor is turned off, the high-side transistor is turned on to allow the reverse current to flow through the primary winding, and After the high-side transistor is turned on The presence of overcurrent due to the reverse current is detected based on the output of the current sensor. When the overcurrent of the reverse current is not detected, the high-side transistor remains on for a first time period, and is turned off after the first time period. When the overcurrent of the reverse current is detected, the high-side transistor is turned off without keeping the high-side transistor on for the first time period.

13. The ACF converter according to claim 12, wherein the current sensor comprises: A sensing capacitor is coupled to an intermediate node, the intermediate node being coupled between the clamping capacitor and the current path of the high-side transistor; as well as A sensing resistor is coupled between the sensing capacitor and the reference terminal.

14. The ACF converter of claim 13, further comprising a comparator having: a first input configured to receive a threshold voltage; a second input coupled to the sensing capacitor; and an output configured to provide an overcurrent detection signal.

15. The ACF converter of claim 14, wherein the primary controller is configured to detect the presence of an overcurrent in the reverse current based on the overcurrent detection signal.

16. The ACF converter of claim 13, wherein the sensing capacitor is at least 100 times smaller than the clamping capacitor.

17. The ACF converter of claim 13, wherein the time constant associated with the sensing capacitor and the sensing resistor is between 10 ns and 50 ns.

18. The ACF converter of claim 12, further comprising a rectifier diode coupled to the secondary winding.

19. The ACF converter of claim 12, further comprising a synchronous rectifier SR transistor coupled to the secondary winding.

20. The ACF converter of claim 12, further comprising a feedback circuit coupled to the secondary winding, the feedback circuit being configured to provide an error voltage, wherein the primary controller is configured to activate a soft-start function when the error voltage saturates to a first voltage and an overcurrent of the reverse current is detected.

21. The ACF converter of claim 12, wherein the primary controller is further configured to: When the overcurrent of the reverse current is not detected, the low-side transistor is turned on during the first dead time after the high-side transistor is turned off; and When the overcurrent of the reverse current is detected, the low-side transistor is turned on during a second dead time after the high-side transistor is turned off, wherein the second dead time is shorter than the first dead time.

22. The ACF converter of claim 12, wherein the low-side transistor and the high-side transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs) or GaN transistors.

23. An integrated circuit, comprising: The reference terminal is configured to receive a reference voltage; A voltage sensing terminal is configured to be coupled to a clamping capacitor via a sensing capacitor and to the reference terminal via a sensing resistor; A first control terminal is configured to be coupled to a control terminal of a high-side transistor having a current path coupled between the voltage sensing terminal and a first terminal of the primary winding of the transformer. The second control terminal is configured to be coupled to the control terminal of the low-side transistor, the low-side transistor having a first current path terminal coupled to the current path of the high-side transistor. The comparator has: a first input configured to receive a threshold voltage; The second input is coupled to the voltage sensing terminal; The output is configured to provide an overcurrent detection signal; as well as The primary controller is configured as follows: The low-side transistor is turned on so that forward current enters the primary winding through the second terminal of the primary winding and exits the primary winding through the first terminal of the primary winding. After turning on the low-side transistor, turn off the low-side transistor. After the low-side transistor is turned off, the high-side transistor is turned on to allow a reverse current to flow through the primary winding, the reverse current having the opposite direction to the forward current. After the high-side transistor is turned on The presence of overcurrent in the reverse current is detected based on the overcurrent detection signal. When the overcurrent detection signal is de-asserted, the high-side transistor remains on for a first time period, and is turned off after the first time period. When the overcurrent detection signal is asserted, the high-side transistor is turned off without keeping it on for the first time period.

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