A soft start circuit and a converter

Abstract

The application discloses a soft start circuit and a converter, and relates to the technical field of the converter. When the converter is powered on, a maximum current is used to charge a capacitor at an output end by using an overcurrent protection circuit, the maximum current is the maximum current that can be borne by electronic components at the output end, the voltage at the output end is rapidly increased to a set value, then a step voltage adjustment stage is entered, a digital-analog conversion circuit in the soft start circuit is controlled by a clock circuit to gradually increase the level of a reference voltage, the reference voltage and the output voltage always follow each other and remain consistent, and a large duty ratio and a large current are avoided. After the reference voltage is increased to the set value, the soft start process is ended, the soft start circuit is immediately turned off to save power consumption, a feedback loop of the converter is established, the whole converter circuit works in a balanced state, and thus, the soft start process is successfully completed, and the converter circuit is stably and reliably powered on.

Description

Technical Field

[0001] This invention relates to the field of converter technology, and more particularly to a soft-start circuit and converter. Background Technology

[0002] DC-DC power converters are widely used in various electronic devices due to their high efficiency, low power consumption, and flexible output voltage control, especially in portable devices and consumer electronics, where they are gradually replacing traditional linear regulators. DC-DC converters need to provide stable and efficient power to other electronic devices or circuit systems, provided that the converter itself remains in a stable and reliable operating state as much as possible. During the initial power-up phase, because the voltage across the output capacitor is zero, the feedback loop is not yet established, and the system is in an unbalanced state. The power transistors switch with extremely high duty cycles, and may even be continuously on, resulting in a high current flow through the power transistors. Combined with the presence of the output inductor and capacitor, this can easily generate large inrush currents and voltage overshoots, damaging the power transistors and other electronic components. Therefore, a soft-start circuit is generally required in the converter as a protection measure during the power-up process to avoid these phenomena.

[0003] The common practice of soft-start circuits is to use a large capacitor to charge and slowly raise the reference voltage, so that the voltage is basically consistent with the voltage at the output terminal during the power-on process. This avoids the power transistor being in a state of continuous conduction, eliminates the surge current and overshoot voltage at the converter output terminal, and allows the converter to smoothly enter the normal operating state.

[0004] However, this soft-start circuit requires a large capacitor and the soft-start process is slow, making it not an optimal choice for DC-DC converters integrated in a system-on-a-chip (SoC). Summary of the Invention

[0005] The purpose of this invention is to provide a soft-start circuit and converter to solve the problems of excessively large capacitors, excessively long soft-start times, and inability to configure and adjust start-up times in existing soft-start circuits.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] One aspect of this invention provides a soft-start circuit, comprising: a frequency divider, the input of which is connected to a clock frequency signal; a first clock phase flipping circuit, a second clock phase flipping circuit, and a multiplexer, wherein the frequency divider divides the clock frequency signal and outputs it to the multiplexer, and the multiplexer processes the divided clock frequency signal and outputs it to the first clock phase flipping circuit and the second clock phase flipping circuit respectively, the inputs of the first clock phase flipping circuit and the second clock phase flipping circuit being connected to a first control signal; a decoder, the input of which is connected to a second control signal, and the control terminal of the multiplexer being connected to the output of the decoder for controlling the operation of the multiplexer; and a digital-to-analog converter circuit, wherein the first clock phase flipping circuit and the second clock phase flipping circuit are connected to control the digital-to-analog converter circuit, and the reference voltage output by the digital-to-analog converter circuit is further adjusted by adjusting the first control signal and the second control signal.

[0008] In some embodiments, the digital-to-analog converter circuit includes: a first resistor, a second resistor, and a first switch, one end of the first resistor being connected to a power supply, and the other end of the first resistor being connected to one end of the second resistor and one end of the first switch; a third resistor and a second switch, one end of the third resistor being connected to the other end of the second resistor and one end of the second switch, and the other end of the third resistor being grounded; a first data selector, the first input terminal of the first data selector being connected to the other end of the first switch and the other end of the second switch, the first data selector acquiring electrical signals of different voltages through the first switch and the second switch respectively; the second input terminal of the first data selector being used to receive a reference electrical signal, and the first data selector adjusting the output reference voltage according to the input signals of the first input terminal and the second input terminal.

[0009] In some embodiments, the digital-to-analog converter circuit further includes: a fourth resistor and a third switch, one end of the fourth resistor being connected to one end of the third switch and the other end of the third resistor; a fifth resistor and a fourth switch, one end of the fifth resistor being connected to the other end of the fourth resistor and one end of the fourth switch, and the other end of the fifth resistor being grounded; a first input terminal of the first data selector being connected to the other ends of the first switch, the second switch, the third switch, and the fourth switch, and the first data selector obtaining electrical signals of different voltages through the first switch, the second switch, the third switch, and the fourth switch, respectively.

[0010] In some embodiments, the digital-to-analog conversion circuit further includes: a fifth switch, one end of which is connected to the other end of the first switch and the other end of the second switch, and the other end of which is connected to the first input terminal of the first data selector; a sixth switch, one end of which is connected to the other end of the third switch and the other end of the fourth switch, and the other end of which is connected to the first input terminal of the first data selector; the control terminals of the first switch and the third switch are each connected to one output terminal of the second clock phase flipping circuit, the control terminals of the second switch and the fourth switch are each connected to the other output terminal of the second clock phase flipping circuit, the control terminal of the fifth switch is connected to one output terminal of the first clock phase flipping circuit, and the control terminal of the sixth switch is connected to the other output terminal of the first clock phase flipping circuit.

[0011] In some embodiments, the soft-start circuit further includes a first NAND gate and a first flip-flop, the output of the first NAND gate is connected to the input of the first flip-flop, the input of the first NAND gate is connected to the outputs of the first clock phase flip circuit and the second clock phase flip circuit respectively, and the output of the first flip-flop is connected to the enable pin of the frequency divider.

[0012] In some embodiments, both the first clock phase flipping circuit and the second clock phase flipping circuit include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a second flip-flop, a second NAND gate, and a second data selector. The output of the first inverter is connected to the input of the second inverter and the first input of the second data selector. The output of the second inverter is connected to the second input of the second data selector. The input of the third inverter is connected to the first control terminal of the second data selector. The output of the third inverter is connected to the second control terminal of the second data selector. The output of the second data selector is connected to the input of the second NAND gate through the fourth inverter. The output of the second NAND gate is connected to the input of the second flip-flop through the fifth inverter. The output of the second flip-flop can be used as one output of the first clock phase flipping circuit or one output of the second clock phase flipping circuit. The output of the second flip-flop after passing through the sixth inverter can be used as another output of the first clock phase flipping circuit or another output of the second clock phase flipping circuit.

[0013] One aspect of this invention provides a converter, comprising: a soft-start circuit as described above, a feedback circuit, a drive circuit, a first output switch, and a second output switch; a reference voltage input terminal of the feedback circuit is connected to a reference voltage output by a first data selector; an output terminal of the feedback circuit is connected to a first input terminal of the drive circuit; an output terminal of the drive circuit is connected to the control terminals of the first and second output switches respectively; an input terminal of the first output switch is connected to a power supply; an output terminal of the first output switch is connected to the input terminal of the second output switch; an output terminal of the second output switch is grounded; and a current sampling pin of the feedback circuit is connected to the output terminal of the first output switch, for the feedback circuit to acquire the output current and output a feedback signal to the drive circuit based on the output current; the drive circuit adjusts the operating state of the first and second output switches based on the feedback signal.

[0014] In some embodiments, the converter further includes a sixth resistor, an inductor, and a capacitor. The output terminal of the first output switch is connected to one end of the inductor, the other end of the inductor is connected to one end of the sixth resistor and the current sampling pin of the feedback circuit, the other end of the sixth resistor is connected to one end of the capacitor, and the other end of the capacitor is grounded.

[0015] In some embodiments, the converter further includes an overcurrent protection circuit and a current sensor. One end of the current sensor is connected to the input terminal of the first output switch and the power supply, and the other end of the current sensor is connected to one end of the overcurrent protection circuit. The other end of the overcurrent protection circuit is connected to the second input terminal of the drive circuit. When the power is first applied, the overcurrent protection circuit detects the power supply signal through the current sensor and feeds it back to the drive circuit. The drive circuit adjusts the operating state of the first output switch and the second output switch according to the power supply signal.

[0016] In some embodiments, the feedback circuit includes a sampling resistor, an error amplifier, a compensation network, a comparator, an SR latch, and an oscillator. The inverting input of the error amplifier is connected to the other end of the inductor and one end of the resistor through the sampling resistor. The non-inverting input of the error amplifier is connected to the reference voltage output by the first data selector. The output of the error amplifier is connected to the compensation network and the inverting input of the comparator. The non-inverting input of the comparator is connected to the first output of the oscillator. The output of the comparator is connected to the first input of the SR latch. The second output of the oscillator is connected to the second input of the SR latch and the soft-start circuit. The output of the SR latch is connected to the first input of the drive circuit.

[0017] According to an embodiment of the present invention, a soft-start circuit and converter have at least the following beneficial effects: At the moment of converter power-on, an overcurrent protection circuit charges the output capacitor with the maximum current, which is the maximum current that the output electronic components can withstand, causing the output voltage to rise rapidly to a set value. Subsequently, a stepped voltage adjustment stage is entered. The clock circuit in the soft-start circuit controls the digital-to-analog converter circuit to gradually raise the level of the reference voltage, ensuring that the reference voltage and output voltage always follow each other and remain consistent, avoiding large duty cycles and large currents. After the reference voltage is raised to the set value, the soft-start process ends, and the soft-start circuit immediately shuts down to save power. The converter's feedback loop is established, and the entire system operates in a balanced state. Thus, the soft-start process is successfully completed, achieving a stable and reliable power-on of the converter circuit.

[0018] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a digital-to-analog converter circuit according to an embodiment;

[0021] Figure 2 This is a partial schematic diagram of a soft-start circuit according to an embodiment;

[0022] Figure 3 This is a schematic diagram of a clock phase reversal circuit according to an embodiment;

[0023] Figure 4 This is a schematic diagram of a converter circuit according to an embodiment.

[0024] The reference numerals in the attached diagram are explained as follows: 1. Multiplexer; 2. Frequency divider; 3. Decoder; 4. First flip-flop; 5. First clock phase flip circuit; 6. Second clock phase flip circuit; 7. Soft-start circuit; 8. Drive circuit; 9. Overcurrent protection circuit; 10. Current sensor; 11. Compensation network; 12. SR latch; 13. Oscillator; 14. Bandgap reference; 15. Second flip-flop. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0027] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connection," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0030] The technical solutions of the embodiments of this application are briefly described below:

[0031] According to some embodiments of this application, the converter described in this application takes a BUCK-type converter as an example, and the soft-start circuit 7 can be applied to the three most common converter topologies: BUCK-type, BOOST-type, and BUCK-BOOST-type.

[0032] According to some embodiments, this application provides a converter, the circuit schematic of which is shown below. Figure 4 As shown, the converter includes a soft-start circuit 7, which in turn includes a digital-to-analog converter circuit, as shown in the figure. Figure 1 As shown, the soft-start circuit 7 is as follows Figures 1 to 2 As shown, the two circuit diagrams are combined into a soft-start circuit 7. The first clock phase flipping circuit 5 and the second clock phase flipping circuit 6 in the soft-start circuit 7 have the same structure, and their circuit schematic structures are as follows. Figure 3 As shown.

[0033] like Figures 1 to 4 As shown, at the moment the converter is powered on, this application uses the overcurrent protection circuit 9 to charge the output capacitor C with a set maximum current. The set maximum current is the maximum current that the output electronic components can withstand. At the start of power-on, since the feedback circuit cannot yet form feedback, the overcurrent protection circuit 9 provides feedback to the drive circuit 8. The drive circuit 8, based on the feedback signal from the overcurrent protection circuit 9, rapidly raises the output voltage to the set maximum current. Then, the soft-start circuit 7 enters a stepped voltage adjustment stage. The clock circuit in the soft-start circuit 7 controls the digital-to-analog converter circuit to gradually raise the level of the reference voltage Vref, ensuring that the reference voltage Vref and the output voltage follow each other in the error amplifier U2, maintaining consistency and avoiding large duty cycles and large currents. After the reference voltage Vref is raised to the set value, the soft-start process ends, and the soft-start circuit 7 immediately shuts down to save power. The converter's feedback circuit is now established, and the entire converter circuit operates in a balanced state. Thus, the soft-start process is successfully completed, achieving a stable and reliable power-on of the converter circuit.

[0034] Furthermore, this application provides a soft-start circuit, the soft-start circuit 7 comprising:

[0035] Frequency divider 2, the input terminal of which is connected to a clock frequency signal;

[0036] The system comprises a first clock phase reversal circuit 5, a second clock phase reversal circuit 6, and a multiplexer 1. The frequency divider 2 divides the clock frequency signal and outputs the result to the multiplexer 1. The multiplexer 1 processes the divided clock frequency signal and outputs it to the first clock phase reversal circuit 5 and the second clock phase reversal circuit 6 respectively. The input terminals of the first clock phase reversal circuit 5 and the second clock phase reversal circuit 6 are connected to a first control signal VD<1:0>, i.e., VD... <0> and VD <1> ;

[0037] Decoder 3, the input terminal of which is connected to the second control signal CLK_S<1:0>, and the control terminal of the multiplexer 1 is connected to the output terminal of the decoder 3, so as to use the decoder 3 to control the operation of the multiplexer 1;

[0038] The digital-to-analog converter circuit includes a first clock phase flipping circuit 5 and a second clock phase flipping circuit 6 connected to control the digital-to-analog converter circuit. The reference voltage Vref output by the digital-to-analog converter circuit is further adjusted by adjusting the first control signal VD<1:0> and the second control signal CLK_S<1:0>.

[0039] The following is in conjunction with the appendix to this instruction manual. Figure 1 The soft-start circuit of this application will be further described in detail.

[0040] According to some embodiments, such as Figure 1 As shown, the digital-to-analog converter circuit includes:

[0041] A first resistor R1, a second resistor R2, and a first switch are provided. One end of the first resistor R1 is connected to a power source, and the other end of the first resistor R1 is connected to one end of the second resistor R2 and one end of the first switch.

[0042] A third resistor R3 and a second switch Q2, wherein one end of the third resistor R3 is connected to the other end of the second resistor R2 and one end of the second switch, and the other end of the third resistor R3 is grounded;

[0043] The first data selector MUX1 has its first input terminal connected to the other end of the first switch and the other end of the second switch. The first data selector MUX1 obtains electrical signals of different voltages through the first switch and the second switch respectively.

[0044] The second input terminal of the first data selector MUX1 is used to receive the reference electrical signal V1. The first data selector MUX1 adjusts the output reference voltage Vref according to the input signals of the first input terminal and the second input terminal.

[0045] Among them, such as Figure 4As shown, the second input terminal of the first data selector MUX1 is connected to a bandgap reference 14, which provides a reference electrical signal V1 to the first data selector MUX1.

[0046] Based on the above embodiments, such as Figure 1 As shown, one end of the first resistor R1 is connected to a current source. The voltage of the current source is divided by the first resistor R1, the second resistor R2, and the third resistor R3. The voltage at the connection point of the first resistor R1 and the second resistor R2 is higher than the voltage at the connection point of the second resistor R2 and the third resistor R3. The first switch and the second switch can be connected to two different control signals to control the first switch and the second switch to switch in a set sequence, inputting two different voltages to the first data selector MUX1 in a set sequence. In some embodiments, the voltage sequence is such that the first input terminal of the first data selector MUX1 receives the voltage signals of the second switch and the first switch in ascending order of voltage, so that the reference voltage Vref output by the first data selector MUX1 gradually increases.

[0047] In some embodiments, both the first switch and the second switch are MOSFETs. The first switch is a first NMOS transistor Q1, and the second switch is a second NMOS transistor Q2. The source of the first NMOS transistor Q1 is connected to the connection of the first resistor R1 and the second resistor R2. The source of the second NMOS transistor Q2 is connected to the connection of the second resistor R2 and the third resistor R3. The drains of both the first NMOS transistor Q1 and the second NMOS transistor Q2 are connected to the first data selector MUX1.

[0048] According to some embodiments, such as Figure 1 As shown, the digital-to-analog converter circuit further includes:

[0049] A fourth resistor R4 and a third switch, wherein one end of the fourth resistor R4 is connected to one end of the third switch and the other end of the third resistor R3;

[0050] A fifth resistor R5 and a fourth switch, one end of the fifth resistor R5 is connected to the other end of the fourth resistor R5 and one end of the fourth switch R4, and the other end of the fifth resistor R5 is grounded;

[0051] The first input terminal of the first data selector MUX1 is connected to the other end of the first switch, the other end of the second switch, the other end of the third switch, and the other end of the fourth switch. The first data selector MUX1 obtains electrical signals of different voltages through the first switch, the second switch, the third switch, and the fourth switch, respectively.

[0052] Based on the above embodiment, the voltage of the current source is divided by a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The voltage at the connection point of the first resistor R1 and the second resistor R2 is higher than the voltage at the connection point of the second resistor R2 and the third resistor R3, the voltage at the connection point of the second resistor R2 and the third resistor R3 is higher than the voltage at the connection point of the third resistor R3 and the fourth resistor R4, and the voltage at the connection point of the third resistor R3 and the fourth resistor R4 is higher than the voltage at the connection point of the fourth resistor R4 and the fifth resistor R5. The first input terminal of the first data selector MUX1 receives the voltage signals of the fourth switch, the third switch, the second switch, and the first switch in ascending order of voltage, so that the reference voltage Vref output by the first data selector MUX1 gradually increases.

[0053] In some embodiments, both the third switch and the fourth switch are MOSFETs. The third switch is a third NMOS transistor Q3, and the fourth switch is a fourth NMOS transistor Q4. The source of the third NMOS transistor Q3 is connected to the junction of the third resistor R3 and the fourth resistor R4, and the source of the fourth NMOS transistor Q4 is connected to the junction of the fourth resistor R4 and the fifth resistor R5. The drains of both the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are connected to the first data selector MUX1.

[0054] According to some embodiments, the digital-to-analog converter circuit further includes:

[0055] The fifth switch has one end connected to the other end of the first switch and the other end of the second switch, and the other end of the fifth switch is connected to the first input terminal of the first data selector.

[0056] A sixth switch, one end of which is connected to the other end of the third switch and the other end of the fourth switch, and the other end of which is connected to the first input terminal of the first data selector;

[0057] The control terminals of both the first switch and the third switch are connected to an output terminal of the second clock phase flip circuit 6 to receive the control signal VS. <0> The control terminals of both the second and fourth switches are connected to another output terminal of the second clock phase flip circuit 6 to receive the control signal VSN. <0> The control terminal of the fifth switch is connected to one output terminal of the first clock phase flipping circuit 5 to receive the third control signal VS. <1> The control terminal of the sixth switch is connected to another output terminal of the first clock phase flipping circuit 5 to receive the fourth control signal VSN. <1> .

[0058] Based on the above embodiments, in some embodiments, the first switch, second switch, third switch, and fourth switch all employ the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4, respectively, as described above. The fifth switch and sixth switch also employ MOS transistors, with the fifth switch employing the fifth NMOS transistor Q5 and the sixth switch employing the sixth NMOS transistor Q6. While the first, second, third, fourth, fifth, and sixth switches mentioned in this application all employ MOS transistors, and specifically NMOS transistors, in other embodiments of this application, PMOS transistors, transistors, or thyristors, or other devices with switching functions, may also be used. This application merely provides specific examples of the use of NMOS transistors and should not be construed as limiting the scope of this application.

[0059] Furthermore, the gates of both the first NMOS transistor Q1 and the third NMOS transistor Q3 receive the control signal VS. <0> The gates of both the second NMOS transistor Q2 and the fourth NMOS transistor Q4 receive the control signal VSN. <0> The gate of the fifth NMOS transistor Q5 receives the control signal VS. <1> The gate of the sixth NMOS transistor Q6 receives the control signal VSN. <1> .

[0060] like Figure 1 As shown, when the first input terminal of the first data selector MUX1 needs to be connected to the voltage at the connection point of the first resistor R1 and the second resistor R2, the control signal VS... <0> and control signal VS <1> All are high level, control signal VSN <0> and control signal VSN <1> All are at low level. The first NMOS transistor Q1, the third NMOS transistor Q3, and the fifth NMOS transistor Q5 are all turned on, but since the sixth NMOS transistor Q6 is not turned on, the first input terminal of the first data selector MUX1 is connected to the voltage at the connection point of the first resistor R1 and the second resistor R2 through the fifth NMOS transistor Q5 and the first NMOS transistor Q1.

[0061] When the first input terminal of the first data selector MUX1 needs to be connected to the voltage at the connection point of the second resistor R2 and the third resistor R3, the control signal VSN is activated. <0> and control signal VS <1> Both are high level, control signal VS <0> and control signal VSN <1> All are at low level. The second NMOS transistor Q2, the fourth NMOS transistor Q4, and the fifth NMOS transistor Q5 are all turned on, but since the sixth NMOS transistor Q6 is not turned on, the first input terminal of the first data selector MUX1 is connected to the voltage at the connection point of the second resistor R2 and the third resistor R3 through the fifth NMOS transistor Q5 and the second NMOS transistor Q2.

[0062] When the first input terminal of the first data selector MUX1 needs to be connected to the voltage at the connection point of the third resistor R3 and the fourth resistor R4, the control signal VS <0> and control signal VSN <1> All are high level, control signal VSN <0> and control signal VS <1> All are at low level. The first NMOS transistor Q1, the third NMOS transistor Q3, and the sixth NMOS transistor Q6 are all turned on. However, since the fifth NMOS transistor Q5 is not turned on, the first input terminal of the first data selector MUX1 is connected to the voltage at the connection point of the third resistor R3 and the fourth resistor R4 through the sixth NMOS transistor Q6 and the third NMOS transistor Q3.

[0063] When the first input terminal of the first data selector MUX1 needs to be connected to the voltage at the connection point of the fourth resistor R4 and the fifth resistor R5, the control signal VSN is activated. <0> and control signal VSN <1> Both are high level, control signal VS <0> and control signal VS <1> All are at low level. The second NMOS transistor Q2, the fourth NMOS transistor Q4, and the sixth NMOS transistor Q6 are all turned on, but since the fifth NMOS transistor Q5 is not turned on, the first input terminal of the first data selector MUX1 is connected to the voltage at the connection point of the fourth resistor R4 and the fifth resistor R5 through the sixth NMOS transistor Q6 and the fourth NMOS transistor Q4.

[0064] According to some embodiments, such as Figures 1 to 3 As shown, the soft-start circuit 7 further includes a first NAND gate NAND1 and a first flip-flop 4. The output of the first NAND gate NAND1 is connected to the input of the first flip-flop 4. The input of the first NAND gate NAND1 is connected to the outputs of the first clock phase flip circuit 5 and the second clock phase flip circuit 6, respectively, i.e., the control signal VS. <0> and control signal VS <1> The output of the first trigger 4 is connected to the enable pin of the frequency divider 2.

[0065] Based on the above embodiments, such as Figure 2 As shown, frequency divider 2 divides the input clock frequency signal CLK, outputting six frequencies in sequence: 1 / 64, 1 / 128, 1 / 256, 1 / 512, 1 / 1024, and 1 / 2048, which are then fed into multiplexer 1. Multiplexer 1 outputs signals with frequencies differing by a factor of one, such as 1 / 64, 1 / 128, and 1 / 256, which are then fed into the clock circuit and the first flip-flop 4, respectively.

[0066] Furthermore, both the first clock phase flipping circuit 5 and the second clock phase flipping circuit 6 include a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a second flip-flop 15, a second NAND gate NAND2, and a second data selector MUX2. The output of the first inverter INV1 is connected to the input of the second inverter INV2 and the first input of the second data selector MUX2. The output of the second inverter INV2 is connected to the second input of the second data selector MUX2. The third inverter... The input terminal of the third inverter INV3 is connected to the first control terminal of the second data selector MUX2. The output terminal of the third inverter INV3 is connected to the second control terminal of the second data selector MUX2. The output terminal of the second data selector MUX2 is connected to the input terminal of the second NAND gate NAND2 through the fourth inverter INV4. The output terminal of the second NAND gate NAND2 is connected to the input terminal of the second flip-flop 15 through the fifth inverter INV5. The output terminal of the second flip-flop 15 can be used as an output terminal of the first clock phase flip circuit 5 or the second clock phase flip circuit 6, that is, outputting the control signal VS. <0> Or control signal VS <1> The output of the second flip-flop 15, after passing through the sixth inverter, can be used as another output of the first clock phase flip circuit 5 or the second clock phase flip circuit 6, i.e., outputting the control signal VSN. <0> Or control signal VSN <1> .

[0067] Based on the above embodiments, the input terminal VD of the first clock phase reversal circuit 5 is connected to VD. <1> The CP pin is connected to the first clock signal output from multiplexer 1, which has a frequency difference of one clock frequency; the RST pin is connected to the reset signal RST; and the CLK pin is connected to the clock frequency signal CLK. The input terminal VD of the second clock phase flipping circuit 6 is connected to VD. <0> The CP pin is connected to the second clock signal output from multiplexer 1, which has a frequency difference of one clock frequency; the RST pin is connected to the reset signal RST; and the CLK pin is connected to the clock frequency signal CLK. The first clock phase flipping circuit 5 and the second clock phase flipping circuit 6 are connected to VD. <0> and VD <1> Under the control of the signal, the phases of the two input clock signals are flipped, and latched using the undivided clock frequency signal CLK and an internal flip-flop, thus forming a simple configurable counter. The output signal of this counter is VS. <0> and VS <1> The signal is fed into the first NAND gate NAND1, and the gates of the first NMOS transistor Q1, the third NMOS transistor, and the fifth NMOS transistor. The output of the first NAND gate NAND1 is connected to the input of the first flip-flop 4, and the output signal SS_END of the first flip-flop 4 is fed into the frequency divider 2.

[0068] The first clock phase flipping circuit 5 and the second clock phase flipping circuit 6 are controlled by VD to flip the phase of the input clock CP, and the second flip-flop 15 performs sampling and latching. The two clock phase flipping circuits constitute a configurable counter for the digital-to-analog converter circuit, counting from 0 to 3, and sending the count value to the digital-to-analog converter circuit to generate a stepped voltage. In the second stage of soft start, the voltage is adjusted by up to 4 steps. The stepped voltage serves as the reference voltage Vref of the error amplifier U2, ensuring that no current surge or voltage overshoot occurs during the soft start of the converter circuit, and effectively protecting the circuit during the power-on stage.

[0069] The converter of this application embodiment is briefly described below:

[0070] According to some embodiments, such as Figure 4 As shown, this application provides a converter, which includes a soft-start circuit 7 as described above, a feedback circuit, a drive circuit 8, a first output switch, and a second output switch. The reference voltage input terminal of the feedback circuit is connected to the reference voltage Vref output by the first data selector. The output terminal of the feedback circuit is connected to the first input terminal of the drive circuit 8. The output terminal of the drive circuit 8 is connected to the control terminals of the first and second output switches respectively. The input terminal of the first output switch is connected to a power supply, and the output terminal of the first output switch is connected to the input terminal of the second output switch. The output terminal of the second output switch is grounded. The current sampling pin of the feedback circuit is connected to the output terminal of the first output switch, so that after the feedback circuit collects the output current, it outputs a feedback signal to the drive circuit 8 according to the output current. The drive circuit 8 adjusts the operating state of the first and second output switches according to the feedback signal.

[0071] In this application, a BUCK converter is used. In some embodiments, the first output switch is a PMOS transistor Q11, and the second output switch is an NMOS transistor Q12. The drains of the PMOS transistor Q11 and the NMOS transistor Q12 are connected to each other. The drain of the PMOS transistor Q11 outputs the final electrical signal. The feedback circuit collects the final electrical signal output by the drain of the PMOS transistor Q11 and the reference voltage Vref output by the first data selector. After processing, the feedback circuit outputs a feedback signal to the driving circuit 8. The driving circuit 8 adjusts the operating state of the NMOS transistor Q12 and the PMOS transistor Q11 according to the feedback signal.

[0072] The following is in conjunction with the appendix to this instruction manual. Figure 4 The converter of this application will be further described in detail.

[0073] According to some embodiments, the converter further includes a sixth resistor R6, an inductor L, and a capacitor C. The output terminal of the first output switch is connected to one end of the inductor L, the other end of the inductor L is connected to one end of the sixth resistor R6 and the current sampling pin of the feedback circuit, the other end of the sixth resistor R6 is connected to one end of the capacitor C, and the other end of the capacitor is grounded.

[0074] Among them, the inductor L, the sixth resistor R6, and the capacitor C are used for output filtering.

[0075] Furthermore, the converter also includes an overcurrent protection circuit 9 and a current sensor 10. One end of the current sensor 10 is connected to the input terminal of the first output switch and the power supply, and the other end of the current sensor 10 is connected to one end of the overcurrent protection circuit 9. The other end of the overcurrent protection circuit 9 is connected to the second input terminal of the drive circuit 8. When powered on, the overcurrent protection circuit 9 detects the power supply signal through the current sensor 10 and feeds it back to the drive circuit 8. The drive circuit 8 adjusts the working state of the first output switch and the second output switch according to the power supply signal.

[0076] The overcurrent protection circuit 9 detects the current flowing through the PMOS transistor Q11 through the current sensor 10.

[0077] Based on the above embodiments, when the converter is powered on, this application uses the overcurrent protection circuit 9 to charge the capacitor C at the output terminal with a set maximum current. The set maximum current is the maximum current that the output terminal electronic components can withstand. When power is first applied, since the feedback circuit cannot form feedback, the overcurrent protection circuit 9 provides feedback to the drive circuit 8 so that the drive circuit 8 controls the current output by the PMOS transistor Q11 to be within the maximum current range that the output terminal electronic components can withstand.

[0078] According to some embodiments, the feedback circuit includes a sampling resistor, an error amplifier U2, a compensation network 11, a comparator U1, an SR latch 12, and an oscillator 13. The inverting input of the error amplifier U2 is connected to the other end of the inductor and one end of the resistor through the sampling resistor. The non-inverting input of the error amplifier U2 is connected to the reference voltage Vref output by the first data selector. The output of the error amplifier U2 is connected to the compensation network 11 and the inverting input of the comparator U1. The non-inverting input of the comparator U1 is connected to the first output of the oscillator 13. The output of the comparator U1 is connected to the first input of the SR latch 12. The second output of the oscillator 13 is connected to the second input of the SR latch 12 and the soft-start circuit 7. The output of the SR latch 12 is connected to the first input of the drive circuit 8.

[0079] Specifically, oscillator 13 provides CLK_S<1:0> to decoder 3 of soft-start circuit 7, clock frequency signal CLK and reset signal RST to frequency divider 2, first clock phase flip circuit 5, second clock phase flip circuit 6 and first flip-flop 4, and VD to first clock phase flip circuit 5 and second clock phase flip circuit 6. <1> and VD <0> Signal.

[0080] Working Principle: Upon power-up, the voltage across the output capacitor C is zero, meaning the feedback loop is not yet established, and the converter is in an unbalanced state. The PMOS transistor Q11 switches with an extremely high duty cycle, possibly even remaining continuously on, resulting in a high current flow. This triggers the overcurrent protection circuit 9. Under the control of the overcurrent protection circuit 9, the converter periodically switches the PMOS transistor Q11 on and off, rapidly charging the output capacitor C with the maximum current set for the PMOS transistor Q11, causing the output voltage to rise quickly. When the output voltage exceeds the set value I*R5 (where I refers to the reference current source in the analog-to-digital converter circuit, and R is the resistor in the analog-to-digital converter circuit), the voltage output by the error amplifier causes the comparator to flip. The converter then enters the feedback circuit's adjustment phase, and the duty cycle decreases. The converter then exits the overcurrent protection state and enters the step-by-step adjustment phase.

[0081] During the stepped adjustment phase, the counter in the clock circuit continuously increments its count value, which is then fed into the digital-to-analog converter (DAC). Since a large load does not need to be driven, an operational amplifier is not required. The DAC controls the switch based on the count value, selecting the voltage at a specific resistor position to achieve a stepped output reference voltage, as shown in Table 1.

[0082] Table 1

[0083] 00 I*R5 01 I*(R5+R4) 10 I*(R5+R4+R3) 11 I*(R5+R4+R3+R2)

[0084] Configurable Implementation: Before the counter in the clock circuit starts counting, the counting period T and the initial count value can be configured. The counter's clock comes from the frequency divider and multiplexer, so a specific clock frequency can be selected via CLK_S<1:0>, which determines the counting period T. The final count value is VS<1:0> = 11, while the initial count value is set by VD<1:0>. VD<1:0> = 00, the initial count value is 00; VD<1:0> = 01, the initial count value is 01; VD<1:0> = 10, the initial count value is 10; VD<1:0> = 11, the initial count value is 11. This can be summarized in Table 2, as shown in Table 2.

[0085] Table 2

[0086]

[0087] Where VS<1:0> is VS <1> and VS <0> VD<1:0> is VD <1> and VD <0> .

[0088] The number of counting cycles can be set according to actual needs. 0.5*T outputs a voltage of one step for the first data selector MUX1, 1.5*T outputs a voltage of two steps for the first data selector MUX1, 2.5*T outputs a voltage of three steps for the first data selector MUX1, and 3.5*T outputs a voltage of four steps for the first data selector MUX1.

[0089] At the four steps, the voltage at the connection of the first resistor R1 and the second resistor R2, the voltage at the connection of the second resistor R2 and the third resistor R3, the voltage at the connection of the third resistor R3 and the fourth resistor R4, and the voltage at the connection of the fourth resistor R4 and the fifth resistor R5 are all input to the first data selector MUX1.

[0090] When there are three steps, select the voltage input at the three connection points to the first data selector MUX1.

[0091] When there are two steps, select the voltage input at the two connection points to the first data selector MUX1.

[0092] At a step, select a connection voltage input to the first data selector MUX1.

[0093] Choose the number of steps, i.e. the number of counting cycles, based on actual needs.

[0094] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0095] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or substance of this application, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A soft-start circuit, characterized in that, The soft-start circuit includes: A frequency divider, wherein the input terminal of the frequency divider is connected to a clock frequency signal; The circuit comprises a first clock phase flipping circuit, a second clock phase flipping circuit, and a multiplexer. The frequency divider divides the clock frequency signal and outputs it to the multiplexer. The multiplexer processes the divided clock frequency signal and outputs it to the first clock phase flipping circuit and the second clock phase flipping circuit respectively. The input terminals of the first clock phase flipping circuit and the second clock phase flipping circuit are connected to a first control signal. A decoder, wherein the input terminal of the decoder is connected to a second control signal, and the control terminal of the multiplexer is connected to the output terminal of the decoder, so as to allow the decoder to control the operation of the multiplexer; The digital-to-analog converter circuit includes a first clock phase flipping circuit and a second clock phase flipping circuit connected to control the digital-to-analog converter circuit. The reference voltage output by the digital-to-analog converter circuit is further adjusted by adjusting the first control signal and the second control signal. Both the first clock phase flipping circuit and the second clock phase flipping circuit include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a second flip-flop, a second NAND gate, and a second data selector. The output of the first inverter is connected to the input of the second inverter and the first input of the second data selector. The output of the second inverter is connected to the second input of the second data selector. The input of the third inverter is connected to the first control terminal of the second data selector. The output of the third inverter is connected to the second control terminal of the second data selector. The output of the second data selector is connected to the input of the second NAND gate through the fourth inverter. The output of the second NAND gate is connected to the input of the second flip-flop through the fifth inverter. The output of the second flip-flop can be used as one output of the first clock phase flipping circuit or one output of the second clock phase flipping circuit. The output of the second flip-flop after passing through the sixth inverter can be used as another output of the first clock phase flipping circuit or another output of the second clock phase flipping circuit. The input terminal of the first inverter is connected to the output terminal of the multiplexer, and the input terminal of the third inverter and the first control terminal of the second data selector are connected to the first control signal.

2. The soft-start circuit according to claim 1, characterized in that, The digital-to-analog converter circuit includes: A first resistor, a second resistor, and a first switch are provided. One end of the first resistor is connected to a power source, and the other end of the first resistor is connected to one end of the second resistor and one end of the first switch. A third resistor and a second switch, wherein one end of the third resistor is connected to the other end of the second resistor and one end of the second switch, and the other end of the third resistor is grounded; A first data selector, wherein the first input terminal of the first data selector is connected to the other end of the first switch and the other end of the second switch, and the first data selector obtains electrical signals of different voltages through the first switch and the second switch respectively; The second input terminal of the first data selector is used to receive a reference electrical signal, and the first data selector adjusts the output reference voltage according to the input signals of the first input terminal and the second input terminal.

3. The soft-start circuit according to claim 2, characterized in that, The digital-to-analog converter circuit also includes: A fourth resistor and a third switch, wherein one end of the fourth resistor is connected to one end of the third switch and the other end of the third resistor; A fifth resistor and a fourth switch, one end of the fifth resistor is connected to the other end of the fourth resistor and one end of the fourth switch, and the other end of the fifth resistor is grounded; The first input terminal of the first data selector is connected to the other end of the first switch, the other end of the second switch, the other end of the third switch, and the other end of the fourth switch. The first data selector obtains electrical signals of different voltages through the first switch, the second switch, the third switch, and the fourth switch, respectively.

4. The soft-start circuit according to claim 3, characterized in that, The digital-to-analog converter circuit also includes: The fifth switch has one end connected to the other end of the first switch and the other end of the second switch, and the other end of the fifth switch is connected to the first input terminal of the first data selector. A sixth switch, one end of which is connected to the other end of the third switch and the other end of the fourth switch, and the other end of which is connected to the first input terminal of the first data selector; The control terminals of the first switch and the third switch are both connected to one output terminal of the second clock phase flipping circuit. The control terminals of the second switch and the fourth switch are both connected to the other output terminal of the second clock phase flipping circuit. The control terminal of the fifth switch is connected to one output terminal of the first clock phase flipping circuit. The control terminal of the sixth switch is connected to the other output terminal of the first clock phase flipping circuit.

5. The soft-start circuit according to claim 4, characterized in that, The soft-start circuit further includes a first NAND gate and a first flip-flop. The output of the first NAND gate is connected to the input of the first flip-flop. The input of the first NAND gate is connected to one output of the first clock phase flip circuit and one output of the second clock phase flip circuit, respectively. The output of the first flip-flop is connected to the enable pin of the frequency divider.

6. A converter, characterized in that, The converter includes the soft-start circuit as described in claim 5, as well as a feedback circuit, a drive circuit, a first output switch, and a second output switch. The reference voltage input terminal of the feedback circuit is connected to the reference voltage output by the first data selector. The output terminal of the feedback circuit is connected to the first input terminal of the drive circuit. The output terminal of the drive circuit is connected to the control terminals of the first and second output switches respectively. The input terminal of the first output switch is connected to a power supply. The output terminal of the first output switch is connected to the input terminal of the second output switch. The output terminal of the second output switch is grounded. The current sampling pin of the feedback circuit is connected to the output terminal of the first output switch so that after the feedback circuit collects the output current, it outputs a feedback signal to the drive circuit based on the output current. The drive circuit adjusts the operating state of the first and second output switches based on the feedback signal.

7. The converter according to claim 6, characterized in that, The converter also includes a sixth resistor, an inductor, and a capacitor. The output terminal of the first output switch is connected to one end of the inductor, the other end of the inductor is connected to one end of the sixth resistor and the current sampling pin of the feedback circuit, the other end of the sixth resistor is connected to one end of the capacitor, and the other end of the capacitor is grounded.

8. The converter according to claim 7, characterized in that, The converter also includes an overcurrent protection circuit and a current sensor. One end of the current sensor is connected to the input terminal of the first output switch and the power supply, and the other end of the current sensor is connected to one end of the overcurrent protection circuit. The other end of the overcurrent protection circuit is connected to the second input terminal of the drive circuit. When the power is first applied, the overcurrent protection circuit detects the power signal through the current sensor and feeds it back to the drive circuit. The drive circuit adjusts the working state of the first output switch and the second output switch according to the power signal.

9. The converter according to claim 7, characterized in that, The feedback circuit includes a sampling resistor, an error amplifier, a compensation network, a comparator, an SR latch, and an oscillator. The inverting input of the error amplifier is connected to the other end of the inductor and one end of the sixth resistor through the sampling resistor. The non-inverting input of the error amplifier is connected to the reference voltage output by the first data selector. The output of the error amplifier is connected to the compensation network and the inverting input of the comparator. The non-inverting input of the comparator is connected to the first output of the oscillator. The output of the comparator is connected to the first input of the SR latch. The second output of the oscillator is connected to the second input of the SR latch and the soft-start circuit. The output of the SR latch is connected to the first input of the drive circuit.

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