Synchronous rectifier control circuit and method

Abstract

Embodiments of the present disclosure relate to synchronous rectifier control circuits and methods. In one embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes determining a first voltage across a conductive terminal of the SR transistor, asserting a conduction signal when a body diode of the SR transistor conducts current, asserting an off signal when current flowing through the conductive terminal of the SR transistor decreases below a first threshold, generating a gate signal based on an output voltage of the flyback converter and the first voltage, turning on the SR transistor based on the conduction signal and the gate signal, and turning off the SR transistor based on the off signal.

Description

Technical Field

[0001] This disclosure generally relates to an electronic system and method, and in particular embodiments relates to a synchronous rectifier control circuit and method. Background Technology

[0002] Various topologies of switching converters exist, including buck, boost, buck-boost, and flyback converters. Figure 1 A schematic diagram of an exemplary flyback converter 100 is shown. The flyback converter 100 includes a transformer 112, a resistor 104, capacitors 106 and 114, diodes 108 and 116, a transistor 102, and a primary controller 110.

[0003] During normal operation, the primary controller 110 turns the transistor 102 on and off in a known manner to allow the primary current I to flow. p The primary current I flows through the primary winding 112a. p Inducing secondary current I s The current flows through the secondary winding 112b. Diode 116, in conjunction with output capacitor 114, operates as a rectifier to achieve an output voltage V. out It is (for example, a DC voltage with superimposed ripple).

[0004] The topology of the flyback converter 100 is also referred to as an RCD-clamped flyback converter because the converter 100 includes an RCD clamping circuit (formed by components 104, 106, and 108). The purpose of this RCD clamping circuit is to dissipate the energy obtained from the input source and stored in the primary winding during each switching period, energy that is not transferred to the secondary winding due to imperfect coupling between them. This unused energy is often referred to as "leakage inductance energy" because it is assumed to be stored in a portion of the primary inductance that is not coupled to the secondary inductance, which is called the leakage inductance. RCD-clamped flyback converters are typically simple and inexpensive circuits.

[0005] Figure 2 A schematic diagram of an exemplary flyback converter 200 is shown. The flyback converter 200 operates in a similar manner to the flyback converter 100. However, the flyback converter 200 replaces the RCD clamp of the converter 100 with an active clamp formed by a transistor 208 and a capacitor 106. Therefore, the topology of the flyback converter 200 is also referred to as an active clamp flyback (ACF) converter.

[0006] The advantages of the ACF converter include recovering leakage inductor energy to achieve soft switching (ZVS) of transistors 208 and 102, high efficiency (e.g., greater than 93%) achievable through high switching frequencies (e.g., above 200 kHz), and the ability to produce smooth waveforms with low EMI. Summary of the Invention

[0007] According to one embodiment, a method for controlling a synchronous rectifier (SR) transistor in a flyback converter includes: determining a first voltage across a conductive terminal of the SR transistor; asserting a turn-on signal when current flows through the body diode of the SR transistor; asserting a turn-off signal when the current flowing through the conductive terminal of the SR transistor decreases below a first threshold; generating a gating signal based on the output voltage of the flyback converter and the first voltage; turning on the SR transistor based on the turn-on signal and the gating signal; and turning off the SR transistor based on the turn-off signal.

[0008] According to one embodiment, a synchronous rectifier (SR) controller includes: an output terminal configured to couple with a control terminal of an SR transistor of a flyback converter; and an input terminal configured to receive an output voltage of the flyback converter, wherein the SR controller is configured to: determine a first voltage across a conductive terminal of the SR transistor; assert a turn-on signal when the body diode of the SR transistor conducts current; assert a turn-off signal when the current flowing through the conductive terminal of the SR transistor decreases below a first threshold; generate a gating signal based on the output voltage of the flyback converter and the first voltage; turn on the SR transistor based on the turn-on signal and the gating signal; and turn off the SR transistor based on the turn-off signal.

[0009] According to one embodiment, a flyback converter includes: a transformer having a first winding and a second winding; an output terminal coupled to the second winding; a first primary transistor coupled to the first winding; a primary controller having an output coupled to a control terminal of the first primary transistor; a synchronous rectifier (SR) transistor coupled to the second winding; and an SR controller configured to: determine a first voltage across a conductive terminal of the SR transistor; assert a turn-on signal when the body diode of the SR transistor conducts current; assert a turn-off signal when the current flowing through the conductive terminal of the SR transistor decreases below a first threshold; generate a gating signal based on the output voltage at the output terminal and the first voltage; turn on the SR transistor based on the turn-on signal and the gating signal; and turn off the SR transistor based on the turn-off signal. Attached Figure Description

[0010] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 and Figure 2A schematic diagram of an exemplary flyback converter is shown;

[0012] Figure 3A and Figure 3B It shows the relationship with Figure 2 The flyback converter is used as a complementary ACF converter to operate the associated exemplary waveform;

[0013] Figure 4A and Figure 4B It shows the relationship with Figure 2 The flyback converter is used as a non-complementary ACF converter to operate the associated exemplary waveform;

[0014] Figure 5A and Figure 5B A schematic diagram of an ACF converter according to an embodiment of the present invention is shown;

[0015] Figure 5C An embodiment of the invention is shown in Figure 5A The waveform associated with the ACF converter when it operates as a non-complementary ACF converter;

[0016] Figure 6A and Figure 6B An embodiment of the invention is shown with Figure 5A The waveform associated with the SR transistor of the ACF converter;

[0017] Figure 7 An embodiment of the invention is shown for generating control Figure 5A A flowchart illustrating an embodiment of a method for gating signals of an SR transistor;

[0018] Figure 8 An embodiment of the present invention is shown. Figure 5A A schematic diagram of the SR controller;

[0019] Figure 9A and Figure 9B Each of the embodiments of the present invention is shown. Figure 8 A schematic diagram of the gated circuit and the associated waveforms;

[0020] Figure 10 and Figure 11 An embodiment of the invention is shown with respect to operation at full load and light load, respectively. Figure 8 The waveform associated with the SR controller; and

[0021] Figure 12A and Figure 12B Schematic diagrams and associated waveforms of a flyback converter according to an embodiment of the present invention are shown.

[0022] Unless otherwise indicated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. These figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Detailed Implementation

[0023] The manufacture and use of the disclosed embodiments will now be discussed in detail. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of particular ways of manufacturing and using the invention and do not limit the scope of the invention.

[0024] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. Embodiments may be obtained without one or more of these specific details, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail to avoid obscuring different aspects of the embodiments. References to “embodiment” in this description indicate that a particular configuration, structure, or feature associated with that embodiment is included in at least one embodiment. Therefore, phrases such as “in one embodiment” that may appear at different points in this description do not necessarily refer exactly to the same embodiment. Furthermore, specific forms, structures, or features may be combined in any suitable manner in one or more embodiments.

[0025] Embodiments of the present invention will be described in a specific context, such as an ACF converter with synchronous rectification for use in applications such as USB-C Type-PD. Embodiments of the present invention can be used in other types of applications.

[0026] In one embodiment of the invention, the ACF converter operating as a non-complementary ACF converter includes a synchronous rectifier (SR) transistor, which in the main conduction region of the secondary current (t... A During the first conduction period, the secondary current conducts, but in the secondary conduction region (t) of the secondary current... B During this period, the transistor does not conduct electricity. The gate signal (ON_EN) is generated based on the output voltage of the ACF converter and the drain-to-source voltage of the SR transistor, and prevents the SR transistor from conducting when the gate signal is asserted (e.g., low).

[0027] The ACF converter 200 can operate as a complementary ACF converter or as a non-complementary ACF converter. Figure 3A and Figure 3B An exemplary waveform is shown that is associated with operating the converter 200 as a complementary ACF converter.

[0028] like Figure 3A As shown, the signals V that drive transistors 102 and 108 respectivelyG_102 and V G_208 They are switched on and off in a complementary manner. Therefore, when transistor 208 is off, transistor 102 is on, and vice versa. Figure 3B As shown, when voltage V1 is high (when transistor 102 is off and transistor 208 is conducting), the primary current I... p and secondary current I s It has a sinusoidal waveform. When voltage V1 is low (when transistor 102 is conducting and transistor 208 is off), the primary current I... p It has a linear shape, while the secondary current I s It is zero.

[0029] Figure 4A and Figure 4B An exemplary waveform is shown that is associated with operating the converter 200 as a non-complementary ACF converter. For example... Figure 4A and Figure 4B As shown, in the secondary current I s After a period of demagnetization, transistor 208 is turned on to allow the primary current I. p This is increased sufficiently to achieve soft switching. As a result, simultaneous conduction occurs on both the primary and secondary sides of the ACF converter 200.

[0030] In a non-complementary way (e.g., as Figure 4A and Figure 4B The advantages of some embodiments of the ACF converter (e.g., 200) illustrated in the figure include lower RMS current cycling on the primary side, lower power loss, higher efficiency, and ease of management with a wide range of input voltages V. in Range and wide range of output voltages V out This range could be particularly advantageous for applications such as USB power delivery (USB-PD).

[0031] In some embodiments, the rectifier diode 116 is replaced with a transistor controlled to mimic diode behavior, which may advantageously achieve a reduction in power loss and an increase in efficiency.

[0032] Figure 5A A schematic diagram of an ACF converter 500 according to an embodiment of the present invention is shown. The ACF converter 500 includes a transformer 512, capacitors 506 and 514, transistors 502, 508, and 516, a primary controller 510, and a synchronous rectifier (SR) controller 518. Capacitor 506 may be referred to as a clamping capacitor. Transistor 516 may be referred to as a synchronous rectifier (SR) transistor.

[0033] although Figure 5AThe illustration shows an SR transistor 516 arranged on the ground side of the secondary winding 512b, but in some embodiments, the SR transistor 516 may be arranged on the other side of the secondary winding 512b.

[0034] For example, transistors 502, 508, and 512 can be implemented as metal-oxide-semiconductor field-effect transistors (MOSFETs). Other implementations may include using GaN transistors.

[0035] In some embodiments, the main controller 510 is configured in a non-complementary manner (e.g., similar to main controller 210, such as...). Figure 4A and Figure 4B (As shown in the diagram) Operating transistors 508 and 502.

[0036] The main controller 510 can be implemented, for example, with a general-purpose or custom microcontroller or processor, which is coupled to memory and configured to execute instructions stored in memory. In some embodiments, the main controller 510 can be implemented with logic circuitry, such as combinational logic, flip-flops, finite state machines, etc. Other implementations are also possible.

[0037] like Figure 5A As shown, the SR controller 518 can sense the output voltage V out and used to generate voltage V G_516 Drain-to-source voltage V DS_516 The SR controller 518 can be implemented, for example, with a general-purpose or custom microcontroller or processor, which is coupled to memory and configured to execute instructions stored in memory. In some embodiments, the SR controller 518 can be implemented with logic circuitry, such as combinational logic, flip-flops, finite state machines, etc. Other implementations are also possible.

[0038] Figure 5B A schematic diagram of an ACF converter 500 according to an embodiment of the present invention is shown, illustrating a model for the primary winding 512a. For example... Figure 5B As shown, the primary winding 512a can be modeled using inductors 512c, 512d, and 512e.

[0039] Figure 5C The diagram illustrates a waveform associated with the ACF converter 500 operating as a non-complementary ACF converter according to an embodiment of the present invention. It can be based on... Figure 5B To understand Figure 5C .

[0040] like Figure 5C As shown, in time period t chargeDuring this period, transistor 502 is turned on, transistor 508 is turned off, and the primary current I... p And the magnetizing current Im increases. Once transistor 502 is turned off, the clamping current I... clamp The surge, and the secondary current I s Increase until the primary current I p It drops to zero, then the secondary current I s It begins to decrease until the magnetizing current I... m It drops to zero. For example... Figure 5C As shown, the secondary current I s During time period t A The period is non-zero.

[0041] During time period t C During this period, the drain-to-source voltage (V) of transistor 502 DS_502 ) and the drain-to-source voltage (V) of transistor 516 DS_516 The primary current I resonates until transistor 508 is turned on. Once transistor 508 is turned on, the primary current I... p Magnetizing current Im and clamping current I clamp It begins to drop below zero, while the secondary current I... s It starts increasing until transistor 502 is turned on.

[0042] like Figure 5C As shown, during the time transistor 502 is off, there is a secondary current I. s Two conductive intervals (time period t) A and t B Conductivity range t A This can be referred to as the main conduction region. When transistor 508 is turned on to allow reverse current (I0) to flow... clamp When the flow occurs, a conductive region t appears. B (Also known as the secondary conductivity region). Therefore, at t B During this period, simultaneous conduction occurs on both the primary and secondary sides of converter 500. Although during time period t... B Secondary current I during the period s The current peak is relatively high and may be related to the time period t. A Secondary current I during the period s The current peaks are similar, but the time interval t is different. B The duration is longer than the time period t A The duration is shorter.

[0043] In some embodiments, at full load (maximum I load When ), the time period t A and t B The time between them is approximately zero (t) C≈O). As the load decreases (e.g., from maximum I... load (Start), for example, time period t C Increase to reduce switching frequency and increase efficiency under light load.

[0044] In some embodiments, it is desirable to have a time period t A During the period t, the SR transistor 516 is turned on, but during the time period t B During this period, it is not conductive. Therefore, in some embodiments, the secondary current I... s During time period t A During this period, the current path flowing through transistor 516, and in time period t B During this period, current flows through the body diode of transistor 516. This is achieved by allowing current I... s During time period t A During the current path flowing through transistor 516, some embodiments advantageously reduce conductivity losses. In some embodiments, by […] during time period t B By keeping transistor 516 off during this period, some embodiments advantageously reduce noise and EMI, allow for a less complex implementation of the SR controller 518, and / or advantageously avoid (e.g., when during time period t) B When transistor 516 ends, a hard switch of transistor 516 occurs. In some embodiments, such as those operating at frequencies above 200 kHz, this is related to the hard switching of transistor 516 during time period t. B Compared to transistor 516, this avoids transistor 516 being in operation during time period t. B Hard switching during this period can advantageously result in lower power consumption.

[0045] The inventor realized that, corresponding to the time period t A voltage V DS_516 The negative edge is higher than V out The voltage begins, corresponding to the time period t. B voltage V DS_516 The negative edge is from below or equal to V out The voltage begins. For example, Figure 6A and Figure 6B The diagram illustrates waveforms associated with the SR transistor 516 of the ACF converter 500 under full load and light load conditions, respectively, according to an embodiment of the present invention. This can be understood based on Figure 5. Figure 6A and Figure 6B .

[0046] Understandable Figure 6A and Figure 6B The diagram illustrates the output voltage V outThis is a specific example of an embodiment that operates at 20V. Other output voltages may also be used, such as below 20V (e.g., 18V, 13V, 12V, 10V, 5V or lower) or above 20V (e.g., 25V or higher).

[0047] like Figure 6A and Figure 6B As shown, corresponding to the time period t A The voltage V (when transistor 516 is turned on) DS_516 The negative edge is higher than the output voltage V out voltage (V) peak (Starting). For example, in some embodiments, the voltage V peak It can be given by the following formula:

[0048]

[0049] Where n represents the turns ratio of transformer 512.

[0050] Corresponding to time period t B (When the secondary current I) s The voltage V (when the transistor 516 remains off) is increased. DS_516 The negative edge starts from below or equal to the output voltage V. out The voltage begins.

[0051] The inventors also realized that, corresponding to the time period t A The voltage V (when transistor 502 is off) DS_516 The descent time (in) Figure 6B The diagram shows the time period t. f Significantly smaller than in time period t C During the period from voltage V DS_516 Peak-to-voltage V out The time elapsed at the intersection (in Figure 6B The diagram shows the time period t. r Time period t r Corresponding to voltage V DS_516 The ringing (resonance) time period .

[0052] In some embodiments, the descent time t f At least compared to the time period t r A smaller order of magnitude. For example, in one embodiment, the voltage V DS_516 The ringing time period is approximately 840 ns, therefore the time period t r It is approximately 210 ns, while the fall time t f It is approximately 20 ns.

[0053] In some embodiments, the SR transistor 516 only operates at voltage V DS_516 The negative edge starts from above (1+k)·V out The voltage starts at a higher level than expected at t. f and t r The predetermined threshold between time intervals allows the output voltage V to cross faster. out The transistor 516 is turned on when the voltage is low. In some embodiments, a gate signal (ON_EN) is used to prevent the transistor 516 from turning on when asserted (e.g., low) and to allow the transistor 516 to turn on when deasserted (e.g., high).

[0054] Figure 7 A flowchart of an embodiment method 700 for generating a gate signal ON_EN for controlling an SR transistor 516, according to an embodiment of the present invention, is shown. The gate signal ON_EN can be used to prevent the SR transistor 516 from turning on when the gate signal ON_EN is asserted (e.g., low), and to allow the SR transistor 516 to turn on when the gate signal ON_EN is deasserted (e.g., high). In some embodiments, a conventional SR controller can be modified to receive the gate signal ON_EN, thereby preventing the SR transistor from turning on when the gate signal ON_EN is asserted (e.g., low), while keeping the remaining on / off logic of the SR controller unchanged.

[0055] During step 702, the reference voltage V ref Generated / set to be higher than the output voltage V out The value of . For example, in some embodiments, the reference voltage V ref It is given by the following formula:

[0056] V ref = (1+k)·V out (2)

[0057] Where k is a number greater than 0. For example, in some embodiments, k may have a value between 0.2 and 0.5. In some embodiments, the reference voltage V ref It can be given by the following formula:

[0058]

[0059] During step 704, the drain-to-source voltage (V) of transistor 516 is... DS_516 ) and reference voltage V ref Compare. When voltage V DS_516 Higher than the reference voltage V ref When the gated signal ON_EN is de-asserted (e.g., high), the assertion is cancelled.

[0060] After the gate signal ON_EN is de-asserted (e.g., high), during step 708, the drain-to-source voltage (V) of transistor 516 is... DS_516 ) and reference voltage V ref Compare. When voltage V DS_516 Below the reference voltage V ref During step 712, during the waiting time t d (During step 710) after which the gate signal ON_EN is asserted (e.g., high), where the waiting time t d With a duration t between the expected descent time and the actual descent time f With time period t r The duration between durations.

[0061] In some embodiments, the waiting time t d (also known as delay time t) d For example, it could be 100ns. Other values ​​can also be used, such as 90ns, 80ns or lower, or 110ns, 150ns or higher. In some embodiments, the waiting time t... d It can be given by the following formula:

[0062]

[0063] Where t ring Indicates time t C Voltage V during the period DS_516 The ringing (resonance) time period.

[0064] In some embodiments, since the gated signal ON_EN is within a certain time frame (descent time t), f A longer time period t d The assertion is cancelled within (step 706), and the SR transistor 516 is turned on during time period t. A It is not gated during this period. In some embodiments, due to voltage V DS_516 Increased but still far below the output voltage V out (Output "No" during step 704) when operating at full load (e.g., as Figure 6A As shown in the figure, the SR transistor 516 is turned on during the time period t. B During this period, it is gated (blocked). In some embodiments, when operating under light load (e.g., as... Figure 6B As shown in the figure, because the gate signal ON_EN is in the time period t f Shorter time period t d It is then asserted (step 712) that the SR transistor 516 is turned on during time period t. B The first (or first few) valley periods are gated (blocked). In some embodiments, when operating under light load (e.g., as Figure 6B As shown in the figure, due to voltage V DS_516 Keep below the output voltage V out (No is output during step 704), the SR transistor 516 is turned on during time period t. B The first (or first few) valleys are then gated (blocked).

[0065] Figure 8 A schematic diagram of an SR controller 800 according to an embodiment of the present invention is shown. The SR controller 800 includes comparators 802 and 804, AND gates 808 and 810, a flip-flop 814, a blanking circuit 816, and a gating circuit 822. An SR controller 518 can be implemented as the SR controller 800.

[0066] Comparator 802 is configured to detect when the body diode of transistor 516 conducts (thus detecting the secondary current I). s (Greater than zero). When the voltage V DS_516 The voltage drops below the threshold voltage V th_on At that time, the output signal S of comparator 802 turn_on Assertioned (high). In some embodiments, the threshold voltage V th_on For example, -0.3V. Other threshold voltages can also be used.

[0067] Comparator 804 is configured to detect secondary current I s When it drops to zero. In some embodiments, such detection is achieved based on the on-resistance of transistor 516, which acts as a sensor for the secondary current I. s The current sensor is used for operation. For example, in some embodiments, when the voltage V... DS_516 Exceeding the threshold voltage V th_off At that time, signal S turn_off Assertioned (high). In some embodiments, the threshold voltage V th_off It is approximately 0V, such as 0.5mV. Other threshold voltages can also be used.

[0068] The gate circuit 822 is configured based on the output voltage V out and voltage V DS_516 To generate the gate signal ON_EN. For example, in some embodiments, the gate circuit 822 generates the gate signal ON_EN according to method 700.

[0069] The blanking circuit 816 is configured to be powered by voltage V G_516 Triggered by the rising and falling edges (i.e., whenever the voltage V... G_516 (When the state changes). The blanking circuit 816 is configured to generate (whenever the blanking circuit 816 is triggered) a duration of t. d1(Also known as the blanking time, or t) Blank The negative pulse is used to prevent AND gates 808 and 810 from being interrupted at t. d1 The assertion is cancelled during the period. In some embodiments, the time period t d1 For example, 300ns. t can also be used. d1 Other values. In some embodiments, the blanking circuit 816 may be implemented in any manner known in the art.

[0070] like Figure 8 As shown, during normal operation, when the body diode of transistor 516 conducts, signal S turn_on The assertion is made (e.g., high). However, the flip-flop 814 only deasserts the gate signal ON_EN (e.g., high) and the blanking signal S blank When the assertion is cancelled (e.g., high), signal S turn_on It is only set when asserted.

[0071] When the secondary current I s When it drops to zero, signal S turn_off It is asserted (e.g., high). However, the flip-flop 814 only applies to the blanking signal S. blank When asserted (e.g., high), signal S turn_off It is only reset when asserted.

[0072] In some embodiments, comparators 802 and 804 may be implemented in any manner known in the art. For example, in some embodiments, such as... Figure 8 As shown in the diagram, comparators 802 and 804 can be implemented using hysteresis.

[0073] In some embodiments, flip-flop 814 is configured to be set (high) based on the output of AND gate 808 and reset (low) based on the output of AND gate 810. Flip-flop 814 may be implemented in any manner known in the art.

[0074] Figure 9A and Figure 9B Schematic diagrams and associated waveforms of a gate circuit 900 according to an embodiment of the present invention are shown. The gate circuit 900 includes a comparator 906, an OR gate 912, a multiplier 918, and a delay circuit 920. A gate circuit 822 can be implemented as the gate circuit 900.

[0075] In some embodiments, the multiplier 918 is configured to multiply the output voltage V out Multiply by (1+k) to generate (e.g., step 702) the reference voltage V ref(For example, according to Equation 2). The multiplier 918 can be implemented in any manner known in the art, such as using an analog amplifier. In some embodiments, the reference voltage V ref It can be generated in other ways, such as according to Formula 3.

[0076] In some embodiments, comparator 906 pairs (e.g., step 704) voltage V ref and V D_516 Compare, and at voltage V DS_516 Higher than voltage V ref Time assertion signal S 906 Comparator 906 can be implemented in any manner known in the art. For example, in some embodiments, such as... Figure 9A As shown in the diagram, comparator 906 can be implemented using hysteresis.

[0077] In some embodiments, the delay circuit 920 is configured to delay the signal S 906 Delay time t d , where t d As given by, for example, Equation 4. Therefore, signal S 920 In signal S 906 t after being asserted (high) d The assertion (high) is made within a time period, and in signal S 906 t after the assertion is cancelled (low) d The assertion is cancelled within a certain time (low). In some embodiments, the delay circuit 920 may be implemented in any manner known in the art.

[0078] As in Figure 9A As can be seen, the delay circuit 920 and the OR gate 912 execute steps 706, 708, 710, and 712. For example, as... Figure 9B As shown in, when the signal S 906 When asserted (high), the gated signal ON_EN is deasserted (high), and the signal S... 906 Duration t after the assertion (low) is cancelled d The internal gating signal ON_EN is held to cancel the assertion (high).

[0079] Figure 10 and Figure 11 Waveforms are shown associated with an SR controller 800, which implements a gate circuit 822 as a gate circuit 900, operating under full load and light load respectively, according to an embodiment of the present invention. Figure 10 and Figure 11 In the embodiment shown, converter 500 operates as a non-complementary ACF converter, with an output voltage V. out 20V, blanking time t BlankThe value is 300 ns, and k is 0.4, therefore V ref =1.4V out . Figure 10 and Figure 11 The diagram also illustrates the voltage V. DS_516 From above V ref The voltage exceeds the output voltage V out The time window t starts at time d .

[0080] like Figure 10 As shown, at time t1 (in time interval t) A At the beginning), the gate signal ON_EN is high (because it is high at delay time t). d (inner), and blanking signal S blank It is high (because no voltage V appeared during the 300ns immediately preceding time t1). G_516 (State transition). Due to signals ON_EN and S blank All are high, so signal S turn_on The voltage V is propagated through AND gate 808 to flip-flop 814, causing the voltage V to... G_516 The SR transistor 516 is turned on by transitioning from low to high. Therefore, the SR transistor 516 conducts during time period t. A Conductivity was maintained during this period.

[0081] like Figure 10 As shown, at time t2, the gate signal ON_EN is low (because the voltage V DS_516 The voltage V has not yet been increased. ref (above), and the blanking time is low (because the voltage V) G_516 The signal transitions from high to low within a period of less than 300 ns before time t2. This is due to the blanking signal S. blank Since both the gate signal ON_EN and the signal S are low, the signal S... turn_on The propagation to flip-flop 814 is blocked, and therefore SR transistor 516 is blocked in time period t. B The deadline remains in effect.

[0082] like Figure 11 As shown, at time t3 (in time interval t) A At the beginning of the process, the gate signal ON_EN is high (because it is high during the delay time t). d (inner), and blanking signal S blank It is high (because no voltage V appears in the 300ns immediately preceding time t1). G_516 (State transition). Due to signals ON_EN and S blank All are high, so signal S turn_on The voltage V is propagated through AND gate 808 to flip-flop 814, causing the voltage V to... G_516The SR transistor 516 is turned on by transitioning from low to high. Therefore, the SR transistor 516 conducts during time period t. A Conductivity was maintained during this period.

[0083] like Figure 11 As shown, at time t4, the gate signal ON_EN is low (because even if the voltage V DS_516 Increase to voltage V ref Above, time t4 occurs during voltage V DS_516 Exceeding the output voltage V out After that, it exceeded t d During the time period), and the blanking time is high (because no voltage V appears during the 300ns period immediately preceding time t1). G_516 (State transition). Because the gate signal ON_EN is low, signal S turn_on The propagation to flip-flop 814 is blocked, thus preventing the SR transistor 516 from propagating during time period t. B The deadline remains in effect.

[0084] In some embodiments, the SR controller 800 can be advantageously used (e.g., without modification) for other types of flyback topologies. For example, Figure 12A and Figure 12B Schematic diagrams and associated waveforms of a flyback converter 1200 according to an embodiment of the present invention are shown. The flyback converter 1200 is an RCD-clamped flyback converter that implements an SR transistor 516, and uses an SR controller 800 to implement a gating circuit 822 as a gating circuit 900 to control the SR transistor 516.

[0085] Figure 12B The waveform shown in the figure is associated with a flyback converter 1200 operating in DCM mode, where the output voltage V out 20V, blanking time t Blank Given 300 ns and k equals 0.4, therefore V ref =1.4V out .like Figure 12B As shown, the SR controller 800 turns the transistor 516 on and off at the expected time for accurate DCM operation.

[0086] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims set forth herein.

[0087] Example 1. A method for controlling a synchronous rectifier (SR) transistor in a flyback converter, the method comprising: determining a first voltage across a conductive terminal of the SR transistor; asserting a turn-on signal when current flows through the body diode of the SR transistor; asserting a turn-off signal when the current flowing through the conductive terminal of the SR transistor decreases below a first threshold; generating a gating signal based on the output voltage of the flyback converter and the first voltage; turning on the SR transistor based on the turn-on signal and the gating signal; and turning off the SR transistor based on the turn-off signal.

[0088] Example 2. The method according to Example 1, wherein generating the gating signal includes: determining a reference voltage based on the output voltage; canceling the assertion of the gating signal when the first voltage increases above the reference voltage; and when the gating signal is canceled, comparing the first voltage with the reference voltage and asserting the gating signal after a first delay time following the first voltage falling below the reference voltage.

[0089] Example 3. The method according to one of Example 1 or Example 2, wherein turning on the SR transistor includes turning on the SR transistor when the turn-on signal is asserted and the gate signal is deasserted.

[0090] Example 4. The method according to one of Examples 1 to 3, wherein the first delay time is less than one-quarter of the ringing time of the first voltage.

[0091] Example 5. The method described according to one of Examples 1 to 4, wherein the first delay time is between 20 ns and 210 ns.

[0092] Example 6. The method according to one of Examples 1 to 5, wherein the reference voltage is given by the following formula:

[0093] V ref = (1+k)·V out ,

[0094] Where V ref Indicates the reference voltage, V out This represents the output voltage, and k is a number higher than 0.

[0095] Example 7. The method described according to one of Examples 1 through 6, where k is between 0.2 and 0.5.

[0096] Example 8. The method according to one of Examples 1 to 7, wherein generating the gated signal includes using a gated circuit comprising: a first comparator having a first input for receiving a first voltage and a second input for receiving a reference voltage; a delay circuit having an input coupled to the output of the first comparator having a delay time equal to a first delay time; and an OR gate having a first input coupled to the output of the first comparator, a second input coupled to the output of the delay circuit, and an output for providing the gated signal.

[0097] Example 9. The method according to one of Examples 1 to 8 further includes generating a blanking signal based on a first voltage, wherein turning on the SR transistor is also based on the blanking signal, and turning off the SR transistor is also based on the blanking signal.

[0098] Example 10. The method according to one of Examples 1 to 9, wherein the assertion turn-on signal includes an assertion turn-on signal when the first voltage drops below a second threshold, and wherein the assertion turn-off signal includes an assertion turn-off signal when the first voltage increases above a third threshold.

[0099] Example 11. The method according to one of Examples 1 to 10 further includes operating the flyback converter as a non-complementary active clamp flyback (ACF) converter.

[0100] Example 12. The method according to one of Examples 1 to 11 further includes operating the flyback converter as an RCD-clamped flyback converter in discontinuous conduction mode (DCM).

[0101] Example 13. A synchronous rectifier (SR) controller includes: an output terminal configured to couple to a control terminal of an SR transistor of a flyback converter; and an input terminal configured to receive an output voltage of the flyback converter, wherein the SR controller is configured to: determine a first voltage across a conductive terminal of the SR transistor; assert a turn-on signal when the body diode of the SR transistor conducts current; assert a turn-off signal when the current flowing through the conductive terminal of the SR transistor decreases below a first threshold; generate a gating signal based on the output voltage of the flyback converter and the first voltage; turn on the SR transistor based on the turn-on signal and the gating signal; and turn off the SR transistor based on the turn-off signal.

[0102] Example 14. The SR controller according to Example 13, wherein the SR controller is configured to generate a gating signal by: determining a reference voltage based on the output voltage; canceling the assertion of the gating signal when a first voltage increases above the reference voltage; and when the gating signal is canceled, comparing the first voltage with the reference voltage and asserting the gating signal after a first delay time following a drop in the first voltage below the reference voltage.

[0103] Example 15. An SR controller according to one of Examples 13 or 14, wherein the SR controller is configured to turn on the SR transistor when an on signal is asserted and a gating signal is deasserted.

[0104] Example 16. The SR controller according to one of Examples 13 to 15 further includes a gating circuit configured to generate a gating signal, the gating circuit comprising: a first comparator having a first input configured to receive a first voltage and a second input configured to receive a reference voltage; a delay circuit having an input coupled to the output of the first comparator having a delay time equal to a first delay time; and an OR gate having a first input coupled to the output of the first comparator, a second input coupled to the output of the delay circuit, and an output configured to provide the gating signal.

[0105] Example 17. The SR controller according to one of Examples 13 to 16 further includes: a turn-on circuit configured to generate a turn-on signal; a turn-off circuit configured to generate a turn-off signal; a first AND gate having a first input coupled to the output of the turn-on circuit and a second input coupled to the output of the OR gate; and a first flip-flop having a first input coupled to the output of the first AND gate, a second input coupled to the output of the turn-off circuit, and an output coupled to an output terminal.

[0106] Example 18. The SR controller according to one of Examples 13 to 17 further includes: a blanking circuit having an input coupled to the output of a first flip-flop; and a second AND gate having a first input coupled to the output of the blanking circuit, a second input coupled to the output of a cutoff circuit, and an output coupled to the second input of the first flip-flop, wherein the first AND gate includes a third input coupled to the output of the blanking circuit.

[0107] Example 19. An SR controller according to one of Examples 13 to 18, wherein the turn-on circuit includes a second comparator having a first input configured to receive a second threshold and a second input configured to receive a first voltage; and wherein the cut-off circuit includes a third comparator having a first input configured to receive a third threshold and a second input configured to receive a first voltage.

[0108] Example 20. A flyback converter includes: a transformer having a first winding and a second winding; an output terminal coupled to the second winding; a first primary transistor coupled to the first winding; a primary controller having an output coupled to a control terminal of the first primary transistor; a synchronous rectifier (SR) transistor coupled to the second winding; and an SR controller configured to: determine a first voltage across a conductive terminal of the SR transistor; assert an on signal when the body diode of the SR transistor conducts current; assert an off signal when the current flowing through the conductive terminal of the SR transistor decreases below a first threshold; generate a gating signal based on the output voltage at the output terminal and the first voltage; turn on the SR transistor based on the on signal and the gating signal; and turn off the SR transistor based on the off signal.

[0109] Example 21. The flyback converter according to Example 20 further includes a second primary transistor coupled to a second winding, wherein a primary controller is configured to control the first and second primary transistors to operate the flyback converter as a non-complementary active clamp flyback (ACF) converter.

[0110] Example 22. A flyback converter according to one of Examples 20 or 21, further comprising a resistor coupled to a first winding, a capacitor coupled in parallel with the resistor, and a diode coupled between a first primary transistor and the capacitor, wherein a primary controller is configured to control the first primary transistor to operate the flyback converter as an RCD-clamped flyback converter in discontinuous conduction mode (DCM).

[0111] Example 23. A flyback converter according to one of Examples 20 to 22, wherein the SR transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET) or a GaN transistor.

[0112] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for controlling a synchronous rectifier (SR) transistor in a flyback converter, the method comprising: Determine the first voltage across the conductive terminals of the SR transistor; When the body diode of the SR transistor conducts current, the conduction signal is activated; When the current flowing through the conductive terminal of the SR transistor decreases below a first threshold, the cutoff signal is activated. A gating signal is generated based on the output voltage of the flyback converter and the first voltage, wherein generating the gating signal includes: The reference voltage is determined based on the output voltage; When the first voltage increases above the reference voltage, the gating signal is disabled; and When the gating signal is invalidated, the first voltage is compared with the reference voltage, and the gating signal is made active after a first delay time after the first voltage drops below the reference voltage. The SR transistor is turned on based on the turn-on signal and the gate signal; and The SR transistor is turned off based on the cutoff signal.

2. The method of claim 1, wherein turning on the SR transistor includes turning on the SR transistor when the turn-on signal is activated and the gating signal is deactivated.

3. The method of claim 1, wherein the first delay time is less than one-quarter of the ringing time of the first voltage.

4. The method of claim 1, wherein the first delay time is between 20 ns and 210 ns.

5. The method of claim 1, wherein the reference voltage is given by the following formula: ， Where V ref V represents the reference voltage. out This represents the output voltage, and k is a number higher than 0.

6. The method of claim 5, wherein k is between 0.2 and 0.

5.

7. The method of claim 1, wherein generating the gating signal includes using a gating circuit, the gating circuit comprising: A first comparator has a first input for receiving the first voltage and a second input for receiving the reference voltage; A delay circuit having an input coupled to the output of the first comparator, the delay circuit having a delay time equal to the first delay time; as well as The OR gate has a first input coupled to the output of the first comparator, a second input coupled to the output of the delay circuit, and an output for providing the gate signal.

8. The method of claim 1, further comprising generating a blanking signal based on the first voltage, wherein turning on the SR transistor is also based on the blanking signal, and wherein turning off the SR transistor is also based on the blanking signal.

9. The method of claim 1, wherein activating the turn-on signal comprises activating the turn-on signal when the first voltage drops below a second threshold, and wherein activating the cut-off signal comprises activating the cut-off signal when the first voltage increases above a third threshold.

10. The method of claim 1, further comprising operating the flyback converter as a non-complementary active clamp flyback ACF converter.

11. The method of claim 1, further comprising operating the flyback converter as an RCD-clamped flyback converter in discontinuous conduction mode (DCM).

12. A synchronous rectifier (SR) controller, comprising: The output terminal is configured to be coupled to the control terminal of the SR transistor of the flyback converter; as well as An input terminal is configured to receive the output voltage of the flyback converter, wherein the SR controller is configured to: Determine the first voltage across the conductive terminals of the SR transistor; When the body diode of the SR transistor conducts current, the conduction signal is activated; When the current flowing through the conductive terminal of the SR transistor decreases below a first threshold, the cutoff signal is activated. A gating signal is generated based on the output voltage of the flyback converter and the first voltage, wherein the SR controller is configured to generate the gating signal in the following manner: The reference voltage is determined based on the output voltage; When the first voltage increases above the reference voltage, the gating signal is disabled; as well as When the gating signal is invalidated, the first voltage is compared with the reference voltage, and the gating signal is made active after a first delay time after the first voltage drops below the reference voltage. The SR transistor is turned on based on the turn-on signal and the gate signal; as well as The SR transistor is turned off based on the cutoff signal.

13. The SR controller of claim 12, wherein the SR controller is configured to turn on the SR transistor when the turn-on signal is activated and the gating signal is deactivated.

14. The SR controller of claim 12, further comprising a gating circuit configured to generate the gating signal, the gating circuit comprising: A first comparator has a first input configured to receive the first voltage and a second input configured to receive the reference voltage; A delay circuit having an input coupled to the output of the first comparator, the delay circuit having a delay time equal to the first delay time; as well as The OR gate has a first input coupled to the output of the first comparator, a second input coupled to the output of the delay circuit, and an output configured to provide the gated signal.

15. The SR controller according to claim 14, further comprising: A conduction circuit is configured to generate the conduction signal; A cutoff circuit is configured to generate the cutoff signal; The first AND gate has a first input coupled to the output of the conducting circuit and a second input coupled to the output of the OR gate; as well as The first flip-flop has a first input coupled to the output of the first AND gate, a second input coupled to the output of the cutoff circuit, and an output coupled to the output terminal.

16. The SR controller of claim 15, further comprising: A blanking circuit having an input coupled to the output of the first flip-flop; as well as The second AND gate has a first input coupled to the output of the blanking circuit, a second input coupled to the output of the cutoff circuit, and an output coupled to the second input of the first flip-flop, wherein the first AND gate includes a third input coupled to the output of the blanking circuit.

17. The SR controller of claim 15, wherein the turn-on circuit includes a second comparator having a first input configured to receive a second threshold and a second input configured to receive the first voltage; and wherein the turn-off circuit includes a third comparator having a first input configured to receive a third threshold and a second input configured to receive the first voltage.

18. A flyback converter, comprising: A transformer has a first winding and a second winding; The output terminal is coupled to the second winding; The first primary transistor is coupled to the first winding; A primary controller having an output coupled to the control terminal of the first primary transistor; The synchronous rectifier SR transistor is coupled to the second winding; as well as The SR controller is configured as follows: Determine the first voltage across the conductive terminals of the SR transistor; When the body diode of the SR transistor conducts current, the conduction signal is activated; When the current flowing through the conductive terminal of the SR transistor decreases below a first threshold, the cutoff signal is activated. A gating signal is generated based on the output voltage at the output terminal and the first voltage, wherein the SR controller is configured to generate the gating signal in the following manner: The reference voltage is determined based on the output voltage; When the first voltage increases above the reference voltage, the gating signal is disabled; as well as When the gating signal is invalidated, the first voltage is compared with the reference voltage, and the gating signal is made active after a first delay time after the first voltage drops below the reference voltage. The SR transistor is turned on based on the turn-on signal and the gate signal; as well as The SR transistor is turned off based on the cutoff signal.

19. The flyback converter of claim 18, further comprising a second primary transistor coupled to the second winding, wherein the primary controller is configured to control the first primary transistor and the second primary transistor to operate the flyback converter as a non-complementary active clamp flyback ACF converter.

20. The flyback converter of claim 18, further comprising a resistor coupled to the first winding, a capacitor coupled in parallel with the resistor, and a diode coupled between the first primary transistor and the capacitor, wherein the primary controller is configured to control the first primary transistor to operate the flyback converter as an RCD-clamped flyback converter in discontinuous conduction mode (DCM).

21. The flyback converter of claim 18, wherein the SR transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET) or a GaN transistor.

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