A low phase noise multi-core oscillator, chip and device

Abstract

The embodiment of the application discloses a kind of low phase noise multi-core oscillator, chip and equipment, n pair P type cross transistor pair and N type cross transistor pair, first capacitor C D , second capacitor C C , inductance of mutual coupling is 2n, resistance network, first capacitor C D It is connected at the two ends of cross transistor, second capacitor C C It is connected between N type cross transistor pair and P type cross transistor pair, first group n inductance and another group n inductance cross coupling together, one N type transistor and one P type transistor are connected at the two ends of each inductance, and each inductance center tap is connected by resistance network.Adopting differential capacitor control common mode and differential mode resonant frequency, avoid single-end capacitor to the deterioration of common mode and differential mode quality factor. The magnetic coupling between inductance does not work on common mode state, so as not to deteriorate common mode inductance quality factor. In the case of same capacitor ratio, the quality factor of common mode and differential mode of inductance is improved.

Description

Technical Field

[0001] This application relates to the field of oscillator technology, specifically to a low phase noise multi-core oscillator, chip, and device. Background Technology

[0002] An LC oscillator is a commonly used type of oscillator on chips for generating high-frequency signals. An LC oscillator consists of an inductor L, a capacitor C, and an active transistor (MOSFET or bipolar transistor). The inductor and capacitor form an LC resonator, whose resonant frequency is... The transistor provides negative resistance, which offsets the resonator's losses by consuming power, thus allowing the oscillator to oscillate continuously at frequency f0, achieving signal output. (Simplified oscillator schematic, resonator resonant point diagram, oscillator output shown...) Figure 1 As shown. To support the high spectral purity requirements of modern wireless communication systems and radar systems, the phase noise of the oscillator needs to be very low. Two important determinants of the oscillator's phase noise are the quality factor Q of the LC resonator (the higher the quality factors of both inductor L and capacitor C, the higher the quality factor of the resonator; the relationship is Q = Q...). L Q C / (Q L +Q C (Higher Q values ​​correspond to lower phase noise and the oscillator's noise sensitivity characteristics.)

[0003] On-chip oscillator designs typically employ a differential configuration. The oscillation signals at both ends of the oscillator are differential, allowing the capacitor to be connected in two ways: a single-ended capacitor, as shown below. Figure 2 C C One end of the capacitor is grounded or connected to a fixed potential, similar to a differential capacitor. Figure 2 C D The capacitor is connected to a differential signal. The quality factor Q of the differential capacitor is... C Greater than the single-ended capacitance. An implicit common-mode resonant oscillator, its schematic diagram is shown below. Figure 3 As shown. It includes cross-coupled transistors, mutually coupled inductors, single-ended capacitors, and differential capacitors. The differential-mode equivalent inductance of this circuit is (1+k)L, and the differential-mode equivalent capacitance is C. D +C C The common-mode equivalent inductance is (1-k)L, and the common-mode equivalent capacitance is C. C This circuit controls the ratio of the single-ended capacitor to the differential capacitor and the coupling coefficient k between the inductors to achieve the common-mode resonant frequency f of the resonator. CM The differential mode resonant frequency f DMThis is twice the value of the common-mode waveform. At this point, a better common-mode waveform shaping effect can be obtained, reducing the oscillator's noise sensitivity and thus optimizing phase noise. To control the common-mode resonant frequency of the resonator, this scheme requires the use of a single-ended capacitor and the self-coupling of an inductor. The common-mode and differential-mode quality factors of a single-ended capacitor are both poor. On the other hand, the coupling coefficient of the inductor will improve the inductor quality factor Q in the differential-mode resonance. L_DM =Q L (1+k), but at the same time it will worsen the quality factor of the inductor in the common-mode resonance, making Q L_CM =Q L (1-k). Therefore, the phase noise of this scheme is limited. The higher the frequency of the oscillator, the more severe the degradation of the quality factor of the single-ended capacitor.

[0004] For single-core oscillators, their phase noise performance is usually limited. Therefore, in applications with high phase noise requirements, multi-core oscillators are often used to achieve better phase noise performance. Figure 4 A resistively coupled multi-core oscillator was demonstrated. By coupling multiple LC oscillators together, simultaneous operation of these LC oscillators enables phase noise suppression. Ideally, N-core coupling can achieve 10logN dB of phase noise suppression. However, this requires additional coupling circuitry and on-chip interconnects, resulting in a large chip footprint. Chip layout constraints make it difficult to achieve multi-core integration with more than four cores.

[0005] Application content

[0006] In view of this, this application provides a low phase noise multi-core oscillator, chip, and device to help solve the problems in the prior art.

[0007] In a first aspect, embodiments of this application provide a low-phase-noise multi-core oscillator, comprising: n pairs of P-type cross-transistor pairs, n pairs of N-type cross-transistor pairs, and 2n first capacitors C. D 2n second capacitors C C A network of 2n mutually coupled inductors and resistors, wherein: the first capacitor C D The second capacitor C is connected across the two ends of the cross transistor. C Connected between N-type and P-type cross-coupled transistor pairs, the first group of n inductors is cross-coupled with another group of n inductors. Each inductor is connected to an N-type transistor and a P-type transistor at both ends, and the center tap of each inductor is connected through a resistor network.

[0008] In one possible implementation, the first capacitor C D Second capacitor C C All are differential capacitors, with a differential-mode equivalent capacitance of C. D +C C The common-mode equivalent capacitance is C.C .

[0009] In one possible implementation, the cross transistor pair is composed of MOS transistors or transistors, including: an NMOS cross transistor pair composed of two N-type MOS transistors, a PMOS cross transistor pair composed of two P-type MOS transistors, an NPN cross transistor pair composed of two NPN transistors, and a PNP cross transistor pair composed of two PNP transistors.

[0010] In one possible implementation, the first capacitor C D Second capacitor C C It consists of a fixed capacitor, an adjustable capacitor, a switching capacitor, or any combination thereof.

[0011] In one possible implementation, when n equals 2, the low phase noise multi-core oscillator is a 4-core oscillator, and the center taps of each inductor are connected together by a resistor, which is a wire resistor.

[0012] In one possible implementation, when n equals 4, the low phase noise multi-core oscillator is an octa-core oscillator, which is based on a combination of 4-core oscillators, and each inductor needs to be connected with an N-type transistor at one end and a P-type transistor at the other end.

[0013] In one possible implementation, the system can be extended to any 4n-core oscillator based on a 4-core oscillator, with the center tap of each inductor connected via a resistor.

[0014] Secondly, embodiments of this application provide a chip, comprising:

[0015] Encapsulation housing;

[0016] microprocessor;

[0017] The low phase noise multi-core oscillator described in any possible implementation of the first aspect is electrically connected to the microprocessor.

[0018] Thirdly, embodiments of this application provide a device, including:

[0019] processor;

[0020] Memory;

[0021] And the chip described in the second aspect, wherein the computer program is stored in the memory, the computer program including instructions that, when executed by the processor, control the chip.

[0022] Fourthly, embodiments of this application provide a device, including:

[0023] Phase-locked loop;

[0024] And the chip described in the second aspect, wherein the phase-locked loop is electrically connected to the chip, and the chip directly controls the frequency of the low phase noise multi-core oscillator within the chip.

[0025] In this embodiment, differential capacitors are used to control the common-mode and differential-mode resonant frequencies, avoiding the degradation of the common-mode and differential-mode quality factors by single-ended capacitors. Magnetic coupling between inductors has no effect on the common-mode state, thus not degrading the common-mode inductor quality factor. With the same capacitance ratio, both the common-mode and differential-mode quality factors of the inductor are improved. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a traditional LC oscillator;

[0028] Figure 2 This is a schematic diagram of an LC oscillator using a single-ended capacitor and a differential capacitor.

[0029] Figure 3 This is a schematic diagram of an implicit common-mode resonant oscillator.

[0030] Figure 4 This is a schematic diagram of a resistively coupled multi-core oscillator.

[0031] Figure 5 A schematic diagram of a low phase noise multi-core oscillator provided in an embodiment of this application;

[0032] Figure 6 Schematic diagrams illustrating the implementation of several LC oscillator crossover transistors provided in embodiments of this application;

[0033] Figure 7 This is a schematic diagram of the capacitor implementation provided in the embodiments of this application;

[0034] Figure 8 A schematic diagram of a quad-core oscillator based on MOS technology provided for an embodiment of this application;

[0035] Figure 9 A schematic diagram of an 8-core oscillator based on MOS technology provided for an embodiment of this application;

[0036] Figure 10A schematic diagram of a 4n-core oscillator based on MOS technology provided in an embodiment of this application;

[0037] Figure 11 This is a schematic diagram comparing the inductor quality factors provided in an embodiment of this application;

[0038] Figure 12 A schematic diagram of phase noise comparison provided for an embodiment of this application;

[0039] Figure 13 FoM and FoM provided in the embodiments of this application A Comparison diagram;

[0040] Figure 14 A schematic diagram of a dual-core oscillator based on MOS technology provided for an embodiment of this application;

[0041] Figure 15 A schematic diagram of a chip provided in an embodiment of this application;

[0042] Figure 16 A schematic diagram of a device provided in an embodiment of this application;

[0043] Figure 17 This is a schematic diagram of another device provided in an embodiment of this application. Detailed Implementation

[0044] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0045] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0046] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0047] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0048] It should be noted that the specific details of the home appliance control method involved in the embodiments of this application can be found in the description of the above embodiments, and will not be repeated here for the sake of brevity.

[0049] Figure 5 The diagram shows the technical solution of this invention (the transistor in the diagram is a MOS transistor, but it can actually be implemented using a MOS transistor or a bipolar transistor). This low phase noise multi-core oscillator consists of n pairs of P-type cross transistors, n pairs of N-type cross transistors, and 2n capacitors C. D 2n capacitors C C It consists of 2n mutually coupled inductors and a resistor network. Capacitor C D Connected across the two ends of the cross-coupled transistor, capacitor C C Connected between N-type and P-type transistors. n inductors are cross-coupled with another n inductors, and each inductor is connected to an N-type transistor and a P-type transistor at its two ends. The center tap of each inductor is connected together through a resistor network.

[0050] In this invention, C D With C C All capacitors are differential capacitors, which avoids the quality factor degradation caused by single-ended capacitors. In this scheme, the differential-mode equivalent inductance is (1+k)L, and the differential-mode equivalent capacitance is C. D +C C The common-mode equivalent inductance is L, and the common-mode equivalent capacitance is C. C Common-mode inductor quality factor Q L_CM =Q L Compared to prior art one, this solution avoids the degradation of the inductor quality factor under common-mode conditions. Compared to prior art two, this solution can be extended to any 2n-core oscillator. The nested coupling between oscillator cores reduces the size.

[0051] The crossover transistor pairs in each oscillator core of this invention can be implemented using MOSFETs or transistors, such as... Figure 6 As shown. A current source can be connected in series at the oscillator power supply and ground to control the oscillator current and power consumption. Specifically, the cross transistor pair is composed of MOS transistors or transistors, including: an NMOS cross transistor pair composed of two N-type MOS transistors, a PMOS cross transistor pair composed of two P-type MOS transistors, an NPN cross transistor pair composed of two NPN transistors, and a PNP cross transistor pair composed of two PNP transistors.

[0052] like Figure 7As shown, each capacitor C in this invention can be implemented by a fixed capacitor (usually an MIM capacitor or MOM capacitor on the chip), an adjustable capacitor (usually a varactor diode or varactor MOSFET on the chip), a switched capacitor (combined with a switching device through a fixed capacitor), and any combination thereof.

[0053] Figure 8 This diagram illustrates a quad-core oscillator implementation based on MOS technology, corresponding to the case where n equals 2 in this design. The thick gray lines in the diagram represent on-chip metal inductors, and the darker areas where these lines intersect represent crossover lines. The center taps of each inductor are connected together via resistors implemented using wire resistors.

[0054] Figure 9 An example of an 8-core oscillator based on MOS technology is shown. Figure 7 The four-core implementation is composed of a combination of cores. It should be noted that each inductor needs to be connected according to the principle of connecting one end to an N-type transistor and the other end to a P-type transistor.

[0055] based on Figure 9 The extension method of the medium scheme can be extended to any 4n-core oscillator scheme, such as... Figure 10 As shown in the diagram. For simplicity, N represents an N-type crossover transistor pair and P represents a P-type crossover transistor pair. The center tap of each inductor is connected via a resistor.

[0056] This invention employs differential capacitors to control the common-mode and differential-mode resonant frequencies, avoiding the degradation of the common-mode and differential-mode quality factors caused by single-ended capacitors. In this invention, the magnetic coupling k between inductors has no effect on the common-mode state, thus preventing degradation of the common-mode inductor quality factor. Compared to prior art (implicit common-mode technology), this invention improves both the common-mode and differential-mode quality factors of the inductor with the same capacitance ratio, such as... Figure 11 As shown. Therefore, this invention achieves better phase noise performance. Furthermore, this invention enables multi-core integration within a smaller chip size, offering the advantage of miniaturization.

[0057] There are trade-offs among several performance indicators of an oscillator, including its operating frequency, power consumption, phase noise, and frequency coverage. Therefore, FoM (FoM) comprehensively considers the oscillator's quality factors, including its operating frequency, power consumption, and phase noise, and can simultaneously represent the oscillator's phase noise performance and energy efficiency performance. A To comprehensively consider the oscillator's quality factor (FoM) in terms of operating frequency, power consumption, phase noise, and size, FoM and FoM are used. A The higher the value, the better the overall performance of the oscillator. Its expression is:

[0058] FoM=20log10(f0 / Δf)–PN–10log10(P DC / 1mW)

[0059] FoM A =20log10(f0 / Δf)–PN–10log10(P DC / 1mW)+10log10(1mm 2 / A)

[0060] Figure 12 A comparison of the normalized phase noise of this invention with that of leading international oscillators in recent years demonstrates that, thanks to its multi-core expansion capability, this invention achieves leading phase noise performance in the millimeter-wave band. Furthermore, its FoM performance shows that this invention can simultaneously achieve low phase noise and high FoM. Figure 13 Comparison of FoM and FoM A With these parameters, the present invention can achieve leading FoM (Form of Model) while also having advantages in size.

[0061] It should be noted that the case where n equals 1 and k equals 0 in the embodiments of this application also falls within the protection scope of this application, see [link to relevant documentation]. Figure 14 This demonstrates a single-core oscillator embodiment based on MOS technology, which corresponds to the case where n equals 1 and k equals 0 in this scheme.

[0062] See Figure 15 This application provides a chip, including: a package housing; a microprocessor and a low phase noise multi-core oscillator disposed within the package housing, wherein the low phase noise multi-core oscillator is electrically connected to the microprocessor.

[0063] It should be noted that the specific details of the low phase noise multi-core oscillator involved in the embodiments of this application can be found in the description of the above embodiments, and will not be repeated here for the sake of brevity.

[0064] See Figure 16 This is a schematic diagram of a device provided in an embodiment of this application, specifically a radar device. Figure 16 As shown, the device 200 may include a processor 201, a memory 202, and a chip 203. These components communicate via one or more buses. Those skilled in the art will understand that the device structure shown in the figures does not constitute a limitation on the embodiments of this application. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0065] The processor 201 serves as the control center of the device, connecting various parts of the device via various interfaces and lines. It executes software programs and / or modules stored in the memory 202, and calls data stored in the memory to perform various functions of the device and / or process data. The processor may be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 201 may consist only of a central processing unit (CPU). In this embodiment, the CPU may have a single processing core or include multiple processing cores.

[0066] Memory 202 is used to store the execution instructions of processor 201. Memory 202 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0067] When the execution instructions in memory 202 are executed by processor 201, control chip 203 uses differential capacitors to control the common-mode and differential-mode resonant frequencies, avoiding the degradation of the common-mode and differential-mode quality factors by single-ended capacitors. Magnetic coupling between inductors has no effect on the common-mode state, thus not degrading the common-mode inductor quality factor. With the same capacitance ratio, both the common-mode and differential-mode quality factors of the inductor are improved.

[0068] See Figure 17 This provides a schematic diagram of another device for embodiments of this application, such as... Figure 17 In the device 300 provided in this application embodiment, the chip 301 controls the frequency through a phase-locked loop 302. The phase-locked loop 302 controls the low-phase-noise multi-core oscillator within the chip 301 to use differential capacitors to control the common-mode and differential-mode resonant frequencies, avoiding the degradation of the common-mode and differential-mode quality factors by single-ended capacitors. Magnetic coupling between inductors has no effect on the common-mode state, thus not degrading the common-mode inductor quality factor. With the same capacitance ratio, both the common-mode and differential-mode quality factors of the inductor are improved.

[0069] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0070] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0071] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0072] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A low-phase-noise multi-core oscillator, characterized in that, include: n pairs of P-type cross transistors, n pairs of N-type cross transistors, and 2n first capacitors. 2n second capacitors 2n mutually coupled inductor and resistor networks, wherein: 1 pair of the P-type cross transistors and 1 pair of the N-type cross transistors form a group of two-core oscillators, forming a total of n groups of two-core oscillators, and every two groups of two-core oscillators are arranged in a cross shape; In each group of dual-core oscillators: the P-type cross-transistor pair and the N-type cross-transistor pair respectively have a first output terminal and a second output terminal, and the second capacitor... The inductor is connected in parallel between the two first output terminals, and the second capacitor... The inductor is also connected in parallel between the two second output terminals; the first capacitor They are respectively connected between the first output terminal and the second output terminal of the N-type cross transistor pair and the P-type cross transistor pair; In the two sets of dual-core oscillators arranged in a cross shape, the n inductors of the first set of dual-core oscillators are cross-coupled with the n inductors of the other set of dual-core oscillators, and the center tap of each inductor is connected through a resistor network. The first capacitor Second capacitor All are differential capacitors, and the differential-mode equivalent capacitance of the low-phase-noise multi-core oscillator is... The common-mode equivalent capacitance is The differential-mode equivalent inductance of the low-phase-noise multi-core oscillator is (1+k)L, the common-mode equivalent inductance is L, and the magnetic coupling k between the inductors has no effect in the common-mode state, where L is the self-inductance of the inductor and k is the coupling coefficient between the inductors.

2. The low phase noise multi-core oscillator according to claim 1, characterized in that, The cross transistor pair is composed of MOS transistors or transistors, including: an NMOS cross transistor pair composed of two N-type MOS transistors, a PMOS cross transistor pair composed of two P-type MOS transistors, an NPN cross transistor pair composed of two NPN transistors, and a PNP cross transistor pair composed of two PNP transistors.

3. The low phase noise multi-core oscillator according to claim 2, characterized in that, The first capacitor Second capacitor It consists of a fixed capacitor, an adjustable capacitor, a switching capacitor, or any combination thereof.

4. The low phase noise multi-core oscillator according to any one of claims 1-3, characterized in that, When n equals 2, the low phase noise multi-core oscillator is a 4-core oscillator, and the center taps of each inductor are connected together by a resistor, which is a metal wire resistor.

5. The low phase noise multi-core oscillator according to claim 4, characterized in that, When n equals 4, the low phase noise multi-core oscillator is an 8-core oscillator. The 8-core oscillator is based on a combination of 4-core oscillators. Each inductor needs to be connected with an N-type transistor at one end and a P-type transistor at the other end.

6. The low phase noise multi-core oscillator according to claim 5, characterized in that, Based on a 4-core oscillator, it can be extended to any 4n-core oscillator, with the center tap of each inductor connected via a resistor.

7. A chip, characterized in that, include: Encapsulation housing; microprocessor; The low phase noise multi-core oscillator according to any one of claims 1-6, wherein the low phase noise multi-core oscillator is electrically connected to the microprocessor.

8. A device, characterized in that, include: processor; Memory; And the chip of claim 7, wherein a computer program is stored in the memory, the computer program including instructions that, when executed by the processor, control the chip.

9. A device, characterized in that, include: Phase-locked loop; And the chip of claim 7, wherein the phase-locked loop is electrically connected to the chip, and the chip directly controls the frequency of the low phase noise multi-core oscillator within the chip.

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