Off-chip configurable frequency-modulated continuous-wave phase-locked loop system and control method

Abstract

The application discloses a frequency-modulated continuous wave phase-locked loop system and a control method, which comprises a phase-locked loop circuit, an on-chip digital circuit, an off-chip digital circuit and a tri-state interface circuit, wherein the output end of the on-chip digital circuit is connected with the phase-locked loop circuit, the output ends of the on-chip digital circuit and the off-chip digital circuit are respectively connected with the first input end and the second input end of the tri-state interface circuit to respectively output an on-chip frequency division ratio control signal and an off-chip frequency division ratio control signal to the tri-state interface circuit, and the first output end of the tri-state interface circuit is connected with the phase-locked loop circuit to respectively send the on-chip frequency division ratio control signal to the phase-locked loop circuit through the first output end when the tri-state interface circuit is in an on-chip mode and send the off-chip frequency division ratio control signal to the phase-locked loop circuit through the first output end and set the second output end to a high-impedance state when the tri-state interface circuit is in an off-chip mode.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to an off-chip configurable frequency-modulated continuous wave phase-locked loop system and control method. Background Technology

[0002] A frequency synthesizer is a device that generates multiple frequencies from one or more reference frequencies, and it is an essential key circuit in electronic systems. It is widely used in wireless communication, radar, and electronic measuring instruments, playing a decisive role in the overall performance of electronic systems. The technical specifications of a frequency synthesizer, such as its output frequency range, frequency resolution, frequency switching speed, phase noise, and spurious components, are of great value to the development of wireless communication, radar, and instrumentation fields.

[0003] Currently, phase-locked loop (PLL) frequency synthesizers are widely used. A PLL frequency synthesizer includes functional units such as a frequency and phase detector, charge pump, voltage-controlled oscillator, loop filter, and controllable frequency divider. When a frequency-modulated continuous wave (FMCW) PLL is applied to a radar system, the radar system transmits a series of continuously frequency-modulated millimeter waves through an antenna and receives the reflected signals from the target. Meanwhile, with the development of modern digital circuit technology, due to the high reliability, high flexibility, and strong robustness of digital circuits, the digitization of PLLs is becoming increasingly popular. In an FMCW PLL system, the PLL achieves functions such as different frequency points, frequency changes, and waveform generation through programmed digital control via a digital circuit system.

[0004] However, Application Specific Integrated Circuits (ASICs) have drawbacks such as long design cycles and high costs, posing challenges to design debugging and iteration. In related technologies, Programmable Gate Arrays (FPGAs) are introduced into the design of Phase-Locked Loops (PLLs) for design assistance. For example, Chinese invention patent application CN102208911A discloses a method for generating and dynamically configuring a window clock based on an on-chip PLL of an FPGA. This method sets the configuration parameters of the on-chip PLL of the FPGA according to the required window clock and the frequency of the input clock, synthesizing the window clock internally within the FPGA, thus requiring less external hardware configuration. Chinese utility model patent CN212850459U discloses a high-precision digital PLL system based on an FPGA, including a phase detector, a TDC time-to-digital converter, a time-temperature calibration module, a digital loop filter, a numerically controlled oscillator, and a temperature sensor connection. A first counting unit composed of a high-speed carry chain of the FPGA is used to count phase signals shorter than the system clock cycle.

[0005] Chinese invention patent application CN114024547A discloses a digital circuit system and phase-locked loop for linear frequency modulation continuous wave phase-locked loop. Based on the input mode selection signal, maximum sweep frequency value, minimum sweep frequency value, and sweep frequency step, it generates control signals for the corresponding mode to control the control signal generation unit, address code generation unit, frequency division ratio lookup unit, differential integral modulator, frequency division ratio decoding unit, and dual-mode frequency divider, thereby realizing a multi-functional sweep frequency mode with continuously adjustable frequency and fixed frequency output.

[0006] This solution applies digital circuitry to phase-locked loop circuit design to achieve both continuously adjustable frequency and fixed frequency output; however, it cannot simultaneously support on-chip and off-chip modes to enable on-chip data reading or writing. Summary of the Invention

[0007] The technical problem to be solved by this invention is how to improve the stability, reliability and configurability of the overall phase-locked loop system.

[0008] The present invention solves the above-mentioned technical problems through the following technical means: On one hand, an off-chip configurable frequency-modulated continuous wave phase-locked loop (PLL) system is proposed. The system includes a PLL circuit, an on-chip digital circuit, an off-chip digital circuit, and a tri-state interface circuit. The output terminal of the on-chip digital circuit is connected to the PLL circuit. The output terminals of the on-chip digital circuit and the off-chip digital circuit are respectively connected to the first input terminal and the second input terminal of the tri-state interface circuit to output on-chip frequency division ratio control signals and off-chip frequency division ratio control signals to the tri-state interface circuit. The first output terminal of the tri-state interface circuit is connected to the PLL circuit, and the second output terminal is connected to the off-chip digital circuit. When the tri-state interface circuit is in on-chip mode, the on-chip frequency division ratio control signal is sent to the PLL circuit through the first output terminal. In off-chip mode, the off-chip frequency division ratio control signal is sent to the PLL circuit through the first output terminal, and the second output terminal is set to a high-impedance state.

[0009] Furthermore, the phase-locked loop circuit includes a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a dual-mode divider. The output of the frequency and phase detector is connected to the VCO after passing through the charge pump and the filter in sequence. The output of the VCO is connected to the frequency and phase detector and the on-chip digital circuit via the dual-mode divider. The output of the on-chip digital circuit is connected to the VCO. The first output terminal of the tri-state interface circuit is connected to the dual-mode frequency divider.

[0010] Furthermore, the second output terminal of the tri-state interface circuit is also connected to the input terminal of the external digital circuit to output the on-chip frequency division ratio control signal to the external digital circuit.

[0011] Furthermore, the on-chip digital circuitry includes a serial peripheral interface, a control signal generation unit, a frequency division unit, an address code generation unit, a frequency division ratio lookup table, a differential integral modulator, a frequency division ratio decoding unit, and a voltage-controlled oscillator digital control code generation unit. The serial peripheral interface includes a configuration register for writing frequency division ratio settings, time step settings, and frequency step settings. The control signal generation unit is used to generate control signals corresponding to the sweep frequency mode and the fixed frequency division ratio mode. The output terminals of the serial peripheral interface are respectively connected to the frequency division unit, the control signal generation unit, and the voltage-controlled oscillator digital control code generation unit. The output terminals of the frequency division unit and the control signal generation unit are respectively connected to the address code generation unit. The output terminals of the address code generation unit are respectively connected to the frequency division ratio lookup table and the voltage-controlled oscillator digital control code generation unit. The output terminals of the frequency division ratio lookup table and the control signal generation unit are respectively connected to the differential integral modulator. The output terminal of the differential integral modulator is connected to the frequency division ratio decoding unit. The output of the frequency division ratio decoding unit is connected to the tri-state interface circuit, and the output of the voltage-controlled oscillator digital control code generation unit is connected to the voltage-controlled oscillator in the phase-locked loop circuit.

[0012] Furthermore, in the frequency sweep mode, the control signal of the address code generation unit is 0, and in the fixed frequency division ratio mode, the control signal of the address code generation unit changes from 0 to 1; the time when the control signal of the address code generation unit is 0 is greater than the locking time of the phase-locked loop circuit.

[0013] Furthermore, the input signal of the voltage-controlled oscillator digital control code generation unit includes a reference clock, an address code sent by the address code generation unit, an initial address code value sent by the serial peripheral interface, and an initial control code value. When the address code is a fixed value, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generator to the voltage-controlled oscillator is equal to the initial value of the control code; When the address code changes continuously and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator begins to change continuously, and the change step size is related to the frequency characteristics of the voltage-controlled oscillator.

[0014] Furthermore, the control signal generation unit is connected to an external system to receive the interface signal wave_start sent by the external system and to send a valid frame_en signal to the external system when the interface signal wave_start is valid. The interface signal wave_start is used to control the start time of the phase-locked loop waveform generation, and the frame_en signal is used as a flag signal for the generation of the phase-locked loop waveform. The address code generation unit is connected to the external system to send a valid adc_en signal to the external system when the interface signal wave_start is valid. The adc_en signal is used as a flag signal for the phase-locked loop waveform linearization region.

[0015] Furthermore, the off-chip digital circuit includes a data acquisition module, a data storage module, and a control signal generation circuit; the input terminal of the data acquisition module is connected to the tri-state interface circuit, the output terminal of the data acquisition module is connected to the data storage module, and the output terminal of the control signal generation circuit is connected to the tri-state interface circuit. The output of the data storage module is connected to the analysis instrument, and the output of the analysis instrument is connected to the control signal generation circuit.

[0016] Furthermore, the off-chip digital circuitry is integrated using an FPGA chip.

[0017] Secondly, the present invention also proposes a control method for an off-chip configurable frequency-modulated continuous wave phase-locked loop system as described above, the control method comprising: The on-chip digital circuit outputs digital control codes to the phase-locked loop circuit to control the operation of the phase-locked loop circuit; The on-chip digital circuitry and the off-chip digital circuitry are used to generate on-chip frequency division ratio control signals and off-chip frequency division ratio control signals, respectively. When the tri-state interface circuit is in on-chip mode, the on-chip frequency division ratio control signal is obtained through its first input terminal and forwarded to the phase-locked loop circuit through the first output terminal. At the same time, the on-chip frequency division ratio control signal is output to the off-chip digital circuit through the second output terminal, so as to realize the off-chip reading of data on the chip. When the tri-state interface circuit is in off-chip mode, the off-chip frequency division ratio control signal is obtained through its second input terminal and forwarded to the phase-locked loop circuit through the first output terminal, while the second output terminal is set to a high impedance state.

[0018] Furthermore, the on-chip digital circuitry is used to generate an on-chip frequency division ratio control signal, including: The serial peripheral interface is used to perform write operations on the configuration registers in different phase-locked loop modes. The information written includes the frequency division ratio setting value, time step setting value, frequency step value, address code initial value, and control code initial value. The phase-locked loop modes include fixed frequency division ratio mode and frequency sweep mode. The frequency division unit reads the frequency division ratio setting value set in the configuration register, divides the input reference clock, obtains the frequency-divided clock, and outputs it to the address code generation unit as the clock signal of the address code generation unit. The control signal generating unit generates a control signal in the frequency sweep mode based on the write information in different modes, and inputs it to the address code generating unit and the differential integral modulator. The address code generation unit generates an address code based on the control signal and sends it to the frequency division ratio lookup table, so that the frequency division ratio lookup table outputs the frequency division ratio corresponding to the address code to the differential integral modulator; The differential integral modulator modulates the division ratio to generate a modulated division ratio, which is then sent to the division ratio decoding unit. The division ratio decoding unit converts the modulated division ratio into a division ratio control signal and outputs it to the tri-state interface circuit.

[0019] Furthermore, the step of using the on-chip digital circuit to output digital control codes to the phase-locked loop circuit to control the operation of the phase-locked loop circuit includes: The voltage-controlled oscillator digital control code generation unit acquires the reference clock, the address code sent by the address code generation unit, the initial address code value sent by the serial peripheral interface, and the initial control code value. In the fixed frequency division ratio mode, when the address code is a fixed value, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator is equal to the initial value of the control code; In frequency sweep mode, when the address code changes continuously and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator begins to change continuously.

[0020] Furthermore, the address code generation unit adjusts the period and slope of the waveform in the frequency sweep mode based on the frequency step size written to the register in the serial peripheral interface and the time step size output by the frequency divider unit.

[0021] Furthermore, in the frequency sweep mode, the control signal of the address code generation unit is 0, and in the fixed frequency division ratio mode, the control signal of the address code generation unit changes from 0 to 1; the time when the control signal of the address code generation unit is 0 and the time when it is 1 are both adjustable, and the time when the control signal of the address code generation unit is 0 is greater than the locking time of the phase-locked loop circuit.

[0022] Furthermore, the method also includes: When the phase-locked loop circuit starts working, it enters the fixed frequency division ratio mode. When the control signal generation unit detects that the wave_start signal input from the external system is valid, it generates a control signal in the frequency sweep mode and sends it to the address code generation unit. Otherwise, it will continue to work in the fixed frequency division ratio mode. When the waveform begins to occur, the control signal generation unit generates a valid frame_en signal and outputs it to the external system; When the frequency of the output waveform of the address code generation unit enters the set region, a valid adc_en signal is generated and output to an external system; Once all waveforms have been generated, return to fixed frequency division ratio mode.

[0023] The advantages of this invention are: (1) By setting up a three-state interface circuit, the present invention can obtain the external frequency division ratio control signal and the internal frequency division ratio control signal output by the external digital circuit and the internal digital circuit respectively. The digital control system that realizes the phase-locked loop frequency modulation continuous wave function can be implemented in the internal digital circuit or the external digital circuit. Therefore, the function of the phase-locked loop system can be configured and controlled externally. The external digital circuit can replace some functions of the internal digital circuit system. Both the internal and external digital systems can input the control signal to the dual-mode frequency divider, which improves the stability, reliability and configurability of the overall phase-locked loop system.

[0024] (2) The external digital circuit can read the output of the on-chip digital circuit and replace some of the functions of the on-chip digital circuit, thereby improving the reliability, configurability and stability of the frequency modulation continuous wave phase-locked loop.

[0025] (3) Use on-chip digital circuits to implement either fixed frequency division ratio mode or frequency sweep mode. In the frequency sweep mode, the waveform type, frequency sweep range and frequency sweep step can be determined according to the system requirements. Based on the system function requirements, different working modes can be realized by controlling the address code generation unit, differential integral modulator and other units through the frequency division unit and control signal generation unit to adapt to the needs of different systems.

[0026] (4) It realizes the function of generating frequency-modulated continuous wave phase-locked loop waveform, which can be applied to different needs of FMCW radar system.

[0027] (5) The phase-locked loop circuit, tri-state interface circuit, and on-chip digital circuit are implemented by ASIC (Application-Specific Integrated Circuit), while the off-chip digital circuit system is implemented by FPGA (Field Programmable Gate Array). By combining the advantages of ASIC (small area, high performance, and low power consumption) and FPGA (high flexibility, programmability, and short development cycle), the two can complement each other to achieve a frequency synthesis source with wide frequency range, fine frequency stepping, low phase noise, and fast frequency switching, so as to realize the function of continuous frequency adjustable or fixed frequency output and adapt to the needs of different phase-locked loop systems.

[0028] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of an off-chip configurable frequency-modulated continuous wave phase-locked loop system proposed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the linear frequency modulated continuous wave phase-locked loop in this invention; Figure 3 This is a schematic diagram of the structure of the on-chip digital circuit in one embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a frequency division unit in one embodiment of the present invention; Figure 5 This is a schematic diagram of waveform generation in a phase-locked loop sweep frequency mode according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the principle of the digital control code generation unit of the voltage-controlled oscillator in one embodiment of the present invention; Figure 7 This is a schematic diagram of the working process of the interface signal between the phase-locked loop and the external system in one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an off-chip digital circuit in one embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of another external digital circuit in one embodiment of the present invention; Figure 10 This is a schematic diagram of the tri-state interface circuit in on-chip operating mode in one embodiment of the present invention; Figure 11 This is a schematic diagram of the tri-state interface circuit in off-chip operation mode in one embodiment of the present invention; Figure 12 This is a schematic diagram of the specific structure of a tri-state interface circuit in one embodiment of the present invention; Figure 13 This is a flowchart illustrating the control method for an off-chip configurable frequency-modulated continuous wave phase-locked loop system according to an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] like Figure 1 As shown, the first embodiment of the present invention proposes an off-chip configurable frequency-modulated continuous wave phase-locked loop (PLL) system. The system includes a PLL circuit 10, an on-chip digital circuit 20, an off-chip digital circuit 30, and a tri-state interface circuit 40. The output terminal of the on-chip digital circuit 20 is connected to the PLL circuit 10. The output terminals of the on-chip digital circuit 20 and the off-chip digital circuit 30 are respectively connected to the first input terminal and the second input terminal of the tri-state interface circuit 40 to output on-chip frequency division ratio control signals and off-chip frequency division ratio control signals to the tri-state interface circuit 40, respectively. The first output terminal of the tri-state interface circuit 40 is connected to the PLL circuit 10 so that when the tri-state interface circuit 40 is in on-chip mode, the on-chip frequency division ratio control signal is sent to the PLL circuit 10 through the first output terminal. In off-chip mode, the off-chip frequency division ratio control signal is sent to the PLL circuit 10 through the first output terminal, and the second output terminal of the tri-state interface circuit 40 is set to a high-impedance state.

[0032] In this embodiment, by setting a tri-state interface circuit 40, the external frequency division ratio control signal and the internal frequency division ratio control signal output by the external digital circuit 30 and the internal digital circuit 20 can be obtained respectively. The digital control system that realizes the phase-locked loop frequency modulation continuous wave function can be implemented in the internal digital circuit 20 or the external digital circuit 30. Therefore, the function of the phase-locked loop system can be configured and controlled externally. The external digital circuit 30 can replace some functions of the internal digital circuit 20 system. Both the internal and external digital systems can input control signals to the dual-mode frequency divider 15, which improves the stability, reliability and configurability of the overall phase-locked loop system.

[0033] In one embodiment, the phase-locked loop circuit 10 includes a frequency and phase detector 11, a charge pump 12, a loop filter 13, a voltage-controlled oscillator 14, and a dual-mode divider 15. The output of the frequency and phase detector 11 is connected to the voltage-controlled oscillator 14 after passing through the charge pump 12 and the filter in sequence. The output of the voltage-controlled oscillator 14 is connected to the frequency and phase detector 11 and the on-chip digital circuit 20 through the dual-mode divider 15. The output terminal of the on-chip digital circuit 20 is connected to the voltage-controlled oscillator 14. The output of the tri-state interface circuit 40 is connected to the dual-mode frequency divider 15.

[0034] like Figure 2 As shown, a traditional frequency-modulated continuous wave phase-locked loop (PLL) includes a phase-frequency detector (PFD) 11, a charge pump (CP) 12, a filter 13, a voltage-controlled oscillator (VCO) 14, a multi-modulus divider (MMD) 15, and a digital SDM 26 connected in sequence. The PFD detects the phase and frequency difference between the input reference signal Fref and the loop feedback signal Fdiv, and outputs a corresponding voltage signal to the charge pump 12. The charge pump 12 circuit converts this voltage signal into a control voltage. The filter removes high-frequency components from this control voltage, outputting a DC level, which is ultimately used as the control voltage for the VCO 14. The output Fvco of the VCO 14 is the output signal of the PLL. As the frequency and phase differences between the two input signals of the frequency and phase detector 11 continuously decrease, the phase-locked loop reaches a locked state when the control voltage is at a constant value. When the loop is locked, if the frequency and phase of the input reference signal change, the frequency and phase of the voltage-controlled oscillator 14 can continuously track the changes in the input reference signal frequency through the loop's control action, causing the loop to re-enter the locked state. This dynamic process is called the loop's "tracking" process. When the input to the differential integral modulator 26 changes continuously, the differential integral modulator 26 modulates and outputs the division ratio NF, which includes integers and fractions, and controls the division ratio of the dual-mode frequency divider 15. When the division ratio of the dual-mode frequency divider 15 changes continuously, the frequency and phase of the output of the dual-mode frequency divider 15, i.e., the loop feedback signal Fdiv, change. The "tracking" state of the phase-locked loop will cause the output Fvco of the voltage-controlled oscillator 14 to change continuously through the loop's control action, thus realizing the frequency sweep function of the frequency-modulated continuous wave phase-locked loop.

[0035] In this embodiment, the second output terminal of the tri-state interface circuit 40 is also connected to the input terminal of the external digital circuit 30 to output the on-chip frequency division ratio control signal to the external digital circuit 30.

[0036] In this embodiment, the off-chip digital circuit 30 can both read the output of the on-chip digital circuit 20 and replace some of the functions of the on-chip digital circuit 20, thereby improving the reliability, configurability and stability of the frequency modulation continuous wave phase-locked loop.

[0037] In one embodiment, such as Figure 3As shown, the on-chip digital circuit 20 includes a serial peripheral interface 21, a control signal generation unit 23, a frequency division unit 22, an address code generation unit 24, a frequency division ratio lookup table 25, a differential integral modulator 26, a frequency division ratio decoding unit 27, and a voltage-controlled oscillator digital control code generation unit 28. The serial peripheral interface 21 includes a configuration register for writing frequency division ratio settings, time step settings, and frequency step settings. The control signal generation unit 23 is used to generate control signals corresponding to the frequency sweep mode and the fixed frequency division ratio mode. The output terminal of the serial peripheral interface 21 is respectively connected to the frequency division unit 22, the control signal generation unit 23, and the voltage-controlled oscillator digital control code generation unit 28. The output terminals of the frequency division unit 22 and the control signal generation unit 23 are respectively connected to the address code generation unit 24. The output of the generation unit 24 is connected to the frequency division ratio lookup table 25 and the voltage-controlled oscillator digital control code generation unit 28, respectively. The output of the frequency division ratio lookup table 25 and the output of the control signal generation unit 23 are connected to the differential integral modulator 26, respectively. The output of the differential integral modulator 26 is connected to the frequency division ratio decoding unit 27. The output of the frequency division ratio decoding unit 27 is connected to the tri-state interface circuit 40. The output of the voltage-controlled oscillator digital control code generation unit 28 is connected to the voltage-controlled oscillator 14 in the phase-locked loop circuit 10.

[0038] It should be noted that the serial peripheral interface 21 is a high-speed, full-duplex, synchronous communication bus used for exchanging information between external devices and the on-chip digital circuit 20. It includes a first output terminal, a second output terminal, and a third output terminal, which are respectively connected to the frequency divider unit 22, the control signal generation unit 23, and the voltage-controlled oscillator digital control code generation unit 28. Depending on the two different operating modes of the phase-locked loop (PLL), namely the fixed frequency division ratio mode and the frequency sweep mode, the serial peripheral interface 21 performs write operations on the configuration register in the corresponding mode. The control signal generation unit 23 and the voltage-controlled oscillator digital control code generation unit 28 read the value of the configuration register and complete the initial value setting.

[0039] The control signal generation unit 23 includes a sweep frequency mode and a fixed frequency division ratio mode, and is used to provide control signals corresponding to the two modes, thereby controlling the function of the frequency-modulated continuous wave phase-locked loop. It includes two input terminals and three output terminals. The two input terminals are respectively connected to the serial peripheral interface 21 and the external system, and the three output terminals are respectively connected to the address code generation unit 24, the differential-integral modulator 26, and the external system. The control signal generation unit 23 is used to generate the corresponding control signals for the two modes, controlling the operation of the address code generation unit 24 and the differential-integral modulator 26.

[0040] Frequency divider unit 22 is used to allocate the clock required by some modules inside the on-chip digital circuit 20, such as... Figure 4 As shown, it includes two input terminals and one output terminal. One input terminal receives a reference clock signal, and the other input terminal is connected to the serial peripheral interface 21 to obtain the frequency division ratio set in the configuration register. One output terminal is connected to the address code generation unit 24. The frequency division unit 22 divides the input reference clock according to the set frequency division ratio to obtain the frequency-divided clock and outputs it to the address code generation unit 24. Depending on the value of the set frequency division ratio, the frequency and period of the frequency-divided clock output by the frequency division unit 22 are also different. The frequency-divided clock is connected to the address code generation unit 24 as the clock signal of the address code generation unit 24, thereby controlling the operating frequency and period of the address code generation unit 24.

[0041] Address code generation unit 24 is used to generate input address codes for frequency division ratio lookup table 25. In fixed frequency division ratio mode, address code generation unit 24 generates a fixed address code and sends it to frequency division ratio lookup table 25; in frequency sweep mode, address code generation unit 24 generates a continuously changing address code and sends it to frequency division ratio lookup table 25.

[0042] The frequency division ratio lookup table 25 is used to generate the frequency division ratio required for modulation by the differential integral modulator 26.

[0043] The differential integral modulator 26 is used to modulate the preset division ratio output by the division ratio lookup table 25 to generate the division ratio of the dual-mode frequency divider 15.

[0044] The frequency division ratio decoding unit 27 is used to convert the modulated frequency division ratio output by the differential integral modulator 26 into a frequency division control signal and output it to the frequency division ratio control port of the dual-mode frequency divider 15.

[0045] The voltage-controlled oscillator (VCO) digital control code generation unit 28 is used to generate VCO digital control codes, which are used to adjust the size of the capacitor array in the VCO 14, thereby changing the frequency value of the VCO 14. The initial value and step size of the VCO digital control codes can be controlled by the digital control code generation unit, thereby controlling the frequency of the VCO 14 to change according to a predetermined pattern.

[0046] Specifically, when the phase-locked loop (PLL) operates in fixed division ratio mode, the serial peripheral interface 21 unit completes the write operation of the configuration register in the corresponding mode. The control signal generation unit 23 and the voltage-controlled oscillator (VCO) digital control code generation unit 28 read the value of the configuration register, thereby setting the initial values ​​of some signals in the two units. The control signal generation unit 23 generates control signals in the fixed division ratio mode to control the operation of the address code generation unit 24 and the differential-integral modulator 26. In the fixed division ratio mode, the address code generation unit 24 generates a fixed address code and sends it to the division ratio lookup table 25. The division ratio lookup table 25 outputs the division ratio corresponding to the address code. The differential-integral modulator 26 modulates this division ratio to generate the modulated division ratio. The division ratio decoding unit 27 converts the modulated division ratio into a division ratio control signal and outputs it.

[0047] Specifically, when the phase-locked loop (PLL) operates in frequency sweep mode, the serial peripheral interface 21 unit completes the write operation of the configuration register in the corresponding mode, and the control signal generation unit 23 and the voltage-controlled oscillator (VCO) digital control code generation unit 28 read the value of the configuration register, thereby completing the setting of the initial values ​​of some signals in the two units. The control signal generation unit 23 generates control signals in frequency sweep mode to control the operation of the address code generation unit 24 and the differential-integral modulator 26. In frequency sweep mode, the address code generation unit 24 generates continuously changing address codes and sends them to the frequency division ratio lookup table 25, which outputs the frequency division ratio corresponding to the address code. Since the address code changes continuously, the frequency division ratio output by the frequency division ratio lookup table 25 also changes continuously. The differential-integral modulator 26 modulates this frequency division ratio to generate a modulated frequency division ratio. The frequency division ratio decoding unit 27 converts the modulated frequency division ratio into a frequency division ratio control signal and outputs it.

[0048] The on-chip digital circuit 20 proposed in this embodiment, based on system functional requirements, controls units such as the address code generation unit 24 and the differential integral modulator 26 through the frequency division unit 22 and the control signal generation unit 23 to achieve different operating modes and adapt to the needs of different systems. It can implement either a fixed frequency division ratio mode or a frequency sweep mode. In the frequency sweep mode, the waveform type, frequency sweep range, and frequency sweep step can be determined according to the system requirements.

[0049] Furthermore, in FMCW radar systems, frequency modulation methods mainly include triangular wave, sawtooth wave, coded modulation, or noise modulation. FMCW radar transmits a continuous wave with varying frequency during the frequency sweep cycle. A portion of the echo signal and the transmitted signal are coherently mixed to obtain an intermediate frequency (IF) signal containing the target's range and velocity information. The target's range and velocity can then be obtained by detecting the IF signal. The relatively low frequency of the IF signal facilitates data acquisition and digital signal processing. Therefore, the waveform generation function of the frequency-modulated continuous wave phase-locked loop (PLL) is crucial for radar systems. The PLL system proposed in this embodiment has a frequency-modulated continuous wave PLL waveform generation function, realizing waveform modulation such as triangular wave modulation and sawtooth wave modulation. It is applicable to different requirements of FMCW radar systems, specifically: When the phase-locked loop (PLL) is operating in frequency sweep mode, the control signal sent from the control signal generation unit 23 to the address code generation unit 24 is 0. At this time, the signal controls the address code generation unit 24 to output a fixed address code, and the PLL operates with a fixed frequency division ratio. After the PLL loop is locked, the control signal of the address code generation unit 24 changes from 0 to 1. At this time, the signal controls the address code generation unit 24 to output a continuously changing address code, and the PLL starts frequency sweep operation.

[0050] The control signal for the differential integral modulator 26 is initially 0, at which point all registers in the differential integral modulator 26 are cleared. After several clock cycles, the control signal for the differential integral modulator 26 becomes 1, at which point the differential integral modulator 26 modulates according to the division ratio corresponding to the address code output by the address code generation unit 24. It is worth noting that during this process, when the control signal of the address code generation unit 24 changes from 0 to 1, the control signal for the differential integral modulator 26 remains at 1. At this time, the differential integral modulator 26 modulates the continuously changing division ratio. When the frequency sweep process ends, i.e., at the start of the next working cycle, the control signal for the differential integral modulator 26 becomes 0, at which point all registers in the differential integral modulator 26 are cleared, ensuring that the register values ​​during the frequency sweep process do not affect the operation of the next cycle.

[0051] When the control signal of the address code generation unit 24 is 1, the address code generation unit 24 outputs a continuously changing address code. The manner in which the address code changes continuously is determined by the desired waveform, such as... Figure 5As shown. When generating a sawtooth wave, the address code needs to be continuously increased. Once the preset maximum sweep frequency value is reached, it needs to be reset to the initial value, i.e., the minimum sweep frequency value. When generating a triangular wave, the address code needs to be continuously increased. Once the preset maximum sweep frequency value is reached, it needs to be continuously decreased until it returns to the initial value, i.e., the minimum sweep frequency value. It is important to note that the phase-locked loop (PLL) frequency cannot change abruptly; otherwise, it will lose lock during the sweep frequency process. Therefore, in the actual implementation of the triangular wave, a holding period is added. That is, after the address code continuously increases to the preset maximum sweep frequency value, it remains unchanged for a period of time before continuously decreasing until it reaches the initial value, i.e., the minimum sweep frequency value.

[0052] In one embodiment, the control signal of the address code generation unit 24 is 0 in the frequency sweep mode, and the control signal of the address code generation unit 24 changes from 0 to 1 in the fixed frequency division ratio mode; the time when the control signal of the address code generation unit 24 is 0 is greater than the locking time of the phase-locked loop circuit 10.

[0053] It should be noted that the timing of the control signal of address code generation unit 24 being 0 or 1 is adjustable. The timing of the control signal of address code generation unit 24 being 0 is determined by the phase-locked loop (PLL) system; that is, before the frequency sweep begins, the PLL must lock to the frequency corresponding to the minimum sweep value. Therefore, it is necessary to ensure that the timing of the control signal of address code generation unit 24 being 0 is greater than the locking time of the PLL. The specific settings can be achieved by configuring the control signal generation unit 23 through the serial peripheral interface 21.

[0054] Furthermore, the rise time, idle time, and repetition period of the sawtooth wave are all adjustable. The slope of the sawtooth wave can be adjusted by controlling the time step and frequency step of the address code change. The time step can be implemented by the clock control of the address code generation unit 24 through the frequency divider unit 22, and the frequency sweep step can be implemented by configuring the control signal generation unit 23 through the serial peripheral interface 21. The rise time, idle time, and repetition period can be configured through the serial peripheral interface 21 to control the control signal generation unit 23.

[0055] Furthermore, the rise time, hold time, fall time, idle time, and repetition period of the triangular wave are all adjustable. The slope of the triangular wave can be adjusted by controlling the time step and frequency step of the address code change. The time step can be implemented by the clock control of the address code generation unit 24 via the frequency divider unit 22, and the frequency sweep step can be implemented by configuring the control signal generation unit 23 via the serial peripheral interface 21. The rise time, hold time, fall time, idle time, and repetition period can be configured via the serial peripheral interface 21 to control the control signal generation unit 23.

[0056] The waveform generation functions such as triangular waves and sawtooth waves provided in the above embodiments are implemented by the control signal generation unit 23 controlling the address code generation unit 24 and the differential integral modulator 26; the slope of the triangular wave and sawtooth wave can be adjusted by the time step and the frequency step, which can be implemented by the frequency division unit 22 and the control signal generation unit 23; the time and repetition period of the triangular wave and sawtooth wave can be configured by the serial peripheral interface 21 to implement the control signal generation unit 23.

[0057] In this embodiment, the control signal generation unit 23 calculates the required working time and period of the address code generation unit 24 and the differential integral modulator 26 in the frequency sweep mode based on the maximum and minimum sweep values ​​and the sweep step size. The function is achieved by changing the control signal output by the control signal generation unit 23. Furthermore, based on different settings of the time step and frequency step in the registers of the serial peripheral interface 21, the period and slope of the waveform in the frequency sweep mode are adjustable.

[0058] In one embodiment, such as Figure 6 As shown, the input signals of the voltage-controlled oscillator digital control code generation unit 28 include a reference clock, the address code sent by the address code generation unit 24, the initial value of the address code sent by the serial peripheral interface 21, and the initial value of the control code. When the address code is a fixed value, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit 28 to the voltage-controlled oscillator 14 is equal to the initial value of the control code. When the address code changes continuously and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit 28 to the voltage-controlled oscillator 14 begins to change continuously, and the change step size is related to the frequency characteristics of the voltage-controlled oscillator 14.

[0059] It should be noted that the initial values ​​of the address code and control code can be configured and changed by the serial peripheral interface 21.

[0060] When the phase-locked loop is in fixed frequency division ratio mode, the address code output by the address code generation unit 24 is a fixed value, which is equal to the initial value of the address code. At this time, the digital control code of the voltage-controlled oscillator is equal to the initial value of the control code and is output to the voltage-controlled oscillator 14.

[0061] When the phase-locked loop is in frequency sweep mode, the address code output by the address code generation unit 24 changes continuously. When the address code exceeds the initial value of the address code, the digital control code of the voltage-controlled oscillator starts to change continuously and is output to the voltage-controlled oscillator 14.

[0062] It should be noted that the initial value of the voltage-controlled oscillator digital control code is the same as the initial value of the control code. The step size can be changed according to the frequency characteristics of the voltage-controlled oscillator 14. The number of bits of the output voltage-controlled oscillator digital control code can also be changed according to the actual situation of the voltage-controlled oscillator 14. In this embodiment of the invention, it is only an exemplary description and is not a limitation.

[0063] In one embodiment, the control signal generating unit is connected to an external system to receive an interface signal wave_start sent by the external system and to send a valid frame_en signal to the external system when the interface signal wave_start is valid. The interface signal wave_start is used to control the start time of the phase-locked loop waveform generation, and the frame_en signal is used as a flag signal for the generation of the phase-locked loop waveform. The address code generation unit 24 is connected to the external system to send a valid adc_en signal to the external system when the interface signal wave_start is valid. The adc_en signal is used as a flag signal for the phase-locked loop waveform linearization region.

[0064] When the frequency-modulated continuous wave phase-locked loop (PLL) starts working, it first enters the fixed frequency division ratio mode, and the PLL locks at the preset frequency value. When the PLL detects that the wave_start signal input from the external system is valid, the PLL starts to enter the frequency sweep mode to prepare for waveform generation; otherwise, it will continue to work in the fixed frequency division ratio mode.

[0065] Specifically, the external system in this embodiment includes, but is not limited to, an FMCW radar system. The core of the FMCW radar is a linear frequency modulated pulse signal, which is a sine wave whose frequency increases linearly with time. The linear frequency modulated pulse signal can be generated by the frequency sweep mode of the phase-locked loop in this embodiment. During radar operation, since the unambiguous radar range is related to the pulse repetition period, the radar system needs to configure the period of the linear frequency modulated pulse signal to avoid ambiguity in range determination. Therefore, this embodiment sets up an interface to interact with the FMCW radar system. Based on the relationship between the reflected signal and the transmitted signal and the principle of radar ranging and velocity measurement, the radar system needs to configure parameters such as the waveform slope, bandwidth, and frequency resolution of the linear frequency modulated pulse. This embodiment can realize the configurability of the waveform repetition period, waveform slope, and frequency resolution according to the requirements of the FMCW radar system.

[0066] like Figure 7As shown, when waveform generation begins, the phase-locked loop (PLL) generates a valid frame_en signal and outputs it to the external system. When the frequency of the PLL output waveform enters the set region, the PLL generates a valid adc_en signal and outputs it to the external system. When all waveforms are generated, meaning the PLL waveform generation is complete, the PLL returns to the fixed frequency division ratio mode. Otherwise, the PLL will generate waveforms for the next cycle and repeat the above process.

[0067] It should be noted that the `wave_start` signal controls the start time of the phase-locked loop (PLL) waveform generation, triggering the frequency sweep mode of the frequency-modulated continuous wave PLL. Therefore, it can be adjusted by the external system as needed, allowing external systems to control the PLL's operation. The `frame_en` signal is provided to the external circuitry of the PLL as a flag signal for PLL waveform generation; the `adc_en` signal is also provided to the external circuitry of the PLL as a flag signal for the linearization region of the PLL waveform, and can be used as an enable signal for the analog-to-digital converter (ADC). The output timing and effective time of both `frame_en` and `adc_en` signals are adjustable, which can be achieved by changing the judgment conditions. Therefore, these adjustments can be made during the PLL design based on the requirements of the external system.

[0068] This invention provides interface signals between a frequency-modulated continuous wave phase-locked loop (PLL) and an external system, namely wave_start, frame_en, and adc_en. The wave_start signal is the input signal of the PLL, provided by the external system. frame_en and adc_en are the output signals of the PLL, provided to the external system. The external system can adjust the start time of the wave_start signal to control the waveform generation of the PLL. The PLL can adjust the output timing and validity period of frame_en and adc_en, thereby providing the output to the external system.

[0069] It should be noted that this embodiment addresses the requirements of linear frequency modulated pulse waveform generation, period, and frequency resolution in FMCW radar systems. It utilizes a phase-locked loop (PLL) to generate waveforms such as triangular waves and sawtooth waves. Furthermore, it enables configurable waveform repetition period, waveform slope, and frequency resolution according to the requirements of the FMCW radar system, and generates interface signals for interaction with the FMCW radar system. To address the drawbacks of long design cycles and high costs associated with application-specific integrated circuits (ASICs), a programmable gate array (FPGA) is introduced into the PLL design for auxiliary design, replacing some functions of the digital circuitry in the PLL. This supports both on-chip and off-chip modes, enabling on-chip data read / write functionality.

[0070] In terms of structural composition, compared with the linear frequency modulated continuous wave phase-locked loop (PLL) digital circuit system and PLL proposed in patent application CN114024547A, in this embodiment, the frequency and phase detector, charge pump, filter, voltage-controlled oscillator, dual-mode divider, tri-state interface circuit, and on-chip digital circuit system are implemented by ASIC (Application-Specific Integrated Circuit), while the off-chip digital circuit system is implemented by FPGA (Field-Programmable Gate Array). In the CN114024547A scheme, it consists of modules such as a frequency and phase detector, charge pump, filter, voltage-controlled oscillator, and digital circuit system. The digital circuit system includes modules such as a control signal generation unit, address code generation unit, frequency division ratio lookup unit, differential-integral modulator, frequency division ratio decoding unit, and dual-mode divider. This embodiment comprises modules such as a phase-locked loop circuit, on-chip digital circuitry, off-chip digital circuitry, and a tri-state interface circuit. The on-chip digital circuitry consists of modules such as a serial peripheral interface, a frequency divider unit, a control signal generation unit, an address code generation unit, a frequency division ratio lookup unit, a differential-integral modulator, a frequency division ratio decoding unit, and a voltage-controlled oscillator (VCO) digital control code generation unit. The on-chip digital system includes a serial peripheral interface, which sets the required initial value through a configuration register; a frequency divider unit, which provides a divided clock signal for different settings; and a VCO digital control code generation unit, which generates and sends continuously changing VCO digital control codes. Furthermore, the control signal generation unit in this embodiment provides control signal generation under different waveforms, periods, and frequencies, and provides interface signals for interaction with the external FMCW radar system, such as wave_start and frame_en. The address code generation unit in this embodiment uses the clock value after frequency division as its operating clock. Under the control of the control signals under different conditions, it generates the corresponding address code and outputs interface signals for interaction with the external FMCW radar system, such as adc_en.

[0071] In terms of application scenarios, the phase-locked loop provided in the CN114024547A solution can generate different frequencies, achieve single-frequency locking, and generate sawtooth wave waveforms in frequency sweep mode. It is suitable for application scenarios with different frequency requirements and for simple waveform generation functions in FMCW radar systems, but does not provide an interface for interaction with the FMCW radar system. This invention provides waveform generation for linear frequency modulated pulses, such as sawtooth waves and triangular waves, suitable for application scenarios corresponding to different pulses in FMCW radar systems. It provides an interface for interaction with the FMCW radar system, suitable for configuration scenarios of this invention within the FMCW radar system, and suitable for application scenarios where the FMCW radar system interacts with this invention.

[0072] In one embodiment, such as Figure 8As shown, the off-chip digital circuit 30 includes a data acquisition module, a data storage module, and a control signal generation circuit; the input terminal of the data acquisition module is connected to the tri-state interface circuit 40, the output terminal of the data acquisition module is connected to the data storage module, and the output terminal of the control signal generation circuit is connected to the tri-state interface circuit 40. The output of the data storage module is connected to the analysis instrument, and the output of the analysis instrument is connected to the control signal generation circuit.

[0073] It should be noted that the off-chip digital circuit 30 enables information exchange with the internal chip and analytical instruments such as computers. The data acquisition module is connected to the data storage module, and it acquires the on-chip frequency division ratio control signal sent by the tri-state interface circuit 40 and outputs it to the data storage module. The data storage module is connected to the data acquisition module and stores the data from the acquisition module, facilitating reading and analysis by computers or other analytical instruments. The control signal generation circuit generates the off-chip frequency division ratio control signal, which, in off-chip mode, is sent to the chip through the tri-state interface circuit 40.

[0074] Among them, the off-chip digital circuit 30 system can both read on-chip signals and generate signals to send into the chip, so it can be used for chip testing and analysis.

[0075] It should be noted that the structure of the control signal generation circuit can refer to the on-chip frequency division ratio control signal generation circuit, thus partially replacing the function of the frequency division ratio control signal in the on-chip digital circuit 20 system. Alternatively, other structures can be adopted, allowing for comparative analysis with the on-chip digital circuit 20 system.

[0076] In one embodiment, the off-chip digital circuit 30's off-chip frequency division ratio control signal generation logic can either refer to the structure of the on-chip digital circuit 20 or utilize the flexibility of the FPGA and its development platform. One possible structural diagram is as follows. Figure 9 As shown. Figure 9As shown, the off-chip digital circuit 30 includes an FPGA clock network, a VIO IP core, and a frequency division ratio control signal storage unit. The outputs of the FPGA clock network and the VIO IP core are connected to the frequency division ratio control signal storage unit. The FPGA clock network provides corresponding clocks for the clock requirements of different modules. In this embodiment, the FPGA clock network provides the clock signal required by the frequency division ratio control signal storage unit, and parameters such as clock frequency and phase can be set and changed. The VIO IP core, or Virtual Input Output, can monitor and drive signals inside the FPGA in real time. The number and width of input and output ports can be set according to specific requirements. The frequency division ratio control signal storage unit, or instantiated storage unit, is used to store the value of the frequency division ratio control signal.

[0077] It should be noted that in this embodiment of the invention, VIO is used to realize signal interaction between the development platform and the FPGA, providing the enable signal and address signal of the frequency division ratio control signal storage unit. In off-chip mode, the FPGA clock network provides the operating clock for the off-chip digital circuits, and the enable signal and address signal of the frequency division ratio control signal storage unit are modified through the VIO IP core, thereby outputting the expected off-chip frequency division ratio control signal.

[0078] and Figure 8 Compared to the off-chip digital circuit 30 shown, this structure utilizes the abundant clock network resources in the FPGA, allowing the use of clocks with different frequencies and phases, enhancing configurability and facilitating debugging. Using the VIO IP core in the FPGA provides a simple interface for easy information exchange. Furthermore, the values ​​stored in the frequency division ratio control signal storage unit can be modified, exhibiting characteristics of repeatable configuration and high flexibility.

[0079] In one embodiment, such as Figures 10-11 As shown, the tri-state interface circuit 40 has two input ports and two output ports, including two operating modes: on-chip mode and off-chip mode. The first input terminal is connected to the on-chip frequency division ratio control signal of the on-chip digital circuit 20 system, and the second input terminal is connected to the off-chip frequency division ratio control signal of the off-chip digital circuit 30 system. The first output terminal is connected to the dual-mode frequency divider 15, and the second output terminal is connected to the off-chip digital circuit 30 system.

[0080] When the mode switch is in on-chip mode, the first output of the tri-state interface circuit 40 outputs the on-chip frequency division ratio control signal to the dual-mode frequency divider 15, and at the same time, the second output output outputs the on-chip frequency division ratio control signal to the off-chip digital circuit 30 system.

[0081] When the mode switch is in external mode, the first output of the tri-state interface circuit 40 outputs the external frequency division ratio control signal of the external digital circuit 30 system to the dual-mode frequency divider 15, while the second output blocks the connection between the on-chip digital circuit 20 system and the external digital circuit 30 system, i.e., it is set to high impedance.

[0082] For the output port, there are three states: output on-chip frequency division ratio control signal, output off-chip frequency division ratio control signal, and high impedance state.

[0083] Specifically, the implementation method of the three-state interface circuit is as follows: Figure 12 As shown: like Figure 12 As shown, the tri-state interface circuit has an input port A, an output port B, and an input / output port INOUT; the EN signal represents the mode switch, with EN being 1 representing on-chip mode and EN being 0 representing off-chip mode.

[0084] When EN is 1, A is the input port, B is the output port, and INOUT is the output port. Input signal A is the on-chip frequency division ratio control signal. EN controls the transmission gate to open, and input signal A passes through the transmission gate, combinational logic 1, combinational logic 2, and the corresponding PMOS and NMOS transistors to the output port INOUT. Additionally, input signal A is transmitted to output port B via wires. Output port INOUT is connected to a chip pin, and output port B is connected to the chip's internal dual-mode divider. Therefore, when EN is 1, the tri-state interface circuit outputs the on-chip frequency division ratio control signal to the dual-mode divider and simultaneously to the chip pin.

[0085] When EN is 0, A is the input port, B is the output port, and INOUT is the input port. Input signal A is the on-chip frequency division ratio control signal, and EN controls the transmission gate to turn off. The signal from input port INOUT, i.e., the off-chip frequency division ratio control signal, is transmitted to output port B through combinational logic 3, combinational logic 4, and the corresponding PMOS and NMOS transistors. Input port INOUT is connected to the chip pins, and output port B is connected to the on-chip dual-mode divider. Therefore, when EN is 0, the tri-state interface circuit outputs the off-chip frequency division ratio control signal to the dual-mode divider, while simultaneously blocking the connection between input port A and output port B, i.e., setting it to high impedance.

[0086] The tri-state interface circuit provided in this embodiment of the invention uses INOUT as an input / output port. By multiplexing pins, this structure can both read signals from inside the chip through the pins and shut down the signal path inside the chip, allowing input signals to be sent to the chip from the pins. Therefore, this structure can reduce the number of chip pins, facilitate chip testing and debugging, and has the advantages of low hardware consumption and high flexibility.

[0087] In one embodiment, the off-chip digital circuit 30 is integrated using an FPGA chip, and the phase-locked loop circuit 10, the on-chip digital circuit 20, and the tri-state interface circuit 40 are integrated using an ASIC chip.

[0088] It should be noted that the phase-locked loop circuit 10, the tri-state interface circuit 40, and the on-chip digital circuit 20 are implemented by ASIC (Application-Specific Integrated Circuit), while the off-chip digital circuit 30 system is implemented by FPGA (Field-Programmable Gate Array). By combining the advantages of ASIC (small area, high performance, and low power consumption) and FPGA (high flexibility, programmability, and short development cycle), the two can complement each other to achieve a frequency synthesis source with a wide frequency range, fine frequency stepping, low phase noise, and fast frequency switching. This enables the function of continuously adjustable or fixed frequency output, adapting to the needs of different phase-locked loop systems.

[0089] In addition, such as Figure 13 As shown, the second embodiment of the present invention proposes a control method for an off-chip configurable frequency-modulated continuous wave phase-locked loop system, the control method comprising the following steps: S10. Use the on-chip digital circuit to output digital control code to the phase-locked loop circuit to control the operation of the phase-locked loop circuit; S20. Generate the on-chip frequency division ratio control signal and the off-chip frequency division ratio control signal using the on-chip digital circuit and the off-chip digital circuit respectively; S30. When the tri-state interface circuit is in on-chip mode, the on-chip frequency division ratio control signal is obtained through its first input terminal and forwarded to the phase-locked loop circuit through the first output terminal. S40. When the tri-state interface circuit is in off-chip mode, the off-chip frequency division ratio control signal is obtained through its second input terminal and forwarded to the phase-locked loop circuit through the first output terminal. At the same time, the second output terminal of the tri-state interface circuit is set to high impedance state.

[0090] This embodiment, by setting a three-state interface circuit, can acquire the external frequency division ratio control signal and the internal frequency division ratio control signal output by the external digital circuit and the internal digital circuit respectively. The digital control system that realizes the phase-locked loop frequency modulation continuous wave function can be implemented in the internal digital circuit or the external digital circuit. Therefore, the function of the phase-locked loop system can be configured and controlled externally, and the external digital circuit can replace some functions of the internal digital circuit system. Both the external and external digital systems can input control signals to the dual-mode frequency divider, which improves the stability, reliability and configurability of the overall phase-locked loop system.

[0091] In one embodiment, step S20, which involves generating an on-chip frequency division ratio control signal using the on-chip digital circuitry, includes the following steps: The serial peripheral interface is used to perform write operations on the configuration registers in different phase-locked loop modes. The information written includes the frequency division ratio setting value, time step setting value, frequency step setting value, address code initial value, and control code initial value. The phase-locked loop modes include fixed frequency division ratio mode and frequency sweep mode. The frequency division unit reads the frequency division ratio setting value set in the configuration register, divides the input reference clock, obtains the frequency-divided clock, and outputs it to the address code generation unit as the clock signal of the address code generation unit. The control signal generating unit generates a control signal in the frequency sweep mode based on the write information in different modes, and inputs it to the address code generating unit and the differential integral modulator. The address code generation unit generates an address code based on the control signal and sends it to the frequency division ratio lookup table, so that the frequency division ratio lookup table outputs the frequency division ratio corresponding to the address code to the differential integral modulator; The differential integral modulator modulates the division ratio to generate a modulated division ratio, which is then sent to the division ratio decoding unit. The division ratio decoding unit converts the modulated division ratio into a division ratio control signal and outputs it to the tri-state interface circuit.

[0092] In one embodiment, step S10: using the on-chip digital circuit to output digital control codes to the phase-locked loop circuit to control the operation of the phase-locked loop circuit includes the following steps: The voltage-controlled oscillator digital control code generation unit acquires the reference clock, the address code sent by the address code generation unit, the initial address code value sent by the serial peripheral interface, and the initial control code value. In the fixed frequency division ratio mode, when the address code is a fixed value, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator is equal to the initial value of the control code; In frequency sweep mode, when the address code changes continuously and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator begins to change continuously.

[0093] In one embodiment, the method further includes: The control signal generation unit calculates the working time and period required by the address code generation unit and the differential integral modulator in the frequency sweep mode based on the maximum value, minimum value and step size of the frequency sweep. The function is achieved by changing the control signal output by the control signal generation unit.

[0094] In one embodiment, the method further includes: The address code generation unit adjusts the period and slope of the waveform in the frequency sweep mode based on the frequency step size written to the register in the serial peripheral interface and the time step size output by the frequency divider unit.

[0095] Specifically, the way the address code changes continuously is determined by the desired waveform. When generating a sawtooth wave, the address code needs to be continuously increased. Once it reaches the preset maximum sweep value, it needs to be reset to the initial value, i.e., the minimum sweep value. When generating a triangular wave, the address code needs to be continuously increased. Once it reaches the preset maximum sweep value, it needs to be continuously decreased until it returns to the initial value, i.e., the minimum sweep value. It is worth noting that the frequency of the phase-locked loop cannot change abruptly, otherwise it will lose lock during the sweep process. Therefore, in the actual implementation of the triangular wave, a holding period is added. That is, after the address code continuously increases to the preset maximum sweep value, it will remain unchanged for a period of time before continuously decreasing until it reaches the initial value, i.e., the minimum sweep value.

[0096] Furthermore, in the frequency sweep mode, the control signal of the address code generation unit is 0, and in the fixed frequency division ratio mode, the control signal of the address code generation unit changes from 0 to 1; the time when the control signal of the address code generation unit is 0 and the time when it is 1 are both adjustable, and the time when the control signal of the address code generation unit is 0 is greater than the locking time of the phase-locked loop circuit.

[0097] In one embodiment, the method further includes: When the phase-locked loop circuit starts working, it enters the fixed frequency division ratio mode. When the control signal generation unit detects that the wave_start signal input from the external system is valid, it generates a control signal in the frequency sweep mode and sends it to the address code generation unit. Otherwise, it will continue to work in the fixed frequency division ratio mode. When the waveform begins to occur, the control signal generation unit generates a valid frame_en signal and outputs it to the external system; When the frequency of the output waveform of the address code generation unit enters the set region, a valid adc_en signal is generated and output to an external system; Once all waveforms have been generated, return to fixed frequency division ratio mode.

[0098] It should be noted that the control method for the off-chip configurable frequency-modulated continuous wave phase-locked loop system described in this invention is used to control the off-chip configurable frequency-modulated continuous wave phase-locked loop system. Other embodiments can refer to the above system embodiments, and will not be repeated here.

[0099] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0101] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An off-chip configurable frequency-modulated continuous wave phase-locked loop system, characterized in that, The system includes a phase-locked loop (PLL) circuit, an on-chip digital circuit, an off-chip digital circuit, and a tri-state interface circuit. The output of the on-chip digital circuit is connected to the PLL circuit. The outputs of the on-chip digital circuit and the off-chip digital circuit are respectively connected to the first and second inputs of the tri-state interface circuit to output on-chip and off-chip frequency division ratio control signals to the tri-state interface circuit. The first output of the tri-state interface circuit is connected to the PLL circuit so that when the tri-state interface circuit is in on-chip mode, the on-chip frequency division ratio control signal is sent to the PLL circuit through the first output; when in off-chip mode, the off-chip frequency division ratio control signal is sent to the PLL circuit through the first output. The second output of the tri-state interface circuit is set to a high-impedance state. The on-chip digital circuitry includes a serial peripheral interface, a control signal generation unit, a frequency division unit, an address code generation unit, a frequency division ratio lookup table, a differential integral modulator, a frequency division ratio decoding unit, and a voltage-controlled oscillator digital control code generation unit. The serial peripheral interface includes a configuration register for writing frequency division ratio settings, time step settings, and frequency step settings. The control signal generation unit is used to generate control signals corresponding to the sweep frequency mode and the fixed frequency division ratio mode. The output terminals of the serial peripheral interface are respectively connected to the frequency division unit, the control signal generation unit, and the voltage-controlled oscillator digital control code generation unit. The output terminals of the frequency division unit and the control signal generation unit are respectively connected to the address code generation unit. The output terminals of the address code generation unit are respectively connected to the frequency division ratio lookup table and the voltage-controlled oscillator digital control code generation unit. The output terminals of the frequency division ratio lookup table and the control signal generation unit are respectively connected to the differential integral modulator. The output terminal of the differential integral modulator is connected to the frequency division ratio decoding unit. The output of the frequency division ratio decoding unit is connected to the tri-state interface circuit, and the output of the voltage-controlled oscillator digital control code generation unit is connected to the voltage-controlled oscillator in the phase-locked loop circuit.

2. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 1, characterized in that, The phase-locked loop circuit includes a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a dual-mode divider. The output of the frequency and phase detector is connected to the VCO after passing through the charge pump and the filter. The output of the VCO is connected to the frequency and phase detector and the on-chip digital circuit via the dual-mode divider. The output of the on-chip digital circuit is connected to the VCO. The first output terminal of the tri-state interface circuit is connected to the dual-mode frequency divider.

3. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 1, characterized in that, The second output terminal of the tri-state interface circuit is also connected to the input terminal of the external digital circuit to output the on-chip frequency division ratio control signal to the external digital circuit.

4. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 1, characterized in that, In the frequency sweep mode, the control signal of the address code generation unit is 0, and in the fixed frequency division ratio mode, the control signal of the address code generation unit changes from 0 to 1; the time when the control signal of the address code generation unit is 0 is longer than the locking time of the phase-locked loop circuit.

5. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 1, characterized in that, The input signals of the voltage-controlled oscillator digital control code generation unit include a reference clock, the address code sent by the address code generation unit, the initial value of the address code sent by the serial peripheral interface, and the initial value of the control code. When the address code is a fixed value, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generator to the voltage-controlled oscillator is equal to the initial value of the control code; When the address code changes continuously and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator begins to change continuously, and the change step size is related to the frequency characteristics of the voltage-controlled oscillator.

6. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 1, characterized in that, The control signal generation unit is connected to an external system to receive the interface signal wave_start sent by the external system and to send a valid frame_en signal to the external system when the interface signal wave_start is valid. The interface signal wave_start is used to control the start time of the phase-locked loop waveform generation, and the frame_en signal is used as a flag signal for the generation of the phase-locked loop waveform. The address code generation unit is connected to the external system to send a valid adc_en signal to the external system when the interface signal wave_start is valid. The adc_en signal is used as a flag signal for the phase-locked loop waveform linearization region.

7. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 3, characterized in that, The off-chip digital circuit includes a data acquisition module, a data storage module, and a control signal generation circuit; the input terminal of the data acquisition module is connected to the tri-state interface circuit, the output terminal of the data acquisition module is connected to the data storage module, and the output terminal of the control signal generation circuit is connected to the tri-state interface circuit. The output of the data storage module is connected to the analysis instrument, and the output of the analysis instrument is connected to the control signal generation circuit.

8. The off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 7, characterized in that, The off-chip digital circuit is integrated using an FPGA chip, while the phase-locked loop circuit, the on-chip digital circuit, and the tri-state interface circuit are integrated using an ASIC chip.

9. A control method for an off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in any one of claims 1-8, characterized in that, The control method includes: The on-chip digital circuit outputs digital control codes to the phase-locked loop circuit to control the operation of the phase-locked loop circuit; The on-chip digital circuitry and the off-chip digital circuitry are used to generate on-chip frequency division ratio control signals and off-chip frequency division ratio control signals, respectively. When the tri-state interface circuit is in on-chip mode, the on-chip frequency division ratio control signal is obtained through its first input terminal and forwarded to the phase-locked loop circuit through its first output terminal; When the tri-state interface circuit is in off-chip mode, the off-chip frequency division ratio control signal is obtained through its second input terminal and forwarded to the phase-locked loop circuit through the first output terminal. At the same time, the second output terminal of the tri-state interface circuit is set to a high-impedance state.

10. The control method for the off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 9, characterized in that, The on-chip digital circuitry is used to generate an on-chip frequency division ratio control signal, including: The serial peripheral interface is used to perform write operations on the configuration registers in different phase-locked loop modes. The information written includes the frequency division ratio setting value, time step setting value, frequency step setting value, address code initial value, and control code initial value. The phase-locked loop modes include fixed frequency division ratio mode and frequency sweep mode. The frequency division unit reads the frequency division ratio setting value set in the configuration register, divides the input reference clock, obtains the frequency-divided clock, and outputs it to the address code generation unit as the clock signal of the address code generation unit. The control signal generation unit generates a control signal in the frequency sweep mode based on the write information in different modes, and inputs it to the address code generation unit and the differential integral modulator. The address code generation unit generates an address code based on a control signal and sends it to the frequency division ratio lookup table, so that the frequency division ratio lookup table outputs the frequency division ratio corresponding to the address code to the differential integral modulator; The differential integral modulator modulates the division ratio to generate a modulated division ratio, which is then sent to the division ratio decoding unit. The division ratio decoding unit converts the modulated division ratio into a division ratio control signal and outputs it to the tri-state interface circuit.

11. The control method for the off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 10, characterized in that, The step of using the on-chip digital circuit to output digital control codes to the phase-locked loop circuit to control the operation of the phase-locked loop circuit includes: The voltage-controlled oscillator digital control code generation unit acquires the reference clock, the address code sent by the address code generation unit, the initial address code value sent by the serial peripheral interface, and the initial control code value. In the fixed frequency division ratio mode, when the address code is a fixed value, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator is equal to the initial value of the control code; In frequency sweep mode, when the address code changes continuously and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code sent by the voltage-controlled oscillator digital control code generation unit to the voltage-controlled oscillator begins to change continuously.

12. The control method for the off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 10, characterized in that, The address code generation unit adjusts the period and slope of the waveform in the frequency sweep mode based on the frequency step size written to the register in the serial peripheral interface and the time step size output by the frequency divider unit.

13. The control method for the off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 10, characterized in that, In the frequency sweep mode, the control signal of the address code generation unit is 0, and in the fixed frequency division ratio mode, the control signal of the address code generation unit changes from 0 to 1. The time when the control signal of the address code generation unit is 0 and the time when it is 1 are both adjustable, and the time when the control signal of the address code generation unit is 0 is greater than the locking time of the phase-locked loop circuit.

14. The control method for the off-chip configurable frequency-modulated continuous wave phase-locked loop system as described in claim 10, characterized in that, The method further includes: When the phase-locked loop circuit starts working, it enters the fixed frequency division ratio mode. When the control signal generation unit detects that the wave_start signal input from the external system is valid, it generates a control signal in the frequency sweep mode and sends it to the address code generation unit. Otherwise, it will continue to work in the fixed frequency division ratio mode. When the waveform begins to occur, the control signal generation unit generates a valid frame_en signal and outputs it to the external system; When the frequency of the output waveform of the address code generation unit enters the set region, a valid adc_en signal is generated and output to an external system; Once all waveforms have been generated, return to fixed frequency division ratio mode.

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