comparator

Abstract

The application provides a comparator, comprising: a preamplifier configured to input an offset voltage and provide the offset voltage to a latch; the latch is configured to latch the offset voltage through positive feedback, convert the offset voltage into an offset control signal, and provide the offset control signal to an offset calibration circuit; the offset calibration circuit is configured to convert the offset control signal into a gate control voltage, and provide the gate control voltage to the preamplifier, so that the preamplifier adjusts a compensation current according to the gate control voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a comparator. Background Technology

[0002] Comparators convert input analog signals into digital signals, serving as a crucial analog-to-digital interface and widely used in circuits such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Preamplified latch comparators, in particular, leverage the speed advantage of latching comparators compared to high-precision but slower amplifier-type comparators due to the preamplifier's ability to amplify the input analog signal, isolate the output digital signal from the input signal, and provide fast comparison and latching. They also offer some improvement in accuracy. Therefore, preamplified latch comparators are widely used in practical engineering. However, with the rapid development of digital circuits, the speed and accuracy requirements for ADCs and DACs are constantly increasing. Traditional preamplified latch comparators are insufficient to meet these high-precision requirements. Therefore, offset calibration of preamplified latch comparators plays a vital role in high-speed, high-precision applications.

[0003] Traditional offset calibration techniques store the offset using capacitors while the comparator is operating, and then calibrate the preamplifier. This method limits the comparator speed and only calibrates the preamplifier's offset, without calibrating the latch's offset. Summary of the Invention

[0004] The purpose of this invention is to provide a comparator that solves the problem that existing offset calibration limits comparator speed and does not perform offset calibration on the latch.

[0005] To solve the above-mentioned technical problems, the present invention provides a comparator, comprising:

[0006] The preamplifier is configured to receive the offset voltage and provide the offset voltage to the latch;

[0007] The latch is configured to latch the offset voltage via positive feedback, convert it into an offset control signal, and provide it to the offset calibration circuit.

[0008] An offset calibration circuit is configured to convert an offset control signal into a gate control voltage and provide it to a preamplifier, such that the preamplifier adjusts the compensation current according to the gate control voltage.

[0009] Optionally, in the comparator,

[0010] The preamplifier is further configured to receive a positive input signal and a negative input signal at its input terminal, and to amplify the differential signal of the positive input signal and the negative input signal to form a differential amplified signal provided to the latch, wherein the differential amplified signal includes an offset voltage;

[0011] The latch is configured to latch the differential amplified signal through positive feedback, converting it into an output signal with logic 0 or 1.

[0012] Optionally, in the comparator, the preamplifier includes:

[0013] The first differential input transistor and the second differential input transistor are configured to receive positive and negative input signals at their gates, respectively.

[0014] The first pull-up / pull-down resistor and the second pull-up / pull-down resistor are configured such that their gates are connected to the first differential input transistor and the second differential input transistor, respectively, to function as diodes.

[0015] Optionally, in the comparator, the preamplifier further includes:

[0016] The first current mirror transistor and the second current mirror transistor are configured to input a clock control signal to their gates, and the first terminals of their source and drain are respectively connected to the first differential input transistor and the second differential input transistor, and the second terminals of their source and drain are both grounded.

[0017] The third and fourth current mirror transistors are configured to have a first gate control voltage and a second gate control voltage input to their gates, respectively. The first terminals of their source and drain are connected to the first differential input transistor and the second differential input transistor, respectively, and the second terminals of their source and drain are both grounded.

[0018] Optionally, in the comparator,

[0019] The first terminals of the source and drain of the first pull-up / pull-down resistor and the second pull-up / pull-down resistor are both connected to the power supply, and the second terminals of the source and drain of the first pull-up / pull-down resistor and the second pull-up / pull-down resistor are respectively connected to the first terminals of the source and drain of the first differential input transistor and the second differential input transistor.

[0020] The first terminals of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the gates of the first pull-up and pull-down resistors and the second pull-up and pull-down resistors.

[0021] The second terminals of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the first terminals of the source and drain of the first current mirror transistor and the second current mirror transistor.

[0022] The second terminals of the source and drain of the first and second differential input transistors are respectively connected to the first terminals of the source and drain of the third and fourth current mirror transistors.

[0023] Optionally, in the comparator, the offset calibration circuit includes:

[0024] A first counter is configured to input a first offset control signal and convert the first offset control signal into a first count value.

[0025] The second counter is configured to input a second offset control signal and convert the first offset control signal into a second count value.

[0026] A first digital-to-analog converter circuit is configured to input a first count value and convert the first count value into a first gate control voltage.

[0027] The second digital-to-analog converter circuit is configured to input the second count value and convert the second count value into a second gate control voltage.

[0028] Optionally, in the comparator, the latch includes:

[0029] The positive feedback latch circuit is configured to amplify the difference between the first differential input signal and the second differential input signal through positive feedback, and convert it into an output signal with logic 0 or 1.

[0030] The first reset transistor and the second reset transistor are configured such that the first terminal of their source and drain is connected to the power supply, and the second terminal of their source and drain is connected to the positive feedback latch circuit.

[0031] The first differential input signal is the voltage at the connection point between the first differential input transistor and the first pull-up / pull-down resistor transistor;

[0032] The second differential input signal is the voltage at the connection point between the second differential input transistor and the second pull-up / pull-down resistor.

[0033] Optionally, in the comparator,

[0034] The first differential input transistor and the second differential input transistor are NMOS, and the first pull-up / pull-down resistor and the second pull-up / pull-down resistor are PMOS;

[0035] The first current mirror transistor, the second current mirror transistor, the third current mirror transistor, and the fourth current mirror transistor are NMOS.

[0036] Optionally, in the comparator, when the clock control signal is 1, the first current mirror transistor and the second current mirror transistor act as current mirrors to power the first differential input transistor and the second differential input transistor respectively, and the third current mirror transistor and the fourth current mirror transistor are controlled by the first digital-to-analog converter circuit and the second digital-to-analog converter circuit respectively, so as to output compensation current as compensation current mirrors.

[0037] The first and second digital-to-analog converters are 8-bit DACs.

[0038] Optionally, in the comparator, the calibration process includes:

[0039] To make both the positive and negative input signals zero, when the offset voltage is positive:

[0040] When the clock control signal is 1 and the reset control signal is 0, the system enters normal operating condition. In this case, the first offset control signal is 1 and the second offset control signal is 0.

[0041] When the clock control signal is 0 and the reset control signal is 1, the system enters the reset state. In this case, the first offset control signal is 1 and the second offset control signal is 1.

[0042] Then the first counter continuously inputs 1, and the second counter inputs a square wave signal;

[0043] When the offset voltage is negative:

[0044] When the clock control signal is 1 and the reset control signal is 0, the system enters normal operating mode. In this case, the first offset control signal is 0 and the second offset control signal is 1.

[0045] When the clock control signal is 0 and the reset control signal is 1, the system enters the reset state. In this case, the first offset control signal is 1 and the second offset control signal is 1.

[0046] Then, the first counter receives a square wave signal, and the second counter continuously receives 1.

[0047] The first digital-to-analog converter circuit and the second digital-to-analog converter circuit output the first gate control voltage and the second gate control voltage respectively based on the continuous 1 and square wave signals.

[0048] In the comparator provided by this invention, the offset voltage is latched by a latch through positive feedback and converted into an offset control signal. The offset calibration circuit converts the offset control signal into a gate control voltage and provides it to the preamplifier, so that the preamplifier adjusts the compensation current according to the gate control voltage. This realizes that the offset control signal directly output by the latch is used as the input feedback offset signal, which not only calibrates the offset of the preamplifier, but also incorporates the latch into the offset calibration. Moreover, it is directly fed back from the offset control signal and passes through the counter and DAC, so it has little impact on the comparator speed. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of a comparator according to an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the preamplifier of a comparator according to an embodiment of the present invention. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0052] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0053] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0054] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0055] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0056] It should also be noted that, in the embodiments of the present invention, only a portion of the components or parts may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, necessary components or parts can be added as needed for specific scenarios. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0057] It should also be noted that, within the scope of this invention, the terms "same," "equal," and "equal to" do not imply that the two values ​​are absolutely equal, but rather allow for a certain reasonable margin of error. In other words, the terms also encompass "substantially the same," "substantially equal," and "substantially equal to." Similarly, in this invention, the directional terms "perpendicular to," "parallel to," etc., also encompass the meanings of "substantially perpendicular to" and "substantially parallel to."

[0058] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0059] The comparator proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0060] The purpose of this invention is to provide a comparator that solves the problem that existing offset calibration limits comparator speed and does not perform offset calibration on the latch.

[0061] To achieve the above objectives, the present invention provides a comparator comprising: a preamplifier configured to input an offset voltage and provide the offset voltage to a latch; a latch configured to latch the offset voltage via positive feedback, convert it into an offset control signal, and provide it to an offset calibration circuit; and an offset calibration circuit configured to convert the offset control signal into a gate control voltage and provide it to the preamplifier, such that the preamplifier adjusts the compensation current according to the gate control voltage.

[0062] Figure 1-2 Embodiments of the present invention are provided, such as Figure 1 As shown, the present invention provides a comparator, comprising: a preamplifier configured to input an offset voltage and provide the offset voltage to a latch; and a latch configured to latch the offset voltage via positive feedback and convert it into an offset control signal V. out+ and V out- and provides to the offset calibration circuit; the offset calibration circuit is configured to convert the offset control signal V out+ and V out- It is converted into a gate control voltage and provided to the preamplifier so that the preamplifier adjusts the compensation current according to the gate control voltage.

[0063] Specifically, in the comparator, the preamplifier is further configured to receive positive input signals V at its input terminals. in+ and negative input signal V in- The differential signal between the positive and negative input signals is amplified to form a differential amplified signal, which is provided to the latch. The differential amplified signal includes an offset voltage. The latch is configured to latch the differential amplified signal through positive feedback and convert it into an output signal with logic 0 or 1.

[0064] like Figure 2 As shown, in the comparator, the preamplifier includes: a first differential input transistor M1 and a second differential input transistor M2, configured to receive a positive input signal and a negative input signal respectively at their gates; a first pull-up / pull-down resistor M3 and a second pull-up / pull-down resistor M4, configured to have their gates connected to the first differential input transistor M1 and the second differential input transistor M2 respectively, to function as diodes.

[0065] Furthermore, in the comparator, the preamplifier further includes: a first current mirror transistor M7 and a second current mirror transistor M8, configured to receive a clock control signal CLK at their gates, with the first terminals of their sources and drains respectively connected to the first differential input transistor and the second differential input transistor, and the second terminals of their sources and drains both grounded; a third current mirror transistor M5 and a fourth current mirror transistor M6, configured to receive a first gate control voltage and a second gate control voltage at their gates, with the first terminals of their sources and drains respectively connected to the first differential input transistor M1 and the second differential input transistor M2, and the second terminals of their sources and drains both grounded.

[0066] like Figure 2 As shown, in the comparator, the first terminals (sources) of the source and drain of the first pull-up / pull-down resistor M3 and the second pull-up / pull-down resistor M4 are both connected to the power supply. The second terminals (drains) of the source and drain of the first pull-up / pull-down resistor M3 and the second pull-up / pull-down resistor M4 are respectively connected to the first terminals (drains) of the source and drain of the first differential input transistor M1 and the second differential input transistor M2. The first terminals (drains) of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the gates of the first pull-up / pull-down resistor and the second pull-up / pull-down resistor. The second terminals (sources) of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the first terminals (drains) of the source and drain of the first current mirror transistor and the second current mirror transistor. The second terminals (sources) of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the first terminals (drains) of the source and drain of the third current mirror transistor and the fourth current mirror transistor.

[0067] like Figure 1 As shown, in the comparator, the offset calibration circuit includes: a first counter configured to input a first offset control signal and convert the first offset control signal into a first count value; a second counter configured to input a second offset control signal and convert the first offset control signal into a second count value; a first digital-to-analog converter configured to input the first count value and convert the first count value into a first gate control voltage; and a second digital-to-analog converter configured to input the second count value and convert the second count value into a second gate control voltage.

[0068] Specifically, in the comparator, the latch includes a positive feedback latch circuit configured to latch the first differential input signal V. out1 Second differential input signal V out2 The difference is amplified through positive feedback and converted into an output signal with logic 0 or 1; the first reset transistor and the second reset transistor are configured such that the first terminal of their source and drain is connected to the power supply, and the second terminal of their source and drain is connected to the positive feedback latch circuit; wherein the first differential input signal V out1 The voltage at the connection point between the first differential input transistor and the first pull-up / pull-down resistor; the second differential input signal Vout2 This is the voltage at the connection point between the second differential input transistor and the second pull-up / pull-down resistor.

[0069] Furthermore, in the comparator, the first differential input transistor and the second differential input transistor are NMOS, the first pull-up / pull-down resistor transistor and the second pull-up / pull-down resistor transistor are PMOS; the first current mirror transistor, the second current mirror transistor, the third current mirror transistor and the fourth current mirror transistor are NMOS.

[0070] In addition, in the comparator, when the clock control signal is 1, the first current mirror transistor and the second current mirror transistor act as current mirrors to power the first differential input transistor and the second differential input transistor respectively. The third current mirror transistor and the fourth current mirror transistor are controlled by the first digital-to-analog converter circuit and the second digital-to-analog converter circuit respectively, so as to output compensation current as compensation current mirrors. The first digital-to-analog converter circuit and the second digital-to-analog converter circuit are 8-bit DACs.

[0071] Specifically, in the comparator, the calibration process includes:

[0072] To make both the positive and negative input signals zero, when the offset voltage is positive:

[0073] When the clock control signal CLK is 1 and the reset control signal is 0, the system enters normal operating mode. Then the first offset control signal V... out+ The second offset control signal V is 1. out- =0;

[0074] When the clock control signal is 0 and the reset control signal is 1, the system enters the reset state. Then the first offset control signal V... out+ The second offset control signal V is 1. out- =1;

[0075] Then the first counter continuously inputs 1, and the second counter inputs a square wave signal;

[0076] When the offset voltage is negative:

[0077] When the clock control signal is 1 and the reset control signal is 0, the system enters normal operating mode. The first offset control signal V... out+ The second offset control signal V is 0. out- =1;

[0078] When the clock control signal is 0 and the reset control signal is 1, the system enters the reset state. Then the first offset control signal V... out+ The second offset control signal V is 1. out- =1;

[0079] Then, the first counter receives a square wave signal, and the second counter continuously receives 1.

[0080] The first digital-to-analog converter circuit and the second digital-to-analog converter circuit output the first gate control voltage and the second gate control voltage respectively based on the continuous 1 and square wave signals.

[0081] In the comparator provided by this invention, the offset voltage is latched by a latch through positive feedback and converted into an offset control signal. The offset calibration circuit converts the offset control signal into a gate control voltage and provides it to the preamplifier, so that the preamplifier adjusts the compensation current according to the gate control voltage. This realizes that the offset control signal directly output by the latch is used as the input feedback offset signal, which not only calibrates the offset of the preamplifier, but also incorporates the latch into the offset calibration. Moreover, it is directly fed back from the offset control signal and passes through the counter and DAC, so it has little impact on the comparator speed.

[0082] This invention employs offline calibration. Without any input, when a positive offset voltage is input, then V... out+ It will remain at a high level, V out- During the comparison, the phase will be pulled low, and V will be reset. out- The phase will return to a high level. Therefore, the first counter, with a high input, will always output 0. The second counter, with a square wave input, will output a set of numbers. This set of numbers will control the second digital-to-analog converter to generate an analog voltage, which is supplied to the compensation current mirror as a low-voltage side compensation current, thereby canceling out the generated offset voltage.

[0083] In summary, the above embodiments have provided detailed descriptions of different comparator configurations. Of course, this invention includes, but is not limited to, the configurations listed in the above embodiments. Any modifications made based on the configurations provided in the above embodiments are within the scope of protection of this invention. Those skilled in the art can apply the knowledge gained from the above embodiments to other similar applications.

[0084] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0085] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A comparator, characterized by include: A preamplifier is configured to receive a positive input signal and a negative input signal at its input terminal, and to amplify the differential signal of the positive input signal and the negative input signal to form a differential amplified signal provided to a latch, wherein the differential amplified signal includes an offset voltage; The latch is configured to latch the differential amplified signal via positive feedback, convert it into an offset control signal of logic 0 or 1, and provide it to the offset calibration circuit. as well as Offset calibration circuitry is configured to convert offset control signal into gate control voltage and provide it to preamplifier, such that preamplifier adjusts compensation current according to gate control voltage; The preamplifier includes: The first differential input transistor and the second differential input transistor are configured to receive positive and negative input signals at their gates, respectively. The first pull-up and pull-down resistors and the second pull-up and pull-down resistors are configured such that their gates are connected to the first differential input transistor and the second differential input transistor, respectively, to function as diodes; The first current mirror transistor and the second current mirror transistor are configured to receive a clock control signal at their gates. The first terminals of their source and drain are respectively connected to the first differential input transistor and the second differential input transistor, and the second terminals of their source and drain are both grounded. The third current mirror transistor and the fourth current mirror transistor are configured to have a first gate control voltage and a second gate control voltage input to their gates, respectively. The first terminals of their source and drain are connected to the first differential input transistor and the second differential input transistor, respectively, and the second terminals of their source and drain are both grounded. The first terminals of the source and drain of the first pull-up / pull-down resistor and the second pull-up / pull-down resistor are both connected to the power supply, and the second terminals of the source and drain of the first pull-up / pull-down resistor and the second pull-up / pull-down resistor are respectively connected to the first terminals of the source and drain of the first differential input transistor and the second differential input transistor. The first terminals of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the gates of the first pull-up and pull-down resistors and the second pull-up and pull-down resistors. The second terminals of the source and drain of the first differential input transistor and the second differential input transistor are respectively connected to the first terminals of the source and drain of the first current mirror transistor and the second current mirror transistor. The second terminals of the source and drain of the first and second differential input transistors are respectively connected to the first terminals of the source and drain of the third and fourth current mirror transistors.

2. The comparator as claimed in claim 1, characterized in that, The offset calibration circuit includes: A first counter is configured to input a first offset control signal and convert the first offset control signal into a first count value. The second counter is configured to input the second offset control signal and convert the second offset control signal into a second count value; A first digital-to-analog converter circuit is configured to input a first count value and convert the first count value into a first gate control voltage; and The second digital-to-analog converter circuit is configured to input the second count value and convert the second count value into a second gate control voltage.

3. The comparator as described in claim 2, characterized in that, The latch includes: The positive feedback latch circuit is configured to amplify the difference between the first differential amplified signal and the second differential amplified signal through positive feedback, and convert it into an offset control signal with a logic value of 0 or 1. The first reset transistor and the second reset transistor are configured such that the first terminal of their source and drain is connected to the power supply, and the second terminal of their source and drain is connected to the positive feedback latch circuit. The first differential amplified signal is the voltage at the connection point between the first differential input transistor and the first pull-up / pull-down resistor transistor; The second differential amplified signal is the voltage at the connection point between the second differential input transistor and the second pull-up / pull-down resistor.

4. The comparator as described in claim 3, characterized in that, The first differential input transistor and the second differential input transistor are NMOS, and the first pull-up / pull-down resistor and the second pull-up / pull-down resistor are PMOS; The first current mirror transistor, the second current mirror transistor, the third current mirror transistor, and the fourth current mirror transistor are NMOS.

5. The comparator as described in claim 4, characterized in that, When the clock control signal is 1, the first current mirror transistor and the second current mirror transistor act as current mirrors to power the first differential input transistor and the second differential input transistor respectively. The third current mirror transistor and the fourth current mirror transistor are controlled by the first digital-to-analog converter circuit and the second digital-to-analog converter circuit respectively, so as to output compensation current as compensation current mirrors. The first and second digital-to-analog converters are 8-bit DACs.

6. The comparator as claimed in claim 5, characterized in that, The calibration process includes: To make both the positive and negative input signals zero, when the offset voltage is positive: When the clock control signal is 1 and the reset control signal is 0, the system enters normal operating condition. In this case, the first offset control signal is 1 and the second offset control signal is 0. When the clock control signal is 0 and the reset control signal is 1, the system enters the reset state. In this case, the first offset control signal is 1 and the second offset control signal is 1. Then the first counter continuously inputs 1, and the second counter inputs a square wave signal; When the offset voltage is negative: When the clock control signal is 1 and the reset control signal is 0, the system enters normal operating mode. In this case, the first offset control signal is 0 and the second offset control signal is 1. When the clock control signal is 0 and the reset control signal is 1, the system enters the reset state. In this case, the first offset control signal is 1 and the second offset control signal is 1. Then, the first counter receives a square wave signal, and the second counter continuously receives 1. The first digital-to-analog converter circuit and the second digital-to-analog converter circuit output the first gate control voltage and the second gate control voltage respectively based on the continuous 1 and square wave signals.

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