Transceiver chip and radio frequency tag

Abstract

The application provides a transceiving chip and a radio frequency tag, and the transceiving chip comprises an antenna interface, a receiving data interface, a transmitting data interface, a radio frequency transceiving unit and a baseband unit. The radio frequency transceiving unit comprises a switch, a receiver and a transmitter. The antenna interface is used for connecting a radio frequency antenna. One end of the switch is connected to the antenna interface, and the other end of the switch is connected to the input end of the receiver. The output end of the receiver is connected to the input end of the baseband unit. The output end of the baseband unit is connected to the receiving data interface. The receiving data interface and the transmitting data interface are used for connecting a processing unit. The transmitting data interface is connected to the input end of the transmitter. The output end of the transmitter is connected to the antenna interface. The receiver, the transmitter and the switch are jointly designed with the radio frequency antenna. The receiver can be provided with radio frequency gain without an additional off-chip matching network. The input capacitance of the receiver can be isolated from the transmitter by introducing the switch, and the transmitting efficiency of the transmitter is improved.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and more specifically, to a transceiver chip and an RFID tag. Background Technology

[0002] For event-driven IoT applications, such as remote control and livestock monitoring, ultra-low power active RFID tags capable of long-distance communication are valuable because they can extend battery life and save on maintenance costs.

[0003] Currently, receivers for ultra-low power active RFID tags consist of envelope detectors (EDs). However, receivers using envelope detectors require an additional off-chip matching network to provide RF gain, which limits the operating frequency band and increases receiver area and manufacturing cost. Furthermore, for the transmitter, if the envelope detector is directly connected to the voltage-controlled oscillator-power amplifier (VCO-PA), the input capacitance of the envelope detector introduces a large fixed capacitance in the LC resonant cavity of the VCO-PA, thereby impairing the quality factor of the resonant cavity and affecting the transmission efficiency of active RF. Summary of the Invention

[0004] In view of this, embodiments of this application provide a transceiver chip and an RFID tag to solve the problems that receivers composed of envelope detectors require an additional off-chip matching network to provide RF gain, which limits the operating frequency band of the receiver and increases the receiver area and manufacturing cost, as well as the introduction of large fixed capacitance in the resonant cavity of the voltage-controlled oscillator-power amplifier, which degrades the quality factor of the resonant cavity and affects the transmission efficiency of active RF.

[0005] In a first aspect, embodiments of this application provide a transceiver chip, including: an antenna interface, a receive data interface, a transmit data interface, a radio frequency transceiver unit, and a baseband unit; wherein, the radio frequency transceiver unit includes: a switching switch, a receiver, and a transmitter;

[0006] The antenna interface is used to connect a radio frequency antenna. One end of the switch is connected to the antenna interface, and the other end of the switch is connected to the input terminal of the receiver. The output terminal of the receiver is connected to the input terminal of the baseband unit, and the output terminal of the baseband unit is connected to the data receiving interface.

[0007] The receiving data interface and the transmitting data interface are used to connect to the processing unit. The transmitting data interface is connected to the input terminal of the transmitter, and the output terminal of the transmitter is connected to the antenna interface.

[0008] In an optional embodiment, the transmitter includes: an adjustable capacitor and an oscillating power amplifier; the input terminal of the oscillating power amplifier is the input terminal of the transmitter, the adjustable capacitor is connected between the two first output terminals of the oscillating power amplifier, and the two first output terminals of the oscillating power amplifier are also connected to the antenna interface.

[0009] In an optional embodiment, the transceiver chip further includes: a frequency calibration unit, a control interface, a clock interface, and a first oscillator, wherein the control interface is used to receive an input preset standard capacitor control word, the first oscillator is connected to an oscillating crystal through the clock interface, the input terminal of the frequency calibration unit is connected to the second output terminal of the transmitter, and the output terminal of the frequency calibration unit is connected to the control terminal of the adjustable capacitor.

[0010] In an optional embodiment, the frequency calibration unit includes: a frequency divider, a calibration logic module, and a register. The second output terminal of the transmitter is connected to the first input terminal of the calibration logic module through the frequency divider. The control interface and the first oscillator are respectively connected to the second input terminal and the third input terminal of the calibration logic module. The output terminal of the calibration logic module is connected to the control terminal of the adjustable capacitor through the register.

[0011] In an optional embodiment, the switching switch includes: a first switching unit and a second switching unit, one end of the first switching unit is connected to the antenna interface, and the other end of the first switching unit is connected to the input terminal of the receiver; one end of the second switching unit is connected to the antenna interface, and the other end of the second switching unit is connected to the input terminal of the receiver.

[0012] In an optional embodiment, the transceiver chip further includes a receive enable interface, the first switching unit includes a first switching transistor and a second switching transistor, the second switching unit includes a third switching transistor and a fourth switching transistor; the control terminals of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all connected to the receive enable interface, and the receive enable interface is used to receive an input enable signal;

[0013] The input terminals of the first switch and the third switch are connected to the antenna interface. The output terminal of the first switch is connected to the input terminal of the second switch. The output terminal of the third switch is connected to the input terminal of the fourth switch. The input terminals of the second switch and the fourth switch are both connected to the input terminal of the receiver. The output terminals of the second switch and the fourth switch are both grounded.

[0014] In an optional embodiment, the adjustable capacitor includes: a first switched capacitor array and a second switched capacitor array, wherein the first switched capacitor array includes: a plurality of first switched capacitors connected in parallel, and the second switched capacitor array includes: a plurality of second switched capacitors connected in parallel.

[0015] One end of the plurality of first switched capacitors is connected to one end of the plurality of second switched capacitors, and the other end of the plurality of first switched capacitors is connected to the other end of the plurality of second switched capacitors. The plurality of first switched capacitors and the plurality of second switched capacitors are disposed between the two first output terminals of the oscillation power amplifier. The control terminals of the plurality of first switched capacitors and the plurality of second switched capacitors are both connected to the output terminal of the frequency calibration unit.

[0016] In an optional embodiment, each switched capacitor includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth switching transistor, and a sixth switching transistor. One end of the first capacitor is connected to the input terminal of the fifth switching transistor, one end of the second capacitor is connected to the input terminal of the sixth switching transistor, one end of the first capacitor is also connected to one end of the third capacitor, and one end of the second capacitor is also connected to one end of the fourth capacitor.

[0017] The other ends of the third capacitor and the fourth capacitor are respectively connected to the two first output terminals of the oscillation power amplifier. The output terminals of the fifth switch and the sixth switch are both grounded. The control terminals of the fifth switch and the sixth switch are both connected to the output terminal of the frequency calibration unit.

[0018] In an optional implementation, the baseband unit includes: a signal amplifier, a comparator, an automatic offset voltage control logic unit, and a second oscillator. The input terminal of the signal amplifier is connected to the output terminal of the receiver, the output terminal of the signal amplifier is connected to the first input terminal of the comparator, the second input terminal of the comparator is grounded, and the output terminal of the comparator is connected to the receive data interface.

[0019] The automatic offset voltage control logic unit is connected between the output and control terminals of the comparator, and both the clock input of the comparator and the clock input of the automatic offset voltage control logic unit are connected to the second oscillator.

[0020] Secondly, embodiments of this application also provide an RFID tag, including: a processing unit, an RFID antenna, and any of the transceiver chips described in the first aspect.

[0021] This application provides a transceiver chip and an RFID tag. The transceiver chip includes an antenna interface, a receive data interface, a transmit data interface, an RF transceiver unit, and a baseband unit. The RF transceiver unit includes a switch, a receiver, and a transmitter. The antenna interface is used to connect to an RF antenna. One end of the switch is connected to the antenna interface, and the other end is connected to the input of the receiver. The output of the receiver is connected to the input of the baseband unit, and the output of the baseband unit is connected to the receive data interface. The receive data interface and the transmit data interface are used to connect to a processing unit. The transmit data interface is connected to the input of the transmitter, and the output of the transmitter is connected to the antenna interface. By using a receiver, transmitter, and switch designed in conjunction with the RF antenna, RF gain can be provided to the receiver without the need for an additional off-chip matching network. Furthermore, by introducing the switch, the input capacitor of the receiver can be isolated from the transmitter, thereby improving the transmission efficiency of the transmitter.

[0022] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram illustrating a scenario involving a reader and an RFID tag, as provided in an embodiment of this application.

[0025] Figure 2 A circuit diagram of an existing active RFID tag provided for an embodiment of this application;

[0026] Figure 3 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 1 ;

[0027] Figure 4 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 2 ;

[0028] Figure 5 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 3 ;

[0029] Figure 6 A schematic diagram of the circuit structure of the frequency calibration unit provided in the embodiments of this application;

[0030] Figure 7 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 4 ;

[0031] Figure 8 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 5 ;

[0032] Figure 9 This is a schematic diagram of the equivalent circuit in the receiving mode provided in the embodiments of this application;

[0033] Figure 10 This is a schematic diagram of the equivalent circuit in the transmission mode provided in the embodiments of this application;

[0034] Figure 11 A schematic diagram of voltage gain in the receiving mode provided in the embodiments of this application;

[0035] Figure 12 A circuit diagram of the switching unit provided in an embodiment of this application;

[0036] Figure 13 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 6 ;

[0037] Figure 14 A schematic diagram of a switched capacitor provided in an embodiment of this application;

[0038] Figure 15 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 7 ;

[0039] Figure 16 A schematic diagram of a specific transceiver chip circuit structure provided for an embodiment of this application;

[0040] Figure 17 This is a schematic diagram illustrating the operation flow of the RFID tag provided in the application embodiment. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0042] Existing active RFID tags have the following characteristics:

[0043] First, while receivers using this structure can achieve sensitivity of less than -60 dBm at nanowatt power, the transmitter's output power limits communication range and battery life. For example, when communicating with a Radio Frequency Identification (RFID) reader at a distance of 160 meters, the downlink (i.e., the link from the reader to the active RFID tag) only requires a sensitivity of -43 dBm, while the active RFID tag's equivalent isotropically radiated power (EIRP) needs to reach -16 dBm to maintain the same communication range as the downlink. Figure 1 This is a schematic diagram of a scenario involving a reader and an RFID tag provided in an embodiment of this application, as shown below. Figure 1 As shown, to achieve a communication distance of 160 meters between the reader and the RFID tag's RF antenna, the transmitter's power consumption budget needs to be four orders of magnitude larger than that of the receiver.

[0044] Second, receivers with envelope detection structures generally require off-chip matching networks with high quality factors to increase sensitivity. This not only increases the system size but also limits the ability to switch operating frequencies between different channels. It is worth noting that switching frequencies between different channels can be used as a marker to avoid erroneous wake-up of the transmitter.

[0045] Third, current transceiver architectures based on single-loop antennas achieve passive voltage gain using the antenna-transceiver interface. However, the resonant frequency (f) of the antenna-transceiver interface... RSN The capacitor generally requires manual adjustment due to changes in temperature and manufacturing process.

[0046] Fourth, regarding the transmitter, the currently used voltage-controlled oscillator-power amplifier (VCO-PA) can reduce transmitter power consumption by utilizing a high-quality factor loop antenna. However, the Class B VCO-PA structure has low power efficiency because the negative transconductance transistor remains in the transistor region for a long time under large output swing, increasing the loss of the VCO-PA resonant cavity. In addition, the input capacitance (C) from the envelope detector (ED) ED A large fixed capacitor is introduced into the resonant cavity of the VCO-PA, which degrades the quality factor of the resonant cavity within the frequency tuning range. The fixed capacitor itself has a very low quality factor. Figure 2A circuit diagram of an existing active RFID tag provided for an embodiment of this application is shown below. Figure 2 As shown, the envelope detector ED demodulates the received signal and outputs it to the baseband demodulated received signal so that the baseband can process the signal. The Class B VCO-PA receives the transmit signal as input so that the Class B VCO-PA can transmit the signal. The input capacitor C of the envelope detector ED... ED Fixed capacitance will be added to the resonant cavity of the VCO-PA, which will reduce the quality factor of the resonant cavity and thus affect the transmitter's transmission efficiency.

[0047] To address the aforementioned issues, this application provides a transceiver chip and an RFID tag to construct a 900MHz ultra-low power long-range active RFID tag, specifically including the following:

[0048] First, a Class B / C VCO-PA (i.e., a hybrid Class B / C VCO-PA) is used to reduce resonant cavity loss. A transmitter and receiver interface designed in conjunction with the RF antenna is adopted, specifically including the RF antenna, receiver, Class B / C VCO-PA, and a switching (T / R) switch. The purpose of adding the T / R switch is to isolate the receiver's input capacitor from the Class B / C VCO-PA, thereby improving the transmitter's transmission efficiency.

[0049] Second, a frequency calibration scheme is provided that can automatically adjust the resonant frequency of the antenna-transceiver interface so that it is unaffected by process changes without passive voltage gain, while supporting two-dimensional wake-up characteristics in the 900MHz (Industrial Scientific Medical Band, ISM) band.

[0050] Third, reverse injection locking technology is used to automatically track the reader's continuous wave output frequency to eliminate transmitter frequency offset.

[0051] The transceiver chip provided in this application will be described below with reference to several specific embodiments.

[0052] Figure 3 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 1 ,like Figure 3 As shown, the transceiver chip 001 includes: an antenna interface 10, a receive data interface 11, a transmit data interface 12, an RF transceiver unit 13, and a baseband unit 14. The RF transceiver unit 13 includes: a switching switch 13a, a receiver 13b, and a transmitter 13c.

[0053] The antenna interface 10 is used to connect the radio frequency antenna. One end of the switch 13a is connected to the antenna interface 10, and the other end of the switch 13a is connected to the input terminal of the receiver 13b. The output terminal of the receiver 13b is connected to the input terminal of the baseband unit 14, and the output terminal of the baseband unit 14 is connected to the data receiving interface 11.

[0054] The receive data interface 11 and transmit data interface 12 are used to connect to the processing unit. The transmit data interface 12 is connected to the input terminal of the transmitter 13c, and the output terminal of the transmitter 13c is connected to the antenna interface 10.

[0055] Receiver 13b can be implemented by an envelope detector to demodulate the received signal. Baseband unit 14 is used to process the demodulated signal, such as signal amplification and signal comparison. Processing unit is used to perform logic processing on the processed signal to obtain the signal to be transmitted and send the signal to be transmitted to transmitter 13c so that transmitter 13c can transmit the signal to be transmitted through radio frequency antenna.

[0056] In one application scenario, the transceiver chip 001 receives the carrier signal sent by the reader through the radio frequency antenna, demodulates the carrier signal, and sends the demodulated signal to the baseband unit 14. The baseband unit 14 then processes the demodulated signal and sends the processed signal to the processing unit through the receive data interface 11. The processing unit obtains the signal to be transmitted based on the processed signal and sends the signal to be transmitted to the transmitter 13c through the transmit data interface 12. The transmitter 13c then sends the signal to be transmitted to the reader through the radio frequency antenna.

[0057] In this mode, the switching switch 13a can be closed by default. In the receiving mode, the receiver 13b receives and demodulates the carrier signal through the radio frequency antenna. The baseband unit 14 processes the carrier signal. When the processing unit determines that the processed signal meets the preset requirements, it generates a wake-up signal for the transmitter and opens the switching switch based on the wake-up signal, switching from the receiving mode to the transmitting mode. In the transmitting mode, the transmitter 13c sends the signal to be transmitted through the radio frequency antenna. In this way, the receiver 13b and the transmitter 13c can be isolated in the transmitting mode, thereby improving the transmitting efficiency of the transmitter.

[0058] It is understandable that after the transmitter 13c finishes transmitting the signal, the processing unit can also control the switching switch 13a to close. In other words, the switching switch 13a is jointly controlled by the wake-up signal and the signal to be transmitted by the transmitter 13c.

[0059] It is worth noting that the transceiver chip 001 may also include a receiver power interface and a transmitter power interface. Both the receiver power interface and the transmitter power interface are used to connect to the power supply to provide power voltage to the receiver 13b and the transmitter 13c.

[0060] In the transceiver chip of this embodiment, the antenna interface is used to connect to the RF antenna. One end of the switch is connected to the antenna interface, and the other end of the switch is connected to the input of the receiver. The output of the receiver is connected to the input of the baseband unit, and the output of the baseband unit is connected to the receive data interface. The receive data interface and the transmit data interface are used to connect to the processing unit. The transmit data interface is connected to the input of the transmitter, and the output of the transmitter is connected to the antenna interface. Compared with the prior art, by designing the receiver, transmitter, and switch in conjunction with the RF antenna, RF gain can be provided to the receiver without the need for an additional off-chip matching network. Furthermore, by introducing the switch, the input capacitor of the receiver can be isolated from the transmitter, thereby improving the transmission efficiency of the transmitter.

[0061] Figure 4 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 2 ,like Figure 4 As shown, in an optional embodiment, the transmitter 13c includes: an adjustable capacitor 13c0 and an oscillating power amplifier 13c1. The input terminal of the oscillating power amplifier 13c1 is the input terminal of the transmitter 13c. The adjustable capacitor 13c0 is connected between the two output terminals of the oscillating power amplifier 13c1. The two first output terminals of the oscillating power amplifier 13c1 are also connected to the antenna interface 10.

[0062] Among them, the oscillation power amplifier 13c1 can be a Class B / C VCO-PA. The oscillation power amplifier 13c1 has two first output terminals, the adjustable capacitor 13c0 is located between the two first output terminals, the antenna interface 10 is connected to the two first output terminals of the oscillation power amplifier 13c1, and the input terminal of the oscillation power amplifier 13c1 is connected to the transmit data interface 12.

[0063] It is worth noting that the B / C class VCO-PA is composed of NMOS and PMOS. The NMOS is biased in class C and the PMOS is biased in class B. The conduction time is different for different biases. The NMOS biased in class C has a shorter dwell time in the transistor region, which can reduce the resonant cavity loss compared to class B.

[0064] Figure 5 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 3 ,like Figure 5As shown, in an optional embodiment, the transceiver chip 001 further includes: a frequency calibration unit 15, a control interface 16, a clock interface 17, and a first oscillator 18. The control interface 16 is used to receive input preset standard capacitor control words, the first oscillator 18 is used to connect to an oscillating crystal through the clock interface 17, the input terminal of the frequency calibration unit 15 is connected to the second output terminal of the transmitter 13c, and the output terminal of the frequency calibration unit 15 is connected to the control terminal of the adjustable capacitor 13c0.

[0065] In this embodiment, both the control interface 16 and the clock interface 17 are connected to the input terminals of the frequency calibration unit 15. Since the resonant frequency of the transceiver is sensitive to the changes in capacitance with temperature and process, the frequency calibration unit 15 can be used to calibrate the resonant frequency of the receiver in the receiving mode and the resonant frequency of the transmitter in the transmitting mode in this embodiment. The frequency calibration unit 15 can be an on-chip frequency-locked loop (FLL) unit. The control interface 16 can receive the preset standard capacitor control word input by the processing unit. The preset standard capacitor control word and the preset standard frequency have a mapping relationship. The preset standard capacitor control word is a frequency control word (FCW).

[0066] The oscillating crystal and the first oscillator 18 constitute a crystal oscillator, such as a pulse-injection crystal oscillator, used to provide a reference clock for the frequency calibration unit 15. The oscillating crystal can be, for example, a quartz crystal. The clock frequency of the reference clock can be 32.768 kHz, meaning that 32.768 kHz can be used as the reference clock signal and can be generated by a 21 nW pulse-injection crystal oscillator, which is always on to reduce system delay.

[0067] For the calibration of the resonant frequency of transmitter 13c in transmit mode, switch 13a is turned off. Frequency calibration unit 15 monitors the output frequency of transmitter 13c through the second output terminal of transmitter 13c and counts the number of rising edges of the output frequency within the oscillation clock cycle using a counter. Based on the counting result and the preset standard capacitor control word, the capacitor control word of adjustable capacitor 13c0 is determined, and the capacitance value of adjustable capacitor 13c0 is adjusted according to the capacitor control word. Finally, the output frequency of transmitter 13c is made to the preset standard frequency. In this way, the calibration of the resonant frequency of transmitter 13c in transmit mode is completed. The output frequency of transmitter 13c is the resonant frequency of transmitter 13c, that is, the resonant frequency of transmitter 13c is calibrated to the preset standard frequency.

[0068] Similarly, for the calibration of the resonant frequency of receiver 13b in receiving mode, switch 13a is closed, frequency calibration unit 15 monitors the output frequency of transmitter 13c through the second output terminal of transmitter 13c and counts the number of rising edges of the output frequency within the oscillation clock cycle using a counter. Based on the counting result and the preset standard capacitor control word, the capacitor control word of adjustable capacitor 13c0 is determined, and the capacitance value of adjustable capacitor 13c0 is adjusted according to the capacitor control word, so that the output frequency of transmitter 13c is the preset standard frequency. In this way, the calibration of the resonant frequency of receiver in receiving mode is completed, wherein the output frequency of transmitter 13c is the resonant frequency of receiver 13b, that is, the resonant frequency of receiver 13b is calibrated to the preset standard frequency.

[0069] It is worth noting that the resonant frequency of transmitter 13c is the transmission frequency of transmitter 13c, and the resonant frequency of receiver 13b is the reception frequency of receiver 13b.

[0070] In this embodiment, the transceiver chip further includes a frequency calibration unit, a control interface, a clock interface, and a first oscillator, thereby enabling calibration of the resonant frequencies of the receiver and transmitter.

[0071] Figure 6 This is a schematic diagram of the circuit structure of the frequency calibration unit provided in the embodiments of this application, as shown below. Figure 6 As shown, in an optional embodiment, the frequency calibration unit 15 includes: a frequency divider 15a, a calibration logic module 15b, and a register 15c. The second output terminal of the transmitter 13c is connected to the first input terminal of the calibration logic module 15b through the frequency divider 15a. The control interface 16 and the first oscillator 18 are respectively connected to the second input terminal and the third input terminal of the calibration logic module 15b. The output terminal of the calibration logic module 15b is connected to the control terminal of the adjustable capacitor 13c0 through the register 15c.

[0072] Among them, frequency divider 15a can be connected to the second output terminal of transmitter 13c, frequency divider 15b is connected to the first input terminal of calibration logic module 15b, control interface 16 is connected to the second input terminal of calibration logic module 15b, and clock interface 17 is connected to the third input terminal of calibration logic module 15b.

[0073] Frequency divider 15a is used to divide the output frequency of transmitter 13c to obtain the divided frequency. The calibration logic module 15b can be implemented by a successive-approximation register (SAR) logic circuit. It is used to count the rising edge of the divided frequency of transmitter 13c within the oscillation clock cycle, and determine the capacitor control word of adjustable capacitor 13c0 according to the counting result and the preset standard capacitor control word. The capacitor control word is stored in register 15c. Register 15c adjusts the capacitance value of adjustable capacitor 13c0 according to the capacitor control word, so that the output frequency of transmitter 13c is the preset standard frequency. In this way, the resonant frequency calibration of receiver and transmitter can be completed.

[0074] It is worth noting that after frequency calibration, the output frequency of transmitter 13c may have an error, i.e., it may not reach the preset standard frequency. After calibration, the continuous wave emitted by the reader can be used to inject and lock the transmitter 13c to eliminate this error. The continuous wave is a fixed-frequency and unmodulated signal. This reverse injection locking technology can ensure the accuracy of the output frequency of transmitter 13c. In other words, the continuous wave emitted by the reader is considered to be a signal of the preset standard frequency. The injection and locking is performed according to the preset standard frequency so that the output frequency of transmitter 13c can be accurately locked to the preset standard frequency, thereby achieving the calibration of the resonant frequency of receiver 13b and transmitter 13c.

[0075] Figure 7 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 4 ,like Figure 7 As shown, in an optional embodiment, the switching switch 13a includes: a first switching unit 13a0 and a second switching unit 13a1. One end of the first switching unit 13a0 is connected to the antenna interface 10, and the other end of the first switching unit 13a0 is connected to the input terminal of the receiver 13b. One end of the second switching unit 13a1 is connected to the antenna interface 10, and the other end of the second switching unit 13a1 is connected to the input terminal of the receiver 13b.

[0076] There are two antenna interfaces 10, which are respectively connected to one end of the first switch unit 13a0 and one end of the second switch unit 13a1. The other ends of the first switch unit 13a0 and the second switch unit 13a1 are both connected to the input end of the receiver 13b. Since the first output end of the transmitter 13c is connected to the antenna interface 10, the number of the first output ends of the transmitter 13c is two, that is, the transmitter has two first output ends.

[0077] In receive mode, the first switch unit 13a0 and the second switch unit 13a1 are closed. In transmit mode, the first switch unit 13a0 and the second switch unit 13a1 are open. In this way, in transmit mode, the receiver 13b and the transmitter 13c can be isolated, thereby improving the transmitter's transmission efficiency.

[0078] This introduction will focus on Class B / C VCO-PAs, which are composed of NMOS and PMOS transistors. Figure 8 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 5 ,like Figure 8 As shown, Q5 and Q6 are PMOS transistors, and Q7, Q8, and Q9 are NMOS transistors. The input terminals of Q5 and Q6 are connected to the power supply, and the control terminals of Q7 and Q8 are connected to V through a resistor. B On the power supply side, the control terminal of Q9 is the input terminal of the transmitter, used to receive the input signal to be transmitted (TX_Data), V OP V is the voltage between the oscillating power amplifier 13C1 and the adjustable capacitor 13C0. ON This refers to the voltage between the oscillating power amplifier 13c1 and the first switching unit 13a0 and the second switching unit 13a1. This PMOS-NMOS complementary topology avoids VDD being supplied from an external antenna. The PMOS transistors are not biased in the Class C region because this would require a feedback loop to generate an additional bias voltage, which would prolong the VCO-PA startup time and thus limit the data rate of OOK modulation.

[0079] See Figure 8 The first switch unit 13a0 and the second switch unit 13a1 are also connected to the input terminal of the receiver 13b, wherein C ED This is the input capacitor for the envelope detector of receiver 13b. Figure 9 This is a schematic diagram of the equivalent circuit in the receiving mode provided in the embodiments of this application. Figure 10 This is a schematic diagram of the equivalent circuit in the transmission mode provided in the embodiments of this application, such as... Figure 9 , Figure 10 As shown, in receive mode, the receive enable signal EN... RX =1, the first switch unit 13a0 and the second switch unit 13a1 are closed, in transmit mode, the receive enable signal EN is activated. RX =0, the first switch unit 13a0 and the second switch unit 1211 are disconnected, thus isolating the receiver 13b and the transmitter 13c, thereby improving the transmitter's transmission efficiency.

[0080] As the transmitter's transmission frequency increases, the capacitance of the resonant cavity needs to decrease, but C ED It remains unchanged because C EDThe order of the ED is related to its sensitivity and the gain of the RF transceiver interface; therefore, C ED This will occupy a large portion of the energy storage capacitor, leading to a decrease in the Q (quality factor) of the adjustable capacitor CT when the frequency tuning range is fixed. At 920MHz, the resonant cavity capacitance is 808fF, and the C of a 30-level ED... ED With a power of 300fF, by isolating the ED from the CT in transmit mode using the first switching unit 13a0 and the second switching unit 13a1, the Q value of the CT increases from 55 to 218, and the transmitter power also increases from 9.4% to 15.2% at -20dBm EIRP.

[0081] exist Figure 10 On this basis, Figure 11 This is a schematic diagram of the voltage gain in the receiving mode provided in the embodiments of this application, as shown below. Figure 11 As shown, Q ANT Q is the quality factor of the radio frequency antenna. CAP V represents the quality factor of the switching switch 13a, the adjustable capacitor 13c0, and the receiver 13b. ANT，IN V is the input voltage of the radio frequency antenna. ED，IN L is the output voltage of the receiver. ANT R is the antenna inductance. rad R is the antenna radiation resistance. loss R is the antenna loss resistance. sw For the loss resistance of switch 13a, C T For adjustable capacitors, C ED R is the input capacitance of the envelope detector. T C T The loss resistance, R ED ω is the loss resistance of the envelope detector, and ω is the angular velocity of the antenna inductance.

[0082] Voltage gain A v for:

[0083]

[0084] It is worth noting that the antenna inductance (L) ANT This is beneficial for improving the equivalent isotropic radiated power (EIRP) and efficiency of the transmitter, and L can be selected. ANT =37nH to ensure C T It maintains a high quality factor over a wide frequency tuning range, and the side length (D) of the RF antenna can be further optimized within a given LANT. ANT ) and line width, due to EIRP and R rad (i.e. D) ANT 4 The proportions are direct; choose a large D.ANT In addition, a wide linewidth can significantly improve EIRP.

[0085] Due to voltage gain A V Weakly dependent on R rad A V It will not follow D ANT The value decreases significantly with the increase of D. ANT Increase from 17mm to 23mm while maintaining L ANT Equal to 37nH, simulation shows that EIRP improved by 3.9dB, but A V The drop is only 1.2dB in receive mode, with the R switch on the toggle switch. sw Let the capacitor's quality factor Q CAP It dropped to 28.7, which made A V It decreased by 2dB.

[0086] It is worth noting that the voltage gain A V It also helps to increase the amplitude of the received continuous wave, thereby increasing the lock-in range. When the adjustable capacitor 13c0 varies due to process variations, frequency calibration in receive mode helps to maintain a high A. V Without calibration, when the capacitance value of the adjustable capacitor 13c0 changes by 10%, A V It will reduce by 7dB. At the same time, the calibration also ensures A under different channels. v Both can be maintained at 26dB. In addition, the resonant frequency affected by the 60℃ temperature change has an impact on A. V The impact is negligible, so frequency calibration can be performed once in receive mode, while in transmit mode, calibration is required every time data is transmitted. Therefore, the resonant frequencies of the receiver and transmitter need to be calibrated separately in receive and transmit modes, with switch 13a open in transmit mode and closed in receive mode.

[0087] Figure 12 A circuit diagram of the switching unit provided in the embodiments of this application is shown below. Figure 12 As shown, in an optional embodiment, the transceiver chip 001 further includes: a receive enable interface, the first switching unit 13a0 includes: a first switch Q1 and a second switch Q2, and the second switching unit 13a1 includes: a third switch Q3 and a fourth switch Q4.

[0088] Among them, the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 can all be MOSFETs.

[0089] The input terminals of the first switch Q1 and the third switch Q3 are connected to the antenna interface 10. The output terminal of the first switch Q1 is connected to the input terminal of the second switch Q2. The output terminal of the third switch Q3 is connected to the input terminal of the fourth switch Q4. The input terminals of the second switch Q2 and the fourth switch Q4 are both connected to the input terminal of the receiver 13b. The output terminals of the second switch Q2 and the fourth switch Q4 are both grounded.

[0090] The control terminals of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are all connected to the receive enable interface. The receive enable interface is used to receive the input enable signal (i.e., EN). RX The enable signal can be a signal that the processing unit inputs to the receiver 13b through the receive enable interface to control the operation of the receiver 13b.

[0091] In this embodiment, the first switch Q1 and the second switch Q2 can be active high, while the third switch Q3 and the fourth switch Q4 can be active low. The control terminals of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 can be connected to a preset resistor and a receive enable interface. That is, the control terminals of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are connected to one end of the preset resistor, and the other end of the preset resistor is connected to the receive enable interface. The resistance value of the preset resistor can be set according to requirements, and this embodiment does not limit it.

[0092] It is worth noting that the transceiver chip 001 may also include a transmit enable interface, which can be a signal sent by the processing unit to the transmitter 13c to control the operation of the transmitter 13c.

[0093] The adjustable capacitor 13c0 includes: a first switched capacitor array C c Second switched capacitor array C F The first switched capacitor array C c Includes: multiple first switched capacitors connected in parallel, and a second switched capacitor array C. F Including: multiple second switched capacitors connected in parallel, the capacitance value C of the adjustable capacitor 13c0. T =C c +C F .

[0094] One end of multiple first switched capacitors is connected to one end of multiple second switched capacitors, and the other end of multiple first switched capacitors is connected to the other end of multiple second switched capacitors. That is, multiple first switched capacitors and multiple second switched capacitors are connected in parallel. Multiple first switched capacitors and multiple second switched capacitors are arranged between the two first output terminals of the oscillation power amplifier. The control terminals of multiple first switched capacitors and multiple second switched capacitors are both connected to the output terminal of the frequency calibration unit.

[0095] It is worth noting that the first switched capacitor array C c Second switched capacitor array C F It can be a binary-weighted switch capacitor array (SCA) to cover a 15aMHz tuning range.

[0096] In some embodiments, the capacitor control word of the adjustable capacitor 13c0 includes a first switched capacitor array C. c Capacitor control word B c The capacitor control word B of the second switched capacitor array F B c It is [6:0], that is, a 7-bit control word, B F The control word is [3:0], which is a 4-bit control word. During frequency calibration, the control word C is a 7-bit control word. c Calibration is performed only when the channel frequency changes, while the 4-bit fine-tuning C covers a frequency range of 1.5MHz. F The calibration is performed before each data transmission, thereby reducing transmission frequency errors caused by temperature variations. Specifically, the calibration involves 4 bits of C. F Eight reference cycles (250 μs) are required. The total power consumption of the frequency divider 15a and FLL is 60.7 μW. They are turned off after calibration.

[0097] exist Figure 8 On this basis, Figure 13 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 6 ,like Figure 13 As shown, the first switched capacitor array C c Second switched capacitor array C F It is connected in parallel between the two output terminals of the oscillating power amplifier 13c1.

[0098] Figure 14 A schematic diagram of a switched capacitor provided in an embodiment of this application is shown below. Figure 14As shown, each switched capacitor includes: a first capacitor C3, a second capacitor C4, a third capacitor C5, a fourth capacitor C6, a fifth switching transistor Q10, and a sixth switching transistor Q11. One end of the first capacitor C3 is connected to the input terminal of the fifth switching transistor Q10, one end of the second capacitor C4 is connected to the input terminal of the sixth switching transistor Q11, one end of the first capacitor C3 is also connected to one end of the third capacitor C5, and one end of the second capacitor C4 is also connected to one end of the fourth capacitor C6.

[0099] The other ends of the third capacitor C5 and the fourth capacitor C6 are respectively connected to the two output terminals of the oscillating power amplifier 13c1. The output terminals of the fifth switch q10 and the sixth switch q11 are both grounded. The control terminals of the fifth switch q10 and the sixth switch q11 are both connected to the output terminal of the frequency calibration unit 15.

[0100] In this configuration, multiple first switched capacitors are connected in parallel, and multiple second switched capacitors are connected in parallel. Each first switched capacitor and each second switched capacitor has the same structure. Specifically, B... i B c Or B F .

[0101] It is worth noting that a parasitic capacitance C is also connected between the control terminal and the input terminal of the fifth switch Q10 and the sixth switch Q11. par In this context, the third capacitor C5 and the fourth capacitor C6 can be Cu, and the first capacitor C3 and the second capacitor C4 can be C. fix In each SCA cell, a high-quality factor capacitor C fix Connecting it in parallel with the parasitic capacitance of the switching transistor can improve the quality factor when the switch is off.

[0102] Figure 15 Schematic diagram of the circuit structure of the transceiver chip provided in the embodiments of this application Figure 7 ,like Figure 15 As shown, the baseband unit 14 includes: a signal amplifier 14a, a comparator 14b, an automatic offset voltage control logic unit 14c, and a second oscillator 14d. The input terminal of the signal amplifier 14a is connected to the output terminal of the receiver 13b, the output terminal of the signal amplifier 14a is connected to the first input terminal of the comparator 14b, the second input terminal of the comparator 14b is grounded, and the output terminal of the comparator 14b is connected to the data receiving interface 11.

[0103] An automatic offset voltage control logic unit 14c is connected between the output and control terminals of comparator 14b. The clock input terminals of both comparator 14b and automatic offset voltage control logic unit 14c are connected to oscillator 14d.

[0104] Understandably, signal amplifier 14a is used to amplify the demodulated signal sent by receiver 13a, and comparator 14b is used to compare the amplified signal with a reference voltage to output a binary signal. The reference voltage is provided by the oscillator. The gain of signal amplifier 14a can be 25dB, and comparator 14b can be a strong-arm comparator.

[0105] The Automatic Offset Voltage Control (AOC) unit 14c is used to adjust the offset voltage connected to the comparator. The second oscillator 14d can be a 4kHz relaxation oscillator, which is used to provide a reference clock signal to the comparator 14b and the AOC unit 14c. In this scheme, the baseband unit 14 of the receiver 13b consumes 17.8nW and is always on.

[0106] exist Figures 1 to 15 On this basis, Figure 16 A schematic diagram of a specific transceiver chip provided in this application embodiment is shown below. Figure 16 As shown, the receiving frequency range is set to 790-925MHz, and the transmitting frequency range is set to 852-978MHz. RX EN To enable the receive interface, TX EN For the transmit enable interface, RX_Data is the signal output by baseband unit 14, V DD，TX For the power supply terminal of transmitter 13c, V DD，RX For the power supply terminal of transmitter 13c, V DD，FLL The power supply terminal of frequency calibration unit 15, the interface corresponding to FCW is the control interface, and the clock interface corresponding to the oscillator in frequency calibration unit 15, f out f is the output frequency of transmitter 13c. div f is the frequency division. ref This is the reference frequency.

[0107] The receiver 13b consists of 30 stages of ED, the transmitter consists of a VCO-PA with B and C components, the switching switch 13a includes a first switched capacitor array and a second switched capacitor array, the baseband unit 14 includes a signal amplifier 14a, a comparator 14b, an automatic offset voltage control logic unit 14c, and an oscillator 14d, and the frequency calibration unit 15 includes a frequency divider 15a, a calibration logic module 15b, and a register 15c.

[0108] The output of the 30-level ED is also grounded through two grounding diodes. A capacitor is connected between the signal amplifier and the comparator. The output of the signal amplifier is connected to the capacitor. The capacitor is connected to the first input of the comparator. One end of the grounding resistor is connected between the capacitor and the first input of the comparator. The other end of the grounding resistor is grounded.

[0109] It is worth noting that the description of the connection relationship can be found in the above embodiments, and will not be repeated here.

[0110] exist Figures 1 to 16 Based on this, the operation process of active RFID tags will be explained below. Figure 17 A schematic diagram illustrating the operation flow of the RFID tag provided in the application embodiment, as shown below. Figure 17 As shown, Tag is an active RFID tag, RX EN For the receive enable interface, RX & XO are the oscillators in the frequency calibration unit 15, VCO-PA is the oscillation power amplifier of the transmitter, FLL is the frequency calibration unit, N indicates on, F indicates off, RX Cal. indicates calibrating the receiver, and TX Cal. indicates calibrating the transmitter.

[0111] The operation process includes:

[0112] Phase 1: In the initial state, RX EN The receive enable signal is high level 1, RX&XO is enabled, VCO-PA is enabled, and FLL is enabled.

[0113] The resonant frequency f of the receiver R In a fluctuating state, the receiver's resonant frequency f is respectively set in a clean channel environment. R The frequency was calibrated to f1 = 900MHz and f1 = 920MHz, and the capacitor control word of the switched capacitor array was stored in the register of the receiver capacitor control body in the FLL.

[0114] Phase 2, Avoiding False Wake-Up in Receive Mode: RX EN When the receive enable signal is high (1), RX&XO is enabled, VCO-PA is disabled, and FLL is disabled.

[0115] The receiver detects a wake-up signal on channel f1. If an interference signal on channel f1 causes a false wake-up, the active RFID tag will move to channel f2. As a result, the interference energy on channel f1 will be weakened by the transceiver. If no wake-up signal is detected on channel f1 within a certain time, the active RFID tag will return to channel f1 and will not wake up the transmitter.

[0116] Phase 3: Transmitter calibration in transmit mode: Transmitter resonant frequency f R In a fluctuating state, RX ENThe receive enable signal is low level 0, RX&XO is enabled, VCO-PA is enabled, and FLL is enabled.

[0117] The above scheme avoids false wake-ups caused by interference signals. Only after detecting two consecutive wake-up signals at channels f1 and f2, i.e., successfully waking up the transmitter, will the active RFID tag calibrate C for the transmission mode. F This involves calibrating the transmitter to its resonant frequency f. R Taking the calibration to f2 as an example.

[0118] Meanwhile, the reader will wait for T wait The duration is then further enhanced by continuous wave injection to lock the VCO-PA, T wait Set it to be slightly longer than the transmitter's calibration time (e.g., 250 μs), that is, a period of stabilization after calibration, where RX EN The receive enable signal is low (0), and the transmitter's resonant frequency f is... R Calibrated to f2, RX & XO enabled, VCO-PA disabled, FLL enabled.

[0119] Signal transmission in transmit mode: RX EN The receive enable signal is low (0), and the transmitter's resonant frequency f is... R Calibrated to f2, RX & XO enabled, VCO-PA enabled, FLL disabled.

[0120] Understandably, the subsequent calibration process for the transmitter is similar to the process described above, and will not be repeated here.

[0121] This embodiment also provides an RFID tag, including: a processing unit, an RFID antenna, and the transceiver chip described above.

[0122] In this scheme, when an active RFID tag transmits a 500kbps data rate, 50% duty cycle OOK signal, by adjusting the transmitter voltage from 0.6V to 1.2V, the transmitter's EIRP can be increased from -23dBm to -15.8dBm, corresponding to a transmitter efficiency greater than 9.7%. At EIRP = -15.8dBm, the energy required to transmit one bit is 540pJ; and with a frequency offset of ±100kHz, -56dBm of input energy is needed for injection lock-in, which is comparable to the receiver sensitivity. With a received data rate of 1kbps and a 50% duty cycle OOK modulated RF input, the receiver achieved a sensitivity of -60.4dBm through automatic calibration. Figure 5 Top left). When holding f RSN At 920MHz, a 30MHz frequency shift will cause a 7dB decrease in sensitivity. This can be achieved by calibrating f... RSNFrom a scanning frequency of 840MHz to 920MHz, the sensitivity remained at -59dBm. At a frequency offset of 20MHz, the receiver achieved a signal-to-noise ratio of -24dB. Figure 5 (Lower left). Assuming a reader sensitivity of -92dBm, field tests show that the active RFID tag of this scheme can achieve a communication distance of 180m (line of sight) in transmit mode.

[0123] Compared to other VCO-PA based transmitters, this scheme achieves the highest transmission efficiency (20.5% at -22dBmEIRP), and the receiver performance is comparable to receivers with other envelope detection structures. The automatic frequency calibration scheme enables the ultra-low power tag to support two-dimensional wake-up features (i.e., the transmitter is only woken up when two wake-up signals are detected).

[0124] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0125] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A transceiver chip, characterized by, The transceiver chip comprises an antenna interface, a receiving data interface, a transmitting data interface, a radio frequency transceiver unit, and a baseband unit; wherein the radio frequency transceiver unit comprises a switching switch, a receiver, and a transmitter; The antenna interface is used to connect a radio frequency antenna, one end of the switching switch is connected to the antenna interface, the other end of the switching switch is connected to an input end of the receiver, an output end of the receiver is connected to an input end of the baseband unit, and an output end of the baseband unit is connected to the receiving data interface; The receiving data interface and the transmitting data interface are used to connect a processing unit, the transmitting data interface is connected to an input end of the transmitter, and a first output end of the transmitter is connected to the antenna interface; In a receiving mode, the switching switch is closed, the receiver receives and demodulates a carrier signal through the radio frequency antenna, so that the baseband unit performs signal processing on the carrier signal, the processing unit generates a wake-up signal for the transmitter when the processed signal meets preset requirements, and the switching switch is disconnected based on the wake-up signal to switch to a transmitting mode, in which the transmitter transmits a signal to be transmitted through the radio frequency antenna to isolate the receiver and the transmitter in the transmitting mode; The transmitter comprises an adjustable capacitor and an oscillation power amplifier; an input end of the oscillation power amplifier is the input end of the transmitter, the adjustable capacitor is connected between two first output ends of the oscillation power amplifier, and the two first output ends of the oscillation power amplifier are also connected to the antenna interface; The transceiver chip further comprises a frequency calibration unit, a control interface, a clock interface, and a first oscillator; the control interface is used to receive an input preset standard capacitor control word, the first oscillator is connected to an oscillation crystal through the clock interface, an input end of the frequency calibration unit is connected to a second output end of the transmitter, and an output end of the frequency calibration unit is connected to a control end of the adjustable capacitor; The frequency calibration unit comprises a frequency divider, a calibration logic module, and a register; the second output end of the transmitter is connected to a first input end of the calibration logic module through the frequency divider, the control interface and the first oscillator are connected to a second input end and a third input end of the calibration logic module, respectively, an output end of the calibration logic module is connected to the control end of the adjustable capacitor through the register, the calibration logic module is implemented by using a successive approximation register type logic circuit, the frequency divider is used to divide the output frequency of the transmitter to obtain a divided frequency, the calibration logic module is used to count rising edges of the divided frequency within an oscillation clock cycle, and a capacitor control word of the adjustable capacitor is determined according to a counting result and the preset standard capacitor control word to store the capacitor control word in the register to control a capacitor value of the adjustable capacitor until the output frequency of the transmitter is a preset standard frequency. ​ 2. The transceiver chip of claim 1, wherein, The switch includes: a first switch unit and a second switch unit, one end of the first switch unit is connected to the antenna interface, the other end of the first switch unit is connected to the input end of the receiver, one end of the second switch unit is connected to the antenna interface, the other end of the second switch unit is connected to the input end of the receiver.

3. The transceiver chip of claim 2, wherein, The transceiver chip further includes: a receiving enable interface, the first switch unit includes: a first switch tube and a second switch tube, the second switch unit includes: a third switch tube and a fourth switch tube; the control end of the first switch tube, the control end of the second switch tube, the control end of the third switch tube and the control end of the fourth switch tube are connected to the receiving enable interface, and the receiving enable interface is used to receive an input enable signal; The input end of the first switch tube and the input end of the third switch tube are connected to the antenna interface, the output end of the first switch tube is connected to the input end of the second switch tube, the output end of the third switch tube is connected to the input end of the fourth switch tube, the input end of the second switch tube and the input end of the fourth switch tube are connected to the input end of the receiver, and the output end of the second switch tube and the output end of the fourth switch tube are grounded.

4. The transceiver chip of claim 1, wherein, The adjustable capacitor includes: a first switch capacitor array and a second switch capacitor array, the first switch capacitor array includes: a plurality of first switch capacitors connected in parallel, and the second switch capacitor array includes: a plurality of second switch capacitors connected in parallel. One end of the plurality of first switch capacitors and one end of the plurality of second switch capacitors are connected, the other end of the plurality of first switch capacitors and the other end of the plurality of second switch capacitors are connected, the plurality of first switch capacitors and the plurality of second switch capacitors are arranged between the two first output ends of the oscillation power amplifier, and the control end of the plurality of first switch capacitors and the control end of the plurality of second switch capacitors are connected to the output end of the frequency calibration unit.

5. The transceiver chip of claim 4, wherein, Each switch capacitor includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth switch tube and a sixth switch tube, one end of the first capacitor and the input end of the fifth switch tube are connected, one end of the second capacitor and the input end of the sixth switch tube are connected, one end of the first capacitor is also connected to one end of the third capacitor, and one end of the second capacitor is also connected to one end of the fourth capacitor; The other end of the third capacitor and the other end of the fourth capacitor are respectively connected to the two first output ends of the oscillation power amplifier, the output end of the fifth switch tube and the output end of the sixth switch tube are grounded, and the control end of the fifth switch tube and the control end of the sixth switch tube are connected to the output end of the frequency calibration unit.

6. The transceiver chip of claim 1, wherein, The baseband unit includes: a signal amplifier, a comparator, an automatic offset voltage control logic unit and a second oscillator, the input end of the signal amplifier is connected to the output end of the receiver, the output end of the signal amplifier is connected to the first input end of the comparator, the second input end of the comparator is grounded, and the output end of the comparator is connected to the receiving data interface; The output terminal and the control terminal of the comparator are connected with the automatic offset voltage control logic unit, and the clock input terminal of the comparator and the clock input terminal of the automatic offset voltage control logic unit are connected with the second oscillator.

7. A radio frequency tag, characterized by Comprise: A processing unit, a radio frequency antenna and the transceiver chip of any one of claims 1-6.

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