Display panel and electronic device

Abstract

This application discloses a display panel and an electronic device. The display panel includes: a display area and a non-display area surrounding at least a portion of the display area; multiple data lines located within the display area; the non-display area includes a first non-display area and a second non-display area opposite each other in a first direction, the first direction being the extension direction of the data lines; a bonding area located in the second non-display area; the bonding area having multiple pads; and multiple gate circuits electrically connected to the data lines and the pads; the gate circuits include a first gate circuit located in the first non-display area. In this application's technical solution, the gate circuits include a first gate circuit located in the first non-display area. If at least a portion of the gate circuits are located in the first non-display area, the number of gate circuits in the second non-display area is reduced, thereby reducing the bezel width of the corresponding second non-display area, and further reducing the bezel width of the second non-display area with the bonding area.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and more specifically, to a display panel and an electronic device. Background Technology

[0002] With the continuous development of science and technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] The main component that enables electronic devices to display functions is the display panel, which includes a display area and a non-display area. As the PPI (pixels per inch) of display panels continues to increase, the number of internal data lines also increases for the same size display panel. This necessitates the installation of more gate circuits between the display area and the bonding area to connect the data lines and the pads in the bonding area, thereby increasing the bezel width of the non-display area with the bonding area in the display panel. Summary of the Invention

[0004] In view of the above, this application provides a display panel and an electronic device, the solution of which is as follows:

[0005] A display panel, comprising:

[0006] The display area and at least the non-display area surrounding a portion of the display area;

[0007] Multiple data cables are located within the display area;

[0008] The non-display area includes a first non-display area and a second non-display area that are opposite each other in a first direction, where the first direction is the direction in which the data line extends.

[0009] The bonding area is located in the second non-display area; the bonding area has multiple pads.

[0010] Multiple gating circuits are included, which are electrically connected to data lines and pads; the gating circuits include a first gating circuit located in the first non-display area.

[0011] This application also provides an electronic device, including the aforementioned display panel.

[0012] As can be seen from the above description, in the display panel and electronic device provided by the technical solution of this application, the gating circuit includes a first gating circuit located in the first non-display area. If at least part of the gating circuit is located in the first non-display area, the number of gating circuits in the second non-display area is reduced, which can reduce the border width of the corresponding second non-display area, and thus reduce the border width of the second non-display area with the binding area. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0015] Figure 1 This is a schematic diagram of the structure of a display panel;

[0016] Figure 2 for Figure 1 The image shown is a magnified view of the upper non-display area of ​​the display panel.

[0017] Figure 3 for Figure 1 The image shows a magnified view of the lower non-display area of ​​the display panel.

[0018] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0019] Figure 5 This application provides a schematic diagram of the partitioning of a non-display area in a display panel according to an embodiment of the present application.

[0020] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0021] Figure 7 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0022] Figure 8 This is a schematic diagram of the structure of a fan-out line in a display panel provided in an embodiment of this application;

[0023] Figure 9 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0024] Figure 10 A cross-sectional view of a display panel provided in an embodiment of this application;

[0025] Figure 11 This is a schematic diagram of a gating circuit provided in an embodiment of this application;

[0026] Figure 12 for Figure 11 The timing diagram of the input clock signal in the gating circuit shown is as follows;

[0027] Figure 13 A schematic diagram of the wiring method for the gating control signal connected to a gating circuit provided in an embodiment of this application;

[0028] Figure 14 A schematic diagram of the wiring method for the gating control signal connected to another gating circuit provided in an embodiment of this application;

[0029] Figure 15 This application provides a schematic diagram of the wiring method for a gating control signal line connected to a second non-display area, as shown in an embodiment of the present application.

[0030] Figure 16 A schematic diagram illustrating another wiring method for the gating control signal line connected to the second non-display area, provided in an embodiment of this application;

[0031] Figure 17 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] The display panel has a display area and a non-display area that at least partially surrounds the display area. The non-display area has a bonding area with pads for electrical connection to the display driver chip. To reduce the number of pads in the bonding area, and consequently the number of pins in the display driver chip used to provide data signals to the data lines, a gating circuit is typically used to connect the data lines to the pads in the bonding area.

[0034] Multiple data lines can be connected to the same pad in the bonding area through the same gating circuit to provide data signals to the multiple data lines in a time-division manner. Currently common design schemes include: setting every 3 data lines to be connected to the same pad through the same gating circuit, or setting every 6 data lines to be connected to the same pad through the same gating circuit, or setting every 9 data lines to be connected to the same pad through the same gating circuit, or setting every 12 data lines to be connected to the same pad through the same gating circuit.

[0035] Gating circuits are typically located in the non-display area between the bonding area and the display area. While connecting data lines to pads in the bonding area via gating circuits can significantly reduce the number of pads in the bonding area, thereby reducing the pin count required in the display driver chip, the gating circuit itself contains transistors. Due to transistor delay performance considerations, the gating circuit requires dedicated layout space, thus greatly increasing the bezel width of the non-display area. In particular, current electronic devices have high requirements for the bezel width of the non-display area used to house the bonding area in the display panel, and gating circuits are not conducive to the narrow bezel design requirements of this side of the non-display area.

[0036] refer to Figures 1-3 As shown, Figure 1 This is a schematic diagram of the structure of a display panel. Figure 2 for Figure 1 The image shown is a magnified view of a portion of the non-display area at the top of the display panel. Figure 3 for Figure 1 The image shows a partial enlarged view of the lower non-display area of ​​the display panel. The display panel includes:

[0037] Display area AA and the non-display area BB surrounding display area AA;

[0038] Multiple data lines D, with data lines D located within the display area AA;

[0039] The non-display area BB includes a first non-display area BB1 and a second non-display area BB2 that are opposite each other in the first direction X, where the first direction X is the extension direction of the data line D; the second non-display area BB2 includes a bonding area 11, which has pads 12 for connecting the display driver chip;

[0040] The gating circuit 20 is located between the binding area 11 and the display area AA. All gating circuits 20 are located between the binding area 11 and the display area AA, and are arranged sequentially along the second direction Y. The second direction Y is perpendicular to the first direction X and parallel to the display surface of the display panel.

[0041] Among them, multiple data lines D are connected to the same gating circuit 20. Figure 1 Each pair of data lines D is connected to the same gating circuit 20. Data lines D are electrically connected to the corresponding gating circuit 20 via the first signal connection line 31. The gating circuit 20 is electrically connected to the pads 12 in the bonding area 11 via the fan-out line 32. A clock signal is provided to the gating circuit 20 via the gating control signal line 30 connected to the gating circuit 20. Based on the clock signal, the gating circuit 20 controls the conduction state of each connected data line and the pad 12 in a timing sequence.

[0042] The display area AA has sub-pixels P for image display. For a circular display panel, in the first direction X, each row of sub-pixels P in the display area AA shrinks inward from the middle to both ends of the display area AA to form an approximately circular display area AA. Sub-pixels P in the same column are electrically connected to the same data line D. The display driver chip, which is electrically connected to pad 12, provides data signals to the data line D to control the sub-pixels P to display images.

[0043] As mentioned above, the gating circuit 20 and the gating control signal line 30 that controls its switching state will greatly increase the bezel width of the second non-display area BB2.

[0044] like Figure 2 As shown, the inventors discovered that by making reasonable use of the layout space of the first non-display area BB1, at least part of the selection circuit 20 can be placed in the first non-display area BB1, thereby reducing the impact of the selection circuit 20 on the border width of the second non-display area BB2. Furthermore, by reusing the existing layout space in the first non-display area BB1, the border width of the first non-display area BB1 will not be increased.

[0045] In view of this, in the display panel provided by the technical solution of this application, the gating circuit includes a first gating circuit located in the first non-display area. If at least part of the gating circuit is located in the first non-display area, the number of gating circuits in the second non-display area is reduced, the border width of the corresponding second non-display area can be reduced, and the border width of the second non-display area with the binding area can be reduced.

[0046] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] refer to Figure 4 As shown, Figure 4 This application provides a schematic diagram of the structure of a display panel, which includes:

[0048] Display area AA and at least the non-display area BB surrounding part of display area AA;

[0049] Multiple data lines D, with data lines D located within the display area AA;

[0050] The non-display area BB includes a first non-display area BB1 and a second non-display area BB2 that are opposite each other in the first direction X, where the first direction X is the extension direction of the data line D;

[0051] Binding area 11 is located in the second non-display area BB2; binding area 11 has multiple pads 12; wherein, binding area 11 is used to set the display driver chip, and the display driver chip is connected to the pads 12;

[0052] Multiple demux circuits 20 are electrically connected to the data line D and the pad 12; the demux circuit 20 includes a first demux circuit 21 located in the first non-display area BB1.

[0053] In this embodiment of the application, the selection circuit 20 includes a first selection circuit 21 located in the first non-display area BB1, that is, at least part of the selection circuit 20 is set in the first non-display area BB1, as is relative to Figures 1-3 By arranging all the gating circuits 20 between the binding area 11 and the display area AA, the technical solution of this application can reduce the number of gating circuits 20 in the second non-display area BB2, thereby reducing the border width of the second non-display area BB2.

[0054] It should be noted that, in order to clearly illustrate the layout and electrical connections of the data lines D and the gating circuit 20 in the illustrated display panel, only a portion of the gating circuit 20 and data lines D are shown in the accompanying drawings, and the dimensions of the data lines D and gating circuit 20 are exaggerated. It is readily apparent that the display panel contains a large number of data lines D and gating circuits 20, and the dimensions of the data lines D and gating circuits 20 are relatively small.

[0055] exist Figure 4 In the illustrated method, the display panel is depicted as a circle. Along the extension direction of data line D, as shown... Figure 4 As shown by the horizontal dashed line, the non-display area BB is divided into two parts: the first non-display area BB1 and the second non-display area BB2. The non-display area BB can be divided into two equal parts, with the upper part designated as the first non-display area BB1 and the lower part as the second non-display area BB2. Alternatively, the non-display area BB can be divided into two unequal parts along the first direction X, serving as the first non-display area BB1 and the second non-display area BB2 respectively.

[0056] It should be noted that, Figure 4 The horizontal dashed line is only used to indicate the division of the non-display area BB in the display panel. In the actual display panel, the first non-display area BB1 and the second non-display area BB2 do not have a visible dividing boundary. Moreover, as mentioned above, the ratio of the first non-display area BB1 and the second non-display area BB2 can be set according to requirements, and the two are not limited to a one-to-one division in the extension direction of the data line D.

[0057] In an optional embodiment of this application, a first gating circuit 21 is provided in the first non-display area BB1. This not only solves the problem that the large number of gating circuits 20 in the second non-display area BB2 affects the bezel width of the second non-display area BB2, but also, as described later, the gating control signal line 30 controlling the first gating circuit 21 can be moved along with the first gating circuit 21 to the end of the display panel away from the bonding area 11, further reducing the bezel width of the second non-display area BB2.

[0058] In addition, by setting the first selection circuit 21 in the first non-display area BB1, the width of the step area between the binding area 11 and the display area AA can be reduced, thus achieving a narrow bezel design for the lower non-display area BB while also achieving a narrow step design.

[0059] Optionally, the display panel may also include a bendable portion 13, which can be bent to the back of the display panel. Some components located in the non-display area can be placed in the bendable portion 13, bent to the back of the display panel, thereby reducing the width of the second non-display area BB2 in the first direction X and increasing the screen-to-body ratio of the display panel. Since at least a portion of the first selection circuit 21 is placed in the first non-display area BB1, the length of the second non-display area BB2 in the second direction Y can also be reduced, decreasing the number of traces and components, thereby reducing the width of the bendable portion 13. It is understandable that, especially for circular display panels, the length of the bendable portion along the first direction X and the second direction Y directly determines the overall size of the device. In the embodiments of this application, placing at least a portion of the first selection circuit 21 in the first non-display area BB1 not only reduces the width of the second non-display area BB2 in the first direction X but also reduces the length of the bendable portion 13 along the second direction Y, further facilitating a reduction in the overall size of the display device.

[0060] Optionally, as described above, since at least part of the gating circuit 20 is set as the first gating circuit 21 in the first non-display area, and the first non-display area BB1, which is far from the bonding area 11, has sufficient space due to the absence of fan-out lines and the lack of pad 12 layout requirements for bonding display area chips, more gating control signal lines 30 and gating transistors 20 can be laid out. Therefore, the first gating circuit 21 can be set in the first non-display area BB1, so that the first gating circuit 21 is connected to more data lines D. While not changing the number of gating circuits 20, the number of data lines D that the gating circuit 20 can connect is increased, thereby improving the resolution of the display panel.

[0061] Optionally, all gating circuits 20 are located in the first non-display area BB1. That is, all gating circuits are the first gating circuits 21 located in the first non-display area BB1. This eliminates the need to set gating circuits 20 in the second non-display area BB2, thus minimizing the border width of the second non-display area BB2.

[0062] To reduce the bezel width of the second non-display area BB2, the second non-display area BB2 is provided with a bendable portion 13 protruding away from the display area AA, and the binding area 11 is located within the bendable portion 13. The bendable portion 13 can be bent to the back of the display panel, thereby further reducing the bezel width of the second non-display area BB2.

[0063] refer to Figure 5 , Figure 5 This is a schematic diagram of the partitioning of a non-display area in a display panel provided in an embodiment of this application. In the second direction Y, the second non-display area BB2 has a first sub-region 01 and two second sub-regions 02 located on both sides of the first sub-region 01. The second direction Y is perpendicular to the first direction X and parallel to the display surface of the display panel; the binding area 11 is located in the first sub-region 01.

[0064] The width of the bent portion 13 in the second direction Y can be set to be equal to the width of the binding area 11. The first sub-region 01 includes the binding area 11, and the width of the first sub-region 01 is equal to the width of the binding area 11. The second non-display areas BB2 on both sides of the first sub-region 01 are two second sub-regions 02.

[0065] At the other end of the display panel away from the binding area 11, the first non-display area BB1 includes: a third sub-area 03, which is directly opposite to the first sub-area 01 in the first direction X; and two fourth sub-areas 04 located on both sides of the third sub-area 03, which are directly opposite to the second sub-area 02 in the first direction X.

[0066] In the display panel, the border width requirement for the second non-display area BB2 is relatively high, that is, the border width requirement for the first sub-area 01 and the second sub-area 02 is very high. For Figures 1-3 The panel structure shown, due to the layout requirements of the selection circuit 20, significantly increases the width of the step area between the first sub-region 01 and the display area AA, failing to meet the customer's demand for an extremely narrow step. For a circular display panel, all selection circuits 20 are placed in the non-display area BB of the lower semicircle (i.e., the second non-display area BB2). Combined with the other wiring designs in the step area of ​​the second non-display area BB2, it is difficult to further compress the step width. Furthermore, the bezel width of the second sub-region 02 is also significantly limited. This poses a considerable challenge to further developing a narrow bezel and narrow step in the second non-display area BB2.

[0067] The inventors discovered that the first non-display area BB1 has redundant space relative to the second non-display area BB2, specifically redundant space in the third sub-region 03 and the fourth sub-region 04 on both sides. This redundant space is currently not utilized by other functional modules. Furthermore, due to boundary effects, the pixel transistors in the display area AA adjacent to this redundant space exhibit electrical differences compared to the pixel transistors in display area AA that are farther from the non-display area BB, resulting in display differences in the connected sub-pixels.

[0068] In the display panel described in this application embodiment, at least a portion of the selection circuit 20 is disposed in the first non-display area BB1, that is, the first selection circuit 21 is disposed in the first non-display area BB1. This not only reduces the width of the stepped area in the second non-display area BB2, thereby reducing the border width of the second non-display area BB2, but also utilizes the redundant space in the first non-display area BB1 to arrange the first selection circuit 21, without increasing the border width of the first non-display area BB1. In addition, since the first selection circuit 21 is disposed in the first non-display area BB1, the selection transistor and selection control signal line in the first selection circuit 21 can change the boundary metal environment of the edge pixel transistors in the adjacent display area AA, thereby improving the electrical properties of the pixel transistors in the display area AA, resolving the electrical difference between the pixel transistors in the display area AA and the pixel transistors in the display area AA that are far from the non-display area BB, and improving display uniformity.

[0069] refer to Figure 6 , Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of this application, combined with... Figure 5 and Figure 6 As shown, in the first direction X, for the data line D opposite to the first sub-region 01, the data line D is electrically connected to the first gating circuit 21; in the first direction X, for the data line D opposite to the second sub-region 02, at least a portion of the data line D is electrically connected to the gating circuit 20 located in the second sub-region 02.

[0070] Figure 6 In the diagram, the width of the area shown by the two vertical dashed lines parallel to the data line D is the width of the first sub-region 01. The data line D opposite to the second sub-region 02 is the data line D located between the two dashed lines. The extension lines of these data lines in the first direction X can extend to the first region 01.

[0071] All data lines D connected to the first sub-region 01 can be configured to use the first selection circuit 21 located in the first non-display area BB1. This minimizes the width of the step area between the binding area 11 and the display area AA. Alternatively, some data lines D connected to the first sub-region 01 can be configured to use the first selection circuit 21 located in the first non-display area BB1.

[0072] If the data line D opposite to the first sub-region 01 is connected to the first gating circuit 21, in order to shorten the length of the first signal connection line 31 between the data line D and the first gating circuit 21, the first gating circuit 21 is located in the first sub-region 01. In order to minimize the length of the first signal connection line 31 connected to the first gating circuit 21, the first gating circuit 21 can be located at the end of the connected data line D away from the binding area 11. As mentioned above, placing the first gating circuit 21 in the first non-display area BB1 can improve the electrical properties of the edge pixel transistors of the display area AA adjacent to the first non-display area BB1, reduce the electrical difference between these pixel transistors and the pixel transistors inside the display area AA, thereby improving display uniformity. Moreover, the second non-display area BB2 has other metal structures such as fan-out lines 32. Moving the gating circuit 20 in the second non-display area BB2 to the first non-display area BB1 has little or no impact on the electrical properties of the pixel transistors adjacent to the second non-display area BB2, and will not cause obvious display differences.

[0073] In this embodiment, all data lines D connected to the first sub-region 01 are configured to use the first selection circuit 20 located in the first non-display area BB1. This is equivalent to... (The sentence is incomplete and requires more context to translate accurately.) Figure 1 The selection circuit 20 located in the first sub-region 01 is moved to the third sub-region 03. This not only reduces the width of the step where the first sub-region 01 is located, but also makes reasonable use of the originally redundant space in the third sub-region 03, and can also improve the electrical properties of the pixel transistors in the display area AA adjacent to the third sub-region 03. By reducing the number of N selection circuits 20 in the first sub-region 01, N first selection circuits 21 are correspondingly added in the third sub-region 03.

[0074] As mentioned above, considering the delay caused by the large length of the fan-out line 32 connected to the first gating circuit 21, generally not all gating circuits 20 in the second non-display area BB2 will be moved to the first non-display area BB1. Optionally, some or all of the gating circuits 20 in the second sub-area 02 can be retained without adjustment.

[0075] The selection circuit 20 connected to the data line D corresponding to the first sub-region 01 is set to the first selection circuit 21 located in the first non-display area BB1, which can reduce the width of the step area in the second non-display area BB2 in the first direction X by at least 100μm, making it easier to achieve a narrow bezel design.

[0076] In addition, by retaining the gating circuit 20 in the second sub-region 02, and placing part of the gating circuit 20 in the first non-display area BB1 and part in the second non-display area BB2, not only can the border width of the second non-display area BB2 be reduced, but the electrical properties of the pixel transistors adjacent to the first non-display area BB1 and the second non-display area BB2 can be improved to the greatest extent. This results in more pixel transistors located at the edge of the display area AA1 having more consistent electrical properties with the pixel transistors inside the display area AA, thereby improving display uniformity.

[0077] For data line D opposite to the second sub-region 02, the extension line of data line D in the first direction X can extend to the second sub-region 02, and this part of data line D is located in Figure 6 The outer side of the area between the two vertical dotted lines.

[0078] Optionally, some or all of the gating circuits 20 connected to the data lines D opposite to the second sub-region 02 may still be located in the second non-display area BB2. In the display panel, the main factor affecting the bezel width of the second non-display area BB2 is the large width of the step area between the binding area 11 and the display area AA. Setting the gating circuit 20 connected to all data lines D opposite to the first sub-region 01 as the first gating circuit 21 in the first non-display area BB1 can effectively reduce the width of the step area, thereby effectively reducing the bezel width of the second non-display area BB2. However, setting the gating circuit 20 connected to the data lines D opposite to the second sub-region 02 in the second sub-region 02 has a smaller impact on the bezel width of the second non-display area BB2. If this part of the gating circuit 20 is set as the first gating circuit 21 in the first non-display area BB1, the effect on reducing the bezel width of the second non-display area BB2 is limited, and it will also increase the length of the fan-out line 32 connected to this part of the gating circuit 20. Therefore, it is possible to set some or all of the gating circuits 20 connected to the data lines D opposite to the second sub-region 02 to still be located in the second non-display area BB2.

[0079] refer to Figure 7 As shown, Figure 7This is a schematic diagram of another display panel structure provided in an embodiment of this application. In the bonding area 11, the pad 12 includes a first pad 121. The gating circuit 20 is electrically connected to the first pad 121 through a fan-out line 32. The first fan-out line 321, which is electrically connected to the first gating circuit 21, passes through the display area AA from the first non-display area BB1 to the second non-display area BB2 and is electrically connected to the first pad 121.

[0080] In this embodiment, at least a portion of the selection circuit 20 is used as the first selection circuit 21 and disposed in the first non-display area BB1. This not only reduces the impact of the first selection circuit 21 on the width of the step area, but also allows the fan-out line 32 (hereinafter referred to as the first fan-out line 321) connected to the first selection circuit 21 to pass through the display area AA from the first non-display area BB1 and extend to the second non-display area BB2. If the conductive vias that electrically connect the first fan-out line 321 to the first selection circuit 21 are also disposed in the first non-display area BB1, this not only avoids the impact of these conductive vias on the width of the border of the second non-display area BB2, but also significantly shortens the length of the first fan-out line 321 in the portion between the binding area 11 and the display area AA due to the lack of a layout requirement for connecting conductive vias, thereby further reducing the width of the step area.

[0081] exist Figure 7 In the illustrated method, a partial selection circuit 20 is used as the first selection circuit 21 and set in the first non-display area BB1 as an example for illustration. As mentioned above, all selection circuits 20 can also be set as the first selection circuit 21.

[0082] In one approach, it can be as follows: Figure 7 As shown, the fan-out line 32 electrically connected to the same first selection circuit 21 is a trace that runs from the first non-display area BB1 to the second non-display area BB2 and through the display area AA. That is, the first fan-out line 321 is a straight line or an approximately straight line extending in the first direction X. The straight first fan-out line 321 is convenient for graphic design and simple to manufacture.

[0083] In another way, it is also possible to... Figure 8 As shown, the fan-out lines 32 electrically connected to the same first gating circuit 21 are configured as interconnected structures to reduce their impedance.

[0084] refer to Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a fan-out line in a display panel provided in an embodiment of this application. In this method, the fan-out line 32 electrically connected to the same first gating circuit 21 includes multiple traces located in the display area, and the traces extend along the first direction X. Among them, for the fan-out line 32 electrically connected to the same first gating circuit 21, the traces are electrically connected to each other, and at least some of the traces are connected in parallel.

[0085] like Figure 8 As shown, the first fan-out line 321 connected to a first gating circuit 21 includes two parallel first traces a and three parallel second traces b, with the two parallel first traces a and the three parallel second traces b connected in series. The upper end of the first trace a extends to the first non-display area BB, connecting to the corresponding first gating circuit 21, and the lower end connects to a connecting line c. The upper ends of the two second traces b on both sides are connected to the first trace a via the connecting line c, and the other ends extend to the second non-display area BB2. The upper end of the middle second trace B is connected to the connecting line c, and the lower end extends into the second non-display area BB2 to connect to the first pad 121, thereby connecting to the display driver chip through the first pad 121.

[0086] As mentioned above, placing the gating circuit 20 in the first non-display area BB1 as the first gating circuit 21 will increase the length of the fan-out line 32 connected to it, resulting in signal delay. The first gating circuit 21 adopts... Figure 8 The fan-out line 32 in the shown graphic structure can reduce its impedance by connecting multiple lines in parallel, thereby reducing signal delay.

[0087] By adjusting the line width and density of the traces in the first fan-out line 321, the delay between different fan-out lines 32 can be matched, thereby reducing the difference in signal response.

[0088] For the fan-out lines 32 electrically connected to the same first gating circuit 21, different traces are electrically connected through connecting lines c; connecting lines c and traces are located in different metal layers, and connecting lines c are electrically connected to traces through conductive vias; wherein, traces extend along a first direction X, and connecting lines c extend along a second direction Y. Figure 8 As shown, in the first fan-out line 321, the first trace a and the second trace b are both connected through the same connecting line c. The first trace a and the connecting line c, and the second trace b and the connecting line c are both electrically connected through conductive holes.

[0089] Since the extension direction of the trace in the first outgoing line 321 is the same as that of the data line D, both extending along the first direction X, the trace can be located on the same metal layer as the data line D. In this case, the metal layer containing the data line D can be reused to fabricate the trace in the first outgoing line 321, eliminating the need to add a separate metal layer. Furthermore, it is compatible with the existing fabrication process for the data line D; only the graphical design of the metal layer containing the data line D needs to be adjusted accordingly, without adding any process steps. By setting the trace in the first outgoing line 321 to be on the same metal layer as the data line D, and ensuring that the trace in the first outgoing line 321 is on a different layer than the connecting line c, it is guaranteed that the connecting line c extending along the second direction Y and the data line D extending along the first direction X will insulate against each other, preventing a short circuit between the data line D and the first outgoing line 321.

[0090] refer to Figure 9 and Figure 10 As shown, Figure 9 This is a schematic diagram of another display panel provided in an embodiment of this application. Figure 10 This is a cross-sectional view of a display panel provided in an embodiment of this application. The display panel has multiple parallel scan lines G, which intersect with data lines D in an insulated manner.

[0091] In the light-emitting direction of the display panel, the display panel includes: a substrate 41; a pixel circuit 42 located on the substrate 41, the pixel circuit 42 including a pixel transistor, the gate of the pixel transistor being located on a first metal layer M1, and the source and drain of the pixel transistor being located on a second metal layer M2, the second metal layer M2 being located on the side of the first metal layer M1 away from the substrate 41; and a sub-pixel P located on the pixel circuit 42. Figure 10 Taking an OLED panel as an example, the illustration shows the sub-pixel P as an OLED device. Only the anode 43 of the OLED device is shown in the diagram; its organic light-emitting layer and common cathode are not shown. In the display panel, an opening for the sub-pixel P is formed based on the pixel definition layer PDL, used to set the sub-pixel P. Support pillars PS are provided on the surface of the pixel definition layer P.

[0092] Referring to the accompanying drawings of the above embodiments and Figure 9 and Figure 10 As shown, the display control chip in the bonding area 11 controls the image display of sub-pixels P in the display area AA by providing scan signals to the scan line G and data signals to the data line D. The scan line G is located in the first metal layer M1, and the data line D is located in the second metal layer M2, which is on a different layer than the first metal layer M1. The second metal layer M2 has a third metal layer M3 on the side facing away from the first metal layer M1; a fourth metal layer Mc is located between the first metal layer M1 and the second metal layer M1.

[0093] Fan-out lines 32 are located in at least one of the first metal layers M1 to the fourth metal layer Mc. Fan-out lines 32 are conductive structures connected in series between the gating circuit 20 and the first pad 121. Given that the fan-out lines 32 connected to the gating circuit 20 in the second non-display area BB2 are located in the second non-display area BB2, while the fan-out lines 32 connected to the first gating circuit 21 need to start from the first non-display area BB1 and extend to the second non-display area BB2, fan-out lines 32 located in different areas can be laid out according to their respective metal layers.

[0094] For the selection circuit 20 located in the second non-display area BB2, the connected fan-out line 32 is designated as the second fan-out line. Since the second fan-out line is located in the second non-display area BB2, it does not require cross-insulation design with the data line D and gate line G in the display area AA. Therefore, the second fan-out line can be located in any of the first metal layer M1 to the fourth metal layer Mc. If the second non-display area BB2 has multiple selection circuits 20, the corresponding multiple second fan-out lines can be on the same layer or different layers. When multiple second fan-out lines are on different layers, the wiring space required for multiple second fan-out lines in the second direction Y can be shortened.

[0095] In one embodiment, the first fan-out line 321 connected to the first gating circuit 21 includes a portion located in the non-display area BB and a portion located in the display area AA.

[0096] The portion of the first fan-out line 321 located in the non-display area BB does not require cross-insulation design with the data line D and gate line G in the display area AA. Therefore, this portion can be located in any of the first metal layer M1 to the fourth metal layer Mc.

[0097] When the first fan-out line 321 is a straight structure extending along the first direction X, it can be positioned in the second metal layer M2. In this case, the first fan-out line 321 is parallel to the data line D, on the same layer, and spaced apart, but on a different layer and insulated from the scan line G. When the first fan-out line 321 is as follows... Figure 8 In the structure shown, the first trace a and the second trace b can both be located in the second metal layer M2, and the connecting trace c can be located in the first metal layer M1.

[0098] The portion of the first outgoing line 321 located in the display area AA requires consideration of insulation design from the metal structure within the display area AA. Therefore, based on the extension path of this portion of the first outgoing line 321 in the display area AA, its location within the first metal layer M1 to the fourth metal layer Mc needs to be selected. The portion of the first outgoing line 321 in the non-display area BB and the portion in the display area AA can be located on the same metal layer or on different metal layers.

[0099] refer to Figure 11 As shown, Figure 11This is a schematic diagram of a gating circuit provided in an embodiment of this application. The gating circuit 20 includes a plurality of gating transistors T. Figure 11 The example shown is a selection circuit 20 comprising three selection transistors T. The number of selection transistors T in the selection circuit 20 can be set according to requirements, and this application does not impose specific limitations on this.

[0100] Referring to the above-mentioned implementation drawings and Figure 11 As shown, the gate of the selection transistor T is electrically connected to the selection control signal line 30, the first electrode of the selection transistor T is electrically connected to the data line D, and the second electrode of the selection transistor T is electrically connected to the first pad 121.

[0101] In the same selection circuit 20, the first terminal of each selection transistor T is connected to a data line D, the second terminal of each selection transistor T is connected to the same fan-out line 32, so as to connect to the same first pad 121 through the fan-out line 32, and the gate of each selection transistor T is connected to different selection control signal lines 30.

[0102] like Figure 11 As shown, the three selection transistors T1, T2, and T3 are designated as first selection transistor T1, second selection transistor T2, and third selection transistor T3. The first terminals of these transistors are connected to three different data lines D, namely, first data line D1, second data line D2, and third data line D3. The second terminals of these transistors are all connected to the same fan-out line 32 via node N0. The gates of these transistors are connected to three different selection control signal lines 30, which are used to input the first clock signal CKHR, the second clock signal CKHG, and the third clock signal CKHB, respectively.

[0103] In the same gating circuit 20, the clock signal input to the gating control signal line 30 connected to the gate of each gating transistor T does not overlap during the turn-on phase, so that each gating transistor T turns on in sequence, and then provides data signal to the data line D connected to the gating circuit 20 through the fan-out line 32.

[0104] refer to Figure 12 As shown, Figure 12 for Figure 11 The timing diagram of the input clock signal in the gating circuit shown indicates that the low-level turn-on phases of the first clock signal CKHR, the second clock signal CKHG, and the third clock signal CKHB do not overlap, thereby causing the first gating transistor T1, the second gating transistor T2, and the third gating transistor T3 to turn on sequentially.

[0105] exist Figure 11 and Figure 12 In the illustrated method, the selection transistor T is a PMOS as an example for explanation. The PMOS is turned on when the voltage level is low and turned off when the voltage level is high. Obviously, in other methods, the selection transistor T can also be set to an NMOS. The implementation method of the selection transistor T in the embodiments of this application is not specifically limited.

[0106] The pads 12 in the bonding area 11 include a first pad 121 and a second pad 122. The gating circuit 20 is connected to the corresponding pad 12 via a fan-out line 32 and to the second pad 122 via a gating control signal line 30. The display control chip provides data signals to the gating circuit 20 via the first pad 121 and clock signals via the second pad 122, providing data signals to the multiple data lines D connected to the gating circuit 20 in a time-division manner.

[0107] refer to Figure 13 , Figure 13 This is a schematic diagram of the wiring method for the selection control signal connected to a selection circuit according to an embodiment of this application. The selection control signal line 30 connected to the first selection circuit 21 passes through the display area AA from the first non-display area BB1 to the second non-display area BB2, and is electrically connected to the second pad 122. In this way, the selection control signal line 30 connected to the first selection circuit 21 does not occupy the width of the non-display area BB, thereby facilitating the implementation of a narrow bezel design.

[0108] exist Figure 13 In the illustrated configuration, for clarity, a first gating circuit 21 that connects three data lines D and the three gating control signal lines 30 connected to it are shown, but the data lines D and other gating circuits 20 are not shown. The layout of the data lines D and other gating circuits 20 can be referred to the above embodiment description.

[0109] refer to Figure 14 , Figure 14 This is a schematic diagram of the wiring method for the gating control signal connected to another gating circuit provided in an embodiment of this application. Figure 13 The difference shown is that, Figure 14 In the configuration shown, the first gating circuit 21 is electrically connected to the gating control signal line 30, which is connected from the non-display area BB to the second pad 122. Figure 1 Compared to other methods, Figure 14 In the illustrated method, a portion of the gating circuit 20 is set as the first gating circuit 21 in the first non-display area BB1, which can greatly reduce the width of the step area in the first non-display area BB1. The gating control signal line 30 connected to the first gating circuit 21 has little impact on the border width of the non-display area BB.

[0110] In this embodiment of the application, in order to reduce the impact of the gating control signal line 30 on the width of the non-display area BB bezel, at least part of the gating control signal line 30 can be located within the display area AA, so as to realize the narrow bezel design of the non-display area BB.

[0111] The gating control signal line 30 connected to the gating circuit 20 can be set to one or more layers among the first metal layer M1 to the fourth metal layer Mc, depending on its wiring requirements.

[0112] refer to Figure 15 As shown, Figure 15 This application provides a schematic diagram of the wiring method for the selection control signal line connected to the second non-display area, in conjunction with the accompanying drawings of the above embodiments. Figure 15 As shown, for the gating circuit 20 located in the second non-display area BB2, the connected gating control signal line 30 is located within the second non-display area BB2.

[0113] The gating control signal line 30 located in the second non-display area BB2 includes: a first portion 301 along the first direction X, for connection to the gate of the gating transistor T in the gating circuit 20; and a second portion 302 along the second direction Y, for connection to the second pad 122; wherein the first portion 301 and the second portion 302 are located in different metal layers and are connected through a conductive hole.

[0114] refer to Figure 16 As shown, Figure 16 This is a schematic diagram illustrating another wiring method for the gating control signal line connected to the second non-display area, as provided in an embodiment of this application. Figure 15 The difference shown is that, Figure 16 In the illustrated configuration, for the selection control signal line 30 connected to the selection circuit 20 located in the second non-display area BB2, at least one second portion 302 of the selection control signal line 30 is located in the display area AA. This significantly reduces the impact of the second portion 302 of the selection control signal line 30 on the border width of the second non-display area BB2. Furthermore, for the second portion 302 located in the display area AA, its conductive via and the first portion 301 can also be located in the display area AA, thereby reducing the impact of the conductive via between them on the border width of the second non-display area BB2.

[0115] In this embodiment, the selection control signal line 30 can be shared by the selection transistors T in different selection circuits 20, which can reduce the number of selection control signal lines 30 and thus reduce the width of the frame.

[0116] In order to reduce the length of the selection control signal line 30 connected to the selection circuit 20 in the first non-display area BB1, thereby reducing or even avoiding the load difference with the selection control signal line 30 connected to the selection circuit 20 in the second non-display area BB2, the selection control signal line 30 connected to the selection circuit 20 in the first non-display area BB1 is designed with multiple lines connected in parallel to reduce its impedance and minimize the load difference with the selection control signal line 30 connected to the selection circuit 20 in the second non-display area BB2.

[0117] In the above embodiments, a circular display panel is used as an example for illustration, where the display area AA is circular. A display panel with a circular display area AA can be used in wearable devices, such as smartwatches, smart glasses, or head-mounted devices.

[0118] Obviously, in this embodiment, the display panel is not limited to a circular display panel, but can also be a common rectangular display panel with a rectangular display area. When a display panel is used, the first non-display area BB1 and the second non-display area BB3 can be two non-display areas at opposite ends.

[0119] Based on the above embodiments, another embodiment of this application also provides an electronic device, the electronic device as follows: Figure 17 As shown.

[0120] refer to Figure 17 As shown, Figure 17 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device includes the display panel 51 described in any of the above embodiments.

[0121] In this embodiment, the electronic device uses the display panel 51 described in the above embodiment, which can greatly reduce the bezel width and facilitate the narrow bezel design of the electronic device.

[0122] In this embodiment, a smartwatch is used as an example for illustration. Obviously, the electronic device described in this application embodiment is not limited to a smartwatch, but can also be other electronic devices with display functions, such as mobile phones, smart glasses and tablet computers.

[0123] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the electronic devices disclosed in the embodiments, since they correspond to the display panels disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the corresponding descriptions of the display panels.

[0124] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0125] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0126] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0127] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: The display area and at least a non-display area surrounding a portion of the display area; Multiple data lines, the data lines being located within the display area; The non-display area includes a first non-display area and a second non-display area that are opposite each other in a first direction, where the first direction is the extension direction of the data line; A bonding area having multiple pads for electrically connecting to a display driver chip; Multiple gating circuits are provided, each gating circuit electrically connected to the data line and the pad; each gating circuit includes a first gating circuit located in the first non-display area; multiple data lines are connected to the same pad in the bonding area through the same gating circuit to provide data signals to multiple data lines in a time-division manner; In the second direction, the second non-display area has a first sub-region and two second sub-regions located on both sides of the first sub-region. The second direction is perpendicular to the first direction and parallel to the display surface of the display panel. The binding area is located in the first sub-region; In the first direction, for the data line opposite to the first sub-region, the data line is electrically connected to the first gating circuit; In the first direction, for the data lines opposite to the second sub-region, at least a portion of the data lines are electrically connected to a gating circuit located in the second sub-region.

2. The display panel according to claim 1, characterized in that, The pad includes a first pad, and the gating circuit is electrically connected to the first pad via a fan-out line; The fan-out line, which is electrically connected to the first gating circuit, passes through the display area from the first non-display area to the second non-display area and is electrically connected to the first pad.

3. The display panel according to claim 2, characterized in that, The fan-out line of the same first gating circuit is a trace that runs from the first non-display area to the second non-display area and through the display area.

4. The display panel according to claim 2, characterized in that, The fan-out line electrically connected to the same first gating circuit includes multiple traces located within the display area, the traces extending along the first direction; Specifically, for fan-out lines electrically connected to the same first gating circuit, the lines are electrically connected to each other, and at least some of the lines are connected in parallel.

5. The display panel according to claim 4, characterized in that, For the same fan-out line electrically connected to the first gating circuit, different traces are electrically connected through connecting lines; the connecting lines and the traces are located in different metal layers, and the connecting lines are electrically connected to the traces through conductive vias; The connecting line extends along a second direction, which is perpendicular to the first direction and parallel to the display surface of the display panel.

6. The display panel according to claim 4, characterized in that, The trace and the data line are located on the same metal layer.

7. The display panel according to claim 1, characterized in that, The display panel has multiple parallel scan lines, which are insulated from and cross the data lines. The scan lines are located on a first metal layer, and the data lines are located on a second metal layer that is different from the first metal layer. The pads include a first pad, and the gating circuit is electrically connected to the first pad via a fan-out line. The second metal layer has a third metal layer on the side facing away from the first metal layer. A fourth metal layer is located between the first metal layer and the second metal layer. The fan-out line is located in at least one of the first metal layer to the fourth metal layer.

8. The display panel according to claim 1, characterized in that, The pads include a first pad; The gating circuit includes: a plurality of gating transistors; The gate of the selection transistor is electrically connected to the selection control signal line, the first electrode of the selection transistor is electrically connected to the data line, and the second electrode of the selection transistor is electrically connected to the first pad.

9. The display panel according to claim 8, characterized in that, The pad also includes a second pad; The selection control signal line electrically connected to the first selection circuit passes through the display area from the first non-display area to the second non-display area and is electrically connected to the second pad.

10. The display panel according to claim 8, characterized in that, The pad also includes a second pad; The gating control signal line electrically connected to the first gating circuit is electrically connected from the non-display area to the second pad.

11. The display panel according to claim 8, characterized in that, At least a portion of the gating control signal lines are located within the display area.

12. The display panel according to claim 8, characterized in that, The gating transistors in different gating circuits share the gating control signal line.

13. The display panel according to any one of claims 1-12, characterized in that, The display area is circular.

14. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1-13.

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