Method and apparatus for identifying contamination in a semiconductor manufacturing plant

Abstract

Methods and related apparatuses of identifying contamination in a semiconductor fabrication plant are disclosed. The method includes determining contamination map data for a plurality of semiconductor wafers after being processed in the semiconductor fabrication plant that are clamped onto a wafer table. Combined contamination map data is determined based at least in part on a combination of the contamination map data for the plurality of semiconductor wafers. The combined contamination map data is combined with reference data. The reference data includes one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fabrication plant.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Application 63 / 064,014, filed August 11, 2020; European Application 20193101.1, filed August 27, 2020; and European Application 21162726.0, filed March 16, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to methods and apparatus for identifying contamination in semiconductor manufacturing plants. In an exemplary arrangement, the invention can detect the impact of contamination on one or more tools in a semiconductor manufacturing plant based on measurements obtained from sensors such as level sensors. In some specific exemplary configurations, the impact of contamination may be combined with plant-related information to influence tool maintenance. Background Technology

[0004] A photolithography apparatus is a machine that applies a desired pattern onto a substrate. Photolithography apparatuses can be used, for example, to manufacture integrated circuits (ICs). A photolithography apparatus can project a pattern (often referred to as a “design layout” or “design”) from a patterning device (e.g., a mask) onto a layer of radiation-sensitive material (resist) disposed on a substrate (e.g., a wafer).

[0005] To project a pattern onto a substrate, a photolithography apparatus can use electromagnetic radiation. The wavelength of this radiation determines the minimum size of the feature that can be patterned on the substrate. Typical wavelengths currently used are 365 nm (i-line), 248 nm, 193 nm, and 13.5 nm. Compared to photolithography apparatuses using radiation with a wavelength of, for example, 193 nm, extreme ultraviolet (EUV) radiation with wavelengths in the range of 4 nm to 20 nm (e.g., 6.7 nm or 13.5 nm) can be used to form smaller features on the substrate.

[0006] Low-k1 lithography can be used to process features smaller than the classical resolution limit of a lithography apparatus. In this process, the resolution formula can be expressed as CD = k1 × λ / NA, where λ is the wavelength of the radiation used, NA is the numerical aperture of the projection optics in the lithography apparatus, CD is the “critical size” (typically the smallest feature size printed, but in this case, half a pitch), and k1 is an empirical resolution factor. Generally, the smaller k1 is, the more difficult it is to reproduce a pattern on the substrate with a shape and size similar to that planned by the circuit designer to achieve specific electrical functions and performance. To overcome these challenges, complex fine-tuning steps can be applied to the lithography projection apparatus and / or design layout. These include, but are not limited to, optimizing NA, customizing the illumination scheme, using phase-shifting patterning devices, various optimizations of the design layout such as optical proximity correction (OPC, sometimes also referred to as “optical and process correction”), or other methods generally defined as “resolution enhancement techniques” (RET). Alternatively, a tight control loop for controlling the stability of the lithography apparatus can be used to improve pattern reproduction at low k1.

[0007] During photolithography, it is often desirable to measure the resulting structure, for example, for process control and verification. Various tools are known for performing such measurements, including scanning electron microscopes commonly used to measure critical dimensions (CD) and specialized tools for measuring overlay and alignment accuracy between two layers in a device. Recently, various types of scatterometers have been developed for use in photolithography.

[0008] For optimal performance, the substrate must be stable and flat during the patterning step. Typically, the substrate is held on a substrate support by clamping force. By convention, clamping is achieved through suction. In some lithography tools using extreme ultraviolet (EUV) radiation, patterning operations are performed in a vacuum environment. In this case, clamping force is achieved through electrostatic attraction.

[0009] As substrates move through the lithography apparatus, they acquire positions measured using substrate alignment and leveling measurements. This occurs after the substrates are clamped onto the substrate support and before exposure. The intention is to characterize any unique inter-substrate deviations. Deviations can originate from several sources: errors in substrate placement onto the substrate support, the manner in which previous processes in the semiconductor fabrication plant shaped the substrate surface, or the presence of contamination on the back side of the substrate. Because the substrates are clamped onto the substrate support, any contamination between the back side of the substrate and the surface of the substrate support, or any non-uniform support features, can affect the substrate surface morphology. Simultaneously, a physical model controlling the inter-substrate alignment of the lithography apparatus uses alignment and leveling measurements to consistently and correctly position each substrate for precise substrate patterning.

[0010] Defects such as damage to the substrate support during clamping can cause substrate deformation. Specifically, it should be understood that the substrate support degrades over time due to friction between the surface of the substrate support and the back side of the substrate and / or the effects of chemicals used to treat the substrate during one or more processing steps. The surface of the support typically includes multiple protrusions or nodules to significantly mitigate the effects of contaminant particles introduced between the substrate and the support. One or more of these protrusions or other aspects of the substrate support (specifically, at the edges) may be affected by this degradation, causing its shape to change over time, which affects the shape of the substrate clamped thereon. Existing control systems may not be able to correct for the effects of this degradation of the substrate support.

[0011] Semiconductor manufacturing plants can contain thousands of different tools used for CMP, diffusion, etching, implantation, lithography (scanners, tracks), thin film (CVD), and cleaning. Each individual wafer passing through the plant can undergo hundreds of process steps, and each step affects the final equipment yield in one way or another. Contamination-related issues are a major factor in die yield loss on wafers passing through the plant. However, even if final probe testing reveals contamination as the cause of yield loss, identifying the exact source of contamination among all the different tools contained in the plant is often very difficult. Summary of the Invention

[0012] The inventors have appreciated that it may be desirable to identify contamination or other errors introduced into the photolithography process due to contamination or defects in the substrate support. Furthermore, the inventors have appreciated that it may be desirable to determine the location within the semiconductor manufacturing plant where such contamination and / or defects have been introduced. The exemplary arrangements disclosed herein may be intended to address or mitigate these problems and / or other problems associated with the art.

[0013] According to one aspect of the present invention, a method for identifying contamination in a semiconductor manufacturing plant is provided, the method comprising: determining contamination map data of a plurality of semiconductor wafers clamped to a wafer stage after processing in the semiconductor manufacturing plant; determining combined contamination map data based at least in part on a combination of the contamination map data of the plurality of semiconductor wafers; and comparing the combined contamination map data with reference data, wherein the reference data includes one or more values ​​for the combined contamination map data indicating contamination in one or more tools in the semiconductor manufacturing plant and data associated with a previous processing stage.

[0014] Optionally, the pollution map data is determined based on data obtained from leveling sensors.

[0015] Optionally, the pollution map data includes focused spot data.

[0016] Alternatively, the contamination map data is determined by applying a blot detection algorithm to the wafer height data.

[0017] Optionally, the wafer height data includes wafer height data fitted with a continuous surface.

[0018] Optionally, determining the combined contamination map data includes: determining the union of contamination map data for multiple semiconductor wafers.

[0019] Optionally, the reference data includes data indicating failures in one or more dies in one or more subsequent semiconductor wafers processed in a semiconductor manufacturing plant.

[0020] Optionally, the reference data includes a focus error threshold, and wherein combined contamination map data above the focus error threshold indicates a failure of one or more dies in one or more subsequent semiconductor wafers.

[0021] Optionally, the reference data includes the die failure probability based at least in part on the combined contamination map data.

[0022] Optionally, the method further includes: determining a die loss map of one or more dies of a subsequent semiconductor wafer that are at risk of failure, based on the combined contamination map data and a focus error threshold.

[0023] Optionally, the reference data includes geometric data relating to one or more tools in a semiconductor manufacturing plant.

[0024] Optionally, the geometry data includes the location of one or more wafer support features of one or more tools.

[0025] Optionally, the location of one or more wafer support features includes polygons over regions on the surfaces of multiple semiconductor wafers.

[0026] Optionally, the method further includes: determining one or more tool types that could be potential sources of contamination in a semiconductor manufacturing plant based on a comparison of the combined contamination map data and geometry data.

[0027] Optionally, the method further includes: identifying one or more tools as potential sources of contamination in a semiconductor manufacturing plant based on a comparison of combined contamination map data and geometry data.

[0028] Optionally, the method further includes: determining one or more parts of one or more tools in a semiconductor manufacturing plant that are potential sources of contamination based on a comparison of the combined contamination map data and geometry data.

[0029] Optionally, the multiple chips include chips that have at least some of a public manufacturing plant background.

[0030] Optionally, the manufacturing plant background includes one or more of the following: products manufactured on semiconductor wafers, device structure layers manufactured on semiconductor wafers, scanners on which device structures have been manufactured on semiconductor wafers, the time period in which semiconductor wafers are at least partially processed in the semiconductor manufacturing plant, and / or the path taken by semiconductor wafers through the semiconductor manufacturing plant.

[0031] Optionally, the reference data includes data associated with previous processing stages and / or with different chip manufacturing plants.

[0032] According to one aspect of the invention, a computer program is provided, comprising instructions that, when executed on at least one processor, cause at least one processor control device to perform any method disclosed above and / or herein.

[0033] According to one aspect of the invention, a carrier is provided that includes a computer program, wherein the carrier is one of the following: an electronic signal, an optical signal, a radio signal, or a non-transitory computer-readable storage medium.

[0034] According to one aspect of the invention, a contamination identification device in a semiconductor manufacturing plant is provided, the device including a computer processor configured to execute computer program code to perform the following methods: determining contamination map data of a plurality of semiconductor wafers clamped to a wafer stage after processing in the semiconductor manufacturing plant; determining combined contamination map data based at least in part on a combination of the contamination map data of the plurality of semiconductor wafers; and comparing the combined contamination map data with reference data, wherein the reference data includes one or more values ​​for the combined contamination map data indicating contamination in one or more tools in the semiconductor manufacturing plant.

[0035] The apparatus may include other features corresponding to one or more method steps, as set forth herein.

[0036] According to one aspect of the present invention, a photolithography apparatus is provided, comprising the apparatus disclosed above and / or herein.

[0037] According to one aspect of the present invention, a photolithography unit is provided, comprising the photolithography apparatus disclosed above and / or herein. Attached Figure Description

[0038] Now, embodiments of the invention will be described by way of example only, with reference to the accompanying schematic diagrams, wherein...

[0039] Figure 1 A schematic diagram of the photolithography apparatus is depicted;

[0040] Figure 2 A schematic diagram of the photolithography unit is depicted;

[0041] Figure 3 A schematic representation of overall photolithography depicting the synergy between three key technologies representing optimized semiconductor manufacturing;

[0042] Figure 4 An exemplary wafer stage is shown that can be formed as part of a semiconductor manufacturing plant;

[0043] Figure 5a and Figure 5b This illustration schematically shows the effect of contamination on a semiconductor wafer as it passes through a photolithography apparatus.

[0044] Figure 6 An exemplary method for identifying contamination in a semiconductor manufacturing plant is shown; and

[0045] Figure 7 This is a block diagram illustrating another exemplary method for identifying contamination in a semiconductor wafer manufacturing plant. Detailed Implementation

[0046] Generally, methods and apparatus for identifying contamination and / or substrate support defects in a semiconductor manufacturing plant are disclosed herein. Exemplary arrangements determine a contamination map or defect map, which in some examples includes a focus spot map. The contamination map can identify areas on the surface of a wafer exhibiting focus errors, i.e., areas with local height differences compared to other areas of the wafer, which can be an indication of contamination or defects. Contamination maps of multiple wafers can be combined to identify common areas of potential contamination across multiple wafers. These common areas can be compared with reference data to determine whether contamination exists in the manufacturing plant and / or whether one or more wafer supports include defects.

[0047] Before describing embodiments of the methods and apparatus disclosed herein, a general description follows, illustrating example environments in which one or more of these embodiments may be implemented.

[0048] In this document, the terms “radiation” and “beam” are used to cover all types of electromagnetic radiation, including ultraviolet radiation (e.g., wavelengths of 365 nm, 248 nm, 193 nm, 157 nm, or 126 nm) and EUV radiation (extreme ultraviolet radiation, e.g., wavelengths between about 5 nm and 100 nm), X-ray radiation, electron beam radiation, and other particle radiation.

[0049] As used in the background, the terms "mask," "mask," or "patterning apparatus" can be broadly interpreted as any general patterning apparatus that can be used to give an incident radiation beam a patterned cross-section corresponding to a pattern to be produced in a target portion of a substrate. In this background, the term "optical valve" may also be used. Examples of such patterning apparatuses, besides classic masks (transmissive or reflective masks; binary masks, phase-shifting masks, hybrid masks, etc.), include programmable mirror arrays and programmable LCD arrays.

[0050] Figure 1 A lithography apparatus LA is schematically depicted. The lithography apparatus LA includes: an irradiation system (also referred to as an irradiator) IL configured to modulate a radiation beam B (e.g., UV radiation, DUV radiation, EUV radiation, or X-ray radiation); a mask support (e.g., a mask stage) MT configured to support a pattern forming apparatus (e.g., a mask) MA and connected to a first positioner PM configured to precisely position the pattern forming apparatus MA according to certain parameters; a substrate support (e.g., a wafer stage) WT configured to hold a substrate (e.g., a wafer coated with resist) W and connected to a second positioner PW configured to precisely position the substrate according to certain parameters; and a projection system (e.g., a refractive projection lens system) PS configured to project a pattern imparted by the radiation beam B onto a target portion C (e.g., comprising one or more dies) of the substrate W via the pattern forming apparatus MA.

[0051] During operation, the irradiation system IL receives a radiation beam from the radiation source SO, for example, via the beam delivery system BD. The irradiation system IL may include various types of optical components, such as refractive, reflective, diffractive, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof, for guiding, shaping, or controlling the radiation. The irradiator IL can be used to adjust the radiation beam B to have a desired spatial and angular intensity distribution in a cross-section at the plane of the pattern forming apparatus MA.

[0052] The term “projection system” as used herein should be interpreted broadly to encompass any type of projection system, including refractive, reflective, diffractive, antirefractive, distorting, magnetic, electromagnetic, and electrostatic optical systems, or any combination thereof, depending on the exposure radiation being used or other factors suitable such as the use of an immersion liquid or a vacuum. Any use of the term “projection lens” herein may be considered synonymous with the more general term “projection system” (PS).

[0053] A lithography apparatus LA can be of the type in which at least a portion of the substrate can be covered by a liquid with a relatively high refractive index (e.g., water) to fill the space between the projection system PS and the substrate W; this is also known as immersion lithography. More information on immersion techniques is given in US6952253, which is incorporated herein by reference in its entirety.

[0054] The lithography apparatus LA can also be of the type having two or more substrate supports WT (also referred to as "dual stages"). In such a "multi-stage" machine, the substrate supports WT can be used in parallel, and / or the step of preparing the substrate W for subsequent exposure can be performed on the substrate W located on one of the substrate supports WT, while another substrate W on another substrate support WT is used to expose the pattern on the other substrate W.

[0055] In addition to the substrate support WT, the lithography apparatus LA may also include a measurement stage. The measurement stage is arranged to hold sensors and / or cleaning equipment. The sensors may be arranged to measure characteristics of the projection system PS or the radiation beam B. The measurement stage may accommodate multiple sensors. The cleaning equipment may be arranged as part of the cleaning lithography apparatus, for example, as part of the projection system PS or as part of a system providing immersion liquid. The measurement stage may move below the projection system PS when the substrate support WT is moved away from the projection system PS.

[0056] During operation, a radiation beam B is incident on a pattern forming apparatus (e.g., a mask) MA held on a mask support MT and is patterned by a pattern (design layout) present on the pattern forming apparatus MA. After traversing the pattern forming apparatus MA, the radiation beam B passes through a projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of a second positioner PW and a position measurement system IF, the substrate support WT can be precisely moved, for example, to position different target portions C at focused and aligned locations within the path of the radiation beam B. Similarly, a first positioner PM and possibly another position sensor ( Figure 1 (Not explicitly depicted) can be used to precisely position a patterning apparatus (e.g., a mask) MA relative to the path of the radiation beam B. The patterning apparatus MA and the substrate W can be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2. Although the substrate alignment marks P1, P2, as illustrated, occupy dedicated target portions, they can be located in the space between the target portions. When the substrate alignment marks P1, P2 are located between target portions C, they are referred to as scribe-lane alignment marks.

[0057] like Figure 2As shown, a lithography apparatus LA can form part of a lithography system LC, sometimes referred to as a lithography unit or (lithography) cluster. The lithography unit LC may also include means for performing pre-exposure and post-exposure processes on the substrate. Conventionally, these means include a spin coater SC for depositing a resist layer, a developer DE for developing the exposed resist, a chill plate CH, and / or a baking plate BK, for example, for regulating the temperature of the substrate W (e.g., for regulating the solvent in the resist layer). A substrate processor or robot RO picks up one or more substrates from input / output ports I / O1, I / O2, moves them between different process units, and then transfers the substrate W to the feed stage LB of the lithography apparatus LA. These devices in the lithography unit are often collectively referred to as tracks and are typically under the control of a track control unit TCU, which is itself controlled by a management control system SCS, which also controls the lithography apparatus LA, for example, via a lithography control unit LACU.

[0058] During photolithography, it is desirable to frequently measure the resulting structure, for example, for process control and verification. The tools used to perform these measurements are generally called metrology tools (MTs). Different types of metrology tools (MTs) are known for performing these measurements, including scanning electron microscopes (SEMs) or various forms of scatterometer metrology tools (MTs). A scatterometer is a versatile instrument that allows the measurement of parameters of the photolithography process by placing a sensor in or on a plane conjugate to the objective lens of the scatterometer (these measurements are generally referred to as pupil-based measurements) or by placing a sensor in or on a plane conjugate to the image plane (in this case, these measurements are generally referred to as image- or field-based measurements). Such scatterometers and associated measurement techniques are further described in U.S. patent applications US20100328655, US2011102753A1, US20120044470A, US20110249244, US20110026032, or EP1,628,164A, the entire contents of which are incorporated herein by reference. The aforementioned scatterer can use light from soft X-rays, extreme ultraviolet light, and light visible in the near-IR wavelength range to measure the grating.

[0059] To ensure accurate and consistent exposure of the substrate W exposed by the photolithography unit LA, it is desirable to inspect the exposed substrate to measure characteristics of the patterned structure, such as overlay error between subsequent layers, line thickness, critical dimension (CD), etc. For this purpose, inspection tools and / or measurement tools (not shown) may be included in the photolithography unit LC. If errors are detected, adjustments can be made, for example, to the exposure of subsequent substrates or other processing steps to be performed on the substrate W, especially when inspection is performed before exposing or processing other substrates W in the same batch or batch.

[0060] An inspection apparatus (also referred to as a measurement apparatus) is used to determine the characteristics of a substrate W, specifically, how the characteristics of different substrates W vary or how the characteristics associated with different layers of the same substrate W vary layer by layer. Alternatively, the inspection apparatus can be configured to identify defects on the substrate W and can be, for example, part of a photolithography unit LC, or integrated into a photolithography apparatus LA, or even a stand-alone device. The inspection apparatus can measure characteristics on latent images (images in a resist layer after exposure), semi-latent images (images in a resist layer after a post-exposure baking (PEB) step), or developed resist images (exposed or unexposed portions where the resist has been removed), or even etched images (after a pattern transfer step, such as etching).

[0061] In the first embodiment, the scatterer MT is an angle-resolved scatterer. In such a scatterer, a reconstruction method can be applied to the measured signal to reconstruct or calculate the characteristics of the grating. For example, this reconstruction can be generated by simulating the interaction between the scattered radiation and a mathematical model of the target structure and comparing the simulation results with the measurement results. The parameters of the mathematical model are adjusted until the simulation interaction produces a diffraction pattern similar to the diffraction pattern observed from the actual target.

[0062] In the second embodiment, the scatterer MT is a spectroscopic scatterer MT. In this spectroscopic scatterer MT, radiation emitted by a radiation source is directed onto the target, and radiation reflected or scattered from the target is directed to a spectroscopic detector, which measures the spectrum of the specularly reflected radiation (i.e., measures the intensity as a function of wavelength). Based on this data, the structure or profile of the target that generated the detected spectrum can be reconstructed, for example, by rigorous coupled-wave analysis and nonlinear regression or by comparison with a simulated spectral library.

[0063] In the third embodiment, the scatterer MT is an elliptically polarized scatterer. This elliptically polarized scatterer allows for the determination of parameters of the photolithography process by measuring the scattered radiation for each polarization state. This measurement device emits polarized light (such as linearly polarized, circularly polarized, or elliptically polarized light) by using, for example, a suitable polarizing filter in the illumination portion of the measurement device. A light source suitable for the measurement device can also provide polarized radiation. Various embodiments of existing elliptically polarized scatterers are described in U.S. patent applications 11 / 451,599, 11 / 708,678, 12 / 256,780, 12 / 486,449, 12 / 920,968, 12 / 922,587, 13 / 000,229, 13 / 033,135, 13 / 533,110, and 13 / 891,410, the entire contents of which are incorporated herein by reference.

[0064] In one embodiment of the scattering instrument MT, the scattering instrument MT is adapted to measure the overlay of two misaligned gratings or periodic structures by measuring the reflectance spectrum and / or detecting the asymmetry of the configuration, which is related to the overlay range. The two (potentially overlapping) grating structures can be applied to two different layers (not necessarily consecutive layers) and can be formed substantially at the same location on the wafer. The scattering instrument can have a symmetrical detection configuration, such as described, for example, in the commonly owned patent application EP1,628,164A, making it possible to clearly distinguish any asymmetry. This provides a simple and direct way to measure misalignment in gratings. Other examples of overlay errors between two layers containing periodic structures when measuring a target by the asymmetry of the periodic structure can be found in PCT patent application publication WO2011 / 012624, which is incorporated herein by reference in its entirety, or in U.S. patent application US 20160161863.

[0065] Other parameters of interest may be focal length and dose. Focal length and dose can be determined simultaneously by scattering measurements (or by scanning electron microscopy) as described in U.S. Patent Application US2011-0249244, the entire contents of which are incorporated herein by reference. A single structure can be used, having a unique combination of critical dimensions and sidewall angle measurements for each point in the focal length energy matrix (FEM – also known as the focal length exposure matrix). If these unique combinations of critical dimensions and sidewall angles are available, the focal length and dose values ​​can be uniquely determined through these measurements.

[0066] The measurement target can be the entirety (ensemble) of a composite grating formed by a photolithography process (primarily in the resist, but also, for example, after an etching process). The pitch and linewidth of the structures in the grating may be strongly dependent on the measurement optics (specifically, the NA of the optics) to capture the diffraction order from the measurement target. As previously indicated, the diffraction signal can be used to determine the offset between two layers (also known as 'overlap'), or it can be used to reconstruct at least a portion of the original grating, such as that produced by the photolithography process. This reconstruction can be used to provide guidance on the quality of the photolithography process and can be used to control at least a portion of the photolithography process. The target can have smaller subsegments configured to mimic the dimensions of functional portions of the design layout in the target. Due to these subsegments, the target will behave more similarly to the functional portions of the design layout, making the overall process parameter measurements better resemble the functional portions of the design layout. The target can be measured in either underfill or overfill modes. In underfill mode, the measurement beam generates a spot smaller than the entire target. In overfill mode, the measurement beam generates a spot larger than the entire target. In this overfill mode, different targets can be measured simultaneously, thereby determining different processing parameters at the same time.

[0067] The overall measurement quality of lithography parameters for a specific target is determined at least in part by the measurement conditions used to measure those parameters. The term "substrate measurement conditions" can include one or more parameters of the measurement itself, one or more parameters of one or more patterns being measured, or both. For example, if the measurement used in the substrate measurement conditions is a diffraction-based optical measurement, one or more of the measured parameters can include the wavelength of the radiation, the polarization of the radiation, the angle of incidence of the radiation relative to the substrate, the orientation of the radiation relative to the pattern on the substrate, etc. One criterion for selecting measurement conditions can be, for example, the sensitivity of one of the measurement parameters to processing variations. Further examples are described in U.S. Patent Application US 2016-0161863 and published U.S. Patent Application US 2016 / 0370717A1, the entire contents of which are incorporated herein by reference.

[0068] The patterning process in a photolithography (LA) apparatus is arguably one of the most critical steps in the process, demanding high precision in the size and arrangement of the structures on the substrate W. To ensure this high precision, three systems can be combined in a single assembly, such as... Figure 3 The illustration depicts a so-called "holistic" control environment. One of these systems is the lithography apparatus LA, which is (virtually) connected to the metrology tool MET (second system) and the computer system CL (third system). The key to this "holistic" environment is optimizing the coordination between these three systems to enhance the overall process window and provide a tight control loop to ensure that the patterning performed by the lithography apparatus LA remains within the process window. The process window defines a range of process parameters (e.g., dose, focal length, overlay) within which a particular manufacturing process produces a defined result (e.g., a functional semiconductor device); perhaps within this range, process parameters during the lithography or patterning process are allowed to vary.

[0069] The computer system CL can use a portion of the design layout to be patterned to predict which resolution enhancement techniques to use, and perform computational lithography simulations and calculations to determine which mask layouts and lithography apparatus settings achieve the largest overall process window (within) the patterning process. Figure 3 (Depicted by double arrows in the first scale SC1). Typically, resolution enhancement techniques are arranged to match the patterning possibilities of the lithography apparatus LA. The computer system CL can also be used to detect which position within the process window the lithography apparatus LA is currently operating (e.g., using input from the metrology tool MT) to predict whether defects are likely to exist due to, for example, suboptimal processing (in... Figure 3 (This is depicted by the arrow pointing to "0" in the second ruler SC2).

[0070] The measurement tool MET can provide input to the computer system CL to enable accurate simulation and prediction, and can provide feedback to the lithography apparatus LA to identify, for example, possible drift of the lithography apparatus LA in a calibration state (in... Figure 3 (This is depicted by multiple arrows in the third ruler SC3).

[0071] Exemplary arrangements of the methods and apparatus disclosed herein will now be described in detail.

[0072] Figure 4 An exemplary wafer stage (or wafer support) 400 of a lithography apparatus (or tool) 402 is shown, which may form part of a semiconductor manufacturing plant. The wafer stage 400 includes a plurality of wafer support features 404. Each wafer support feature 404 includes a plurality of pins (or protrusions). As explained below, the plurality of pins 404 support the wafer as it undergoes one or more processing steps within the lithography apparatus 402. The plurality of wafer support features 404 may be positioned on the wafer stage 400 in a specific geometry. One or more relative geometries of the wafer support features 404 may form at least a portion of the geometry data of the lithography apparatus 402. The relative geometries of the wafer support features may be specific to a particular lithography apparatus and / or a particular type of lithography apparatus.

[0073] As mentioned above, contamination may accumulate within the lithography apparatus 402 over time; and when the wafer is clamped or held on the wafer stage 400, the contamination may come into contact with the back side of the wafer.

[0074] Figure 5a and Figure 5b This illustration schematically shows the effect of contamination on a semiconductor wafer as it passes through a photolithography apparatus.

[0075] exist Figure 5a In this process, the wafer stage 400 includes a plurality of wafer support features 404. A contaminant 500 is shown on the upper surface of one of the wafer support features 404. Typically, the contaminant 500 may be present under the wafer 502 as an alternative to or supplement to the contaminant 500 on the support feature 404. The semiconductor wafer 502 descends onto the wafer stage 400, and more specifically, onto the wafer support feature 404.

[0076] Figure 5bA wafer 502 is shown clamped to the wafer stage 400 and thus to the wafer support feature 404. It can be seen that contamination 500 causes localized height variations 504 on the surface of the wafer 502. These localized height variations 504 can cause focusing errors and lead to errors in the lithography process, which can affect wafer yield. To combat the effects of this contamination, the lithography apparatus can be scheduled for periodic maintenance or cleaning. However, such costs are significant, and such maintenance or cleaning is desirable when necessary. Furthermore, understanding the extent of contamination and / or wafer stage defects within the lithography apparatus allows maintenance or cleaning to be scheduled at a convenient time that minimizes downtime at the manufacturing plant.

[0077] The methods and apparatus disclosed herein can use contamination mapping to identify zones on the surface of a wafer that experience localized height variations, such as... Figure 5b The partitions are shown. Therefore, a contamination map can include one or more polygons on an image of the wafer's surface, which identify areas where contamination may cause localized height variations. A contamination map can be determined in a variety of different ways, and in one exemplary arrangement, it can be determined based on height data related to the height of the wafer's surface (such as data obtained from a level sensor).

[0078] Figure 6 An exemplary method for identifying contamination in a semiconductor manufacturing plant is shown. Figure 6 The methods shown include exemplary methods for determining a contamination map, in this case, exemplary methods for determining a blot map.

[0079] The wafer is clamped 600 onto the wafer stage of the photolithography apparatus. A wafer pattern is determined 602, which can be determined using, for example, wafer height data obtained from a leveling sensor for a particular wafer. The wafer height data may include wafer height data fitted to the continuous surface of a particular wafer. A spot detection algorithm 604 is run on the wafer pattern. Spot detection algorithms are known to those skilled in the art and will not be discussed in detail herein. The output is a contamination map, in this case including a list (or other representation) 606 of spots detected on the surface of the wafer, the detected spots representing partitions of the wafer surface including local height variations. The list of detected spots may include data associated with one or more spots, including one or more of the following: the xy position of the spot on the wafer surface, the height of the spot, and the diameter of the spot. Figure 6 In an exemplary method, a list of detected spots is determined multiple times to determine contamination map data for multiple wafers.

[0080] Multiple contamination maps from multiple wafers are combined 608. This combination produces combined contamination map data (which may be combined focused spot data) that identifies common areas on the surfaces of the multiple wafers, these common areas exhibiting the effects of potential contamination. That is, in Figure 6 In the example shown, the combined contamination map data identifies common areas on the surfaces of multiple wafers that contain focus spotting errors. In one exemplary arrangement, the combined contamination map data includes the union of contamination map data from multiple wafers.

[0081] The combined contamination map data is compared with reference data 610 to determine whether contamination exists in the semiconductor manufacturing plant. In one example, the reference data may include height threshold data of the focused spots in the combined contamination map data. Contamination map data exhibiting focused spot errors greater than the threshold can be identified as a result of contamination.

[0082] Alternatively or additionally, the reference data may include die failure probabilities based at least in part on the combined contamination map data. That is, the reference data may include the probability of die failure in partitions of the wafer surface where the focused spots of the combined contamination map data exhibit a certain height. Therefore, a die loss map can be determined based on the combined contamination map data and the reference data. The die loss map can identify one or more dies manufactured on subsequent wafers with a high failure probability.

[0083] In other exemplary arrangements, the reference data may relate to the context (manufacturing plant context) of multiple semiconductor wafers. As used herein, the term "manufacturing plant context" includes data relating to one or more of the following: one or more products manufactured on a semiconductor wafer, layers of device structures manufactured on a semiconductor wafer, scanners on which device structures have been manufactured on semiconductor wafers, the time period in which a semiconductor wafer is at least partially processed in a semiconductor manufacturing plant, and / or the path taken by a semiconductor wafer through the semiconductor manufacturing plant. In a particular arrangement, the wafer path may include multiple processes, each of which may be performed by P ij This indicates that i is the type of process and j is the chamber of the manufacturing plant or the tool used to perform the process.

[0084] In an exemplary arrangement, the reference data may include data relating to the geometry of a tool or tool type in the manufacturing plant. The geometry of the tool or tool type may relate to any feature of the tool that introduces errors in the wafer's contamination mapping data when the wafer is contaminated. For example, the geometry of the tool or tool type may include the location of one or more wafer support features of the tool or tool type, or the location of a portion of the tool or tool type. These locations may include partitions or regions on the wafer surface, where, if focus spot errors occur, they can be attributed to effects related to wafer support features (e.g., contamination on those wafer support features).

[0085] The combined contamination map data can identify common areas on the surfaces of multiple wafers that exhibit focus spotting errors. If the common area corresponds to tool geometry data or tool type—for example, if the location or relative location of the common area corresponds to the location or relative location of one or more wafer support features—then the tool or tool type can be identified as a cause of contamination. In some arrangements, the geometry data may correspond to a specific portion of the tool or tool type, and that specific portion can be identified as a cause of contamination. Identification of the cause of contamination may include one or more of the following: tool or tool type, tool component, and the severity of contamination. As mentioned above, the severity of contamination may include die loss data.

[0086] In some exemplary methods and apparatuses, multiple semiconductor wafers for which contamination mapping data is determined can be selected to have at least a common manufacturing plant background. This increases the likelihood that the combined contamination mapping data will produce a common area on the surfaces of the multiple wafers exhibiting focus spot errors, thereby increasing the accuracy of determining a tool, tool type, or portion thereof that can be identified as causing contamination-based errors in a die manufactured on the wafer.

[0087] Therefore, the exemplary methods and apparatus can identify die loss data due to contamination of dies manufactured on wafers, and can identify tools, tool types, and / or chambers within a semiconductor manufacturing plant that may be the cause of die loss due to contamination. This can be used to schedule maintenance and / or cleaning of specific tools within the manufacturing plant based on the impact of specific tools on yield.

[0088] Figure 7This is a block diagram illustrating another exemplary method for identifying contamination in a semiconductor wafer fabrication plant. Since the actual production sequence has far more steps than shown, this diagram is a simplified representation of a portion of the production sequence. The method combines the following features: (i) contamination detection (spot detection) using a wafer height map obtained from horizontal sensor scans performed at different layers during wafer fabrication processing; (ii) contamination spot tracking to identify newly emerging spots and those remaining since the previous layer was scanned; and (iii) background linking to identify characteristics of the process steps taken and correlate these characteristics with dynamic changes in spots (i.e., spot appearance and spot disappearance). The purpose of background linking is to identify characteristics of steps that can explain spot appearance (e.g., a chamber in a given etching step may be acting as a source of contamination, making the corresponding wafer dirtier) or spot disappearance. At this point, it should be noted that contamination spots can occur for a variety of reasons. For example, some spots may be “chuck spots,” that is, spots also observed in wafers previously exposed in the same scanner and chuck, which may be caused by contamination adhering to the wafer stage, causing the spots to appear in the leveling data when a new wafer is clamped. Other spots may be “old spots” specific to the wafer, as they were observed in previous leveling measurements of the wafer. Other spots may be “new spots” specific to the wafer, as they were not observed in previous wafers exposed using the same scanner and chuck or in previous leveling measurements of the wafer. This particular type of spot is critical because, causally, these spots may have been introduced through steps that occurred after previous leveling measurements of the wafer. Similarly, spots may disappear for a variety of reasons. For example, if contamination adheres to the wafer support structure (wafer stage), the contamination can be removed and thus disappear due to a cleaning operation triggered on the device and designed to remove any such contamination that may have accumulated. Another example is contamination adhering to the back side of the wafer being processed and removed by a cleaning step performed on the wafer before the next stage of the photolithography process: in the case of using this "back-side cleaning" operation, there is no guarantee that all contamination will be removed.

[0089] like Figure 7As shown, steps A through G are steps in the processing of a semiconductor wafer fabrication plant. The steps shown occur sequentially as part of a production sequence and may include multiple steps after step G or before step A. Steps A, B, and C can be considered to constitute the first stage 701 of wafer processing, followed by a first horizontal sensor scan L1. Steps D and E constitute the second stage 702 of wafer processing, followed by a second horizontal sensor scan L2. Steps D and E may add one or more layers to the wafer fabrication plant. Steps F and G constitute the third stage 703 of wafer processing, followed by a third horizontal sensor scan L3. Steps F and G may add one or more additional layers to the wafer fabrication plant. Data from each horizontal sensor scan L1, L2, and L3 is analyzed by corresponding spot contamination detectors 704, 705, and 706 to determine corresponding contamination maps or spot maps 707, 708, and 709. Therefore, after the processing in steps A through C, a first spot map 707 of the layer (first layer) is determined. Following the additional processing in steps D and E, a second spot pattern 708 of the second layer is determined, and following further processing in steps F and G, a third spot pattern 709 of the third layer is determined. Note that for most semiconductor wafer fabrication processes, the first and second layers, as well as the second and third layers, are adjacent layers. However, in some cases, the processing of steps D, E, F, and G may include forming additional intervening layers that are not scanned by horizontal sensors.

[0090] The contamination map data determined from horizontal sensor scans L1, L2, and L3 are provided to a speckle dynamic tracker 710, which analyzes the data to identify which specks first appeared in each scan and which specks were retained from previous scans. When analyzing the speckle map 708 data from the second horizontal scan L2, the speckle dynamic tracker 710 compares the speckle map 708 data with the speckle map 707 data from the previous horizontal scan L1 to identify any specks that appeared but were not present in the previous layer, and to identify any specks retained from the previous layer. There may also be specks that appeared in previous layers but are no longer present in recent scans. The speckle dynamic tracker performs a similar analysis on the specks in the third speckle map 708 obtained from the third horizontal scan L3, compared to the speckle map 707 obtained from the second horizontal scan L2.

[0091] Note that if the first horizontal scan L1 is the first layer to be scanned, there is no scan of the previous layer to compare it with. However, for the first spot pattern 707 obtained from the first horizontal scan L1, and for scans L2 and L3 and any other scans, the spot dynamic tracker can use data 720 obtained from scans of the same layer of a previous wafer processed in the same manner using the same tool (e.g., the same scanner, chuck, etc.). Furthermore, the spot dynamic tracker can assign probabilities about whether contamination spots are likely to appear at a particular location due to contamination introduced during wafer fabrication processing. This can include assigning probabilities that spots belong to a particular category (e.g., "chuck spot," "old spot," "new spot" as described above), since any inference about a spot belonging to a category has a degree of uncertainty. For example, two spots that appear identical in consecutive horizontal scans of a given wafer could actually be two different spots that happen to appear at the same location (i.e., from two different sources of contamination).

[0092] As a result of the analysis by the speckle dynamic tracker 710, for each of the speckle maps 707, 708, 709 obtained from the horizontal scans L1, L2, L3, updated contamination maps 711, 712, 713 can be generated, which show only newly appearing specks or those retained from previously scanned layers.

[0093] Then, as Figure 7 As shown in 717, 718, and 719, background linking is performed on each updated contamination map 711, 712, and 713, respectively. The identified contamination spots are compared with background information on the processes and tools used in the processing steps prior to the last scan on which the contamination map data is based. Thus, for example, the updated contamination map 712 generated by the spot dynamic tracker 710 is based on contamination map 708, which is generated by the spot contamination detector 705 based on height map data provided by scan data from the horizontal sensor scan L2. The L2 horizontal sensor scan occurs after wafer fabrication processing steps D and E in processing stage 702. Background data related to processing steps D and E (such as...) is provided. Figure 7 As shown by line 715 in the diagram, background link analysis is performed on the contamination spot map 712. Similarly, background data from steps A, B, and C is provided in stage 701 (as shown by line 714) for background link analysis on the contamination spot map 711, and background data from steps F and G is provided in stage 703 (as shown by line 716) for background link analysis on the contamination spot map 713.

[0094] Background link identification process steps ( Figure 7The background link (A through G) can be used to identify characteristics of contamination spots (appearance and disappearance) that can be correlated with the dynamics of the contamination spots (appearance and disappearance) and can be based on knowledge of the wafer fabrication process acquired over time. The background link can be designed to easily detect which characteristics of a production step (e.g., the chamber ID for an etching step) are statistically correlated with changes in the number of newly introduced spots in the corresponding wafer. It can also indicate whether a specific characteristic is associated with a dirtier wafer: for example, whether the chamber ID with the strongest statistical signal is associated with a wafer having more new spots than the average, indicating that these chamber IDs somehow make the wafer “dirtier.” For example, this can be used to trigger actions to clean one or more identified chambers. The background link can output a ranking of the most relevant production steps to prioritize the cleaning of associated units. The background link can also be used for more general production / quality purposes: for example, to identify chambers with the strongest statistical link to “cleaner” wafers compared to the average, as these chambers can be used as reference chambers to track that production step. Background links can be associated with the probability that a spot appearing at any given location on a contamination map is the result of contamination introduced at a specific step in the manufacturing process and / or from a specific processing tool. Background links can analyze data from the entire wafer surface, or they can consider only data from one or more specific sub-regions of the wafer surface (e.g., such as...). Figure 5a and Figure 5b As shown, the wafer is supported on partitions of features such as pins or protrusions 404.

[0095] The information derived from background link analysis can then be used to trigger actions, such as adjusting or cleaning tools identified by the background links. Therefore, instead of relying on the final scan data of a fully processed wafer, the above reference... Figure 7 The described method can be used to identify sources of contamination in intermediate steps of a manufacturing plant, thereby enabling faster identification and correction of contamination sources.

[0096] Other embodiments are disclosed below in the numbered list of terms:

[0097] 1. A method for identifying contamination in a semiconductor manufacturing plant, the method comprising:

[0098] To determine contamination data of multiple semiconductor wafers clamped onto a wafer stage after processing in a semiconductor manufacturing plant;

[0099] The combined contamination map data is determined at least in part based on a combination of contamination map data from multiple semiconductor wafers; and

[0100] Compare the combined pollution map data with the reference data.

[0101] The reference data includes one or more values ​​for combined contamination map data, indicating contamination in one or more tools in a semiconductor manufacturing plant.

[0102] 2. The method according to Clause 1, wherein the pollution map data is determined based on data obtained from the leveling sensor.

[0103] 3. The method according to Clause 1 or 2, wherein the contamination map data includes focused spot data.

[0104] 4. The method according to any one of Clauses 1 to 3, wherein the contamination map data is determined based on the application of a blot detection algorithm to wafer height data.

[0105] 5. The method according to Clause 4, wherein the wafer height data includes wafer height data fitted with a continuous surface.

[0106] 6. The method according to any of the preceding clauses, wherein determining the combined contamination map data comprises: determining the union of contamination map data of a plurality of semiconductor wafers.

[0107] 7. The method according to any of the preceding clauses, wherein the reference data includes data indicating a fault in one or more dies in one or more subsequent semiconductor wafers being processed in a semiconductor manufacturing plant.

[0108] 8. The method according to Clause 7, wherein the reference data includes a focus error threshold, and wherein combined contamination map data above the focus error threshold indicates a failure of one or more dies in one or more subsequent semiconductor wafers.

[0109] 9. The method according to any of the preceding clauses, wherein the reference data includes, at least in part, the die failure probability based on the combined contamination map data.

[0110] 10. The method according to any one of Clauses 7 to 9 further comprises: determining a die loss map of one or more dies of a subsequent semiconductor wafer that are identified as having a failure risk based on the combined contamination map data and a focus error threshold.

[0111] 11. The method according to any of the preceding clauses, wherein the reference data includes geometric data relating to one or more tools in a semiconductor manufacturing plant.

[0112] 12. The method according to Clause 11, wherein the geometry data includes the location of one or more wafer support features of one or more tools.

[0113] 13. The method according to Clause 12, wherein the location of one or more wafer support features comprises a polygon over a region on the surface of a plurality of semiconductor wafers.

[0114] 14. The method according to any one of Clauses 11 to 13, based on a comparison of combined contamination map data and geometry data, to determine one or more tool types in a semiconductor manufacturing plant as potential contamination types.

[0115] 15. The method according to any one of Clauses 11 to 14 further includes: determining one or more tools as potential sources of contamination in a semiconductor manufacturing plant based on a comparison of combined contamination map data with geometric data.

[0116] 16. The method according to any one of Clauses 11 to 15 further comprises: determining one or more parts of one or more tools in a semiconductor manufacturing plant as potential sources of contamination based on a comparison of combined contamination mapping data with geometric data.

[0117] 17. The method according to any of the preceding clauses, wherein the plurality of wafers includes wafers having at least a portion of a public manufacturing plant background.

[0118] 18. The method according to Clause 17, wherein the manufacturing plant background includes one or more of the following: a product manufactured on a semiconductor wafer, a device structure layer manufactured on a semiconductor wafer, a scanner on which a device structure has been manufactured on a semiconductor wafer, the time period in which the semiconductor wafer is at least partially processed in the semiconductor manufacturing plant and / or the path taken by the semiconductor wafer through the semiconductor manufacturing plant.

[0119] 19. A computer program comprising instructions that, when executed on at least one processor, cause at least one processor control device to perform the method according to any one of clauses 1 to 18.

[0120] 20. A carrier comprising a computer program as described in Clause 19, wherein the carrier is one of the following: an electronic signal, an optical signal, a radio signal, or a non-transitory computer-readable storage medium.

[0121] 21. An apparatus for identifying contamination in a semiconductor manufacturing plant, the apparatus comprising a computer processor configured to execute computer program code to perform the following methods:

[0122] To determine contamination data of multiple semiconductor wafers clamped onto a wafer stage after processing in a semiconductor manufacturing plant;

[0123] The combined contamination map data is determined at least in part based on a combination of contamination map data from multiple semiconductor wafers; and

[0124] Compare the combined pollution map data with the reference data.

[0125] The reference data includes one or more values ​​for combined contamination map data, indicating contamination in one or more tools in a semiconductor manufacturing plant.

[0126] 22. A photolithography apparatus, comprising the apparatus described in Clause 21.

[0127] 23. A photolithography unit comprising the photolithography apparatus as described in Clause 22.

[0128] 24. The method according to any one of Clauses 1 to 17, wherein the reference data includes data associated with previous processing stages and / or with different wafer manufacturing plants.

[0129] 25. A method for identifying contamination in a semiconductor wafer manufacturing plant, the method comprising:

[0130] Identify contamination map data obtained after processing layers of a semiconductor wafer;

[0131] Compare the identified contamination map data with previously obtained contamination maps related to the wafer manufacturing plant to identify contamination spots that have appeared since the previous maps, remain the same as the previous maps, or have disappeared since the previous maps; and

[0132] The identification of contamination spots is associated with steps in the processing of the wafer manufacturing plant.

[0133] 26. The method according to Clause 25, wherein the pollution map data is determined based on data obtained from the leveling sensor.

[0134] 27. The method according to Clause 25 or Clause 26, wherein the previously obtained contamination map is obtained after processing a previous layer in the same wafer fabrication plant.

[0135] 28. The method according to Clause 25 or Clause 26, wherein the previously obtained contamination map was obtained after processing the same layer in another wafer fabrication plant.

[0136] 29. The method according to any one of Clauses 25 to 28, wherein the comparison step comprises: assigning a probability about whether the identified contamination spot is the result of contamination introduced during processing in the wafer fabrication plant.

[0137] 30. As described in Clause 29, the assignment probability is based on the probability that a spot belongs to a certain category.

[0138] 31. The method described in Clause 29, wherein the category to which the spot may belong includes one or more of the following: chuck spot, old spot, and new spot.

[0139] 32. The method according to Clause 29, wherein the probability is assigned based on the level of uncertainty regarding whether the identified spot is a new spot or a previously existing spot.

[0140] 33. The method according to any one of Clauses 25 to 32, wherein the identification and linking of contamination spots are performed on predetermined sub-regions of the wafer.

[0141] 34. The method according to any one of Clauses 25 to 33, wherein the previously obtained contamination map related to the wafer manufacturing plant is related to a common manufacturing plant background, wherein the manufacturing plant background includes one or more of the following: products manufactured on semiconductor wafers, device structure layers manufactured on semiconductor wafers, scanners on which device structures have been manufactured on semiconductor wafers, the time period in which the semiconductor wafer is at least partially processed in the semiconductor manufacturing plant and / or the path taken by the semiconductor wafer through the semiconductor manufacturing plant.

[0142] A computer program can be configured to provide any of the methods described above. The computer program can be provided on a computer-readable medium. The computer program can be a computer program product. This product may include a non-transitory computer-usable storage medium. The computer program product may have computer-readable program code contained in the medium, which is configured to perform the methods. The computer program product can be configured to cause at least one processor to perform some or all of the methods.

[0143] This document describes various methods and apparatuses with reference to block diagrams or flowcharts of computer-implemented methods, apparatuses (systems and / or devices) and / or computer program products. It should be understood that blocks in block diagrams and / or flowcharts, as well as combinations of blocks in block diagrams and / or flowcharts, can be implemented by computer program instructions executed by one or more computer circuits. These computer program instructions can be provided to processor circuits of general-purpose computer circuits, special-purpose computer circuits, and / or other programmable data processing circuits to produce a machine that causes instructions executed by the processor of a computer and / or other programmable data processing device, transformation and control transistors, values ​​stored in memory locations, and other hardware components within such circuit systems to implement the functions / actions specified in the block diagram and / or flowchart blocks, thereby creating means (functions) and / or structures for implementing the functions / actions specified in the block diagram and / or flowchart blocks.

[0144] Computer program instructions may also be stored in a computer-readable medium that can instruct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in block diagram blocks and / or flowchart blocks.

[0145] Tangible, non-transitory computer-readable media can include electronic, magnetic, optical, electromagnetic, or semiconductor data storage systems, apparatuses, or devices. More specific examples of computer-readable media will include the following: portable computer hard disks, random access memory (RAM) circuitry, read-only memory (ROM) circuitry, erasable programmable read-only memory (EPROM or flash memory) circuitry, portable optical disc read-only memory (CD-ROM), and portable digital video disc read-only memory (DVD / Blu-ray).

[0146] Computer program instructions may also be loaded onto a computer and / or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer and / or other programmable apparatus, thereby producing a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions / actions specified in the block diagram and / or flowchart blocks.

[0147] Therefore, the present invention can be implemented as hardware and / or software (including firmware, resident software, microcode, etc.) running on a processor, which can be collectively referred to as a "circuit system", "module" or a variant thereof.

[0148] It should also be noted that in some alternative implementations, the functions / actions indicated in the boxes may not appear in the order shown in the flowchart. For example, depending on the functions / actions involved, two consecutively shown boxes may actually be executed substantially simultaneously, or sometimes in reverse order. Moreover, the functionality of a given box in the flowchart and / or block diagram can be divided into multiple boxes, and / or the functionality of two or more boxes in the flowchart and / or block diagram can be at least partially integrated. Finally, additional boxes may be added / inserted between the shown boxes.

[0149] The apparatus can be configured to perform any of the methods disclosed herein. Specifically, the photolithography apparatus can be configured to perform any of the methods disclosed herein. Additionally, a photolithography unit may include such a photolithography apparatus.

[0150] Those skilled in the art can conceive of other embodiments without departing from the scope of the appended claims.

Claims

1. A method for identifying contamination in a semiconductor manufacturing plant, the method comprising: To determine contamination map data of multiple semiconductor wafers clamped onto a wafer stage after they have been processed in the semiconductor manufacturing plant; The combined contamination map data is determined at least in part based on a combination of the contamination map data from the plurality of semiconductor wafers; as well as The combined contamination map data is compared with reference data, wherein the reference data includes one or more values ​​for the combined contamination map data indicating contamination in one or more tools in the semiconductor manufacturing plant and data associated with previous processing stages.

2. The method of claim 1, wherein the pollution map data is determined based on data obtained from a leveling sensor.

3. The method according to claim 1 or 2, wherein the contamination map data includes focused spot data.

4. The method of claim 1, wherein the contamination map data is determined based on a blot detection algorithm applied to wafer height data.

5. The method of claim 1, wherein determining the combined contamination map data comprises: Determine the union of the contamination map data of the plurality of semiconductor wafers.

6. The method of claim 1, wherein the reference data includes data indicating a fault in one or more dies in one or more subsequent semiconductor wafers being processed in the semiconductor manufacturing plant.

7. The method of claim 6, wherein the reference data includes a focus error threshold, and wherein combined contamination map data above the focus error threshold indicates a fault in the one or more dies in the one or more subsequent semiconductor wafers.

8. The method of claim 1, wherein the reference data includes geometric data relating to one or more tools in the semiconductor manufacturing plant.

9. The method of claim 8, wherein the geometry data includes the location of one or more wafer support features of the one or more tools.

10. The method of claim 9, wherein the location of the one or more wafer support features comprises a polygon on a region of the surface of the plurality of semiconductor wafers.

11. The method of claim 8, further comprising: Based on a comparison of the combined contamination map data with the geometry data of the one or more tools, the one or more tools or tool types in the semiconductor manufacturing plant are identified as potential sources of contamination.

12. The method of claim 1, wherein the plurality of wafers includes wafers having at least a portion of a common manufacturing plant background, wherein the manufacturing plant background includes one or more of the following: products manufactured on the semiconductor wafer, device structure layers manufactured on the semiconductor wafer, scanners on which device structures have been manufactured on the semiconductor wafer, the time period in which the semiconductor wafer is at least partially processed in the semiconductor manufacturing plant and / or the path taken by the semiconductor wafer through the semiconductor manufacturing plant.

13. A computer program comprising instructions that, when executed on at least one processor, cause the at least one processor control device to perform the method according to any one of claims 1 to 12.

14. A carrier comprising the computer program of claim 13, wherein the carrier is one of the following: an electronic signal, an optical signal, a radio signal, or a non-transitory computer-readable storage medium.

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