Bitstream transformation in parallel data interfaces

Abstract

A circuit (102) includes: a parallel data interface (108); and a conversion control circuit system (1101) coupled to the parallel data interface (108). The conversion control circuit system (1101) is configured to: receive an input bitstream sample (S(m)); determine a bit transformation mode (510) of the input bitstream sample (S(m)) according to a target criterion; and generate an output bitstream symbol (S'(m)) from the input bitstream sample (S(m)) and the bit transformation mode (510), wherein the output bitstream symbol (S'(m)) has more bits than the input bitstream sample (S(m)).

Description

Technical Field Background Technology

[0002] With the development of new electronic devices and advancements in integrated circuit (IC) technology, new IC products have been commercialized. An example IC product for use in an electronic device includes one or more circuits configured to communicate via a parallel data interface. The parallel data interface of an IC can be used for communication between different circuits or chiplets within the IC, or between different ICs (chips). Problems caused by parallel data interfaces include: power supply ripple may be introduced into sensitive subsystems of the IC due to transitions on associated parallel data interface channels; the power consumption of the IC increases with the number of transitions on the parallel data interface channels; and simultaneous switching associated with transitions on parallel data interface channels can negatively impact output driver performance.

[0003] An example IC with a parallel data interface includes a radio frequency (RF) sampling transceiver with an analog front-end (AFE) or other components sensitive to power supply ripple. In one example, the parallel data interface couples the AFE to a baseband processor, such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this example, the parallel data interface transmits complex baseband I / Q samples between the AFE and the baseband processor by mapping samples to a parallel bit stream (e.g., as 16-bit input words or symbols) and transmitting the mapped input words through the parallel data interface channel. As an example, the parallel data interface can transform 1 gigabits per second (Gsps) of I / Q samples (e.g., each sample corresponding to a 16-bit symbol or other multi-bit symbol) into a 16-bit parallel stream at 2 gigabits per second (GBPS). In this case, the AFE is sensitive to power supply ripple caused by data-dependent transitions in the complementary metal-oxide-semiconductor (CMOS) switches of the parallel data interface channel. Furthermore, the power consumption of the parallel data interface increases with the switching factor (i.e., the average number of transitions).

[0004] A common approach to reducing power supply ripple is to use differential traces instead of single-ended traces for each parallel data interface channel. This partially mitigates power supply ripple because a transition in one trace of a differential pair (e.g., from supply voltage (VDD) to ground) is accompanied by the opposite transition on the other trace. However, differential traces require twice the number of traces needed (e.g., 512 channels instead of 256 for 8 receiver channels), which is impractical given the large number of parallel interface channels to be supported. Another common approach introduces additional logic to perform virtual transitions (e.g., from ground to VDD) on each clock edge, which eliminates switching activity in each interface channel. However, this virtual transition technique may not adequately mitigate power supply ripple because the virtual transitions provided by the additional logic do not propagate to the port and the trace load is not matched. Furthermore, virtual transition techniques increase power consumption. Summary of the Invention

[0005] In one example embodiment, a circuit includes: a parallel data interface; and a conversion control circuit system coupled to the parallel data interface. The conversion control circuit system is configured to: receive an input bitstream sample; determine a bit transformation mode of the input bitstream sample according to a target criterion; and generate an output bitstream symbol from the input bitstream sample and the bit transformation mode, wherein the output bitstream symbol has more bits than the input bitstream sample.

[0006] In another exemplary embodiment, a system includes: a first electronic circuit; and a parallel data interface channel coupled to the first electronic circuit and adapted to be coupled to a second electronic circuit. The first electronic circuit is configured to: receive an input bitstream sample; determine a bit transformation mode of the input bitstream sample according to a target criterion; generate an output bitstream symbol from the input bitstream sample and the bit transformation mode, wherein the output bitstream symbol has more bits than the input bitstream sample; and provide the output bitstream symbol to the parallel data interface channel.

[0007] In yet another embodiment, a method includes: receiving an input bitstream sample; determining a bit transformation mode of the input bitstream sample according to a target criterion; generating an output bitstream symbol from the input bitstream sample and the bit transformation mode, wherein the output bitstream symbol has more bits than the input bitstream sample; and providing the output bitstream symbol to a parallel data interface channel. Attached Figure Description

[0008] Figure 1 This is a block diagram of a system according to an example embodiment.

[0009] Figure 2 is a graph showing how the bit transition distribution of conventional techniques varies with the relative frequency of the parallel data interface.

[0010] Figure 3 This is a block diagram of a system according to an example embodiment.

[0011] Figure 4 This is a block diagram of a transmitter with a switching control circuit system according to an example embodiment.

[0012] Figure 5 This is a block diagram of a bitstream converter according to an example embodiment.

[0013] Figure 6 This is a block diagram of a conversion optimizer according to an example embodiment.

[0014] Figure 7 This is a block diagram of an inverted bitstream converter according to an example embodiment.

[0015] Figure 8 This is a block diagram of a receiver according to an example embodiment.

[0016] Figure 9 It compares the original bit transitions with the coded bit transitions caused by the bitstream converter, based on a graph showing the bit transition distribution as a function of relative frequency in an example embodiment.

[0017] Figure 10 It is a table of bit transformation patterns according to an example embodiment.

[0018] Figure 11 The original bit transitions and the coded bit transitions caused by the bitstream converter are compared, based on a graph showing how the bit transition distribution varies with relative frequency according to another example embodiment.

[0019] Figure 12A and Figure 12B This is a block diagram of a transmitter with a parallelized implementation of a switching control circuitry system according to an example embodiment.

[0020] Figure 13 This is a block diagram of a serialized implementation of a conversion control circuit system according to an example embodiment.

[0021] Figure 14 This is a block diagram of another parallelized implementation of a conversion control circuit system according to an example embodiment.

[0022] Figure 15 This is a block diagram of a modified conversion optimizer based on an example embodiment.

[0023] Figure 16 This is a block diagram of a conversion control circuit system according to another example embodiment.

[0024] Figure 17 This is a flowchart of a bit transition control method according to an example embodiment.

[0025] Figure 18 It is a table of bit transformation patterns according to another example embodiment.

[0026] Figure 19 It is a table of bit transformation patterns according to yet another example embodiment.

[0027] Figure 20 The original bits are compared with the transformed bits due to the conversion control circuitry system of the parallel data interface, based on a spectrum of bit stream switching (amplitude varies with frequency) of an example embodiment.

[0028] Figure 21 The original bits are compared with the transformed bits caused by the conversion control circuitry system of the parallel data interface, based on a spectrum of bit stream switching (amplitude varies with frequency) of an example embodiment.

[0029] The same reference numerals (or other reference numerals) are used in the accompanying drawings to indicate the same or similar (structural and / or functional) features. Detailed Implementation

[0030] Some example embodiments include a conversion control circuitry for use with a parallel data interface between electronic circuits (e.g., integrated circuits (ICs), chiplets, multi-chip modules (MCMs), system-on-a-chip (SoCs), circuit systems on printed circuit boards (PCBs), combinations thereof, etc.). The conversion control circuitry is configured to mitigate unwanted power ripple and / or power consumption caused by bit transitions (changing bit values ​​from "0" to "1" or from "1" to "0") on the parallel data interface. More specifically, power ripple is caused by variations in the number of bit transitions for each output symbol transmitted via the parallel data interface. Meanwhile, power consumption increases with the total number of bit transitions for all output symbols transmitted by the parallel data interface. In one example embodiment, the parallel data interface and the conversion control circuitry are used for communication between a first electronic circuit and a second electronic circuit. In different example embodiments, the first and second electronic circuits differ. Example first and / or second electronic circuits include baseband processors, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), memory, data samplers, transceivers, peripheral devices, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog front-ends (AFEs), and / or other circuits with parallel data interfaces.

[0031] In one example embodiment, the conversion control circuitry is configured to reduce bit transitions on the parallel data interface to mitigate power supply ripple for components of the first and / or second electronic circuits relative to electronic circuits having a parallel data interface but lacking a conversion control circuitry. In other example embodiments, the conversion control circuitry is configured to reduce the total number of bit transitions on the parallel data interface to reduce power consumption of the first and / or second electronic circuits relative to electronic circuits without a conversion control circuitry.

[0032] In some example embodiments, the conversion control circuitry uses additional parallel data interface channels (e.g., nk additional interface channels) to transmit a k-bit word as an n-bit symbol, where k is a first integer and n is a second larger integer greater than k. In one example, n = 20, k = 16, where n parallel data interface channels are used to transmit a k-bit word using n-bit symbols. In this example, there are 4 (nk) additional parallel data interface channels, which allows the conversion control circuitry to flexibly optimize bit transitions on the parallel data interfaces to either reduce the number of bit transition variations on the parallel data interface channels or reduce the total number of bit transitions on the parallel data interface channels.

[0033] In some example embodiments, the conversion control circuitry includes: a bitstream converter configured to map a k-bit input word to an n-bit output symbol; and a conversion optimizer configured to select an optimal bitstream conversion pattern based on a target criterion (e.g., reducing bitstream conversion variations and / or reducing the total number of bitstream conversions). In one example embodiment, the optimal bitstream conversion pattern is based on the previously transmitted n-bit output symbol and the current k-bit input word. On the receiver side, a complementary conversion control circuitry (relative to the transmitter-side circuitry) receives the n-bit symbol and uses an inverting bitstream converter to recover each k-bit input word.

[0034] In some example implementations, the transformation optimizer determines the bit transformation pattern based on a quality factor approach. As used herein, a "quality factor" refers to comparing the performance of multiple options against a target criterion (e.g., the minimum change in the number of bit transformations for the output symbol due to the application of the bit transformation pattern, or the minimum total number of bit transformations for the output symbol due to the application of the bit transformation pattern) and selecting the option with the best performance. In one example, the quality factor uses a target criterion to minimize the total number of bit transformations for the parallel data interface. In another example, the quality factor uses a target criterion to minimize the change in bit transformations (the same number of transformations for each n-bit output symbol).

[0035] In some example embodiments, the conversion control circuitry prepares output symbols for parallel data transmission between first and second electronic circuits, with one or more of the following design goals: minimizing the number of bit transitions on the parallel data interface to reduce power consumption; maintaining a constant number of bit transitions on the parallel data interface (reducing the standard deviation of bit transitions) to reduce power supply ripple; ensuring reasonable encoding and decoding complexity; and supporting error detection (e.g., flagging errors in the data stream) as much as possible. By maintaining a constant number of bit transitions (or reducing bit transition variations), the conversion control circuitry reduces the coupling of power supply ripple to the analog subsystem and / or other sensitive subsystems of the IC by reducing variations in switching activity (e.g., switching activity of high-current complementary metal-oxide-semiconductor (CMOS) switches due to conversion). Other benefits of the conversion control circuitry may include: better analog performance in terms of signal-to-noise ratio (SNR) and parasitic noise reduction; reduced power supply interference; and reduced synchronous switching noise (SSN).

[0036] The described conversion control circuitry options and related operations reduce the variation in the number of bit transitions on the parallel data interface for each n-bit output symbol at the cost of some additional channels. Using the conversion control circuitry, a trade-off can be struck between reducing the variation in the number of bit transitions and reducing the total number of transitions (i.e., reducing noise interference or power ripple at the cost of increased power consumption). In some example embodiments, an additional parity bit on the parallel data interface is used in conjunction with the conversion control circuitry to reduce the chance of undetected data corruption. Furthermore, different versions of the described encoding algorithm can be developed using different conversion modes (sometimes referred to herein as “masks”) and / or selection criteria for bit transition targets at the transmitter. Regardless of the specific encoding algorithm used, the receiver implementation is simple, involving only a demasking operation to recover the original input word.

[0037] In the accompanying drawings, blocks are sometimes used to describe circuits, components, or related operations. In different embodiments, these blocks can be combined or further subdivided without altering the intended function described. In a non-limiting sense, such blocks can represent hardware, firmware, and / or software. In some example embodiments, blocks represent instructions stored in memory and executable by a processor to perform the described function. The described operations can be implemented using different combinations of logic, hardware, firmware, and / or software, as needed.

[0038] Figure 1 This is a block diagram of a system 100 according to an example embodiment. As shown, system 100 includes a first electronic circuit 102 (e.g., an IC, chiplet, MCM, SoC, or circuitry on a PCB) that communicates with a second electronic device (e.g., an IC, chiplet, MCM, SoC, or circuitry on a PCB). Figure 1 In one example, the first electronic circuit 102 includes an RF sampling transceiver 104. In other example embodiments, the first circuit includes a baseband processor, FPGA, ASIC, memory, data sampler, ADC, DAC, peripheral devices, AFE, and / or other circuitry with a parallel data interface.

[0039] RF sampling transceiver 104 includes an AFE 106 and a parallel data interface 108. The parallel data interface 108 includes hardware, firmware, and / or software configured to: prepare input data for transmission via parallel data interface channel 116; and / or recover data from symbols received from parallel data interface channel 116. RF sampling transceiver 104 also includes an input bitstream source 115 coupled to the parallel data interface 108 and configured to provide an input bitstream or associated samples to a conversion control circuitry system 110 of the parallel data interface 108. Without limitation to other example embodiments, the input bitstream source 115 may provide complex baseband I / Q samples from the AFE 106 to the conversion control circuitry system 110 for transmission to a second electronic circuit (e.g., a baseband processor). In different example embodiments, the input bitstream source 115 may be a serial communication interface or a parallel communication interface between the AFE 106 and the parallel data interface 108. In some example embodiments, the first electronic circuitry 102 communicates with one or more wireless transceivers (not shown) that provide data as analog signals to the RF sampling transceiver 104. The RF sampling transceiver 104 converts the received analog signals into digital form, causing the input bitstream to be buffered, stored, and / or otherwise provided by the input bitstream source 115 to the conversion control circuitry system 110. As described herein, samples of the input bitstream are converted into output symbols according to a bit transformation mode and transmitted to the second electronic circuitry 122 via the parallel data interface channel 116.

[0040] The second electronic circuit 122 is configured to recover input bitstream samples from output symbols. The recovered input bitstream samples are appropriately combined and then processed, analyzed, stored, and / or forwarded by the second electronic circuit 122. In different example embodiments, the second electronic circuit 122 may generate an input bitstream (correlated and / or uncorrelated with the recovered input bitstream) to be transmitted to the first electronic circuit 122 via parallel data interface 128 and parallel data interface channel 116. The first electronic circuit 102 is configured to recover the input bitstream from the second electronic circuit 122, appropriately prepare the recovered input bitstream for wireless transmission, and transmit the input bitstream as an analog signal to other wireless transceivers. In other example embodiments, the first electronic circuit 102 and the second electronic circuit 122 differ from the given RF transceiver and baseband processor examples.

[0041] The parallel data interface 108 is coupled to or includes a conversion control circuitry system 110, which operates to: mitigate power ripple due to variations in the number of bit transitions on the parallel data interface 108, relative to electronic circuitry having a parallel data interface but without the conversion control circuitry system 110; and / or reduce power consumption due to bit transitions on the parallel data interface 108, relative to electronic circuitry having a parallel data interface but without the conversion control circuitry system 110. Figure 1 In one example, the conversion control circuitry 110 includes a bitstream converter 112 (labeled “BST”) configured to prepare output symbols for parallel data transfer operations. In one example embodiment, each output symbol is prepared by an input word and a bit transformation pattern. In some example embodiments, the conversion control circuitry 110 also includes an inverse bitstream converter 114 (labeled “IBST”) to recover the input word from the output symbols received via the parallel data interface channel 116. In one example, the inverse bitstream converter 114: receives or determines the bit transformation pattern used by the bitstream converter 132 of the second electronic circuitry 122; and performs an inverse transformation using the bit transformation pattern to recover the input word from the received output symbol. As described herein, the conversion control circuitry 110 may include other components, such as circuitry supporting additional parallel data interface channels (nk additional interface channels in addition to k interface channels) for transmitting n-bit output symbols, a conversion optimizer, a delay block, and / or other components.

[0042] exist Figure 1 In one example, the first electronic circuit 102 is coupled to the second electronic circuit 122 via a parallel data interface channel 116. As shown, the second electronic circuit 122 may include a processor 124 (e.g., a baseband processor) and a parallel data interface 128 (in some example embodiments, it is implemented as the same as or similar to the parallel data interface 108). In other example embodiments, the second electronic circuit 122 includes an FPGA, ASIC, memory, data sampler, transceiver, peripheral device, ADC, DAC, AFE, and / or other circuitry with a parallel data interface. As shown, the second electronic circuit 122 also includes an input bitstream source 135 coupled to the conversion control circuitry system 130 and configured to provide an input bitstream or associated samples to the conversion control circuitry system 130. Without limiting other example embodiments, the input bitstream source 135 may provide an input bitstream generated by the processor 124 to the conversion control circuitry system 130 for transmission to the first electronic circuit 102. The input bitstream can be generated by the processor 124, for example, in response to instructions stored in memory and executed by the processor 124 and / or in response to data received from the first electronic device 102. In different example embodiments, the input bitstream source 135 can be a serial communication interface or a parallel communication interface between the processor 124 and the conversion control circuitry system 130.

[0043] Processor 124 can be any processing system or subsystem configured to process data transmitted to and from AFE 106. In some example embodiments, processor 124 is a baseband processor, FPGA, or ASIC. The division between the hardware and firmware used for processor 124 may differ in different example embodiments.

[0044] The parallel data interface 128 of the second electronic circuit 122 includes hardware, firmware, and / or software configured to: prepare input data for transmission via the parallel data interface channel 116; and / or recover symbolic data received from the parallel data interface channel 116. Figure 1 In the example, parallel data interface 128 is coupled to or includes conversion control circuitry 130. Conversion control circuitry 130 includes a bitstream converter 132 configured to encode the input word with additional bits to provide output symbols (encoded input words) to parallel data interface line 116. In some example embodiments, conversion control circuitry 130 also includes an inverse bitstream converter 134 configured to decode the output symbols received from parallel data interface channel 116 and recover the associated input word. As described herein, conversion control circuitry 130 may include other components, such as circuitry supporting additional parallel data interface channels (nk additional interface channels and k interface channels) to transmit n-bit output symbols, conversion optimizers, delay blocks, and / or other components.

[0045] In some example embodiments, parallel data transmission is unidirectional. As an example, if unidirectional parallel data transmission is used, the conversion control circuitry 110 may include only bitstream converter 112 (omitting the inverting bitstream converter 114), while the conversion control circuitry 130 may include only the inverting bitstream converter 134 (omitting the bitstream converter 132). In another example, the conversion control circuitry 110 may include only the inverting bitstream converter 114 (omitting the bitstream converter 112), while the conversion control circuitry 130 may include only the bitstream converter 132 (omitting the bitstream converter 132). In other example embodiments, parallel data transmission is bidirectional, with each electronic circuit including a corresponding bitstream converter and an inverting bitstream converter, such as... Figure 1 As shown in the image.

[0046] The RF sampling transceiver 104 of the first electronic circuit 102 can be used in multiple wireless applications (e.g., wireless communication or radar) to support high channel counts (e.g., 8 transmitter and 8 receiver chains) and wide bandwidth (e.g., 1.2 GHz) operation. In one example, the RF sampling transceiver 104 samples the RF signal using a high-performance data converter with multiple gigabits per second (Gsps). Example data converters include 14-bit, 4 Gsps analog-to-digital converters (ADCs) and / or 12 Gsps digital-to-analog converters (DACs). These example embodiments using converters with high sampling rates allow the AFE 106 to operate without a mixer. Large amounts of data are transmitted between the RF sampling integrated transceiver 104 and the processor 124 (e.g., an FPGA or ASIC) via parallel data interfaces 108 and 128. In one example embodiment, the system 100 transmits data for 8 receiver (RX) channels using 16-bit, 1 Gsps I / Q samples (~800 MHz bandwidth or BW) and requires an equivalent data interface of 256 gigabits per second (GBPS). System throughput is proportional to the sampling rate (BW of interest), the number of bits per sample (real / imaginary), and the number of channels. In an N-channel system, there will be N data streams to be sent / received. In different example embodiments, the number of channels, sampling rate, and / or BW can vary.

[0047] In conventional methods, a serializer / deserializer (SerDes) interface (e.g., JESD 204B / C) is used with the RF sampling transceiver 104 and processor 124, but these SerDes interfaces consume significant power (e.g., several watts). Instead of a SerDes interface, the described first sub-circuit 102 and second electronic circuit 122 use corresponding conversion control circuit systems 110 and 130 to perform parallel data transmission of output symbols, where the output symbols include input words with additional bits or encoding to improve conversion performance objectives (e.g., reduced variation in the number of bit transitions for output symbols and / or reduced total number of bit transitions for output symbols). In some example embodiments, each conversion control circuit system 110 and / or conversion control circuit system 130 is configured to encode the input words (generating output symbols) for parallel data transmission by: obtaining a k-bit input word (e.g., a 16-bit input word); and mapping each k-bit input word to a corresponding n-bit output symbol (e.g., a 20-bit output symbol). This process results in nk redundant bits (e.g., 4 redundant bits if k = 16 and n = 20), where each consecutively transmitted output symbol has the target number of transitions. Without a transition control circuitry, transmitting an unencoded k-bit word results in an average of k / 2 bit transitions on the parallel data interface, and the standard deviation will be large. With a transition control circuitry (e.g., transition control circuitry 110 or 130), one option is to reduce the standard deviation of the bit transitions in the parallel data transmission, where the input word is encoded as an output symbol to achieve the target number of transitions on the parallel data interface (e.g., parallel data interface 108 or 128). Another option is to reduce the total number of bit transitions in the parallel data transmission, where the input word is encoded as an output symbol to achieve a minimum number of bit transitions on the parallel data interface (e.g., parallel data interface 108 or 128). To perform the parallel data recovery operation, transition control circuitry 110 or 130 performs a reverse operation (reversing the encoding process) to decode the received output symbol and recover the expected input word.

[0048] Figure 2 is a graph 200 showing the distribution of bit transitions as a function of the relative frequency of a parallel data interface, based on conventional techniques. For Figure 200, it is assumed that there is no parallel data interface with a system lacking transition control circuitry. As shown, Figure 200 illustrates a widely distributed number of bit transitions, with eight transitions as the average number of transitions. As discussed herein, a large number of bit transitions and large variations (expansion) in the number of transitions are undesirable for parallel data interfaces. More specifically, increasing the number of transitions increases power consumption, while increasing the variation in the number of bit transitions increases power supply ripple.

[0049] Figure 3 This is a block diagram of an IC system 300 (an example of system 100) according to an example embodiment. Figure 3In the IC system 300, there is a first electronic circuit 102A that communicates via a parallel data interface channel 306. Figure 1 Example of the first electronic circuit 102) and the second electronic circuit 122A ( Figure 1 Example of the second electronic circuit 122 in the example) is an MCM or IC.

[0050] In some example embodiments, the first electronic circuit 102A includes an RF sampling transceiver (e.g., Figure 1 The RF sampling transceiver 104 in the figure. In other example embodiments, the first electronic circuit 102A includes a baseband processor, FPGA, ASIC, memory, data sampler, peripheral devices, AFE, ADC, DAC and / or another circuit having a parallel data interface. As shown, the first electronic circuit 102A includes a parallel data interface 108A ( Figure 1 Example of parallel data interface 108) and conversion control circuit system 110A ( Figure 1 Example of the conversion control circuitry system 110 in [the example]. In some example embodiments, the second electronic circuitry 122A includes a processor (e.g., [example of the processor]). Figure 1 The processor 124 in the memory. In other example embodiments, the second electronic circuit 122A includes an FPGA, ASIC, memory, data sampler, peripheral devices, transceiver, AFE, ADC, DAC and / or another circuit having a parallel data interface. As shown, the second electronic device 122A includes a parallel data interface 128A (in the processor 124 in the memory). Figure 1 Example of parallel data interface 128) and conversion control circuit system 130A ( Figure 1 Example of the conversion control circuit system 130 in the example). Although the first electronic circuit 102A and the second electronic circuit 122A are shown side by side, it should be understood that other arrangements are possible (e.g., a vertical arrangement of the first electronic circuit 102A above or below the second electronic circuit 122A, or separate ICs for the first electronic circuit 102A and the second electronic circuit 122A).

[0051] During operation of IC system 300, increased switching activity associated with parallel data interface channel 306 results in higher power consumption. Furthermore, the increased variation in switching activity associated with parallel data interface channel 306 leads to higher power supply ripple, which may propagate (e.g., via RF / analog coupling as multiplication / addition spurious noise) to the first 102A or the second circuit 122A, or other components of IC system 300. In some example embodiments, this power supply ripple is due to the switching activity of high-current CMOS switches for bit transitions (from 0 to 1, or from 1 to 0) on the parallel data interface channel. In other words, as switching activity changes on the parallel data interface channel, current draw on the power supply changes, causing the power supply voltage to shift up and down. As current draw due to bit transitions increases, the power supply voltage decreases. As current draw due to bit transitions decreases, the power supply voltage increases. This change in power supply voltage over time causes power supply ripple that can affect different components of the electronic circuitry that rely on the power supply voltage for their respective operations. Some components are sensitive to this power supply.

[0052] This could potentially limit the SNR and spurious-free dynamic range (SFDR) performance of the RF sampling transceiver or other IC subsystems. For the conversion control circuitry systems 110A and / or 130A, one option is to provide the output symbol to the parallel data interface channel 306 through encoding. This encoding reduces power supply ripple by decreasing the number of bit transitions for the parallel data interface channel 306. By reducing power supply ripple, the signal bandwidth or other performance parameters of the first electronic circuitry 102A can be improved. Another option available for the conversion control circuitry system 110A is to provide the output symbol to the parallel data interface channel 306 through encoding. This encoding reduces the total number of bit transitions and thus reduces the power consumption of the first electronic circuitry 102A and / or the second electronic circuitry 122A.

[0053] Figure 4 This is a block diagram of a transmitter 400 with a conversion control circuitry system according to an example embodiment. In some example embodiments, the transmitter 400 is a parallel data interface (e.g., Figure 1 This is part of the parallel data interface 108 or 128 in the figure. As shown, transmitter 400 includes a bitstream converter block 404, a conversion optimizer block 406, and a delay block 410. Bitstream converter block 404 is configured to receive input words of input bitstream 402 over time (e.g., input bitstream 402 or related samples may be generated by...). Figure 1 (Provided by input bitstream source 115 or input bitstream source 135), and provides associated output symbols for output bitstream 408 over time. Figure 1 In the example, the operation of bitstream converter block 404 is based on optimizer result 414 provided by conversion optimizer block 406.

[0054] In some example embodiments, the conversion optimizer block 406 is configured to receive input words from the input bitstream 402 (e.g., the input bitstream 402 or related samples may be provided by...). Figure 1 The input bitstream source 115 or input bitstream source 135 is provided; a delayed version 412 of the previous output symbol is received from the output bitstream 408 via delay block 410; and an optimizer result 414 is determined relative to a quality factor or target criterion (e.g., the minimum change in the number of bit transitions of the output symbol due to the application of a bit transition mode, or the minimum number of total bit transitions of the output symbol due to the application of a bit transition mode). The quality factor or target criterion may be selected and programmed into the conversion control circuitry (e.g., conversion control circuitry 110 or 130) for a given scenario. In some example embodiments, the conversion control circuitry may be programmed and / or the previous quality factor or target criterion may be adjusted more than once.

[0055] In one example, transmitter 400 is configured to map a k-bit input word (e.g., k = 16 or another integer less than n) to an n-bit output symbol (e.g., n = 20 or another integer greater than k) to keep the number of bit transitions on the parallel data interface constant. In some example embodiments, transition optimizer block 406: maps a set of 2 n Each output symbol is divided into 2 k Group 2 n-k 2 candidate bit transformation patterns (i.e., 2) n-k The candidate position transformation pattern is mapped through a bijective function and 2 k Associate each of the input words); associate the delayed version 412 of the previous output symbol of the output bitstream 408 with the current input word corresponding to the input bitstream 402. n-k n bits are compared; and a transform index 414 (e.g., codeword) is determined based on the comparison. In one example, k = 16 and n = 20. In other examples, k and n vary, where k is less than n. Regardless of the values ​​of k and n, the bitstream converter block 404 uses the transform index 414 from the transform optimizer block 406 to obtain an output bitstream 408 with n-bit output symbols from the k-bit input word of the input bitstream 402. At the receiver, the k-bit input word of the input bitstream 402 is recovered from the n-bit output symbols of the output bitstream 408 using a reverse mapping. In some example embodiments, Figure 4 The operation is performed using hardware and / or software executed by a microcontroller / processor.

[0056] Figure 5 It is a bitstream converter 500 according to an example embodiment ( Figure 1 and Figure 4 A block diagram of an example bitstream converter 112, 132, or 404. Figure 5In some of the following figures, time is segmented (e.g., "m" is a given sampling time, "m-1" is the previous sampling time relative to m, and "m+1" is the next sampling time relative to m). As shown, bitstream transformer 500 includes a first block 504 configured to perform bitstream transformation on input bitstream samples {S(m)} of input bitstream 402 (each input bitstream sample is sometimes referred to herein as an input word). In some example embodiments, S(m) is a k-bit input word. Regardless of the specific length of S(m), bitstream transformation is performed based on a bitstream transformation pattern 510 received from a second block 508. The second block 508 is configured to: receive a transform index 414 of the bitstream transformation pattern options; and select the bitstream transformation pattern 510 for use with the first block 504 according to a target criterion (e.g., a quality factor or target standard associated with the bitstream transformation target). The output of the first block 504 is the output bitstream samples {S'(m)} of the output bitstream 408 (each output bitstream sample is sometimes referred to herein as an output symbol). In some example embodiments, S'(m) is an n-bit output symbol. Figure 5 In the example embodiment, the input bit stream is “1010010101101111” and the output bit stream is “00011111000000111010”.

[0057] exist Figure 5 In the example, index 414 is determined by the transformation optimizer (e.g., Figure 4 The (nk) bit index {I(m)} provided by the transformation optimizer 406 is used to generate a bit transformation pattern 510 for a given sampling time m. In some example embodiments, the nk bit index information {I(m)} is embedded directly (e.g., as a bit block) or indirectly (e.g., as distributed bits) into the output bit stream sample S'(m). In one example embodiment, bits of index {I(m)} are added to either end of S(m) to generate S'(m). In another example embodiment, bits of index {I(m)} are distributed as separate bits throughout S(m) to generate S'(m). In some example embodiments, Figure 5 The operation is performed using hardware and / or software executed by a microcontroller / processor.

[0058] Figure 6 It is a conversion optimizer 600 according to an example embodiment ( Figure 4A block diagram of an example of a transformation optimizer block 406 is shown. As illustrated, the transformation optimizer 600 includes a first block 604 configured to generate L candidate bit transformations 606 in response to each input word (e.g., S(m)). The L candidate bit transformations 606 for each input word are provided to a second block 608, which is configured to perform a quality factor calculation 610 based on the L candidate bit transformations 606 and a quality factor or target criterion. The quality factor result 610 is provided to a third block 612, which is configured to select a bit transformation pattern based on the quality factor result 610 to be used as an index 414. Figure 6 In this process, delay block 410 receives S'(m) and provides a delayed version 412 of the previous output bitstream sample S'(m-1) to the second block 608 for calculating the quality factor result 610. In some example embodiments, Figure 6 The operation is performed using hardware and / or software executed by a microcontroller / processor.

[0059] In some example embodiments, the transformation optimizer 600 applies possible transformation patterns to each input word (e.g., S(m)) to generate L candidate n-bit output symbols (e.g., 2^n). n-k For each of the L selections, output L candidate n-bit symbols {Y0(m)...Y...} L-1 The total number of bit transitions is calculated by comparing {S'(ml)} with the previous n-bit output bitstream sample {S'(ml)}. The optimal transformation mode is selected based on the desired quality factor or target criterion. In one example embodiment, the quality factor or target criterion prioritizes keeping the total number of bit transitions as close as possible to a constant target value G. In another embodiment, the quality factor or target criterion prioritizes minimizing the total number of bit transitions.

[0060] In some example embodiments, the conversion optimizer 600: converts each k-bit input bitstream sample (e.g., 2 if k = 16) into a single bitstream sample. 16 (1 input character) and sixteen (2) 4A candidate pattern / mask is associated with each input word; and sixteen n-bit (e.g., 20-bit) output symbols are constructed for each input word. In other words, each output symbol is the result of combining the input word with a bit-transformation pattern (e.g., using a pattern index {[16-bit][4-bit]}). In different example embodiments, the bit-transformation pattern is combined with the input word using a direct or indirect embedding function. For example, if the input word is a k-bit word and the pattern is n-bit, the input word can be zero-padded to construct an n-bit output symbol. Alternatively, the k-bit input word can be combined with the pattern (e.g., the k-bit input word is appended with an nk-bit index). In some example embodiments, for each input word, the output symbol closest to the target number of transitions is selected. This can be modified to any criterion (e.g., the fewest bit-transformation changes, the fewest total bit-transformations, or some other criterion). In some example embodiments, the quality factor or target criterion is: to make the relative probability of the most frequent number of transitions as close to 1 as possible; to have a low standard deviation; and to reduce the average number of transitions.

[0061] Figure 7 It is an inverse bitstream converter block 704 according to an example embodiment (e.g., Figure 1 The block diagram 700 shows the inverting bitstream converter (114 or 134) in the circuit. Figure 7 In the example, the inverse bitstream converter block 704 receives the output symbols of the received bitstream 702 via a parallel data interface (e.g., Figures 4-6 The output bit stream 408 is in the output bit stream; and the recovered output bit stream 706 is in the output bit stream 706 (e.g., Figures 4-6 The input bitstream 402 is used as an example. To perform the inverse bitstream transformation and recover the input word from the output symbols, the inverse bitstream transformer block 704 includes an inverse transformation algorithm, instructions, and / or associated hardware to undo transformations previously applied to the input word. In some example embodiments, Figure 7 The operation is performed using hardware or software executed by a microcontroller / processor.

[0062] Figure 8 Receiver 800 according to an example embodiment ( Figure 1 A block diagram of an example of the receiver side of the RF sampling transceiver 104 is shown. As shown, the receiver 800 includes a first block 804 configured to: obtain output bit stream samples S'(m) (e.g., n-bit output symbols) of the output bit stream 408 via a parallel data interface channel; and recover S(m) of the input bit stream 402 in response to an inverse transformation mode 812. Figure 8In the example, the second block 806 and the third block 810 are used to obtain the inverse transform pattern 812. The second block 806 is configured to receive S'(m) and extract the bit transform index {l(m)}808 from S'(m). Note: The extracted bit transform index may, but does not have to, vary for each output symbol according to the target standard. The third block 810 then generates the inverse bit transform pattern 812 for use by the first block 804 based on the extracted bit transform index 808. The inverse transform pattern 812 is applied by the first block 804 to S'(m) to cancel the effect of the bit transform performed at the transmitter and thus recover S(m). In a similar manner, the receiver 800 is able to obtain other output bit stream samples of the output bit stream 408 (e.g., S(m+1), S(m+2), etc.) and recover the corresponding input words of the input bit stream 402. Figure 8 The operation is performed using hardware or software executed by a microcontroller / processor.

[0063] Figure 9 Figure 900, illustrating the bit transition distribution as a function of relative frequency according to an example embodiment, compares the raw bit transitions (without encoding / transformation) of a 16-bit input word on a parallel data interface (dashed line) with the encoded bit transitions (with encoding / transformation) of a 20-bit output symbol on a parallel data interface due to bitstream conversion operations (solid line). In Figure 900, the encoded bit transitions result in 10 bit transitions occurring 98% of the time. Furthermore, the total number of bit transitions varies by approximately 0.023. In contrast, the raw bit transitions result in 8 transitions occurring 20% ​​of the time, and the total number of bit transitions varies by approximately 4. The reduced change in the switching factor (bit transition variation) provided by the encoded bit transitions mitigates power supply ripple and related issues compared to the raw bit transitions.

[0064] Figure 10 Table 1000 is a table of bit transformation patterns according to an example embodiment. Specifically, the indices of Table 1000 are 0-15 (4-bit values) because the difference between n (the bit length of the output symbol) and k (the bit length of the input word) is 4. The indices may vary depending on the k value of the input word and the n value of the output symbol. The 16-bit patterns in Table 1000 that apply 4-bit index values ​​are predetermined and can vary. In some example embodiments, the bit transformation pattern is determined by calculating the number of transformations between two consecutive output symbols (e.g., each with a length of n bits). In one example embodiment, the bit transformation pattern is determined by padding the input word with k bits to make a total of n bits, and then XORing the padded input word with an n-bit mask.

[0065] In some example embodiments, the transmitter-side bitstream transformation operation includes: selecting a candidate bitstream transformation pattern or a static mask (e.g., a 16-bit pattern and a 4-bit index pattern as shown in Table 1000); analyzing the number of conversions between the previous n-bit output symbols and the output symbols resulting from using a candidate bitstream transformation pattern with a given input word; selecting the bitstream transformation pattern (from the candidate bitstream transformation pattern) that best meets the target bitstream transformation constraints; and generating an output symbol for the given input word using the selected bitstream transformation pattern. Subsequently, the receiver-side reverse bitstream transformation operation includes: determining a (nk) bitstream pattern index for converting a k-bit input word to an n-bit output symbol; and demasking the k-bit input word according to the pattern index.

[0066] Figure 11 Figure 1100 shows the bit transition distribution as a function of relative frequency, comparing the raw bit transitions (dashed line) of a 16-bit input word on a parallel data interface with the encoded bit transitions (solid line) of a 20-bit output symbol on the parallel data interface. The encoded bit transitions are due to the operation of the bitstream transformer, as described herein. In some example embodiments, the encoded bit transitions in Figure 1100 are the result of bit transition options involving a simple XOR operation of the 16-bit input word with a 16-bit transition pattern. In this example, the transition optimizer uses the minimum total number of transitions as a quality factor or target criterion. The pattern that achieves the minimum total number of transitions is selected from all possible transition patterns. As shown in Figure 1100, the average number of bit transitions used for encoded bit transitions is approximately 6 (in 20 parallel data interface channels). Furthermore, the variation in bit transitions for encoded bit transitions in the parallel data interface channels is approximately 1.2. In contrast, the average number of bit transitions for raw bit transitions is 8 (in 16 parallel data interface channels), and the variation in the total number of bit transitions used for raw bit transitions is approximately 4. Compared to raw bit transitions, the reduced switching factor (bit transition variation) provided by coded bit transitions (approximately 25%) mitigates power supply ripple and related issues. Furthermore, reducing the total number of transitions by using coded bit transitions instead of raw bit transitions reduces power consumption.

[0067] In different example embodiments, the switching control circuitry (e.g., Figure 1 The conversion control circuitry systems 110 and 130, and the associated bitstream conversion options and topologies (e.g., serial, parallel, or pipelined), can vary. This variation may be due to the expected clock rate, complexity considerations, operating speed, or other considerations for a particular system. In some example embodiments, conversion control circuitry systems 110 and 130 may use different bitstream conversion options and topologies. As an example, conversion control circuitry system 110 may use a parallelization factor of 1, while conversion control circuitry system 130 may use a parallelization factor of 2 with half the clock rate.

[0068] Figure 12A and Figure 12B This is a block diagram of a parallel implementation of conversion control circuitry systems 1200 and 1250 according to an example embodiment. Figure 12A In the figure, the conversion control circuit system 1200 includes a topology that can be parallelized as needed. As shown, the conversion control circuit system 1200 includes a bitstream converter block 404A ( Figure 4 Example of bitstream converter 404), conversion optimizer block 406A ( Figure 4 Example of conversion optimizer block 406), and index remapping block 1202. Bitstream converter block 404A is configured to receive S(m) of input bitstream 402 and provide S'(m) of output bitstream 408. Conversion optimizer block 406A ( Figure 4 An example of the conversion optimizer block 406 is configured to determine the intermediate bit transformation index (m) 1206 based on S(m) and S(m-1). The index remapping block 1202 is configured to determine the final bit transformation index (m) 1208 based on the intermediate bit transformation index (m) 1206 and the final bit transformation index (ml) 1204 (the bit transformation index for time m-1). The bitstream converter block 404A generates S'(m) based on S(m) and the final bit transformation index (m) 1208. The index remapping block 1202 facilitates the parallelization of the conversion control circuit system 1200 and the determination of the final transformation index for time m by using the preceding transformation index for time m-1.

[0069] exist Figure 12B In the middle, the conversion control circuit system 1250 includes conversion control circuits 1200A and 1200B ( Figure 12A Each example of the intermediate conversion control circuit system 1200 is provided to offer a topology that is parallelized to 2. Specifically, the conversion control circuit system 1200A includes a bitstream converter block 404A, which is configured to receive S(m) of the input bitstream 402 and provide S'(m) of the output bitstream 408. The conversion optimizer block 406A uses S(m) and S(m-1) to determine the intermediate bitstream conversion index (m) 1206A. The conversion control circuit system 1200A includes an index remapper block 1202A ( Figure 12A Example of index remapping 1202 in the example), which determines final bit transformation index (m) 1208A based on intermediate bit transformation index (m) 1206 and final bit transformation index (ml) 1204. Bitstream converter block 404A generates S'(m) based on S(m) and final bit transformation index (m) 1208A.

[0070] The conversion control circuit 1200B includes a bitstream converter block 404B. Figure 4Example of a bitstream converter 404 in the example, which is configured to receive S(m+1) of input bitstream 402 and provide S'(m+1) of output bitstream 408. Conversion optimizer block 406B ( Figure 4 The example of conversion optimizer block 406 uses S(m) and S(m+1) to determine the intermediate bit transformation index (m+1) 1206B. Conversion control circuitry system 1200B includes index remapping block 1202B, which determines the final bit transformation index (m+1) 1208B based on the intermediate bit transformation index (m+1) 1206B and the final bit transformation index (m) 1208A. Bitstream converter block 404B is configured to generate S'(m+1) based on S(m+1) and the final bit transformation index (m+1) 1208B. Further parallelization is possible as needed (e.g., four parallel conversion control circuitry systems 1200, etc.).

[0071] Figure 13 It is a conversion control circuit system 1300 according to an example embodiment ( Figure 1 Examples of conversion control circuit systems 110 or 130, or Figure 3 A block diagram of a serialized implementation of an example of a conversion control circuit system 110A or 130A. As shown, the conversion control circuit system 1300 includes a first bit stream converter block 1304, which is configured to receive S(m) of the input bit stream 402 and provide S'(m) of the output bit stream 408 based on S(m) and the bit conversion index (m) 1310. Figure 13 In the example, the bit transformation index (m) 1310 is provided by a first transformation optimizer block 1308 configured to generate the bit transformation index (m) 1310 based on the input bit stream 402 S(m) and the output bit stream 408 S'(m-1).

[0072] As shown in the figure, the S'(m) of the output bit stream 408 is provided from the first stream converter block 1304 to the second conversion optimizer block 1314. Figure 13 In the example, the second conversion optimizer block 1314 is configured to generate a bit transformation pattern (m+1) 1316 based on S'(m) of the output bit stream 408 and S(m+1) of the input bit stream 402. The conversion control circuit system 1300 also includes a second bit stream converter block 1318, which is configured to generate S'(m+1) of the output bit stream 408 based on S(m+1) and the bit transformation index (m+1) 1316. Figure 13 In the case of a serial topology, with Figure 12A and Figure 12B Compared to parallel topologies, the conversion control circuit system 1300 offers reduced complexity and associated benefits (smaller size, lower cost, etc.). In some example embodiments, Figure 13The operation is performed using hardware and / or software executed by a microcontroller / processor.

[0073] In some example implementations, the parallel data interface can support rates of 2 Gbps. However, such a high-speed digital clock (CLK) may be incompatible with a given FPGA or AFE. To address this issue, parallelization implementations (e.g., such as...) are used. Figure 12B The parallelization in the above is 2), where the bitstreams corresponding to two consecutive sample instances m and m+1 are processed in a single clock cycle. Conversely, the conversion control circuitry system 1300 performs bitstream conversion on the two consecutive samples, as follows: Figure 13 As shown. Note: The second conversion optimizer block 1314 is configured to determine the optimal bit conversion index {I(m+1)} using S(m+1) and S'(m), which can be computed in the same clock cycle. Therefore, this conversion control circuit system 1300 is not easily compliant with a parallelized implementation.

[0074] Figure 14 It is a conversion control circuit system 1400 according to an example embodiment ( Figure 1 Examples of conversion control circuit systems 110 or 130, or Figure 3 A block diagram of another parallelized implementation of the conversion control circuit system 110A or 130A (examples). As shown, the conversion control circuit system 1400 includes a first bit stream converter block 1404, which is configured to receive S(m) of the input bit stream 402 and provide S'(m) of the output bit stream 408 based on S(m) and the bit transformation index (m) 1410. Figure 14 In the example, the bit transformation index (m) 1410 is provided by the transformation optimizer block 1408, which is configured to generate the bit transformation index (m) 1410 based on the input bit stream 402 S(m) and the output bit stream 1406 S'(m-1).

[0075] The conversion control circuit system 1400 also includes a second bitstream converter block 1420, which is configured to provide an output bitstream S'(m+1) based on the input bitstream 402's S(m+1) and the next bitstream conversion index (m+1) 1422. Figure 14 In the example, the next bit transform index (m+l) 1422 is provided by a modified transform optimizer block 1414, which is configured to generate the next bit transform index (m+l) 1422 based on S(m), S(m+1), and the bit transform mode or index (m) 1410. In some example embodiments, Figure 14 The operation is performed using hardware and / or software executed by a microcontroller / processor.

[0076] Through parallel implementation and a modified conversion optimizer 1414, the conversion control circuit system 1400 generates S'(m) and S'(m+1) of the output bit stream 408 within one clock cycle. Since S'(m) can be generated using any of L possible conversion modes, the modified conversion optimizer block 1414 applies all possible conversion modes to S(m) and S(m+1) to generate L candidate n-bit output symbols for each conversion mode. In one or more example embodiments, the L candidate output symbols {Y0(m+1)...Y...} L-1 (m+1)} and the previous L candidate output symbols {Y0(m)……Y L-1 (m)} is used to calculate the comparison for L 2 The total number of bit transitions for each of the combinations. Then, for {I0(m+l)……I L-1 For each possible choice of {I(m+l)}, L optimal transformation mode indices are selected for {I(m+1)}. Once {I(m)} is determined, L:1MUX selects the optimal transformation mode index {I(m+1)}. However, this leads to a significant increase in the complexity of the modified transformation optimizer block 1414.

[0077] In some example implementations, a pipelined topology is used when the processing time exceeds the sampling period (1 / Fs). In this case, processing is split across different sampling periods, and throughput (processing rate) matches the input rate at the cost of delay (latency). The delay is a result of splitting processing across multiple time periods. The pipeline operation during different time periods is shown in Table 1 below.

[0078] Table 1

[0079]

[0080]

[0081] As shown in Table 1, the three pipelined operations include the transformation optimizer operation, the index remapper operation, and the bitstream converter operation. Since the transformation optimizer is the most complex operation, in some example embodiments, a full sampling period (time instance m) is allocated to it to complete its operation. Within the same time instance (m), the index remapper operates on the previous symbol (corresponding to time instance m-1), and the bitstream converter is operating on the symbol preceding m-1 (i.e., time instance m-2). Therefore, the output corresponding to the symbol at time instance m is available at time instance m+2 → deferred to two time intervals. Except that the submodules are processing samples corresponding to different time instances, the hardware unit of the pipelined topology is similar to... Figure 12AThe topology is a parallel structure of 1. Since there is one output available for each cycle (in addition to a delay of 2 units in this example), the output throughput matches the input.

[0082] In some example embodiments, the conversion control circuitry, arranged in a pipelined or parallel manner, performs the following operations: 1) it can perform conversion weight calculations on the original input word; 2) it selects a temporary pattern index that meets the target conversion criterion. In some example embodiments, these two operations involve an XOR operation and bit counting. For some operations, input from a previous time instance is not required. Furthermore, in some example embodiments, the pattern index (MaskIndex)... T () refers to the index and mask index. T-1 The function. In other words, the temporary index T+1 and index T are used to determine the index used for T+1. The advantage of this technique is that some related complex operations (e.g., generating L candidates and selecting the best one) can be performed in parallel, and the subsequent operations to determine index T+1 from the temporary index T+1 and index T are relatively less complex. Furthermore, the pattern index can be a bijective function. In some example embodiments, the index (Index) and MaskIndex are executed. T+1 XOR.

[0083] In some example embodiments, the k-bit input word is divided into (nk) bit groups g i Each group (G). Grouping is completed so that the sum is added to k digits, i.e. As an example, the 17 bits can be divided into 6, 6, and 5 bits respectively. Each (nk) group in G is associated with a flip bit to form a padding group G'. The initial value of the flip bit is 0 (i.e., not flipped). Each group is ANDed with an integer equal to 0. The threshold is associated with this. In some example embodiments, the input word is encoded as follows: 1) Each bit in group (nk) G' is compared with the corresponding bit emitted in the previous time instance; 2) The number of bit transitions in each group g′∈G′ is calculated. For each group in G', if the number of bit transitions > the threshold, the group is inverted. This will make the inverted bit in that particular group 1 (because it is initialized to 0).

[0084] Figure 15 This is a modified conversion optimizer 1500 according to an example embodiment. Figure 14A block diagram of an example of a modified transformation optimizer 1414 is shown. As shown, the modified transformation optimizer 1500 includes a first block 1504 configured to generate L candidate transforms 1506 for the input bitstream 402's S(m). In block 1508, quality factor calculation is performed on the L*L combinations. As shown, block 1508 also receives L candidate transforms 1529 from block 1528, which is configured to generate L candidate transforms 1529 from the input bitstream 402's S(m-1). For example, S(m-1) is obtained by causing S(m) to pass through delay block 1524.

[0085] The output of block 1508 is the set of candidate 1510s that best matches the quality factor applied at block 1508. Figure 15 In block 1512, candidate group 1510 is received and an L-bit transformation index 1514 is selected based on the quality factor for each of the S(m-1) candidates. In block 1516, index (Index(m)) 1520 is selected based on index (ml) and L-bit transformation index 1514. In some example embodiments, Figure 15 The operation is performed using hardware and / or software executed by a microcontroller / processor.

[0086] In some example embodiments, the modified transformation optimizer 1500 constructs a set of L transformation patterns by: 1) imposing a "closed set" constraint under the transformation operation; and 2) replacing S'(m+1) with S(m+1) in the modified transformation optimizer 1500 to compute the intermediate index {I}. int (m+1)}; and 3) using an index remapping mechanism from {I int Calculate {I(m+1)} from {m+1}. In an example embodiment, the L transformation patterns are generated using the following constraints: 1) The XOR result of any two patterns selected from the L patterns is also a member of the set; 2) The patterns x ⊕ mode y =pattern z z = f(x, y); 3) The modified transformation optimizer 1500 uses S(m) instead of the unavailable S'(m) to determine the optimal intermediate index; and 4) it avoids the increase in complexity (L alternatives L). 2 (One computation). Using the modified transformation optimizer 1500, the previous output symbol is XORed with the potential output of the current input word. This does not allow for parallel implementation.

[0087] In some example implementations, more careful mode selection can be performed for parallelization operations. For example, mode selection for implementing parallelization might involve: 1) generating 2 L1) Select L candidate patterns (L = nk); 2) Select L 'base patterns' of length k; 3) Mark the candidate patterns as M0, M1...M L-1 ;4) Generate 2 L Each pattern represents all possible linear combinations of the L-mask (e.g., ) and 5) construct the 20-bit pattern as (Modes concatenated with binary weights). In this example, the mask set has the following property: any mask XORed with another mask is a valid mask. The mask formation is a closed set under the XOR operation (i.e., the bitstream transformation operation chosen in the current example). Therefore, the distribution of the number of transformations between the L candidate transformations corresponding to S(m) and S'(ml) is the same as the distribution of the number of transformations between the L candidate transformations corresponding to S(m) and S(m-1) transformed by any mask. In the given example mask set, the transformation modes include the all-zero mode, and S(ml) transformed by any mask is simply a zero-padded version of S(ml).

[0088] As an example, pattern generation can be performed as follows: 1) Split k into nk bit groups, each with a width g i Make 2) has 3)M i Will have (g) i The binary representation of 1's, followed by

[0089] For example, if {g i If} = {5, 5, 6} then

[0090] M0=′0000000000011111′, M1=′0000001111100000′, M2=′1111110000000000′

[0091] In another example, mask generation is performed by selecting a pattern using the following expression.

[0092] Second-rate.

[0093] As an example, if k = 16 and L = 4,

[0094] M0=′0000000011111111′,M1=′0000111100001111′

[0095] M2=′1100110011001100′,M3=′0101010101010101′

[0096] In another example, L masks M are selected from a list of k-length orthogonal / nearly orthogonal bit patterns. i To perform pattern generation. As an example, if k = 17 and L = 3,

[0097] M0=′10101010101010101′,M1=′10100101010110100′,M2=′11000011001111001′

[0098] Figure 16 This is a parallel processing of more than one symbol according to another example embodiment (e.g., Figure 16 A conversion control circuit system 1600 (in an embodiment involving parallel processing of two symbols) Figure 1 The conversion control circuit system 110 or 130, or Figure 3 A block diagram of an example of a conversion control circuit system 110A or 130A is shown. As illustrated, the conversion control circuit system 1600 includes a first bit stream converter block 1604, which is configured to receive S(m) of the input bit stream 402 and provide S'(m) of the output bit stream 408 based on the bit transformation index (m) 1610. Figure 16 In the example, the bit transformation index (m) 1610 is provided by the transformation optimizer block 1608, which is configured to generate the bit transformation index (m) 1610 based on S(m) and S'(m-1).

[0099] The conversion control circuit system 1600 also includes a second bitstream converter block 1616, which is configured to receive S(m+1) of the input bitstream 402 and provide S'(m+1) of the output bitstream 408 based on the bit transformation index (m+1) 1624. Figure 16 In the example, providing the bit transformation index (m+l) 1624 to the second bitstream converter block 1616 involves a conversion optimizer block 1618 and an index remapping block 1622. The conversion optimizer block 1618 is configured to generate an intermediate index 1620 based on S(m) and S(m+1). The index remapping block 1622 is configured to generate the bit transformation index (m+l) 1624 from the intermediate index 1620 and the bit transformation index (m) 1610. Alternatively, the upper and lower parts of the conversion control circuitry system 1600 can be identical to each other.

[0100] In some example embodiments, the conversion control circuitry 1600 determines L(2) that satisfies the constraint of a closed set under the XOR operation. n-k A set of ) transformation modes. L(2 n-k The set of ) transformation patterns can be constructed as follows: 1) Select nk candidate generator patterns of length k {M n-k-1……M0}, which forms a "minimal set" under the XOR operation; 2) Define a minimal set such that the XOR operation performed on any selected subset of j (1 < j ≤ n - k) unique elements is not an element of the set; 3) Generate L transformation patterns as generator patterns M i as the binary weighted XOR result; or 4) 5) The binary weights {a n-k-1 ,..., a0} form an (n - k)-bit pattern index. In one example, the transformation control circuit system 1600 generates patterns as follows for n = 20 and k = 16:

[0101] M3 = '11111111000000000', M2 = '1111000011110000'

[0102] M1 = '1100110011001100', M0 = '1010101010101010'

[0103] Compared with the pipelined / parallel transformation control circuit system, the non-pipelined transformation control circuit system performs the selection of the pattern index as follows: 1) Compare the previously transmitted symbol with all candidate output symbols corresponding to Symbol T ; 2) Transmit the candidate output symbol closest to the target transformation count; 3) Continue for subsequent input words; and 4) Once the previous output symbol is determined, the processing begins.

[0104] Figure 17 is a flowchart of a transformation pattern generation method 1700 according to an example embodiment. The method 1700 is performed, for example, by a transformation control circuit system (e.g., Figure 1 the first electronic circuit 102 or the second electronic circuit 122 in Figure 3 , or the first electronic circuit 102A or the second electronic circuit 122A in Figure 1 the first electronic circuit or the second electronic circuit (e.g., Figure 3 the transformation control circuit system 110 in (n-k)A binary weighted XOR combination. In block 1710, the binary weights are inserted as nk-bit indices. In block 1712, the transform pattern generation ends.

[0105] Figure 18 This is a transformation pattern table 1800 according to an example embodiment. Transformation pattern table 1800 is applicable to cases where k=16 and n=20 as described herein. Note: Transformation pattern table 1800 is independent of the specific conversion control circuitry system topology used.

[0106] Figure 19 This is a transformation pattern table according to yet another example embodiment. Transformation pattern table 1900 is applicable to cases where k=16 and n=20 as described herein. Transformation pattern table 1900 is independent of the specific transformation control circuit system topology used. One advantage of the transformation patterns shown in Table 1900 is that, since the patterns are generated using generator patterns that do not have 1 at common bit positions, transformation weights can be calculated hierarchically. In this case, the generator pattern is:

[0107] M3='1111000000000000',M2='0000111100000000',

[0108] M1=′0000000011110000′,M0=′0000000000001111′

[0109] The number of transformations can be counted as four sub-accumulations corresponding to the bits that are 1 in patterns M0, M1, M2, and M3. A sum of 16 can then be obtained from these sub-accumulations.

[0110] Although pattern table 1900 is suitable for situations where 16-bit input words are independently and identically distributed, it can achieve further performance improvements in scenarios where the bits are not independently and identically distributed.

[0111] In some example embodiments, the conversion control circuit system ( Figure 1 Examples of conversion control circuit systems 110 or 130, or Figure 3Examples of conversion control circuitry systems 110A or 130A perform bitstream conversion from a k-bit input word to an n-bit output symbol, optimizing the total number of bit transitions between consecutive output symbols based on a quality factor or target criterion. In some examples, the conversion control circuitry uses a conversion optimizer to determine the transform pattern using the current input word and previous output symbols. In one example, a quality factor is used, where the total number of bit transitions is matched as close as possible to a target value. In another example, a quality factor is used, where the total number of bit transitions is minimized. In some example embodiments, the conversion control circuitry employs an XOR operation to perform bitstream conversion by selecting from L pre-stored transform patterns. In some example embodiments, the conversion control circuitry employs parallelized bitstream conversion, where the computation of the preferred transform pattern is decoupled by selecting L pre-stored transform patterns forming a “closed set” under an XOR operation. In some example embodiments, the conversion control circuitry employs an enhanced conversion optimizer configured to determine intermediate transform pattern indices using the current and previous input words. In some example embodiments, the conversion control circuitry employs an index remapper that computes the current transform pattern index based on the current intermediate index and the previous transform pattern index. In some example embodiments, the conversion control circuitry constructs a set of L pre-stored transform patterns by using a weighted binary combination (via XOR) of nk generator patterns to form a closed set under the XOR operation. In this case, the selection of nk "generator" patterns satisfies the minimum set property.

[0112] In some example embodiments, the spectral characteristics of the digital switching activities used for output symbols and raw input words can be compared due to bit transitions in the parallel data interface. To perform the comparison, power supply ripple is modeled at the digital clock edge (1 GHz) and is proportional to the number of bit transitions. Bit-stream transformation reduces broadband components by ~22 dB. For single-tone inputs, bit-stream transformation achieves worst-case harmonic spurious suppression exceeding 30 dB. For inputs such as... Figure 20 and Figure 21 The two different signal inputs shown in Figures 2000 and 2100 achieve a significant reduction in multiplicative in-band noise and signal harmonic spurious signals due to digital interface data switching.

[0113] Using a conversion control circuit system (e.g., Figure 1 The conversion control circuit system 110 or 130 in the middle Figure 3 The conversion control circuit system in the middle is 110A or 130A. Figure 13 The conversion control circuit system 1300 Figure 14 The conversion control circuit system 1400, in Figure 16The conversion control circuitry system 1600 reduces conversion variations on the parallel data interface at the cost of additional channels. Furthermore, a trade-off between reduced conversion variations and a lower number of conversions is possible. Additionally, a trade-off between noise interference and power is also possible. The receiver implementation is simple, requiring only a demasking operation. Therefore, the receiver does not need to be modified based on different conversion selection algorithms. In some example embodiments, additional parity bits on the interface can reduce the chance of undetected data corruption. Furthermore, different conversion control options can be developed by using different modes or selection criteria for bit transformations at the transmitter.

[0114] In some example implementations, the conversion control interface modifies a k-bit input word to an n-bit output symbol, such that the output symbol has a target number of bit transitions. In one example, the input word is modified by constructing a 2-bit transformation for each input word. k-n The operation is performed using n candidate output symbols (one-time operation). At the transmitter, for the input word of the current instance, the conversion control circuitry system switches from 2... k-n The optimal output symbol is selected from among the candidate output symbols. In some example embodiments, the selection criterion for the optimal output symbol is the target number of bit transitions. The selected output symbol is then transmitted to the receiver. At the receiver, the k-bit input word is recovered by decoding the received n-bit output symbol.

[0115] In some example embodiments, the output symbol is XORed with [[input word] [mask]] 索引 The index is given, where the index is (nk) bits long. In some example embodiments, 2 k-n The mask is generated as one of the following: 1) a k-bit sequence that is mutually orthogonal or nearly orthogonal; or 2) a 2^k basis vector. k-n A linear combination. The basis vectors are generated as follows: divide k into nk bit groups, each with a width of g. i , making And has In this example, M i The binary representation of (gi 1's) followed by As an example, if {g i If} = {5, 5, 6}, then M0 = '0000000000011111', M1 = '0000001111100000', M2 = r1111110000000000'. In some examples, M i The base mask is generated using the following expression. This is one example. If k = 16 and L = 4, then M0 = '0000000011111111', M1 = '0000111100001111', M2 = '1100110011001100', M3 = '0101010101010101'. In some examples, L masks M i It is selected from a list of orthogonal / nearly orthogonal bit patterns of length k. As an example, if k = 17 and L = 3, then M0 = '101010101010101', M1 = '10100101010110100', M2 = '11000011001111001'.

[0116] In some example embodiments, the conversion control circuitry system implements sequential or pipelined / parallel processing. For sequential processing, the selection of the output symbol is based on a conversion weight calculation using a pattern / mask index, which compares the previously emitted output symbol with the corresponding Symbol. T All candidate output symbols are compared; and the candidate symbol closest to the target number of bit transitions is selected. For pipelined / parallel processing, the selection of output symbols is based on the transformation weight calculation using a mask index, which uses an XOR operation to compare the current input word and the previous input word and calculate the number of bit transitions; and the selection of a temporary mask index that satisfies the target bit transition criterion; and the obtaining of the mask index of the current time instance by applying a transformation function on the temporary mask index using the mask index selected in the previous time instance. One such transformation function is XOR(Index, MaskIndex)... T-1 ).

[0117] In some example embodiments, the conversion control circuitry maps a k-bit input word to an n-bit output symbol by dividing the k bits into nk bit groups g. i Each group makes A new group G' is formed by associating each of the groups nk with a reverse bit, where the initial value of the reverse bit is 0 (i.e., no reverse). In this example, a threshold can be used. At the transmitter, each bit in group (nk) G' is compared with the corresponding bit transmitted in the previous time instance. For each in group nk, if the number of bit transitions is greater than a threshold, that particular group is inverted. This will make the inverted bit in that particular group 1 (because it was initialized to 0). At the receiver, the inverted bit of each group in group (nk) is observed. If the inverted bit is 1, the corresponding group of bits is inverted. Otherwise, if the inverted bit is 0, these bits are transmitted without inversion.

[0118] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in the first example, device A is coupled to device B via a direct connection; or (b) in the second example, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C such that control signals generated by device B via device A are controlled by device A.

[0119] A device “configured” to perform a task or function can be configured (e.g., programmed and / or hardwired) at the time of manufacture to perform the function and / or can be configured (or reconfigured) by the user after manufacture to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the hardware components of the device and the construction and / or layout of interconnections, or a combination thereof. Circuits or devices described herein that include certain components may alternatively be adapted to be coupled to those components to form the described circuit or device.

[0120] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0121] This document describes circuits or functions that include certain components or functions that may alternatively be coupled to those components or functional blocks to form the described circuit system or functional system. While some components or functional blocks may be described herein as being implemented in an integrated circuit or on a single semiconductor substrate (or conversely, in multiple integrated circuits or on multiple semiconductor substrates), this implementation can be achieved using more or fewer integrated circuits or more or fewer semiconductor substrates. The circuit / functional blocks of the example embodiments may be packaged in one or more device packages.

[0122] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are also possible.

Claims

1. A circuit comprising: Parallel data interface; as well as A conversion control circuit system, coupled to the parallel data interface, is configured to: Receive input bitstream samples; The bit transformation mode of the input bitstream sample is determined according to the target criteria; and An output bitstream symbol is generated from the input bitstream sample and the bit transformation pattern, wherein the output bitstream symbol has more bits than the input bitstream sample.

2. The circuit of claim 1, wherein the parallel data interface includes a parallel data interface channel configured to transmit bits of the output bit stream symbol in parallel, and the target standard minimizes bit transitions on the parallel data interface channel.

3. The circuit of claim 1, wherein the parallel data interface includes a parallel data interface channel configured to transmit bits of the output bit stream symbol in parallel, and the target standard minimizes the variation in the number of bit transitions on the parallel data interface channel.

4. The circuit of claim 1, wherein the conversion control circuit system has a parallelized topology configured to generate multiple output bitstream symbols at once.

5. The circuit of claim 1, wherein the conversion control circuit system has a serialized topology configured to generate a plurality of output bitstream symbols within a clock cycle.

6. The circuit of claim 1, wherein the conversion control circuit system has a pipelined topology with a conversion optimizer, an index remapper, and a bitstream converter, and the conversion control circuit system is configured to perform conversion optimizer operation, index remapper operation, and bitstream converter operation in different clock cycles to generate the output bitstream symbol.

7. The circuit of claim 1, wherein the conversion control circuit system includes an index remapper configured to generate the bit transformation pattern based on a preceding bit transformation pattern.

8. The circuit of claim 1, wherein the conversion control circuit system is configured to: generate a plurality of candidate bit transformation patterns; and select one of the candidate bit transformation patterns based on the target criterion.

9. The circuit of claim 1, wherein the parallel data interface and the conversion control circuit system are components of an integrated circuit, the integrated circuit including an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) adapted to be coupled to another circuit via the parallel data interface.

10. The circuit of claim 1, wherein the parallel data interface and the conversion control circuit system are components of an integrated circuit, the integrated circuit including a baseband processor adapted to be coupled to another circuit via the parallel data interface.

11. A system for communication, comprising: First electronic circuit; as well as A parallel data interface channel, coupled to the first electronic circuit and adapted to be coupled to a second electronic circuit, wherein the first electronic circuit is configured to: Receive input bitstream samples; The bit transformation mode of the input bit stream sample is determined according to the target standard; An output bitstream symbol is generated from the input bitstream sample and the bit transformation pattern, wherein the output bitstream symbol has more bits than the input bitstream sample; as well as The output bitstream symbol is provided to the parallel data interface channel.

12. The system of claim 11, wherein the first electronic circuitry includes an analog front-end, i.e., an AFE, and the second electronic circuitry includes a baseband processor.

13. The system of claim 11, wherein the first electronic circuit and the second electronic circuit are on different integrated circuits.

14. The system of claim 11, wherein the first electronic circuit and the second electronic circuit are on different chips of an integrated circuit.

15. The system of claim 11, wherein the parallel data interface channel is configured to transmit bits of the output bit stream symbol in parallel, and the target standard minimizes bit transitions on the parallel data interface channel.

16. The system of claim 11, wherein the parallel data interface channel is configured to transmit bits of the output bit stream symbol in parallel, and the target standard minimizes the variation in the number of bit transitions on the parallel data interface channel.

17. The system of claim 11, wherein the first electronic circuit has a parallelized topology configured to generate multiple output bitstream symbols at once.

18. The system of claim 11, wherein the first electronic circuit has a serialized topology configured to generate a plurality of output bitstream symbols within a clock cycle.

19. The system of claim 11, wherein the first electronic circuit has a pipelined topology with a conversion optimizer, an index remapper, and a bitstream converter, and the first electronic circuit is configured to perform conversion optimizer operation, index remapper operation, and bitstream converter operation in different clock cycles to generate the output bitstream symbol.

20. A method for communication, comprising: Receive input bitstream samples; The bit transformation mode of the input bit stream sample is determined according to the target standard; An output bitstream symbol is generated from the input bitstream sample and the bit transformation pattern, wherein the output bitstream symbol has more bits than the input bitstream sample; and The output bitstream symbol is provided to the parallel data interface channel.

21. The method of claim 20, wherein the target criterion minimizes bit transitions on the parallel data interface channel.

22. The method of claim 20, wherein the target criterion minimizes the variation in the number of bit transitions on the parallel data interface channel.

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