Mapping conditional execution logic to quantum computing resources

Abstract

Systems, computer-implemented methods, and computer program products for facilitating mapping of conditional execution logic to different quantum computing resources are provided. According to embodiments, a system can include a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include a compiler component that maps a logical reference of a qubit data structure in an instruction to a first engine component and a deployment component that deploys the first engine component to a first block controller component that is operably connected to a first quantum computing resource, where the first engine component controls the first quantum computing resource based on the instruction.

Description

Background Technology

[0001] This disclosure relates to the use of quantum computing resources, and more specifically, to mapping conditionally executed logic to different quantum computing resources.

[0002] Some existing quantum computing development techniques allow developers to use simple operators to develop and implement applications for quantum computing resources. The problem with these existing techniques is that developing applications for specific quantum computing resources is challenging, as is reusing them for other quantum computing resources. This challenge arises because different quantum backend computing resources can vary significantly in their architecture, command availability, communication latency between different components, and the availability of program resources (e.g., registers). Applications with conditional execution rely on the storage and relay of information within a specific quantum computing resource, making them particularly difficult to migrate to different resources.

[0003] Given the aforementioned challenges, the problem with this existing quantum computing development technique is that, for example, by requiring a unique compiler for each instance of the application, they can involve complex and time-consuming adaptations for applications with specific quantum backend computing resources. Summary of the Invention

[0004] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, nor is it intended to define any scope of any particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, apparatuses, computer-implemented methods, and computer program products are described that facilitate mapping conditional execution logic to quantum computing resources.

[0005] According to one embodiment, a system may include: a memory storing computer-executable components; and a processor executing the computer-executable components stored in the memory. The computer-executable components may include: a compiler component that can map logical references to qubit data structures in instructions to a first engine component; and a deployment component that can deploy the first engine component to a first controller component operatively connected to a first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instructions. An advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0006] According to another embodiment, the compiler component of the system can also map the logical references of the instructions to a third engine component operatively coupled to a third qubit of a second quantum computing resource, wherein the first and second quantum computing resources are quantum computing devices with different structures. An advantage of such a system is that it enables quantum state measurement backend systems to more quickly and efficiently identify a larger number of quantum backend computing resources that can capture quantum state measurements based on criteria defined by one or more entities. Another advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0007] According to another embodiment, a computer-implemented method may include: a system operatively coupled to a processor mapping logical references to qubit data structures in instructions to a first engine component. An advantage of such a system is that it enables mapping systems for quantum computing applications to be developed and deployed more quickly and efficiently on one or more quantum computing resources.

[0008] In some embodiments, the computer-implemented method described above may further include: deploying the first engine component by the system to a first controller component operatively connected to the first quantum computing resource. In one or more embodiments, the first engine component may control the first quantum computing resource based on the instructions. An advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0009] In some embodiments, the computer-implemented method described above may further include: deploying a second engine component to a second controller component, the second controller component being operatively connected to a second qubit of the first quantum computing resource and the first controller component, wherein the second engine component controls the first quantum computing resource based on the second qubit, the first engine component, and the instructions. An advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0010] According to another embodiment, a computer program product is provided to facilitate the back-end process of quantum state measurement. The computer program product includes a computer-readable storage medium containing program instructions executable by a processor to facilitate the mapping of conditionally executable logic to a quantum computing resource. In this example, the computer program product may include a computer-readable storage medium containing program instructions executable by a processor to cause the processor to: map logical references to a qubit data structure in the instructions to a first engine component; and deploy the first engine component to a first controller component operatively connected to a first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instructions. An advantage of such a system is that it enables mapping systems for quantum computing applications to be developed and deployed more quickly and efficiently on one or more quantum computing resources.

[0011] In some embodiments, the program instructions may also be executed by the processor to cause the processor to utilize the first block controller component operatively connected to the first qubit of the first quantum computing resource; and to facilitate the first engine component to control the first quantum computing resource based on the first qubit. An advantage of such a system is that it enables mapping systems for quantum computing applications to be developed and deployed more quickly and efficiently on one or more quantum computing resources. Attached Figure Description

[0012] Figure 1 A block diagram of an example non-limiting system that facilitates mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein, is shown.

[0013] Figure 2 and Figure 3 Example non-limiting flowcharts and block diagrams of systems that facilitate the mapping of conditional execution logic to quantum computing resources, according to one or more embodiments described herein, are shown.

[0014] Figure 4 A block diagram of an example non-limiting system according to one or more embodiments described herein is shown, which facilitates the use of distributed processing to facilitate the mapping of conditional execution logic to quantum computing resources;

[0015] Figure 5 A block diagram of an example non-limiting system is shown, according to one or more embodiments described herein, that facilitates linking different distributed processing resources to achieve the benefit of improved performance including conditional execution logic mapped to quantum computing resources;

[0016] Figure 6 A block diagram of an example non-limiting system capable of including a qubit controller according to one or more embodiments is shown, the qubit controller being able to facilitate access to qubits in order to operate the compiled instructions discussed herein;

[0017] Figure 7A A block diagram illustrating a non-limiting example of an implementation of an engine component to be deployed within a block controller component according to one or more embodiments;

[0018] Figures 7B to 7C A block diagram illustrating a non-limiting example of a combiner of engine components according to one or more embodiments;

[0019] Figures 7D-7E A non-limiting description of the operation of the instruction sorting component according to one or more embodiments is provided;

[0020] Figure 8 A block diagram of an example non-limiting system that facilitates mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein, is shown.

[0021] Figure 9 A block diagram of an example non-limiting system that facilitates mapping conditional execution logic to quantum computing resources, according to one or more embodiments described herein, is shown.

[0022] Figure 10 A block diagram is shown illustrating an example non-limiting operating environment that can facilitate one or more embodiments described herein;

[0023] Figure 11 A block diagram of an example non-limiting cloud computing environment according to one or more embodiments of the present disclosure is shown;

[0024] Figure 12 A block diagram of an example non-limiting abstract model layer according to one or more embodiments of the present disclosure is shown. Detailed Implementation

[0025] The following detailed description is illustrative only and is not intended to limit the embodiments or their application or use. Furthermore, it is not intended to be construed as being limited by any explicit or implicit information presented in the prior art or invention description or detailed description sections.

[0026] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0027] Quantum computing typically uses quantum-mechanical phenomena to perform computational and information processing functions. It can be viewed as the opposite of classical computing, which typically uses transistors to manipulate binary values. That is, while classical computers operate on bit values ​​that are either 0 or 1, quantum computers operate on qubits, which are a superposition of both 0 and 1. Multiple qubits can be entangled, and interference can be used.

[0028] In view of the problems described above using some existing quantum application development and deployment techniques, this disclosure can be implemented as solutions to these problems in the form of systems, computer-implemented methods, and computer program products, which facilitate the use of compiler components that can access organizational data about specific quantum computing resources. The advantage of such systems, computer-implemented methods, and computer program products is that they can be implemented to facilitate the development and distribution of quantum applications across different quantum computing resources.

[0029] In some embodiments, this disclosure can be implemented to generate solutions to the aforementioned problems in the form of systems, computer-implemented methods, and computer program products that can organize data using information about quantum computing resources. Another advantage of such systems, computer-implemented methods, and computer program products is that they can be implemented not only to deploy applications on different quantum computing resources, but also to improve the performance of quantum applications, for example, by evaluating multiple aspects such as communication latency between different components of the quantum computing resources.

[0030] It will be understood that when an element is referred to herein as “coupled” to another element, it may describe one or more different types of coupling. For example, when an element is referred to herein as “coupled” to another element, it may describe one or more different types of coupling, including but not limited to chemical coupling, communication coupling, capacitive coupling, electrical coupling, electromagnetic coupling, inductive coupling, operational coupling, optical coupling, physical coupling, thermal coupling, and another type of coupling.

[0031] As mentioned herein, an entity may include a person, client, user, computing device, software application, agent, machine learning model, artificial intelligence, and another entity. It should be understood that such an entity may implement one or more embodiments of this disclosure as described herein.

[0032] Figure 1 A block diagram of an example non-limiting system 100, which facilitates the mapping of conditional execution logic to quantum computing resources according to one or more embodiments described herein, is shown. For the sake of brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted.

[0033] In one or more embodiments, system 100 may include a conditional execution logic mapping system 102 coupled to quantum computing resource organization data 150, both of which may be associated with a cloud computing environment. For example, the conditional execution logic mapping system 102 may be associated with the following references Figure 11 The cloud computing environment described is 1150 and the following references Figure 12 One or more functional abstraction layers (e.g., hardware and software layer 1260, virtualization layer 1270, management layer 1280, and workload layer 1290) are described and associated.

[0034] Example tasks that can be performed using cloud computing resources by one or more embodiments include, but are not limited to, interpreting and organizing data 150 using quantum computing resources and compiling jobs into deployable execution logic components. It should be noted that, as discussed in detail below, some advantageous features of the embodiments described herein include the design and distribution of conditional execution logic so that it can be executed with very low command latency, for example, by being deployed in the block controller components described in detail below. Given the description herein, those skilled in the art will understand that this low latency can be significant due to the coherence time of some of the qubits used by the system.

[0035] The conditional execution logic mapping system 102 and its components (e.g., deployment component 108, compiler component 110, etc.) can be implemented as follows (see below). Figure 11 The described cloud computing environment 1150 includes one or more computing resources and see below. Figure 12One or more functional abstraction layers (e.g., quantum software, etc.) are described to perform one or more operations according to one or more embodiments of the present disclosure described herein. For example, cloud computing environment 1150 and such one or more functional abstraction layers may include one or more classical computing devices (e.g., classical computers, classical processors, virtual machines, servers, etc.), quantum hardware and quantum software (e.g., quantum computing devices, quantum computers, quantum processors, quantum circuit simulation software, superconducting circuits, etc.), which may be used by conditional execution logic mapping system 102 and its components to perform one or more operations according to one or more embodiments of the present disclosure described herein. For example, conditional execution logic mapping system 102 and its components may employ one or more classical and quantum computing resources to perform one or more classical and quantum: mathematical functions, calculations and equations; calculation and processing scripts; algorithms; models (e.g., artificial intelligence (AI) models, machine learning (ML) models, etc.); and another operation according to one or more embodiments of the present disclosure described herein.

[0036] It should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0037] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0038] The features are as follows:

[0039] On-demand self-service: Cloud consumers can unilaterally and automatically provide computing power, such as server time and network storage, as needed, without requiring manual interaction with the service provider.

[0040] Extensive network access: Capabilities are available on the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0041] Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated based on demand. Location independence has significance because consumers typically do not control or know the exact location of the resources provided, but can specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0042] Rapid Flexibility: In some cases, the ability to scale outwards and inwards quickly and flexibly can be provided. For consumers, the available capacity often appears unlimited and can be purchased in any quantity at any time.

[0043] Measurement services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the service type (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency for both service providers and consumers.

[0044] The service model is as follows:

[0045] Software as a Service (SaaS): The capability offered to consumers is the ability to use the provider's applications running on cloud infrastructure. Applications can be accessed from various client devices through thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or even individual application capabilities, with possible exceptions such as limited user-specific application configuration settings.

[0046] Platform as a Service (PaaS): This provides consumers with the ability to deploy consumer-created or acquired applications onto cloud infrastructure using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and the configuration of any application hosting environments.

[0047] Infrastructure as a Service (IaaS): This provides consumers with the capability to deliver processing, storage, networking, and other basic computing resources that enable them to deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they do have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0048] The deployment model is as follows:

[0049] Private cloud: Cloud infrastructure operated solely by an organization. It can be managed by the organization or a third party and can exist on-site or off-site.

[0050] Community cloud: Cloud infrastructure shared by several organizations and supporting a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). It can be managed by an organization or a third party and can exist on-site or off-site.

[0051] Public cloud: Cloud infrastructure available to the general public or large industrial groups and owned by organizations that sell cloud services.

[0052] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain a single entity but are bound together by standardized or proprietary technologies that enable data and applications to be ported together (e.g., cloud bursting for load balancing between clouds).

[0053] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure of a network of interconnected nodes.

[0054] like Figure 1 As illustrated in the example embodiments, the conditional execution logic mapping system 102 may include a memory 104, a processor 106, a deployment component 108, a compiler component 110, and a bus 112.

[0055] It should be understood that the embodiments of this disclosure depicted in the various accompanying drawings are for illustrative purposes only, and therefore, the architecture of these embodiments is not limited to the systems, devices, and components depicted herein. For example, in some embodiments, system 100 and conditional execution logic mapping system 102 may also include the operating environment 1000 referenced herein and Figure 10 The various computers and computing-based components described herein. In several embodiments, such computers and computing-based components can be combined with implementations. Figure 1 It may be used in conjunction with one or more of the operations implemented by the systems, devices, components and computers shown and described in other accompanying drawings disclosed herein.

[0056] Memory 104 may store one or more computer- and machine-readable, writable, and executable components and instructions that, when executed by processor 106 (e.g., a classical processor, a quantum processor, etc.), facilitate the execution of operations defined by these executable components and instructions. For example, memory 104 may store computer- and machine-readable, writable, and executable components and instructions that, when executed by processor 106, facilitate the execution of various functions described herein related to the conditional execution logic mapping system 102, deployment component 108, compiler component 110, and another component associated with the conditional execution logic mapping system 102 (as described herein with or without reference to the various figures of this disclosure).

[0057] Memory 104 may include volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) and non-volatile memory (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.) employing one or more memory architectures. The following references system memory 1016 and... Figure 10 Other examples of memory 104 are described below. Such examples of memory 104 can be used to implement any embodiment of this disclosure.

[0058] Processor 106 may include one or more types of processors and electronic circuits (e.g., classical processors, quantum processors, etc.) that can implement one or more computer- and machine-readable, writable, and executable components and instructions that can be stored on memory 104. For example, processor 106 can perform various operations that can be specified by such computer- and machine-readable, writable, and executable components and instructions, including but not limited to logic, control, input / output (I / O), arithmetic, etc. In some embodiments, processor 106 may include one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system-on-a-chip (SoC), array processors, vector processors, quantum processors, and other types of processors. Reference is made to processing unit 1014 and... Figure 10 Other examples of processor 106 are described below. Such examples of processor 106 can be used to implement any embodiment of this disclosure.

[0059] As described herein, the conditional execution logic mapping system 102, memory 104, processor 106, deployment component 108, compiler component 110, and any other components of the conditional execution logic mapping system 102 can be communicatively, electrically, operatively, and optically coupled to each other via bus 112 to perform the functions of system 100, the conditional execution logic mapping system 102, and any components coupled thereto. Bus 112 may include one or more memory buses, memory controllers, peripheral buses, external buses, local buses, quantum buses, and another type of bus that may employ various bus architectures. Reference is made below to system bus 1018 and... Figure 10 Other examples of bus 112 are described below. Such examples of bus 112 can be used to implement any embodiment of this disclosure.

[0060] The Conditional Execution Logic Mapping System 102 may include any type of component, machine, device, facility, apparatus, and instrument, including a processor and capable of communicating effectively and operatively with wired and wireless networks. All such embodiments are contemplated. For example, the Conditional Execution Logic Mapping System 102 may include server equipment, computing devices, general-purpose computers, special-purpose computers, quantum computing devices (e.g., quantum computers), tablet computing devices, handheld devices, server-type computing machines and databases, laptop computers, notebook computers, desktop computers, cellular phones, smartphones, consumer appliances and instruments, industrial and commercial equipment, digital assistants, multimedia internet-enabled phones, multimedia players, and another type of device.

[0061] The conditional execution logic mapping system 102 can be coupled (e.g., communication ground, electrical ground, operational ground, optical ground, etc.) to one or more external systems, sources, and devices (e.g., classical and quantum computing devices, communication devices, etc.) via data cables (e.g., High Definition Multimedia Interface (HDMI), Recommended Standard (RS) 232, Ethernet cables, etc.). In some embodiments, the conditional execution logic mapping system 102 can be coupled (e.g., communication ground, electrical ground, operational ground, optical ground, etc.) to one or more external systems, sources, and devices (e.g., classical and quantum computing devices, communication devices, etc.) via networks.

[0062] In some embodiments, such a network may include wired and wireless networks, including but not limited to cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, the conditionally enforced logic mapping system 102 can communicate with one or more external systems, sources, and devices (e.g., computing devices) using virtually any desired wired or wireless technology (and vice versa), including but not limited to: Wi-Fi, Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Global Microwave Access Interoperability (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), 3GPP Long Term Evolution (LTE), 3GPP2 Ultra Mobile Broadband (UMB), High Speed ​​Packet Access (HSPA), Zigbee and other 802.XX wireless technologies and traditional telecommunications technologies. Session Initiation Protocol (SIP) RF4CE protocol, wireless HART protocol, 6LoWPAN (IPv6 over low-power wireless local area networks), Z-Wave, ANT, ultra-wideband (UWB) standard protocol, and other proprietary and non-proprietary communication protocols. In such an example, the conditional execution logic mapping system 102 may therefore include hardware (e.g., central processing unit (CPU), transceiver, decoder, quantum hardware, quantum processor, etc.), software (e.g., a set of threads, a set of processes, executing software, quantum pulse scheduling, quantum circuits, quantum gates, etc.), or a combination of hardware and software that facilitate the transfer of information between the conditional execution logic mapping system 102 and external systems, sources, and devices (e.g., computing devices, communication devices, etc.).

[0063] The Conditional Execution Logic Mapping System 102 may include one or more computer- and machine-readable, writable, and executable components and instructions that, when executed by processor 106 (e.g., a classical processor, a quantum processor, etc.), facilitate the execution of operations defined by such components and instructions. Further, in various embodiments, as described herein with or without reference to the accompanying drawings, any component associated with the Conditional Execution Logic Mapping System 102 may include one or more computer- and machine-readable, writable, and executable components and instructions that, when executed by processor 106, facilitate the execution of operations defined by such components and instructions. For example, deployment component 108, compiler component 110, and any other component associated with the Conditional Execution Logic Mapping System 102 disclosed herein (e.g., communicatively, electronically, operatively, and optically coupled to and employed by the Conditional Execution Logic Mapping System 102) may include such computer- and machine-readable, writable, and executable components and instructions. Therefore, according to various embodiments, the conditional execution logic mapping system 102 and any components associated therewith, as disclosed herein, can employ processor 106 to execute such computer- and machine-readable, writable, and executable components and instructions to facilitate the performance of one or more operations described herein with reference to the conditional execution logic mapping system 102 and any such components associated therewith.

[0064] The conditional execution logic mapping system 102 can facilitate (e.g., via processor 106) the execution of operations performed by one or more of its components (e.g., deployment component 108, compiler component 110, etc.) and associated with one or more of its components (e.g., deployment component 108, compiler component 110, etc.). For example, the conditional execution logic mapping system 102 can facilitate (e.g., via processor 106) the definition of system configuration and programming functions for quantum computing resources.

[0065] In another example, the conditional execution logic mapping system 102 can facilitate (e.g., via processor 106) the mapping of logical references to a qubit data structure in an instruction to a first engine component by a system operatively coupled to the processor, and the deployment of the first engine component to a first block controller component operatively connected to a first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instruction. In a variant of this example, the conditional execution logic mapping system 102 can facilitate (e.g., via processor 106) the deployment of a second engine component to a second block controller component operatively connected to a second qubit of the first quantum computing resource and the first block controller component, wherein the second engine component controls the first quantum computing resource based on the second qubit, the first engine component, and the instruction.

[0066] In one or more embodiments, compiler component 110 may (e.g., via processor 106) map logical references to the qubit data structure in the instructions to the first engine component. Furthermore, deployment component 108 may deploy the first engine component to a first block controller component operatively connected to the first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instructions. According to another embodiment, as combined below… Figure 2 The compiler component 110 discussed can also map the program logic of job 225 to a third engine component that is operatively coupled to a third qubit of a second quantum computing resource, wherein the first quantum computing resource and the second quantum computing resource are quantum computing devices with different structures.

[0067] Figure 2 and Figure 3 Example non-limiting flowcharts 300 and system 200, according to one or more embodiments described herein, are shown as block diagrams that can facilitate the mapping of conditional execution logic to quantum computing resources. For brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted.

[0068] In one or more embodiments, system 200 may include compiler component 110, deployment component 108, quantum computing resources 250A-B, and any other components that facilitate the functionality of system 200, as described below. As discussed further below, compiler component 110 may receive information and organization data 210A-B corresponding to job 225.

[0069] Given the problem of reusing jobs (e.g., job 225) with multiple quantum computing resources 250A-B using some existing methods as described above, such as Figure 2The present disclosure can be implemented to produce a solution to the problem as described herein and discussed below. The methods described herein can take the form of systems, computer-implemented methods, and computer program products capable of compiling jobs 225 for multiple quantum computing resources 250A-B using a single compiler component 110 (e.g., not necessarily using different versions of compiler component 110 for different quantum computing resources 250A-B). Once compiled, deployment component 108 can be guided by the compiled job 225 to deploy different engine components to different elements of the quantum computing resources 250A-B.

[0070] Given the description herein, those skilled in the art should recognize that the different characteristics of quantum computing resources can vary between systems, and these differences currently require customization of the time consumption of compilation instructions to improve the possibility of unified functionality between quantum computing resources 250A-B. Examples of differences between quantum computing resources 250A-B that can affect job deployment include, but are not limited to, the structure and interconnections of various layers that may or may not be involved (e.g., the following with...). Figure 4 and 5 Together, we discussed layers, the location and mapping of registers implemented in resources, support for conditional logic and extended measurements, and latency associated with paths between components. This utilizes the following... Figure 6 Further differences are discussed in the detailed examples of the implementation methods described in Figure 7.

[0071] In the example implementation, after the deployment component 108 deploys the program logic at an element of quantum computing resource 250A, the compiler component 110 can use organization data 210B to map the program logic of job 225 to an engine component that is operatively coupled to an element of quantum computing resource 250B. The advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0072] Figure 3 The description includes features that can facilitate the above-mentioned aspects. Figure 2 Example implementations of the features of the beneficial results discussed. For illustrative purposes, Figure 3 The flowchart depicts a conditional abstraction layer representing the general structure and characteristics that can be used to select quantum computing resources. Some of the embodiments discussed herein can be used with these quantum computing resources, for example, to increase the likelihood of successful execution.

[0073] In one or more embodiments, various different quantum computing resources that can be utilized can be improved by using organizational data 210A-B. Therefore, as Figure 3As depicted, by using organization data 210A, job instructions 310, together with box 325, can be mapped and scheduled 320 for specific quantum computing resources 250A. In one implementation, specific characteristics of the resource can be used to customize the conditional abstraction layer by using parameters.

[0074] See below for reference Figure 4 Among the additional features discussed in section -7, in one or more embodiments, once parameterized instructions (e.g., block 325) are generated for a specific quantum computing resource, the functionality 345 of the instructions can be assigned to different execution components for execution, for example, in engine component 340, which is generated by compiler component 110 and deployed to block controller component by deployment component 108. Thus, at block 350, as generally described above, one or more embodiments can implement job instructions 310 as commands for specific quantum computing resources 250A-B in various ways.

[0075] It should be understood that compiling a single representation of a job and facilitating the use of the same job on multiple quantum machines reduces the customization work required for different machines and improves the standardization of deployment across different machines. These and other examples discussed herein illustrate, in some cases, the reduction in computational costs that can be achieved by using the different embodiments described herein.

[0076] Figure 4 A block diagram of an example non-limiting system 400, according to one or more embodiments described herein, is shown that facilitates the use of distributed processing to enable the mapping of conditional execution logic to quantum computing resources. For brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted.

[0077] like Figure 4 As shown, in one or more embodiments of system 400, block controller assemblies 440A-C and qubits 485A-C arranged in a hierarchical structure, as well as any other components that facilitate the functionality of system 200, as described below. Block controller assemblies 440A to 440B may respectively include engine assemblies 480A to 480B, digital-to-analog converters (DACs) 475A to 475B, analog-to-digital converters (ADCs) 472A to 472B, and qubit controllers 470A to 470B.

[0078] It should be understood that throughout this disclosure, the term "block controller component" is used to describe the destination of example deployments of various elements of quantum computing resources, from customized program logic to the target. In one or more embodiments, one or more block controller components 440A-440B may be programmed and have logic implemented (e.g., hereinafter referred to as...) received from deployment component 108. Figure 4This example is implemented using a Field Programmable Gate Array (FPGA). This example is non-limiting, and other types of program storage devices can be used to facilitate the use of the distributed engine component 480A-B.

[0079] exist Figure 4 In the example shown, a sample job could be created that tests the conditions in the first qubit and, based on the test results, applies a quantum gate using the second and third qubits. For this example, the above-mentioned... Figure 4 The components are part of the quantum computing resource 250A discussed above. Thus, in this example, in order to compile and have the structure of the resource, compiler component 110 identifies organization data 210A. Using organization data 210A, in this example, the compiler component selects qubit 485A-C as reference first, second, and third qubits, respectively, based, for example, on the characteristics of qubit 485A-C and its arrangement within the quantum computing resource 250A.

[0080] Due to this qubit selection, in this example, the block controller components 440A-B can be selected by the compiler component 110, for example, because these controllers are described using other hardware associated with the control of the respective bits. Based on the selection of the block controller components 440A-B, in this example, as detailed below, different tasks can be assigned to the block controller components 440A-B, and paths can be selected for intermediate data values ​​(e.g., the result of testing the first qubit) and the result of applying a specified gate.

[0081] After the engine components 480A-B are deployed, operation of this example embodiment can begin with the engine component 480A sending data corresponding to the test to the DAC 475A and the qubit controller 470A via the excitation channel 442A. Through the operation of the qubit controller 470A, the result is received from the qubit 485A and converted into digital data by the ADC 472A. The execution of the program logic of the engine component 480A can be resumed by receiving this digital data, and the result can be interpreted as a true (1) or false (0) value, which can be stored in register 460A. Continuing this example, automatically or through the operation of the program logic of the engine component 480A, condition bits can be relayed to register 460B at the block controller component 440B.

[0082] For this relay operation, the following should be noted: Figure 4As depicted, two paths are shown between registers 460A and 460B: a hierarchical route via switch 410 and a direct route between the hardware of block controller components 440A-B (e.g., peering connection 405). In one or more embodiments, the existence of these routes and the estimated latency of each route may be stored in organization data 210A. In this example, compiler component 110 evaluates both routes, and peering connection 405 is selected for the relay of the result values ​​from registers 460A to 460B, and this selection is incorporated into the logic of block controller component 440A. However, if an alternative route through switch 410 is selected, one or more embodiments may have already deployed logic for processing the result values ​​in block controller component 440C.

[0083] Continuing this example, block controller component 440B receives the result value from register 460B by employing program logic deployed by compiler component 110, and the program logic determines whether to apply a specified gate using qubit 485B-C. In this example, when a condition indicates gate application, excitation channel 442B is triggered to send data corresponding to the applied gate to DAC 475B and qubit controller 470B. The gate is applied via operation of qubit controller 470A, and a success indicator is detected by qubit controller 470B. This success indicator can be converted into digital data by ADC 472B via operation of engine component 480B's logic. Ending this example, the execution of the compiled and deployed example job concludes by receiving and reporting the success of the applied gate application.

[0084] It should be understood that this example is non-restrictive and is intended to illustrate one approach that can be used to implement the program logic deployed above.

[0085] Figure 5 A block diagram of an example non-limiting system 500, according to one or more embodiments described herein, is shown, which facilitates the linking of different distributed processing resources to achieve improved performance including conditional execution logic mapped to quantum computing resources. For brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted. In one or more embodiments, system 500 may include qubits 580A-D, stage 1 (L1) qubit controllers 570A-D, stage 2 (L2) engine components 560A-D, stage 3 (L3) engine components 585A-B, and stage 4 (L4) engine component 587. It should be noted that in this example, the block controller component for the engine components and the above-mentioned... Figure 4 The DAC or ADC described.

[0086] As mentioned above, it is possible to utilize Figure 5One aspect of the one or more embodiments discussed is the selection of the location for deploying engine components 560A-D and the paths that can be evaluated and selected by compiler component 110 to implement the compiled job (e.g., paths that can be used to pass values ​​to different components according to program logic). As an illustration of one or more benefits that can be achieved by using some embodiments, an example can be considered where the sole relay of the programmed value is performed hierarchically, for example, where the value to be relayed by L2 engine component 560C is not relayed by peer connection 505B, but via L3 engine component 585A, L4 engine component 587, and L3 engine component 585B.

[0087] To avoid this, one or more embodiments can advantageously organize the links of engine components in any manner supported by hardware connectivity within the quantum computing resource, wherein the connection topology includes, but is not limited to, peer-to-peer, interactive grids, rings, trees, and hierarchical arrangements. It should be noted that although the depicted example uses a four-layer hierarchical structure, this arrangement is merely illustrative, and one or more embodiments are capable of implementing other numbers of layers. An advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources, for example, by compiling applications using organized data for an improved use of the structure of a particular quantum computing resource. Examples of negative consequences that can be avoided by using organized data in this structure include congestion points (e.g., blockage points) between quantum computing resource elements.

[0088] exist Figure 5 In the additional embodiment shown, it should be noted that qubit 580C is marked as out of service. In existing implementations of implantation that select qubits 580A-D for operation, this up-to-date information about the specific resources of the quantum computing device would not necessarily be evaluated. In contrast, in one or more embodiments, the operational states of different components of the quantum computing resources can be included in the resource organization data, as described above. This state can range from the depicted example (e.g., out of service) to measurements of component performance (e.g., processing speed measurements).

[0089] Figure 6 A block diagram of an example non-limiting system 600, according to one or more embodiments, is shown, which can include components such as a qubit controller that facilitates access to qubits to operate the compiled instructions discussed herein. For brevity, repeated descriptions of similar elements and processes used in corresponding embodiments are omitted. For example, system 600 includes a qubit controller 615B, acquisition channels 630A-C, a device layer 612, and qubits 690A-B.

[0090] In one or more embodiments, to facilitate conditional execution of commands based on qubit values, the qubit controller may have additional features that facilitate condition evaluation, and different qubit controller operations may be based on this evaluation. For example, system 600 includes two qubit controllers 615A-B, each having an example drive channel (D), a measurement channel (M), and a U channel for use with device layer 612. In one or more embodiments, each of the aforementioned excitation channels may have a multiplexer (MUX) for testing conditions (e.g., conditions 610A-D and 612A-D). In one or more embodiments, this can be implemented to improve the performance of conditional execution applications, for example, because the source of the condition bit being tested can be changed during circuit execution. It should be understood that this logic can be controlled by compiler component 110 as part of deploying program logic on a particular quantum computing resource.

[0091] In an additional feature, to reduce the delay in making the result of a qubit measurement available, in one or more embodiments, the registers of channels 630A-C can be used for each acquisition channel 670A-C. For example, the qubit measurement can be passed to the corresponding register when it is generated, and the register output can be directly routed to the excitation channel in the same qubit controller or to other conditional execution logic outside the block controller by program logic.

[0092] It should be understood that for many of the memory resources discussed herein (e.g., registers, memory, buffers), the location, performance, latency, size, and availability of such resources can be incorporated into organization data used by compiler component 110. Given the description herein, those skilled in the art will understand the different ways such data can be used to improve performance, as well as other suggested information that can be used similarly.

[0093] Figure 7A A block diagram illustrating a non-limiting example 700 of an implementation of an engine component to be deployed in a quantum computing resource (e.g., within a block controller) according to one or more embodiments is shown. For brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted. As depicted, example 700 of the conditional engine component 790 includes receive buffers 720A-C, a receive register 760, a result register 750, combiners 740A-B, and combiner-specific instruction sequencing components (ISEQ) 724A-B (hereinafter referred to as...). Figure 7D -E discussion), and sending channels 710A-C.

[0094] exist Figure 7AIn the non-limiting examples depicted herein, an engine component may be referred to as a conditional engine component, such as conditional engine component 790, when one or more embodiments of the engine component described herein have specific features that facilitate conditional execution. It should be noted that while examples of conditional execution are used throughout this disclosure, these are intended to be illustrative only, and the embodiments are not limited thereto; for example, other combinations of programming elements may be used with one or more embodiments. Returning to the above regarding... Figure 4 The described example of conditional execution involves a conditional engine component 790 that, after measuring a value from a qubit, can convert the measurement into a testable conditional bit that is distributed to another engine component for conditional use. As described below, one or more embodiments can utilize additional features to further improve the performance of the conditional execution process.

[0095] In one or more embodiments, the engine component can be configured to programmatically combine and pass qubit values ​​around the system in one way as described above, using existing commands implemented in some systems. For example, in one or more embodiments, a set of flat global registers and operators that use them. Example operators ('copy' and Boolean functions such as 'OR', 'NOR', shift, rotate, etc.) may have binary qubit measurements distinguished after shifting between registers to facilitate their combination with Boolean functions, for example, to produce single-bit testable conditions. A waveform player can then use these testable conditions to determine whether a quantum gate should be applied. It should be understood that by combining the use of these operators with the operations of compiler component 110 and deployment component 108 (as described and suggested herein), the performance, flexibility, and ease of distributing the application to additional resources can be improved. Some elements of an embodiment of the conditional engine component 790 are described below.

[0096] The receive buffer 720A-C is described as follows:

[0097] In an example method of implementing the bfunc command, in one or more embodiments, binary qubit values ​​can be received by an engine component (e.g., conditional engine component 790) through a bit array referred to as receive buffers 720A-C. At the start of the job, all receive buffers can begin to fill and remain filled. In one or more embodiments, the presence and size of the receive buffers can be available to compiler component 110 to help improve the operation of the program logic. For example, if more qubit measurements arrive than the buffers can hold, this can be considered an error, and compiler component 110 can be configured to minimize or eliminate the possibility of such an error.

[0098] Receive register 760 is described as follows:

[0099] For processing by combiners 740A-B, in which Boolean functions can be executed, the receive buffer values ​​can be concatenated into a single receive register 760 vector. In one or more embodiments, the quantum computing resources can implement this register as a virtual or physical concatenation. In virtual concatenation, one or more embodiments can utilize the receive register 760 as a virtual object; for example, the 'copy' command cannot be used to copy qubit values ​​from the receive buffer 720A into the receive register 760.

[0100] The result register 750 is described as follows:

[0101] In one or more embodiments, as depicted, the result register 750 can receive and store the results of combiners 740A-B for further use. In contrast, the receive register 760 can be written to by other elements, such as the qubit controller and other engine components. In one example, to implement the 'copy' command or allow the result of the 'bfunc' command to be used by another part of the system, the result can be fed back to combiners 740A-B as input. Furthermore, as described above regarding... Figure 4 The values ​​discussed can also be sources of bits sent to other blocks (e.g., values ​​relayed using peer connection 405), such as relaying values ​​from block controller component 440A to register 460A of block controller component 440B. In some implementations, the generated input vector can be the same for all combiners in the conditional engine component 790.

[0102] In another embodiment, receive register 760 and result register 750 can be cascaded and passed to combiner 740A-B, which can execute the 'bfunc' command by combining the selected inputs to receive register 760 into a single binary output. Further details regarding combiner 740A-B are provided in the following reference. Figure 7B To provide.

[0103] Figures 7B to 7C A block diagram illustrating a non-limiting example 702 of a combiner for engine components according to one or more embodiments is shown. Example 702 includes a combiner 740A receiving instruction sequence information (see below) from an instruction sequencer 789. Figure 7D -E discussion), where input 783 and output 787 go to and from other system processes mentioned above.

[0104] In one or more embodiments, in addition to the implementation of Boolean functions, as described above, combiners 740A-B may have additional features that can be utilized by one or more embodiments to further improve the performance of the conditional engine component 790. For example, input 783 to combiner 740A may be masked individually based on settings from compiler component 110. The advantage of this masking capability includes the ability to improve processing efficiency by facilitating the selection of a subset of inputs on which combiner 740A operates at a given time.

[0105] In another application of masking: In one or more embodiments, at the start of a job, the contents of all receive buffers 720A-C and result register 750 may be considered to contain unknown values, for example, because they may not be reset between job or experimental iterations. In one or more embodiments, organizational data describing quantum computing resources may include indications that the initial values ​​of the buffers 720A-C and result register 750 are unknown. Based on this, compiler component 110 includes configuration settings for initially masking inputs from these sources, for example, preventing unknown values ​​from affecting the combiner output and the overall result of the job. In one or more embodiments, this masking setting may be received from instruction sequencer 789 as part of the overall ordering of commands. In some implementations, further configuration of the engine component by compiler component 110 can be enabled by compiler component 110 selecting and setting the number of combiners in the engine component.

[0106] In the related functions of combiners 740A-B, in addition to masking settings, the instruction sequencer can also provide patterns to be applied to masked input values. Similar to the other settings mentioned above, these patterns are affected by program control generated and deployed by compiler component 110.

[0107] Figure 7C Example table 703 provides binary codes for selecting functions to be executed by combiners 740A-B. This table includes function selection codes 782 with example operations that can be executed by combiners 740A-B. Similar to a masking setup, these function codes can be received from instruction sequencer 789 as part of the overall command sequence. The following... Figures 7D-7E Additional details about the instruction sequencing component are provided.

[0108] Figures 7D-7E A non-limiting description of the operation of an instruction sequencing component according to one or more embodiments is provided. Figure 7D An example list 704 of commands for quantum computing resources, such as utilizing hardware control field 774, is shown. In one or more embodiments, compiler 110 may generate such a list for instruction sequencer 789 to control program execution.

[0109] In an advantageous implementation of this feature, one or more embodiments may compress this list 777 to a smaller size, for example, by conserving system resources through limiting processing. In example 706, Figure 7E A compressed list of results that can be assigned to engine components 480A-B to provide a sequence of instructions is shown. In this example, the hardware control field 774 is specified by compiler component 110 as five cycles to be executed during the first five cycles of job execution. In one or more embodiments, before distributing the information sequencer list 777 as part of the distributed program logic, references to these five sequential hardware control fields can be simplified, for example, by specifying the cycle number 772(5) and the hardware control field 774. Figure 7D The compressed 778 entries described in -E.

[0110] In a specific type of entry within sequencer entry 773, a zero (0) value 769 and a hardware control field 776 may be included. In some implementations, the value 769 may execute instructions that do not need to be specified by compiler component 110 (e.g., hardware control field 776). For example, in one or more embodiments, the value 769 may cause the initialization of system data storage resources, for example, to avoid the unknown values ​​pointed out above in the discussion of combiners 740A-B. In another example, in one or more embodiments, the value 269 may be used to apply a valid hardware control field between the execution of jobs. In these embodiments, the value 269 being zero (0) indicates an indeterminate amount of time associated with these processes.

[0111] In one or more embodiments, the functionality of the instruction sequencer 789 can be specifically provided to selected components. For example, to further improve performance in certain cases, each combiner may have its own instruction sequencer (e.g., ISEQ742A-B) that can facilitate the compiler component 110 in scheduling 'copy' and 'bfunc' operations during compilation jobs. In other embodiments, additional components that may use the compressed instruction sequencer 789 include (but are not limited to) the output registers of acquisition channels 630A-630C, conditional selection multiplexers in the qubit controller (e.g., test conditions 610A-610D), and registers in the conditional engine component that include a result register 750 selector and a transmit register selector for transmit channel 710. While similar in use, each component is able to utilize the compressed instruction sequencer 789 with hardware control fields tailored for the logic managed by the sequencer.

[0112] Figure 8A flowchart is shown of an example non-limiting computer implementation of a method 800 that facilitates mapping conditional execution logic to quantum computing resources according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted.

[0113] At 802, the computer-implemented method 800 may include a system operatively coupled to the processor mapping logical references to a qubit data structure in instructions to a first engine component. For example, in one or more embodiments, method 800 may include a system 100 operatively coupled to processor 106 mapping logical references to a qubit data structure in instructions in job 225 to a first engine component (e.g., engine component 480A).

[0114] At 804, the computer-implemented method 800 may include deploying a first engine component by the system to a first block controller component operatively connected to a first quantum computing resource. For example, in one or more embodiments, method 800 may include deploying engine component 480A by system 100 to a block controller component 440A operatively connected to a quantum computing resource. In one or more embodiments, the conditional execution logic mapping system 102 can provide technical improvements to the systems, devices, components, operational steps, and processing steps associated with the various techniques identified above. For example, the conditional execution logic mapping system 102 may include mapping logical references to the qubit data structure in the instructions of a job to the first engine component. An advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0115] In some embodiments, method 800 may further include deploying a first engine component to a first controller component operatively connected to a first quantum computing resource. In one or more embodiments, the first engine component may control the first quantum computing resource based on the instructions. An advantage of such a system is that it enables mapping systems for quantum computing applications to develop and deploy applications more quickly and efficiently on one or more quantum computing resources.

[0116] It should be understood that the Conditional Execution Logic Mapping System 102 provides a novel approach driven by relatively new quantum computing technologies. For example, the Conditional Execution Logic Mapping System 102 provides a new method for developing and implementing quantum computing software across various quantum computing platforms.

[0117] At least in practical implementations, on a large scale, the Conditional Execution Logic Mapping System 102 can employ a combination of hardware and software to solve problems that are inherently highly technical, non-abstract, and cannot be performed by humans as a set of mental actions. In some embodiments, one or more of the processes described herein can be executed by one or more dedicated computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, etc.) to perform the defined tasks associated with the different technologies identified above. The Conditional Execution Logic Mapping System 102 and / or its components can be used to solve new problems arising from advancements in the technologies mentioned above, as well as from the adoption of quantum computing systems, cloud computing systems, computer architectures, and / or other technologies.

[0118] It should be understood that, in one or more embodiments, the conditional execution logic mapping system 102 may utilize different combinations of electrical components, mechanical components, and circuits that cannot be replicated in the human mind or performed by a human. Given the description herein, those skilled in the art will understand that, for large-scale practical implementation, the various operations that can be performed by the conditional execution logic mapping system 102 and its components exceed the capabilities of the human mind. For example, the amount of data processed by the conditional execution logic mapping system 102 over a specific time period, the speed at which such data is processed, or the type of data processed may be greater than, faster than, or different from the amount, speed, or type of data processed by the human mind over the same time period.

[0119] According to several embodiments, the conditional execution logic mapping system 102 can also perform one or more other full operations (e.g., full power-on, full execution, etc.) while simultaneously performing the various operations described herein. It should be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be understood that the conditional execution logic mapping system 102 may include information that is impossible for an entity (such as a human user) to obtain manually. For example, the type, quantity, and / or diversity of information included in the conditional execution logic mapping system 102, deployment component 108, and / or compiler component 110 may be more complex than information that a human user could obtain manually.

[0120] Figure 9 A flowchart of an example non-limiting computer implementation of a method 900, which facilitates mapping conditional execution logic to quantum computing resources according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of similar elements and processes employed in the corresponding embodiments are omitted.

[0121] At 902, the computer-implemented method 900 may include receiving a job with an identified quantum computing resource. At 904, organization data for the quantum computing resource may be identified. At 906, job instructions may be compiled based on the organization data. At 907, engine components generated during compilation may be deployed to block controller components at the identified quantum computing resource. At 908, during the execution of the deployed compiled job, the block controller for the target gate may test the result bit received from a measurement of another controller. At 910, no gate is applied when the condition is false, and at 914, a gate specified by the program logic is applied when the condition is true (1).

[0122] For the sake of simplicity, the computer-implemented method is depicted and described as a series of actions. It will be understood and appreciated that the invention is not limited to the actions and their order shown; for example, actions may occur in various orders and concurrently, and may occur alongside other actions not presented or described herein. Furthermore, not all actions shown are necessary to implement the computer-implemented method according to the disclosed subject matter. Additionally, those skilled in the art will understand and appreciate that the computer-implemented method may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the computer-implemented methods disclosed below and throughout this specification can be stored on an article of manufacture to facilitate the transfer and assignment of these computer-implemented methods to a computer. As used herein, the term "article of manufacture" is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0123] In order to provide context for the various aspects of the disclosed subject, Figure 10 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 10 A block diagram is shown illustrating an example non-limiting operating environment that can facilitate one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0124] refer to Figure 10The suitable operating environment 1000 for implementing various aspects of this disclosure may further include a computer 1012. The computer 1012 may further include a processing unit 1014, system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to system memory 1016, to the processing unit 1014. The processing unit 1014 may be any of a variety of available processors. Dual microprocessor and other multiprocessor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of a variety of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, and local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronic Devices (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0125] System memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. The Basic Input / Output System (BIOS), which contains basic routines such as those for transferring information between components within computer 1012 during startup, is stored in non-volatile memory 1022. Computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 10 Disk storage device 1024 is shown. Disk storage device 1024 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Disk storage device 1024 may also include a single storage medium or a storage medium combined with other storage media. To facilitate connection of disk storage device 1024 to system bus 1018, a removable or non-removable interface, such as interface 1026, is typically used. Figure 10 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1000 is also described. Such software may also include, for example, an operating system 1028. The operating system 1028, which can be stored on a disk storage device 1024, is used to control and allocate the resources of the computer 1012.

[0126] System application 1030 utilizes operating system 1028 to manage resources through program modules 1032 and program data 1034 stored, for example, on system memory 1016 or disk storage device 1024. It should be understood that this disclosure can be implemented using various operating systems or combinations of operating systems. Users input commands or information into computer 1012 via input device 1036. Input device 1036 includes, but is not limited to, pointing devices such as mice, trackballs, pens, touchpads, keyboards, microphones, joysticks, game controllers, disc satellite antennas, scanners, TV tuners, digital cameras, digital camcorders, webcams, etc. These and other input devices are connected to processing unit 1014 via system bus 1018 and interface port 1038. Interface port 1038 includes, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1040 uses some of the ports of the same type as input device 1036. Therefore, for example, a USB port can be used to provide input to computer 1012 and output information from computer 1012 to output device 1040. Output adapter 1042 is provided to illustrate the existence of certain output devices 1040, such as monitors, speakers, and printers, as well as other output devices 1040 that require dedicated adapters. By way of example and not limitation, output adapter 1042 includes graphics cards and sound cards that provide a means of connection between output devices 1040 and system bus 1018. It should be noted that other devices and systems provide input and output capabilities, such as remote computer 1044.

[0127] Computer 1012 can operate in a networked environment via a logical connection to one or more remote computers (such as remote computer 1044). Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other common network node, and typically may also include many or all of the elements described relative to computer 1012. For simplicity, only storage device 1046 is shown alongside remote computer 1044. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and then physically connected via communication connection 1050. Network interface 1048 includes wired and wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks like Integrated Services Digital Network (ISDN) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 1050 refers to the hardware / software used to connect network interface 1048 to system bus 1018. Although communication connection 1050 is shown as being inside computer 1012 for clarity, it can also be external to computer 1012. For illustrative purposes only, the hardware / software used for the connection to network interface 1048 may also include internal and external technologies such as modems including conventional telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0128] Now for reference Figure 11 The figure depicts an illustrative cloud computing environment 1150. As shown, the cloud computing environment 1150 includes one or more cloud computing nodes 1110 to which local computing devices used by cloud consumers can communicate. These local computing devices include, for example, personal digital assistants (PDAs) or cellular phones 1154A, desktop computers 1154B, laptop computers 1154C, and automotive computer systems 1154N. Although... Figure 11 As not shown, cloud computing node 1110 may also include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, etc.), with which the local computing devices used by cloud consumers can communicate. Nodes 1110 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows cloud computing environment 1150 to provide Infrastructure as a Service, Platform as a Service, and Software as a Service without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 11The types of computing devices 1154A-N shown are intended to be illustrative only, and computing node 1110 and cloud computing environment 1150 can communicate with any type of computerized device via any type of network and network-addressable connection (e.g., using a web browser).

[0129] Now for reference Figure 12 This demonstrates the 1150 cloud computing environment ( Figure 11 This provides a set of functional abstraction layers. It should be understood beforehand that... Figure 12 The components, layers, and functions shown are intended to be illustrative only, and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0130] The hardware and software layer 1260 includes hardware and software components. Examples of hardware components include: a host 1261; a server 1262 based on a RISC (Reduced Instruction Set Computer) architecture; a server 1263; a blade server 1264; a storage device 1265; and network and networking components 1266. In some embodiments, software components include network application server software 1267, database software 1268, and quantum platform routing software (…). Figure 12 (not shown in the image) and quantum software ( Figure 12 (Not shown in the image).

[0131] The virtualization layer 1270 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 1271; virtual storage device 1272; virtual network 1273, including virtual private network; virtual application and operating system 1274; and virtual client 1275.

[0132] In one example, management layer 1280 may provide the following functionalities: Resource Provisioning 1281 Provides dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and Pricing 1282 Provides cost tracking as resources are utilized within the cloud computing environment and bills or invoices for the consumption of these resources. In one example, these resources may include application software licenses. Security Provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User Portal 1283 Provides consumers and system administrators with access to the cloud computing environment. Service Level Management 1284 Provides allocation and management of cloud computing resources to ensure that required service levels are met. Service Level Agreement (SLA) Planning and Fulfillment 1285 Provides pre-scheduling and procurement of cloud computing resources, anticipating future requirements for those resources according to the SLA.

[0133] Workload layer 1290 provides examples of functionalities that can leverage a cloud computing environment. Non-limiting examples of workloads and functionalities that can be provided from this layer include: mapping and navigation 1291; software development and lifecycle management 1292; virtual classroom education delivery 1293; data analytics and processing 1294; transaction processing 1295; and quantum state measurement logic software 1296.

[0134] This invention can be a system, method, apparatus, and computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combinations of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0135] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, local area network, wide area network, and wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(e.g., the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can connect to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can connect to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of the invention, electronic circuits including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can execute computer-readable program instructions to personalize the electronic circuits by utilizing state information of computer-readable program instructions.

[0136] Various aspects of the present invention are described herein with reference to flowchart illustrations and block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and block diagrams, and combinations of blocks in the flowchart illustrations and block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and block diagrams. The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational actions to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / actions specified in one or more blocks of the flowchart illustrations and block diagrams.

[0137] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a non-consecutive order as shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0138] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure can also be implemented in conjunction with other program modules or can be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and implement specific abstract data types. Furthermore, those skilled in the art will understand that the computer implementation methods of the present invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules can reside in local and remote memory storage devices. For example, in one or more embodiments, computer-executable components can be executed from memory, which may include or consist of one or more distributed memory cells. As used herein, the terms “memory” and “storage cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing code from computer-executable components in a distributed manner, for example, multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" can encompass a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0139] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., can refer to and include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein can be hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and a computer. For illustration, applications running on a server and servers can both be components. One or more components can reside within a process and a thread of execution, and components can reside on a single computer and be distributed across two or more computers. In another example, a corresponding component can be executed from various computer-readable media on which various data structures are stored. These components can communicate via local and remote processes, for example, based on signals having one or more data packets (e.g., data from a component via which it interacts with a local system, another component in a distributed system, and other systems via a network such as the Internet). As another example, a component can be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by software or firmware applications executed by a processor. In this scenario, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a device that provides a specific function through electronic components rather than mechanical parts, wherein the electronic components can include a processor or other means to execute software or firmware that at least partially endows the electronic components with the functions. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0140] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Furthermore, unless otherwise specified or clear from the context to mean the singular form, the articles "a" and "an" as used in this specification and figures should generally be interpreted as meaning "one or more". As used herein, the terms "example" and "exemplary" are used to indicate that something is used as an example, instance, or illustration. To avoid ambiguity, the subject matter disclosed herein is not limited to these examples. Moreover, any aspect or design described herein as "example" and "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0141] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can employ nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "storage device," "data storage," "data storage device," "database," and substantially any other information storage component related to the operation and function of a component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may be used as, for example, external cache memory. For example, by way of illustration and not limitation, RAM may be available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0142] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components or computer-implemented methods in order to describe this disclosure; however, those skilled in the art will recognize that many other combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a manner similar to how the term "comprising" is interpreted when used as a transitional term in the claims.

[0143] Various embodiments have been described for illustrative purposes, but these descriptions are not exhaustive or intended to limit them to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer system, comprising: Memory, which stores computer-executable components; as well as A processor that executes the computer-executable components stored in the memory, wherein the computer-executable components include: The compiler component maps logical references to the qubit data structure in the instructions to the first engine component, and A deployment component that deploys the first engine component to a first block controller component operatively connected to the first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instructions; The compiler component is a single-version compiler component. Using the single-version compiler component for different quantum computing resources facilitates the use of the same job on multiple quantum machines, which can reduce the customization work required for different machines and improve the standardization of deployment on different quantum machines, thereby reducing computing costs. The block controller component includes one or more engine components, one or more digital-to-analog converters, or one or more analog-to-digital converters; Based on the instructions, the deployment component also deploys the second engine component to the second block controller component, which is operatively connected to the second qubit of the first quantum computing resource and the first block controller component. The second engine component controls the first quantum computing resource based on the second qubit, the first engine component, and the instructions.

2. The system according to claim 1, wherein, The first controller component is operatively connected to a first qubit of the first quantum computing resource, and the first engine component further controls the first quantum computing resource based on the first qubit.

3. The system according to claim 2, wherein, The first engine component is operatively linked to the first qubit via a qubit controller coupled to the first qubit, wherein the qubit controller interacts with the first qubit by sending analog signals to and receiving analog signals from the first qubit.

4. The system according to claim 2, wherein, The first engine component also conditionally controls the first quantum computing resource based on the value of the first qubit.

5. The system according to claim 4, wherein, The compiler component also maps the logical references of the instructions to a third engine component that is operatively coupled to a second block controller component of the second quantum computing resource, wherein the first quantum computing resource and the second quantum computing resource have different structures.

6. The system according to claim 5, wherein, The compiler component selects the third engine component based on second organization data for the second quantum computing resource, wherein the second organization data includes the structure of the engine component of the second quantum computing resource.

7. The system according to claim 1, wherein, Based on the first organization's data, the compiler component: The execution of the instructions is also mapped to the first engine component and the second engine component; as well as The first engine component is configured to access a first element of the first quantum computing resource, wherein the first organization data includes first organization data describing the first element of the first quantum computing resource.

8. The system according to claim 7, wherein, The instructions also include an additional logical reference to a register storing the result of measuring the first qubit, wherein the first element includes the register.

9. The system according to claim 7, wherein, The first organization data also includes a delay value corresponding to the duration of the transmission of program values ​​between the first block controller component and the second block controller component, and wherein, based on the delay value, the deployment component deploys the second engine component to the first engine component of the second block controller component and the second quantum computing resource component.

10. The system according to claim 7, wherein, Based on the first organization data, the first engine component and the second engine component of the first quantum computing resource are operatively linked to each other in a hierarchical structure.

11. The system according to any one of claims 1-10, wherein, The deployment component also deploys the fourth engine component to the fourth execution controller component, wherein, without being mapped by the compiler component, the fourth engine component controls the first quantum computing resource to execute default instructions.

12. A computer-implemented method, comprising: The system, operatively coupled to the processor, maps logical references to the quantum bit data structure in the instructions to the first engine component, and The system deploys the first engine component to a first controller component operatively connected to the first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instructions. The compiler component is a single-version compiler component. Using the single-version compiler component for different quantum computing resources facilitates the use of the same job on multiple quantum machines, which can reduce the customization work required for different machines and improve the standardization of deployment on different quantum machines, thereby reducing computing costs. The block controller component includes one or more engine components, one or more digital-to-analog converters, or one or more analog-to-digital converters; Based on the instructions, the deployment component also deploys the second engine component to the second block controller component, which is operatively connected to the second qubit of the first quantum computing resource and the first block controller component. The second engine component controls the first quantum computing resource based on the second qubit, the first engine component, and the instructions.

13. The computer-implemented method according to claim 12, further comprising: Based on the first organization data, the system also maps the execution of the instructions to the first engine component and the second engine component; as well as The system configures the first engine component to access a first element of the first quantum computing resource, wherein the first organization data includes first organization data describing the first element of the first quantum computing resource.

14. The computer-implemented method according to claim 13, wherein, The instructions also include a logical reference to a register storing the result of measuring the first qubit, wherein the first element includes the register.

15. The computer-implemented method according to claim 14, wherein, The first organization data also includes a delay value corresponding to the duration of the transmission of program values ​​between the first block controller component and the second block controller component, and wherein, based on the delay value, the deployment component deploys the second engine component to the first engine component of the second block controller component and the second quantum computing resource component.

16. A computer program product that facilitates the mapping of conditional execution logic to quantum computing resources, the computer program product comprising program instructions executable by a processor to cause the processor to: The processor maps logical references to the quantum bit data structure in the instructions to the first engine component, and The processor deploys the first engine component to a first controller component operatively connected to the first quantum computing resource, wherein... The first engine component controls the first quantum computing resource based on the instructions; The compiler component is a single-version compiler component. Using the single-version compiler component for different quantum computing resources facilitates the use of the same job on multiple quantum machines, which can reduce the customization work required for different machines and improve the standardization of deployment on different quantum machines, thereby reducing computing costs. The block controller component includes one or more engine components, one or more digital-to-analog converters, or one or more analog-to-digital converters; Based on the instructions, the deployment component also deploys the second engine component to the second block controller component, which is operatively connected to the second qubit of the first quantum computing resource and the first block controller component. The second engine component controls the first quantum computing resource based on the second qubit, the first engine component, and the instructions.

17. The computer program product according to claim 16, wherein, The first controller component is operatively connected to a first qubit of the first quantum computing resource, and the first engine component further controls the first quantum computing resource based on the first qubit.

18. The computer program product according to claim 17, wherein, The first engine component also conditionally controls the first quantum computing resource based on the value of the first qubit.

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