Techniques for generating interpolated video frames

Abstract

Apparatus, systems, and techniques for generating interpolated video frames. In at least one embodiment, a second set of pixel data of a second video frame is sampled at least in part based on a set of forward motion vectors from a first video frame to a second video frame, and the interpolated video frame is generated at least in part based on a first set of pixel data sampled from the first video frame and a second set of pixel data sampled from the second video frame.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 944,071, filed July 30, 2020, entitled “Technology for Generating Interpolated Video Frames,” the entire contents of which are incorporated herein by reference and used for all purposes. Technical Field

[0003] At least one embodiment relates to processing resources for generating video frames. For example, at least one embodiment relates to a processor or computing system for generating interpolated video frames according to the various new technologies described herein. Background Technology

[0004] Generating video frames can consume significant amounts of memory, time, or computational resources. The amount of memory, time, or computational resources required to generate video frames can be improved. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating a system for generating interpolated video frames according to at least one embodiment;

[0006] Figure 2 This is a block diagram illustrating frame interpolation according to at least one embodiment;

[0007] Figure 3 This is a diagram illustrating the synthesis of intermediate frames according to at least one embodiment;

[0008] Figure 4 It is a diagram showing forward and backward twisting according to at least one embodiment;

[0009] Figure 5 This is a block diagram illustrating a system for generating interpolated video frames according to at least one embodiment;

[0010] Figure 6 This is a block diagram illustrating frame interpolation according to at least one embodiment;

[0011] Figure 7 This is a diagram illustrating the synthesis of intermediate frames according to at least one embodiment;

[0012] Figure 8 A flowchart illustrating a technique for generating intermediate video frames according to at least one embodiment is shown;

[0013] Figure 9 A flowchart illustrating a technique for sampling a first set of pixel data according to at least one embodiment is shown;

[0014] Figure 10 A flowchart illustrating a technique for sampling a second set of pixel data according to at least one embodiment is shown;

[0015] Figure 11 A flowchart illustrating a technique for generating intermediate video frames according to at least one embodiment is shown;

[0016] Figure 12 A first input video frame and a second input video frame according to at least one embodiment are shown;

[0017] Figure 13 An occlusion mask and a de-occlusion mask covering an intermediate video frame are shown according to at least one embodiment;

[0018] Figure 14 An intermediate video frame generated according to at least one embodiment is shown;

[0019] Figure 15 An exemplary data center according to at least one embodiment is shown;

[0020] Figure 16 A processing system according to at least one embodiment is shown;

[0021] Figure 17 A computer system according to at least one embodiment is shown;

[0022] Figure 18 A system according to at least one embodiment is shown;

[0023] Figure 19 An exemplary integrated circuit according to at least one embodiment is shown;

[0024] Figure 20 A computing system according to at least one embodiment is shown;

[0025] Figure 21 An APU according to at least one embodiment is shown;

[0026] Figure 22 A CPU according to at least one embodiment is shown;

[0027] Figure 23 An exemplary accelerator integration slice according to at least one embodiment is shown;

[0028] Figures 24A-24B An exemplary graphics processor according to at least one embodiment is shown;

[0029] Figure 25A A graphics core according to at least one embodiment is shown;

[0030] Figure 25BA GPGPU according to at least one embodiment is shown;

[0031] Figure 26A A parallel processor according to at least one embodiment is shown;

[0032] Figure 26B A processing cluster according to at least one embodiment is shown;

[0033] Figure 26C A graphics multiprocessor according to at least one embodiment is shown;

[0034] Figure 27 A graphics processor according to at least one embodiment is shown;

[0035] Figure 28 A processor according to at least one embodiment is shown;

[0036] Figure 29 A processor according to at least one embodiment is shown;

[0037] Figure 30 A graphics processor core according to at least one embodiment is shown;

[0038] Figure 31 A PPU according to at least one embodiment is shown;

[0039] Figure 32 A GPC according to at least one embodiment is shown;

[0040] Figure 33 A streaming multiprocessor according to at least one embodiment is illustrated;

[0041] Figure 34 A software stack of a programming platform according to at least one embodiment is shown;

[0042] Figure 35 The illustration shows an embodiment according to at least one of the embodiments. Figure 34 The CUDA implementation of the software stack;

[0043] Figure 36 The illustration shows an embodiment according to at least one of the embodiments. Figure 34 The ROCm implementation of the software stack;

[0044] Figure 37 The illustration shows an embodiment according to at least one of the embodiments. Figure 34 The OpenCL implementation of the software stack;

[0045] Figure 38 Software supported by a programming platform according to at least one embodiment is shown;

[0046] Figure 39Compilation code according to at least one embodiment is shown to be used in Figure 34-37 Executed on the programming platform;

[0047] Figure 40 A more detailed explanation of compiling code according to at least one embodiment to... Figure 34-37 Executed on the programming platform;

[0048] Figure 41 This illustrates translating source code before compiling it, according to at least one embodiment;

[0049] Figure 42A A system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment, is shown;

[0050] Figure 42B The diagram illustrates a configuration, according to at least one embodiment, for compiling and executing using a CPU and a CUDA-enabled GPU. Figure 42A The system of CUDA source code;

[0051] Figure 42C The illustration shows a configuration, according to at least one embodiment, for compiling and executing using a CPU and a GPU without CUDA enabled. Figure 42A The system of CUDA source code;

[0052] Figure 43 The diagram illustrates a method according to at least one embodiment. Figure 42C An example kernel converted by the CUDA to HIP conversion tool;

[0053] Figure 44 A more detailed description is provided according to at least one embodiment. Figure 42C GPUs without CUDA enabled; and

[0054] Figure 45 This illustrates how threads of an exemplary CUDA grid, according to at least one embodiment, are mapped to... Figure 44 Different computational units. Detailed Implementation

[0055] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the inventive concept can be practiced without one or more of these specific details.

[0056] Figure 1This is a block diagram of a system 100 for generating interpolated video frames according to at least one embodiment. In at least one embodiment, system 100 includes an interpolation frame generator 102 that generates a set of interpolated frames 104 based at least in part on frame data 106. In at least one embodiment, the interpolation frame generator 102 is a computer program accessible via an application programming interface (API). In at least one embodiment, the interpolation frame generator 102 runs on a processor (e.g., a central processing unit (CPU), not shown for clarity). It should be understood that when one or more computer programs and / or APIs (e.g., in relation to the interpolation frame generator 102) are referred to as performing an aspect of an action or technique relating to an embodiment, one or more hardware components (e.g., CPU, GPU, and / or other hardware components) of the computer system running the computer program and / or API perform that aspect of the action or technique.

[0057] In at least one embodiment, frame data 106 includes first video frame information 108 and second video frame information 110. In at least one embodiment, the first video frame information 108 includes a first video frame 112 and a set of depth indicators 114. In at least one embodiment, the second video frame information 110 includes a second video frame 116 and a set of depth indicators 118. In at least one embodiment, the first video frame 112 includes a first set of pixel values ​​and the second video frame 116 includes a second set of pixel values. In at least one embodiment, the set of pixel values ​​for the first video frame 112 and the second video frame 116 includes color information (e.g., RGB values) of the pixels (e.g., their positions in a two-dimensional grid represented by x and y values). In at least one embodiment, the depth indicator set 114 is a set of depth values ​​(e.g., z values ​​in a z buffer) of the pixels of the first video frame 112. In at least one embodiment, the depth indicator set 118 is a set of depth values ​​of the pixels of the second video frame 116. In at least one embodiment, some or all of the frame data 106 may be available in one or more buffers from the video game engine (e.g., in memory such as graphics memory) and may be used by the interpolation frame generator 102.

[0058] In at least one embodiment, the first video frame information 108 includes a set of forward motion vectors 120, while the second video frame information 110 includes a set of backward motion vectors 122. In at least one embodiment, the set of forward motion vectors 120 includes motion vectors of pixels in the first video frame 112 pointing to pixel positions in the second video frame 116. In at least one embodiment, the set of backward motion vectors 122 includes motion vectors of pixels in the second video frame 116 pointing to pixel positions in the first video frame 112. In at least one embodiment, each forward motion vector is a vertex movement of the projection (e.g., to a pixel position in the second video frame), and each backward motion vector is a vertex movement of the projection (e.g., from a pixel position in the first video frame). Although only two sets of video frame information are shown with respect to frame data 106, it should be understood that in at least one embodiment, frame data 106 includes additional video frame information (e.g., information about video frames appearing before frame 112 and / or after frame 116). In at least one embodiment, the video frame information of a particular video frame includes forward and backward motion vectors (e.g., in at least one embodiment, the second video frame information 110 also includes forward motion vectors pointing to pixels of subsequent video frames, which are not shown for clarity).

[0059] In at least one embodiment, the interpolation frame generator 102 generates a first interpolation frame 124, a second interpolation frame 126, and a third interpolation frame 128 between the first video frame 112 and the second video frame 116. In at least one embodiment, the interpolation frame generator 102 generates a different number of frames (e.g., a single frame or more than three frames) between the first video frame 112 and the second video frame 116 than shown.

[0060] Figure 2 This is a diagram illustrating frame interpolation 200 based at least in part on forward motion vectors (e.g., forward motion vector 120) and backward motion vectors (e.g., backward motion vector 122) according to at least one embodiment. In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 102) performs frame interpolation 200. In at least one embodiment, frame interpolation 200 is referred to as bidirectional motion vector (BiMV) interpolation. In at least one embodiment, the interpolation frame generator generates interpolated frames (e.g., using pixel color data, depth, and motion vectors) based at least in part on video frame information of the frames shown at times (t), (t+1), and (t+2). In at least one embodiment, given a pair of frames (e.g., at times (t) and (t+1)), the interpolation frame generator synthesizes interpolated frames at a predetermined time (e.g., at (t+0.25)).

[0061] In at least one embodiment, the interpolation frame generator performs frame interpolation 200 based at least in part on the input RGB color images (e.g., first video frame 112 and second video frame 116), depth buffers (e.g., depth indicators 114 and 118), and geometric motion vectors (e.g., forward motion vector 120 and backward motion vector 122). In at least one embodiment, these inputs are represented as (I0, D0, F). 0→1 ) and (I1,D1,F 1→0 These correspond to the input RGB color image, depth buffer, and geometric motion vector at times T=0 and T=1, respectively. In at least one embodiment, the input RGB color image is a low frame per second (FPS) image.

[0062] In at least one embodiment, frame interpolation 200 is based at least in part on the assumption that pixels move along motion vector F associated with the source pixel and the destination pixel. 0→1 and F 1→0 Linear motion from T=0 to T=1 (or T=1 to T=0). In at least one embodiment, when the interpolation frame generator generates an intermediate interpolation frame at time t=0.5, the interpolation frame generator estimates the intermediate frame as a pixel landing at t (e.g., t=0.5, or midway) along the linear path. In at least one embodiment, frame interpolation 200 is based at least in part on acceleration parameters (e.g., acceleration inferred by the interpolation frame generator 102 at least in part based on information from one or more additional frames prior to T=0).

[0063] In at least one embodiment, in most cases, simply moving a pixel from T=0 or T=1 to an intermediate time t is sufficient to obtain a reasonable intermediate pixel. However, in at least one embodiment, the appearance of a pixel may change drastically from T=0 to T=1, for example, when a well-lit scene darkens. In at least one embodiment, the geometric motion vector cannot fully account for this change, and moving a pixel from only a single source will result in suboptimal interpolation. In at least one embodiment, to illustrate this, the pixel at intermediate time t is synthesized by a linear combination of pixels taken from two source images along a linear line defined by the motion vector. In at least one embodiment, this is mathematically represented as follows:

[0064] I t = (1-t)*Warp(I0,F t→0 )+t*Waro(I1,F t→1 (1)

[0065] Where F t→0 and F t→1 It is generated by the interpolation frame generator (e.g., as about Figure 4The bidirectional intermediate motion vector generated by the motion vector, while Warp is a bilinear sampling operation that pulls pixels from the source RGB image guided by the motion vector.

[0066] Figure 3 This is a diagram illustrating intermediate frame synthesis 300 based at least in part on forward motion vectors (e.g., forward motion vector 120) and backward motion vectors (e.g., backward motion vector 122) according to at least one embodiment. In at least one embodiment, intermediate frame synthesis 300 is a simplified representation for illustrative purposes, showing only five pixels in one dimension at different times, rather than a large number of pixels in two dimensions as would be used in at least one embodiment. In at least one embodiment, interpolation frame generator 102 performs intermediate frame synthesis 300. In at least one embodiment, intermediate frame synthesis 300 is referred to as bidirectional motion vector (BiMV) intermediate frame synthesis. In at least one embodiment, intermediate frame synthesis 300 includes intermediate motion vectors (F... t→1 ,F t→0 Furthermore, intermediate frame synthesis 300 is guided by occlusion and dis-occlusion masks. In at least one embodiment, circle 302 represents an occlusion artifact that warps the frame starting from T=1, while circle 304 represents a dis-occlusion artifact that warps the frame starting from T=0.

[0067] In at least one embodiment, the source pixels may be invisible in both input images for all intermediate pixels because they have been occluded. For example, in at least one embodiment, using F t→0 Sampling I0 will produce trailing edge artifacts (also known as de-occlusion artifacts) because the correct content filling the occluded area is not visible in I0, but may be visible in I1 (the second image). Similarly, in at least one embodiment, F... t→1 Sampling I1 will result in leading-edge artifacts (also known as occlusion artifacts). However, for most intermediate pixels, the source pixel is visible in both input frames, so equation (1) will result in reasonable interpolation in these regions.

[0068] In at least one embodiment, in order to account for the leading and trailing edge artifacts not considered in equation (1), equation (2) is used to model the occluded region, the deoccluded region, and the visible region, as follows:

[0069]

[0070] Where M 0→t and M 1→t It refers to occlusion masks and de-occlusion masks. In at least one embodiment, M 0→t Allows sampling of pixels visible only from input I0, and M1→t Sampling is allowed for pixels visible only from input I1. In at least one embodiment, Figure 3 An example process for frame synthesis using equation (2) is shown. In at least one embodiment, the interpolation frame generator samples pixels of an additional input frame (e.g., the first frame that occurs before I0, in which the corresponding pixels are visible) for pixels of an intermediate frame that is not visible from input I0 or I1 (e.g., simultaneously de-occluded and occluded).

[0071] In at least one embodiment, the interpolation frame generator applies weighting factors to pixel data pulled from pixels from the first video frame (e.g., at T=0) and the second video frame (e.g., at T=1) based at least in part on whether an occlusion and / or de-occlusion mask is applied, and / or based on the relative time values ​​of the interpolation frame with respect to the first and second video frames (e.g., whether the interpolation frame corresponds to times t=0.25, t=0.5, or t=0.75). In at least one embodiment, for pixels affected by the occlusion mask (e.g., circle 302), the interpolation frame generator applies a weighting factor of 1 to pixels pulled from the first frame (e.g., from T=0 to T=t) and a weighting factor of 0 to pixels pulled from the second frame (e.g., from T=1 to T=t), as... Figure 3 As shown. In at least one embodiment, for pixels affected by the demasking mask (e.g., circle 304), the interpolation frame generator applies a weighting factor of 0 to pixels pulled from the first frame (e.g., from T=0 to T=t), and a weighting factor of 1 to pixels pulled from the second frame (e.g., from T=1 to T=t), as... Figure 3 As shown. In at least one embodiment, for pixels unaffected by occlusion or de-occlusion masks, the interpolation frame generator applies a weighting factor based on the relative temporal distance between the interpolation frame and the first and second video frames (e.g., applying 0.5 to both when the interpolation frame lies between them, as shown). Figure 3 (As shown).

[0072] Figure 4 This diagram illustrates backward and forward warping 400 according to at least one embodiment. In at least one embodiment, for forward warping, each pixel in the source is migrated to a destination pixel guided by a motion vector pointing from the source to the destination. In at least one embodiment, for forward warping, the destination pixel may never be reached and assigned a value (e.g., in pixel group 402), or multiple source pixels may point to the same destination pixel (e.g., pixel 404), thus creating blurring in the forward warping.

[0073] In at least one embodiment, Figure 3In the intermediate frame synthesis 300, the interpolation frame generator (e.g., interpolation frame generator 102) projects the input bidirectional motion vector (F) through the intermediate pixel position. 0→1 ,F 1→0 To approximate the intermediate motion vector (F) t→1 ,F t→0 In at least one embodiment, the interpolation frame generator forward-biased the input motion vector from T=0 or T=1 to T=t, and then, at the destination pixel in T=t, the interpolation frame generator scaled the motion vector at the source pixel by a factor of (1-t). In at least one embodiment, the scaling factor is larger when t is small, and vice versa.

[0074] In at least one embodiment, the interpolation frame generator uses the depth at the source pixel (e.g., from depth indicator 114 and / or depth indicator 118) to resolve the blurring of the forward warp. In at least one embodiment, among multiple pixels arriving at the same destination pixel, the interpolation frame generator records the motion vector of the source pixel with the smallest depth, i.e., the pixel not occluded by the source. In at least one embodiment, this is mathematically represented as follows:

[0075] F t→1 (x,y)=(1-t)*F 0→1 (x′, y′), where

[0076] (x′,y′)=(x,y)-t*F 0→1 (x,y) (3)

[0077] F 0→1 (x, y) is a motion vector that has the minimum depth among all possible vectors that reach (x, y) when twisting from T = 0 to T = t. In at least one embodiment, the interpolation frame generator generates additional intermediate motion vectors (e.g., intermediate backward motion vectors) pointing from T = t to T = 0, such as...

[0078] F t→0 (x,y)=t*F 1→0 (x′, y′), where

[0079] (x′,y′)=(x,y)-(1-t)*F 1→0 (x,y) (4)

[0080] And F 1→0 (x, y) is a motion vector that has the minimum depth among all possible vectors that reach (x, y) when twisting from T=1 to T=t.

[0081] In at least one embodiment, intermediate frame synthesis 300 includes generating a mask to provide masking for occlusion and de-occlusion artifacts appearing in the backward image distortion with respect to equation (2). In at least one embodiment, intermediate frame synthesis 300 uses forward projection of depth at times T = 0 or T = 1 to T = t, and defines intermediate pixels as occluded / de-occluded pixels if no source pixel can reach it when the source pixel is projected forward with its motion vector. In at least one embodiment, the occlusion mask is mathematically represented as,

[0082] M 0→t (x,y)=1, if D t (x,y)=0, meaning (x,y) is unreachable during the forward motion from 1→t; otherwise

[0083] M 0→t x,y_=0, where

[0084] D t =ForwardWarp(D1,(1-t)F 1→0 (5)

[0085] In at least one embodiment, similarly, the demasking mask is represented by the following:

[0086] M 1→t (x,y)=1, if D t (x,y)=0, that is, (x,y) is unreachable during the forward motion from 0→t, otherwise

[0087] M 1→t (x,y)=0, where

[0088] D t =ForwardWarp(D0,tF 0→1 (6)

[0089] Figure 5 This is a block diagram of a system 500 for generating interpolated video frames according to at least one embodiment. In at least one embodiment, system 500 includes an interpolation frame generator 502 that generates a set of interpolated frames 504 based at least in part on frame data 506. In at least one embodiment, the interpolation frame generator 502 is a computer program accessible via an application programming interface (API). In at least one embodiment, the interpolation frame generator 502 runs on a processor (e.g., a central processing unit (CPU), not shown for clarity). In at least one embodiment, some or all of the frame data 506 is available in one or more buffers from a video game engine (e.g., in memory such as graphics memory) and is available for use by the interpolation frame generator 502.

[0090] In at least one embodiment, frame data 506 includes first video frame information 508 and second video frame information 510. In at least one embodiment, the first video frame information 508 includes a first video frame 512 and a set of depth indicators 514. In at least one embodiment, a forward motion vector is not available in frame data 506. In at least one embodiment, the second video frame information 510 includes a second video frame 516 and a set of depth indicators 518. In at least one embodiment, the first video frame 512 includes a first set of pixel values ​​and the second video frame 516 includes a second set of pixel values. In at least one embodiment, the set of pixel values ​​for the first video frame 512 and the second video frame 516 includes color information (e.g., RGB values) of the pixels (e.g., their positions in a two-dimensional grid represented by x and y values). In at least one embodiment, the set of depth indicators 514 is a set of depth values ​​(e.g., z values ​​in a z buffer) of the pixels of the first video frame 512. In at least one embodiment, the set of depth indicators 518 is a set of depth values ​​of the pixels of the second video frame 516.

[0091] In at least one embodiment, the first video frame information 508 includes camera data 520 and the second video frame information 510 includes a set of backward motion vectors 522 and camera data 524. In at least one embodiment, the camera data 520 and camera data 524 are stored as a matrix in a buffer. In at least one embodiment, the set of backward motion vectors 522 includes motion vectors of pixels in the second video frame 516 pointing to pixel positions in the first video frame 512. In at least one embodiment, each backward motion vector is a projection of vertex movement (e.g., from a pixel position in the first video frame). Although only two sets of video frame information are shown with respect to frame data 506, it should be understood that in at least one embodiment, frame data 506 includes additional video frame information (e.g., information about video frames that appear before frame 512 and / or after frame 516).

[0092] In at least one embodiment, the interpolation frame generator 502 generates a first interpolation frame 526, a second interpolation frame 528, and a third interpolation frame 530 between the first video frame 512 and the second video frame 516. In at least one embodiment, the interpolation frame generator 502 generates a different number of frames (e.g., a single frame or more than three frames) between the first video frame 512 and the second video frame 516 than shown.

[0093] Figure 6This is a diagram illustrating frame interpolation 600 based at least in part on a backward motion vector (e.g., backward motion vector 522) according to at least one embodiment. In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 502) performs frame interpolation 600. In at least one embodiment, frame interpolation 600 is referred to as UniMV interpolation. In at least one embodiment, the interpolation frame generator generates interpolated frames (e.g., using pixel color data, depth, and backward motion vectors) based at least in part on video frame information of the frames shown at times (t), (t+1), and (t+2).

[0094] In at least one embodiment, the interpolation frame generator performs frame interpolation 600 based at least in part on the input RGB color images (e.g., first video frame 512 and second video frame 516), depth buffers (e.g., depth indicators 514 and 518), and geometric motion vectors (e.g., backward motion vector 522). In at least one embodiment, these inputs are represented as (I0,D0) and (I1,D1) and F 1→0 (I0,D0) and (I1,D1) correspond to the input RGB color image and depth buffer at times T=0 and T=1, respectively. 1→0 It is a unidirectional backward motion vector. In at least one embodiment, the input RGB color image is a low frame per second (FPS) image.

[0095] Figure 7 This is a diagram illustrating intermediate frame synthesis 700 based at least in part on a backward motion vector (e.g., backward motion vector 522) according to at least one embodiment. In at least one embodiment, an interpolation frame generator 502 performs intermediate frame synthesis 700. In at least one embodiment, intermediate frame synthesis 700 is a simplified representation for illustrative purposes, showing only five pixels in one dimension at different times, rather than a large number of pixels in two dimensions as would be used in at least one embodiment. In at least one embodiment, intermediate frame synthesis 700 is referred to as Uni-Motion Vector (UniMV) intermediate frame synthesis. In at least one embodiment, intermediate frame synthesis 700 includes intermediate motion vectors (F... t→1 ,F t→0 Furthermore, intermediate frame synthesis 700 is guided by occlusion and de-occlusion masks. In at least one embodiment, circle 702 represents an occlusion artifact that warps the frame starting from T=1, while circle 704 represents a de-occlusion artifact that warps the frame starting from T=0.

[0096] In at least one embodiment, the forward motion vector cannot be used for intermediate frame synthesis 700, and cannot be used with respect to... Figure 3The described intermediate frame synthesis 700 technique includes, in at least one embodiment, estimating a lost forward motion vector from a given backward motion vector via a forward warping operation. In at least one embodiment, the forward warping operation is referred to as a scattering operation. In at least one embodiment, intermediate frame synthesis 700 includes generating an intermediate motion vector using the estimated forward motion vector and the given backward motion vector.

[0097] In at least one embodiment, intermediate frame synthesis 700 includes estimating the forward motion vector by scattering and then flipping the backward vector. In at least one embodiment, the estimated forward motion vector is mathematically described as follows:

[0098] in

[0099] (x′,y′)=(x,y)-F 1→0 (x,y) (7)

[0100] It is a motion vector that has the minimum depth among all possible vectors that reach (x,y) when twisted from T=0 to T=1. In at least one embodiment, the scattering and preservation of information with minimum depth is used by intermediate frame synthesis 700 to resolve occlusion, because pixels with the same destination but greater depth are substantially occluded when moving from T=1 to T=0, and therefore they are suppressed.

[0101] In at least one embodiment, as regarding Figure 4 The forward warping discussed leads to blurring, such as holes in the destination pixel. In at least one embodiment, intermediate frame synthesis 700 includes marking these holes as occlusion masks (when warping forward from T=1 to T=0) or de-occlusion masks (when warping forward from T=0 to T=1). In at least one embodiment, forward motion vector estimation using equation (7) will result in holes at the destination (T=0), creating pixels with undefined motion vectors in the occluded region.

[0102] In at least one embodiment, the interpolation frame generator applies weighting factors to pixel data pulled from pixels from the first video frame (e.g., at T=0) and the second video frame (e.g., at T=1) based at least in part on whether an occlusion and / or de-occlusion mask is applied, and / or based on the relative time values ​​of the interpolation frame with respect to the first and second video frames (e.g., whether the interpolation frame corresponds to times t=0.25, t=0.5, or t=0.75). In at least one embodiment, for pixels affected by an occlusion mask (e.g., circle 702), the interpolation frame generator applies a weighting factor of 1 to pixels pulled from the first frame (e.g., from T=0 to T=t) and a weighting factor of 0 to pixels pulled from the second frame (e.g., from T=1 to T=t), as... Figure 7 As shown. In at least one embodiment, for pixels affected by the demasking mask (e.g., circle 704), the interpolation frame generator applies a weighting factor of 0 to pixels pulled from the first frame (e.g., from T=0 to T=t), and a weighting factor of 1 to pixels pulled from the second frame (e.g., from T=1 to T=t), as... Figure 7 As shown. In at least one embodiment, for pixels unaffected by occlusion masks or de-occlusion masks, the interpolation frame generator applies a weighting factor based on the temporal relative distance between the interpolation frame and the first and second video frames (e.g., applying 0.5 to both when the interpolation frame is in the middle, such as...). Figure 7 (As shown). In at least one embodiment, the interpolation frame generator samples (e.g., simultaneously de-occluded and occluded) pixels of an additional input frame (e.g., an additional frame occurring before T=0 in which the corresponding pixel is visible, or an additional frame T=2 in which the corresponding pixel is visible after T=1) for pixels of an intermediate frame that is not visible at T=0 or T=1.

[0103] In at least one embodiment, the interpolation frame generator (e.g., interpolation frame generator 502) recovers (e.g., generates) one or more motion vectors of the occluded region at T=0 (e.g., the region where equation (7) produces an undefined vector). In at least one embodiment, the interpolation frame generator recovers the motion vectors at least in part based on an implementation of the Procrustes analysis. In at least one embodiment, while using this approximation generally results in acceptable intermediate frame synthesis, it can only capture static object motion, also known as camera motion. In at least one embodiment, the interpolation frame generator uses the deoccluded region at T=t that is visible from T=1. In at least one embodiment, the interpolation frame generator uses the intermediate motion vector F t→1 Guided by this, a one-to-one correspondence is established between each point in the de-occlusion region and its corresponding point in the frame at T=1. In at least one embodiment, the interpolation frame generator uses a method with respect to... Figure 3 and Figure 4Intermediate motion vectors are generated in a similar manner to those described, but when the actual forward motion vector is not available from the buffer (e.g., not available from the buffer in system 500), it is at least partially based on the estimated forward motion vector. In at least one embodiment, once the correspondence is established, the interpolation frame generator forms a 3D point set for each pixel, treating the integral index (x,y) and their depth z as a point (x,y,z) in 3D. In at least one embodiment, the interpolation frame generator computes a matrix registering those 3D point sets, giving an approximate estimate of global or camera translation, rotation, and scaling information. In at least one embodiment, when camera information (e.g., camera data 520 and camera data 524) is available from the buffer, the interpolation frame generator determines the camera position and / or movement (e.g., translation, rotation, and / or scaling) at least partially based on the buffered camera information (e.g., the camera matrix at the time of the first and second video frames), rather than estimating camera movement at least partially based on the 3D point set.

[0104] In at least one embodiment, since the camera matrix is ​​global information applicable to the entire video frame, the interpolation frame generator extrapolates the same camera matrix to other regions (e.g., non-de-occluded regions), including occluded regions. In at least one embodiment, a forward motion vector is not defined in the occluded region, and extrapolating the camera matrix to the occluded region generates an approximate motion vector used when the forward motion vector is not defined. In at least one embodiment, once the camera matrix is ​​generated, the interpolation frame generator creates a corresponding motion vector for each corresponding pixel (e.g., in regions with undefined vectors).

[0105] In at least one embodiment, the final estimated intermediate vector from T = t to T = 1 is mathematically given by the following formula:

[0106]

[0107] in Is using In order to target Figure 3 and 4 The method described is similar to that used in the generation process. In at least one embodiment, additional information is used for the synthesis of intermediate frames using equation (2). Is it in use Replace F 0→1 After that, such as regarding Figure 3 and Figure 4 It was generated as described.

[0108] Figure 8A flowchart of a technique 800 for generating intermediate video frames according to at least one embodiment is shown. In at least one embodiment, technique 800 is performed by at least one circuit, at least one system (e.g., system 100), at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components thereof described and / or shown herein. In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 102) performs technique 800.

[0109] In at least one embodiment, at block 802, technique 800 includes sampling a first set of pixel data for a first video frame (e.g., frame 112). In at least one embodiment, at block 804, technique 800 includes sampling a second set of pixel data for a second video frame (e.g., frame 116) based at least partially on a set of forward motion vectors (e.g., forward motion vector 120) from the first video frame to the second video frame. In at least one embodiment, at block 806, technique 800 includes generating an intermediate video frame (e.g., interpolated frame 124) based at least partially on the first and second sets of pixel data. In at least one embodiment, at block 808, technique 800 includes performing other actions.

[0110] In at least one embodiment, performing other actions includes storing the generated intermediate video frame in a buffer. In at least one embodiment, performing other actions includes displaying the intermediate video frame. In at least one embodiment, performing other actions includes transmitting the intermediate video frame over a network. In at least one embodiment, performing other actions includes generating one or more additional intermediate video frames between the first video frame and the second video frame, based at least in part on a first video frame, a second video frame, a set of forward motion vectors, a set of backward motion vectors, and a set of depth indicators. In at least one embodiment, performing other actions includes: identifying a pixel in the intermediate video frame that does not have a corresponding pixel in the second video frame identified using forward motion vectors (e.g., along the forward motion vector and / or a function corresponding to the forward motion vector), or a corresponding pixel in the first video frame identified using backward motion vectors (e.g., along the backward motion vector and / or a function corresponding to the backward motion vector); and setting the color of the identified pixel in the intermediate video frame to one of the colors of pixels at the same location as the identified pixel in the first or second video frame, based at least in part on the depth value of pixels at the same location as the identified pixel in the first or second video frame. In at least one embodiment, setting the identified pixel color is based at least in part on setting the pixel color to the color of the pixel at the same position in a first or second video frame having the maximum depth. In at least one embodiment, performing other actions includes storing one or more interpolated frames in a buffer and / or notifying (e.g., by setting a flag value or sending an indicator) the game engine that the interpolated frames are available for display.

[0111] Figure 9 A flowchart illustrating a technique 900 for sampling a first set of pixel data according to at least one embodiment is shown. In at least one embodiment, technique 900 is performed by at least one circuit, at least one system (e.g., system 100), at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components thereof described and / or shown herein. In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 102) performs technique 900. In at least one embodiment, technique 900 is... Figure 8 A more detailed representation of box 802.

[0112] In at least one embodiment, at block 902, technique 900 includes generating a set of intermediate backward motion vectors (e.g., including...). Figure 3 The F shown t→0 In at least one embodiment, at block 904, technique 900 includes generating an occlusion mask (e.g., Figure 3 M shown 0→tIn at least one embodiment, at block 906, technique 900 includes sampling a first set of pixel data of the first video frame based at least in part on a set of intermediate backward motion vectors and a generated occlusion mask. In at least one embodiment, at block 908, technique 900 includes performing other actions.

[0113] Figure 10 A flowchart illustrating a technique 1000 for sampling a second set of pixel data according to at least one embodiment is shown. In at least one embodiment, technique 1000 is performed by at least one circuit, at least one system (e.g., system 100), at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components thereof described and / or shown herein. In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 102) performs technique 1000. In at least one embodiment, technique 1000 is... Figure 8 A more detailed representation of box 804.

[0114] In at least one embodiment, at block 1002, technique 1000 includes generating a set of intermediate forward motion vectors (e.g., including...). Figure 3 The F shown t→1 In at least one embodiment, at block 1004, technique 1000 includes generating a demasking mask (e.g., Figure 3 M shown 1→t In at least one embodiment, at block 1006, technique 1000 includes sampling a second set of pixel data based at least in part on a set of intermediate forward motion vectors and a generated demasking mask. In at least one embodiment, at block 1008, technique 1000 includes performing other actions.

[0115] Figure 11 A flowchart of a technique 1100 for generating intermediate video frames according to at least one embodiment is shown. In at least one embodiment, technique 1100 is performed by at least one circuit, at least one system (e.g., system 500), at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components thereof described and / or shown herein. In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 502) performs technique 1100.

[0116] In at least one embodiment, at block 1102, technique 1100 includes generating a set of estimated forward motion vectors (e.g., including a set of backward motion vectors 522) based at least in part on a set of backward motion vectors 522. Figure 7 shown In at least one embodiment, at block 1104, technique 1100 includes generating a set of intermediate forward motion vectors (e.g., including...). Figure 7 The F shown t→1 ) and a set of intermediate backward motion vectors (e.g., including Figure 7 The F shown t→0 In at least one embodiment, the interpolation frame generator generates a set of intermediate forward motion vectors based at least in part on a generated set of estimated forward motion vectors. In at least one embodiment, the interpolation frame generator generates a set of intermediate backward motion vectors based at least in part on a set of backward motion vectors.

[0117] In at least one embodiment, at block 1106, technique 1100 includes sampling a first set of pixel data of a first video frame (e.g., video frame 512) based at least in part on a generated set of intermediate backward motion vectors. In at least one embodiment, sampling the first set of pixel data includes generating an occlusion mask (e.g., Figure 7 M shown 0→t The technique 1100, at least partially based on a generated occlusion mask, samples a second set of pixel data for a second video frame (e.g., video frame 516) at least partially based on a generated set of intermediate forward motion vectors at block 1108. In at least one embodiment, sampling the second set of pixel data includes generating an occlusion mask (e.g., ...). Figure 7 M shown 1→t And at least in part, the second set of pixel data is sampled based on the generated demask.

[0118] In at least one embodiment, at block 1110, technique 1100 includes generating a third video frame (e.g., interpolated frame 520) based at least in part on a sampled first set of pixel data and a sampled second set of pixel data. In at least one embodiment, the third video frame is an intermediate video frame between the first and second video frames. In at least one embodiment, generating the third video frame is referred to as interpolating the third video frame. In at least one embodiment, interpolating the third video frame is based at least in part on one of a plurality of possible motions of pixels from the first video frame to the second video frame, wherein the plurality of possible motions correspond to a set of backward motion vectors pointing to the same destination pixel in the first video frame, and the interpolated frame generator selects one of the set of backward motion vectors based at least in part on the shortest depth of the source pixel associated with the selected backward motion vector compared with other source pixels of the backward motion vector pointing to the same destination pixel. In at least one embodiment, at block 1112, technique 1100 includes performing additional actions.

[0119] In at least one embodiment, performing additional actions includes storing the generated third video frame in a buffer. In at least one embodiment, performing additional actions includes displaying intermediate video frames. In at least one embodiment, performing additional actions includes transmitting intermediate video frames over a network. In at least one embodiment, performing additional actions includes generating one or more additional intermediate video frames (e.g., interpolated frames 522 and / or interpolated frames 524) between the first and second video frames, based at least in part on the first video frame, the second video frame, a set of backward motion vectors (e.g., backward motion vector 522), and a set of depth indicators (e.g., depth indicator 514 and / or depth indicator 518). In at least one embodiment, performing additional actions includes storing one or more interpolated frames in a buffer and / or notifying (e.g., by setting a flag value or sending an indicator) the game engine that the interpolated frames are available for display.

[0120] Figure 12 A first video frame 1200 and a second video frame 1202 according to at least one embodiment are shown. In at least one embodiment, the first video frame 1200 corresponds to frame 112 and the second video frame 1202 corresponds to frame 116. In at least one embodiment, the first video frame 1200 corresponds to frame 512 and the second video frame 1202 corresponds to frame 516. In at least one embodiment, the first video frame 1200 corresponds to a first video frame of technique 800 and the second video frame 1202 corresponds to a second video frame of technique 800. In at least one embodiment, the first video frame 1200 corresponds to a first video frame of technique 1100 and the second video frame 1202 corresponds to a second video frame of technique 1100. In at least one embodiment, the first video frame 1200 appears before the second video frame 1202 in a video frame sequence. In at least one embodiment, pixel data (e.g., RGB color values), depth data, and one or more of backward motion vectors and forward motion vectors are generated by a video game engine and stored in one or more buffers before display. Although the first video frame 1200 and the second video frame 1202 are displayed in grayscale, it should be understood that the first video frame 1200 and the second video frame 1202 are generally displayed in color. In at least one embodiment, it can be seen that the character represented in the first video frame 1200 and the second video frame 1202 moves slightly to the left and slightly raises the barrel between a first time associated with the first video frame 1200 and a second later time associated with the second video frame 1202.

[0121] Figure 13Intermediate video frame 1300 with a covered demask and intermediate video frame 1302 with a covered occlusion mask are shown according to at least one embodiment. In at least one embodiment, the demask includes region 1304, which shows the area initially hidden by the gun in the demasked first video frame 1200. In at least one embodiment, the occlusion mask includes region 1306, which shows the area corresponding to the area hidden by the gun barrel in the second video frame 1202. In at least one embodiment, the demask includes additional regions and / or the occlusion mask includes additional regions; however, for clarity, not all demasked and occlusion regions in intermediate video frames 1300 and 1302 are specifically identified.

[0122] Figure 14 An intermediate video frame 1400 generated according to at least one embodiment is shown. In at least one embodiment, the generated intermediate video frame 1400 corresponds to an interpolation frame in a set of interpolation frames 104. In at least one embodiment, the generated intermediate video frame 1400 corresponds to an interpolation frame in a set of interpolation frames 504. In at least one embodiment, the generated intermediate video frame 1400 corresponds to an intermediate video frame generated by technique 800. In at least one embodiment, the generated intermediate video frame 1400 corresponds to a third video frame generated by technique 1100. In at least one embodiment, the region of intermediate video frame 1400 corresponding to the de-occluded region (e.g., region 1304) of intermediate video frame 1300 includes pixel data sampled from second video frame 1202 instead of first video frame 1200. In at least one embodiment, the region of intermediate video frame 1400 corresponding to the occluded region (e.g., region 1306) of intermediate video frame 1302 includes pixel data sampled from first video frame 1200 instead of second video frame 1202. In at least one embodiment, the region of intermediate video frame 1400 that does not correspond to the de-occluded region of intermediate video frame 1300 or the occluded region of intermediate video frame 1302 is interpolated at least in part based on pixel data sampled from both the first video frame 1200 and the second video frame 1202.

[0123] In at least one embodiment, intermediate video frames 1300, 1302, and / or 1400 will differ depending on whether the intermediate video frame corresponds to an interpolated frame in interpolated frame group 104 or an interpolated frame in interpolated frame group 504, based at least in part on the interpolation difference resulting from the availability of forward motion vectors in the buffers for interpolated frames in interpolated frame group 104, but using the backward motion vectors and depth information of the interpolated frames in interpolated frame group 504 to estimate the forward motion vectors. In at least one embodiment, although intermediate video frames 1300 and 1302 are shown for illustrative purposes, the interpolation frame generator (e.g., interpolation frame generator 102 or interpolation frame generator 502) will generate intermediate frame 1400 at least in part based on occlusion and de-occlusion information (e.g., occlusion and de-occlusion masks), without generating and / or using intermediate frames (e.g., intermediate video frames 1300 and / or 1302) with covered de-occlusion and occlusion regions. In at least one embodiment, the interpolation frame generator (e.g., interpolation frame generator 102 or interpolation frame generator 502) generates interpolated frames (e.g., intermediate video frame 1400) in real time (e.g., fast enough to generate interpolated frames during gameplay). In at least one embodiment, the interpolation frame generator generates interpolated frames in video games and / or ray tracing applications.

[0124] In at least one embodiment, an interpolation frame generator (e.g., interpolation frame generator 102 or interpolation frame generator 502) performs frame interpolation by synthesizing high frames per second (FPS) video for low-FPS video. In at least one embodiment, the interpolation frame generator synthesizes one or more intermediate frames from a given pair of consecutive input frames (e.g., first video frame 1200 and second video frame 1202). In at least one embodiment, using an interpolation frame generator to synthesize high-FPS video offers advantages over alternative methods (e.g., using a high-speed camera, which has high power costs, large storage requirements, and reduced video resolution). In a final embodiment, using an interpolation frame generator to synthesize high-FPS video offers advantages over using an initial high frame rate for rendering in video games via a graphics processing unit (GPU), at the cost of reduced image quality and / or power consumption. In at least one embodiment, an interpolation frame generator is used to synthesize high-FPS video from a low-FPS frame sequence, generating an arbitrary high-FPS frame sequence with minimal latency or power requirements. This can improve game performance during gameplay and provide advantages over other methods with higher power requirements (e.g., the initial high-FPS sequence of the GPU) or higher latency (e.g., certain machine learning methods). In at least one embodiment, synthesizing high-FPS video using an interpolation frame generator does not use inference operations from machine learning (e.g., deep learning) methods. In at least one embodiment, synthesizing high-FPS video using an interpolation frame generator offers advantages over some deep learning methods (e.g., better handling of occluded and deoccluded regions). In at least one embodiment, interpolating frames using an interpolation frame generator is based at least in part on the assumption that pixels move linearly over time and that pixels are sampled along a linear path formed by graphical motion vectors to create complete frames at any number (e.g., a predetermined number, or a parameter-controlled number, e.g., via an API) intermediate time points. In at least one embodiment, interpolating frames using an interpolation frame generator is based at least in part on the assumption that pixels move as a function of a graphic motion vector, and that pixels identified using the graphic motion vector are sampled to create a complete frame (e.g., sampling pixels along the graphic motion vector, approximating pixels along the graphic motion vector, e.g., by sampling based on the graphic motion vector and noise values, sampling based on the graphic motion vector and predetermined acceleration parameters, and / or some other suitable sampling method). In at least one embodiment, interpolating frames using an interpolation frame generator based at least in part on two consecutive frames provides advantages over methods that do not use two frames (e.g., reduced artifact levels).

[0125] Data Center

[0126] Figure 15An example data center 1500 according to at least one embodiment is shown. In at least one embodiment, the data center 1500 includes, but is not limited to, a data center infrastructure layer 1510, a framework layer 1520, a software layer 1530, and an application layer 1540.

[0127] In at least one embodiment, such as Figure 15 As shown, the data center infrastructure layer 1510 may include a resource coordinator 1512, grouped computing resources 1514, and node computing resources (“nodes CR”) 1516(1)-1516(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 1516(1)-1516(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1516(1)-1516(N) may be servers having one or more of the aforementioned computing resources.

[0128] In at least one embodiment, the grouped computing resources 1514 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. The individual groups of node CRs within the grouped computing resources 1514 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0129] In at least one embodiment, resource coordinator 1512 may be configured or otherwise control one or more nodes CR1516(1)-1516(N) and / or grouped computing resources 1514. In at least one embodiment, resource coordinator 1512 may include a software design infrastructure (“SDI”) management entity for data center 1500. In at least one embodiment, resource coordinator 1512 may include hardware, software, or some combination thereof.

[0130] In at least one embodiment, such as Figure 15As shown, framework layer 1520 includes, but is not limited to, job scheduler 1532, configuration manager 1534, resource manager 1536, and distributed file system 1538. In at least one embodiment, framework layer 1520 may include a framework of software 1552 supporting software layer 1530 and / or one or more applications 1542 supporting application layer 1540. In at least one embodiment, software 1552 or application 1542 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1520 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can utilize distributed file system 1538 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1532 may include Spark drivers to facilitate the scheduling of workloads supported by the various layers of data center 1500. In at least one embodiment, configuration manager 1534 may be able to configure different layers, such as software layer 1530 and framework layer 1520 including Spark and distributed file system 1538 for supporting large-scale data processing. In at least one embodiment, resource manager 1536 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1538 and job scheduler 1532. In at least one embodiment, cluster or group computing resources may include grouped computing resources 1514 on data center infrastructure layer 1510. In at least one embodiment, resource manager 1536 may coordinate with resource coordinator 1512 to manage these mapped or allocated computing resources.

[0131] In at least one embodiment, the software 1552 included in the software layer 1530 may include software used by at least a portion of nodes CR1516(1)-1516(N), grouped computing resources 1514, and / or the distributed file system 1538 of the framework layer 1520. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0132] In at least one embodiment, the application layer 1540 may include one or more applications 1542 that can be used by at least a portion of nodes CR1516(1)-1516(N), grouped computing resources 1514, and / or the distributed file system 1538 of the framework layer 1520. The one or more types of applications may include, but are not limited to, CUDA applications.

[0133] In at least one embodiment, any of the configuration manager 1534, resource manager 1536, and resource coordinator 1512 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1500 and can prevent underutilization and / or poor performance of the data center.

[0134] Computer-based systems

[0135] The following figures illustrate, but are not limited to, exemplary computer-based systems that can be used to implement at least one embodiment. In at least one embodiment, one or more computer-based systems of the figures below can implement, regarding... Figure 1-14 One or more aspects of one or more of the embodiments described, and / or about Figure 8-11 Describes one or more technologies.

[0136] Figure 16 A processing system 1600 according to at least one embodiment is illustrated. In at least one embodiment, the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In at least one embodiment, the processing system 1600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0137] In at least one embodiment, the processing system 1600 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, the processing system 1600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 1600 may also include components coupled to or integrated into a wearable device, such as a smartwatch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, the processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0138] In at least one embodiment, each of the one or more processors 1602 includes one or more processor cores 1607 to process instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 1607 is configured to process a particular instruction set 1609. In at least one embodiment, the instruction set 1609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the plurality of processor cores 1607 may each process a different instruction set 1609, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 1607 may also include other processing devices, such as digital signal processors (DSPs).

[0139] In at least one embodiment, processor 1602 includes cache memory 1604. In at least one embodiment, processor 1602 may have a single internal cache or more levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of processor 1602. In at least one embodiment, processor 1602 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 1607 using known cache coherence techniques. In at least one embodiment, processor 1602 further includes a register file 1606, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1606 may include general-purpose registers or other registers.

[0140] In at least one embodiment, one or more processors 1602 are coupled to one or more interface buses 1610 to transmit communication signals, such as address, data, or control signals, between the processors 1602 and other components in the system 1600. In at least one embodiment, the interface bus 1610 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1610 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1602 includes an integrated memory controller 1610 and a platform controller hub 1630. In at least one embodiment, the memory controller 1610 facilitates communication between storage devices and other components of the processing system 1600, while the platform controller hub (PCH) 1630 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0141] In at least one embodiment, storage device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, storage device 1620 may be used as system memory of processing system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute an application or process. In at least one embodiment, memory controller 1610 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 of processor 1602 to perform graph and media operations. In at least one embodiment, display device 1611 may be connected to processor 1602. In at least one embodiment, display device 1611 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1611 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0142] In at least one embodiment, the platform controller hub 1630 enables peripheral devices to connect to the storage device 1620 and the processor 1602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1646, a network controller 1634, a firmware interface 1628, a wireless transceiver 1626, a touch sensor 1625, and a data storage device 1624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1624 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1625 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1626 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 1628 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 1634 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1610. In at least one embodiment, audio controller 1646 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 1600 includes an optional legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to processing system 1600. In at least one embodiment, platform controller hub 1630 may also be connected to one or more Universal Serial Bus (USB) controllers 1642 that connect input devices, such as a keyboard and mouse combination 1643, a camera 1644, or other USB input devices.

[0143] In at least one embodiment, instances of the memory controller 1610 and platform controller hub 1630 may be integrated into a discrete external graphics processor, such as external graphics processor 1612. In at least one embodiment, the platform controller hub 1630 and / or the memory controller 1610 may be external to one or more processors 1602. For example, in at least one embodiment, the processing system 1600 may include an external memory controller 1610 and a platform controller hub 1630, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with the processor 1602.

[0144] Figure 17A computer system 1700 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1700 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 1700 is formed by a processor 1702, which may include execution units for executing instructions. In at least one embodiment, the computer system 1700 may include, but is not limited to, components such as the processor 1702, which employs execution units including logic to execute algorithms for process data. In at least one embodiment, the computer system 1700 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon™ XScale™ and / or StrongARM™ Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1700 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0145] In at least one embodiment, the computer system 1700 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0146] In at least one embodiment, computer system 1700 may include, but is not limited to, processor 1702, which may include, but is not limited to, one or more execution units 1708 configured to execute a Computational Unified Device Architecture (“CUDA”). The CUDA program is developed by NVIDIA Corporation in Santa Clara, California. In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 1700 is a single-processor desktop or server system. In at least one embodiment, the computer system 1700 may be a multiprocessor system. In at least one embodiment, the processor 1702 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1702 may be coupled to a processor bus 1710, which can transmit data signals between the processor 1702 and other components in the computer system 1700.

[0147] In at least one embodiment, processor 1702 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1704. In at least one embodiment, processor 1702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1702. In at least one embodiment, processor 1702 may include a combination of internal and external caches. In at least one embodiment, register file 1706 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0148] In at least one embodiment, an execution unit 1708, including but not limited to logic for performing integer and floating-point operations, is also located within processor 1702. Processor 1702 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1708 may include logic for processing a packaged instruction set 1709. In at least one embodiment, by including the packaged instruction set 1709 in the instruction set of general-purpose processor 1702, along with associated circuitry for executing the instructions, packaged data in general-purpose processor 1702 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on a data element at a time.

[0149] In at least one embodiment, execution unit 1708 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1700 may include, but is not limited to, memory 1720. In at least one embodiment, memory 1720 may be implemented as a DRAM device, SRAM device, flash memory device, or other storage device. Memory 1720 may store instructions 1719 and / or data 1721 represented by data signals that can be executed by processor 1702.

[0150] In at least one embodiment, the system logic chip may be coupled to processor bus 1710 and memory 1720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1716, and processor 1702 may communicate with MCH 1716 via processor bus 1710. In at least one embodiment, MCH 1716 may provide a high-bandwidth memory path 1718 to memory 1720 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1716 may initiate data signals between processor 1702, memory 1720, and other components in computer system 1700, and bridge data signals between processor bus 1710, memory 1720, and system I / O 1722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1716 can be coupled to memory 1720 via high-bandwidth memory path 1718, and graphics / video card 1712 can be coupled to MCH 1716 via Accelerated Graphics Port (“AGP”) interconnect 1714.

[0151] In at least one embodiment, computer system 1700 may use system I / O 1722 as a proprietary hub interface bus to couple MCH 1716 to I / O controller hub (“ICH”) 1730. In at least one embodiment, ICH 1730 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1720, chipset, and processor 1702. Examples may include, but are not limited to, an audio controller 1729, a firmware hub (“Flash BIOS”) 1728, a wireless transceiver 1726, data storage 1724, a conventional I / O controller 1723 including user input 1725 and a keyboard interface, a serial expansion port 1727 (e.g., USB), and a network controller 1734. Data storage 1724 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0152] In at least one embodiment, Figure 17 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 17 An exemplary SoC can be shown. In at least one embodiment, Figure 17 The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1700 are interconnected using a Compute Fast Link (CXL) interconnect.

[0153] Figure 18 A system 1800 according to at least one embodiment is illustrated. In at least one embodiment, system 1800 is an electronic device utilizing processor 1810. In at least one embodiment, system 1800 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0154] In at least one embodiment, system 1800 may include, but is not limited to, processor 1810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1810 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, USB (versions 1, 2, and 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 18 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 18 An exemplary SoC can be shown. In at least one embodiment, Figure 18 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 18 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0155] In at least one embodiment, Figure 18 This may include a display 1824, a touchscreen 1825, a touchpad 1830, a near-field communication unit (“NFC”) 1845, a sensor hub 1840, a thermal sensor 1846, a fast chipset (“EC”) 1835, a trusted platform module (“TPM”) 1838, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1822, a DSP 1860, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 1820, a wireless local area network unit (“WLAN”) 1850, a Bluetooth unit 1852, a wireless wide area network unit (“WWAN”) 1856, a global positioning system (GPS) 1855, a camera (“USB 3.0 camera”) 1854 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1815 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0156] In at least one embodiment, other components may be communicatively coupled to processor 1810 via the components discussed above. In at least one embodiment, accelerometer 1841, ambient light sensor (“ALS”) 1842, compass 1843, and gyroscope 1844 may be communicatively coupled to sensor hub 1840. In at least one embodiment, thermal sensor 1839, fan 1837, keyboard 1846, and touchpad 1830 may be communicatively coupled to EC 1835. In at least one embodiment, speaker 1863, earphone 1864, and microphone (“mic”) 1865 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1864, which in turn may be communicatively coupled to DSP 1860. In at least one embodiment, audio unit 1864 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1857 may be communicatively coupled to WWAN unit 1856. In at least one embodiment, components such as WLAN unit 1850, Bluetooth unit 1852, and WWAN unit 1856 can be implemented as next-generation form factor (NGFF).

[0157] Figure 19 An exemplary integrated circuit 1900 according to at least one embodiment is illustrated. In at least one embodiment, the exemplary integrated circuit 1900 is a SoC (System-on-a-Chip) that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1900 includes peripheral or bus logic, which includes a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I... 2 S / I 2 C controller 1940. In at least one embodiment, integrated circuit 1900 may include display device 1945 coupled to one or more of high-definition multimedia interface (HDMI) controller 1950 and mobile industrial processor interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by flash memory subsystem 1960, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1970.

[0158] Figure 20A computing system 2000 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset assembly or may be integrated within one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, the I / O subsystem 2011 includes an I / O hub 2007 that enables the computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, the I / O hub 2007 may enable a display controller, included in one or more processors 2002, for providing output to one or more display devices 2010A. In at least one embodiment, one or more display devices 2010A coupled to the I / O hub 2007 may include local, internal or embedded display devices.

[0159] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 2012 form a computationally concentrated parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 2012 form a graphics processing subsystem capable of outputting pixels to one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, the one or more parallel processors 2012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2010B.

[0160] In at least one embodiment, system storage unit 2014 may be connected to I / O hub 2007 to provide a storage mechanism for computing system 2000. In at least one embodiment, I / O switch 2016 may be used to provide an interface mechanism to enable connectivity between I / O hub 2007 and other components, such as network adapter 2018 and / or wireless network adapter 2019 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2020. In at least one embodiment, network adapter 2018 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2019 may include one or more network devices including Wi-Fi, Bluetooth, NFC, or other network devices comprising one or more radios.

[0161] In at least one embodiment, the computing system 2000 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 2007. In at least one embodiment, for Figure 20 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocols).

[0162] In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, memory hub 2005, processor 2002, and I / O hub 2007 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 2000 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2000 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system. In at least one embodiment, the I / O subsystem 2011 and display device 2010B are omitted from the computing system 2000.

[0163] Processing system

[0164] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment. In at least one embodiment, one or more processing systems of the figures below can implement, regarding... Figure 1-14 One or more aspects of one or more of the embodiments described, and / or about Figure 8-11 Describing one or more technologies.

[0165] Figure 21 An accelerated processing unit (“APU”) 2100 according to at least one embodiment is illustrated. In at least one embodiment, the APU 2100 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the APU 2100 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 2100 includes, but is not limited to, a core complex 2110, a graphics complex 2140, an architecture 2160, an I / O interface 2170, a memory controller 2180, a display controller 2192, and a multimedia engine 2194. In at least one embodiment, the APU 2100 can be, but is not limited to, any combination of any number of core complexes 2110, any number of graphics complexes 2140, any number of display controllers 2192, and any number of multimedia engines 2194. For illustrative purposes, multiple instances of similar objects are indicated herein by reference numerals, wherein the reference numerals identify the object, and the numbers in parentheses identify the desired instances.

[0166] In at least one embodiment, core complex 2110 is a CPU, graphics complex 2140 is a GPU, and APU 2100 is a processing unit that is not limited to 2110 and 2140 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 2110, while other tasks may be assigned to graphics complex 2140. In at least one embodiment, core complex 2110 is configured to execute main control software associated with APU 2100, such as an operating system. In at least one embodiment, core complex 2110 is the main processor of APU 2100, which controls and coordinates the operation of other processors. In at least one embodiment, core complex 2110 issues commands to control the operation of graphics complex 2140. In at least one embodiment, core complex 2110 may be configured to execute host executable code derived from CUDA source code, and graphics complex 2140 may be configured to execute device executable code derived from CUDA source code.

[0167] In at least one embodiment, the core complex 2110 includes, but is not limited to, cores 2120(1)-2120(4) and L3 cache 2130. In at least one embodiment, the core complex 2110 may include, but is not limited to, any combination of any number of cores 2120 and any number and type of cache. In at least one embodiment, the cores 2120 are configured to execute instructions of a specific instruction set architecture (“ISA”). In at least one embodiment, each core 2120 is a CPU core.

[0168] In at least one embodiment, each core 2120 includes, but is not limited to, a fetch / decode unit 2122, an integer execution engine 2124, a floating-point execution engine 2126, and an L2 cache 2128. In at least one embodiment, the fetch / decode unit 2122 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 2124 and the floating-point execution engine 2126. In at least one embodiment, the fetch / decode unit 2122 may simultaneously dispatch one micro-instruction to the integer execution engine 2124 and another micro-instruction to the floating-point execution engine 2126. In at least one embodiment, the integer execution engine 2124 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 2126 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 2122 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 2124 and the floating-point execution engine 2126.

[0169] In at least one embodiment, each core 2120(i) can access an L2 cache 2128(i) included in core 2120(i), where i is an integer representing a specific instance of core 2120. In at least one embodiment, each core 2120 included in core complex 2110(j) is connected to other cores 2120 included in core complex 2110(j) via an L3 cache 2130(j) included in core complex 2110(j), where j is an integer representing a specific instance of core complex 2110. In at least one embodiment, a core 2120 included in core complex 2110(j) can access all L3 caches 2130(j) included in core complex 2110(j), where j is an integer representing a specific instance of core complex 2110. In at least one embodiment, the L3 cache 2130 may include, but is not limited to, any number of slices.

[0170] In at least one embodiment, the graphics complex 2140 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 2140 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 2140 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 2140 is configured to perform both graphics-related and graphics-independent operations.

[0171] In at least one embodiment, the graphics complex 2140 includes, but is not limited to, any number of computing units 2150 and an L2 cache 2142. In at least one embodiment, the computing units 2150 share the L2 cache 2142. In at least one embodiment, the L2 cache 2142 is partitioned. In at least one embodiment, the graphics complex 2140 includes, but is not limited to, any number of computing units 2150 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 2140 includes, but is not limited to, any number of dedicated graphics hardware.

[0172] In at least one embodiment, each computing unit 2150 includes, but is not limited to, any number of SIMD units 2152 and shared memory 2154. In at least one embodiment, each SIMD unit 2152 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each computing unit 2150 may execute any number of thread blocks, but each thread block executes on a single computing unit 2150. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 2152 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 2154.

[0173] In at least one embodiment, structure 2160 is a system interconnect that facilitates data and control transfers across core complex 2110, graphics complex 2140, I / O interface 2170, memory controller 2180, display controller 2192, and multimedia engine 2194. In at least one embodiment, in addition to or instead of structure 2160, APU 2100 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either internally or externally to APU 2100. In at least one embodiment, I / O interface 2170 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 2170. In at least one embodiment, the peripheral device coupled to the I / O interface 2170 may include, but is not limited to, a keyboard, mouse, printer, scanner, joystick or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0174] In at least one embodiment, the display controller AMD92 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 2180 facilitates data transfer between the APU 2100 and the unified system memory 2190. In at least one embodiment, the core complex 2110 and the graphics complex 2140 share the unified system memory 2190.

[0175] In at least one embodiment, the APU 2100 implements a memory subsystem, including but not limited to any number and type of memory controllers 2180 and memory devices (e.g., shared memory 2154) that may be dedicated to a single component or shared among multiple components. In at least one embodiment, the APU 2100 implements a cache subsystem, including but not limited to one or more cache memories (e.g., L2 cache 2228, L3 cache 2130, and L2 cache 2142), each cache memory being component-private or shared among any number of components (e.g., core 2120, core complex 2110, SIMD unit 2152, compute unit 2150, and graphics complex 2140).

[0176] Figure 22A CPU 2200 according to at least one embodiment is illustrated. In at least one embodiment, the CPU 2200 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the CPU 2200 can be configured to execute an application. In at least one embodiment, the CPU 2200 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 2200 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 2200 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 2200 includes, but is not limited to, any number of core complexes 2210, architectures 2260, I / O interfaces 2270, and memory controllers 2280.

[0177] In at least one embodiment, the core complex 2210 includes, but is not limited to, cores 2220(1)-2220(4) and L3 cache 2230. In at least one embodiment, the core complex 2210 may include, but is not limited to, any combination of any number of cores 2220 and any number and type of cache. In at least one embodiment, the cores 2220 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 2220 is a CPU core.

[0178] In at least one embodiment, each core 2220 includes, but is not limited to, a fetch / decode unit 2222, an integer execution engine 2224, a floating-point execution engine 2226, and an L2 cache 2228. In at least one embodiment, the fetch / decode unit 2222 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 2224 and the floating-point execution engine 2226. In at least one embodiment, the fetch / decode unit 2222 may simultaneously dispatch one micro-instruction to the integer execution engine 2224 and another micro-instruction to the floating-point execution engine 2226. In at least one embodiment, the integer execution engine 2224 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 2226 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 2222 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 2224 and the floating-point execution engine 2226.

[0179] In at least one embodiment, each core 2220(i) can access an L2 cache 2228(i) included in core 2220(i), where i is an integer representing a specific instance of core 2220. In at least one embodiment, each core 2220 included in core complex 2210(j) is connected to other cores 2220 in core complex 2210(j) via an L3 cache 2230(j) included in core complex 2210(j), where j is an integer representing a specific instance of core complex 2210. In at least one embodiment, a core 2220 included in core complex 2210(j) can access all L3 caches 2230(j) included in core complex 2210(j), where j is an integer representing a specific instance of core complex 2210. In at least one embodiment, the L3 cache 2230 may include, but is not limited to, any number of slices.

[0180] In at least one embodiment, structure 2260 is a system interconnect that facilitates data and control transfers across core complexes 2210(1)-2210(N) (where N is a positive integer), I / O interface 2270, and memory controller 2280. In at least one embodiment, in addition to or instead of structure 2260, CPU 2200 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 2200. In at least one embodiment, I / O interface 2270 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 2270. In at least one embodiment, peripheral devices coupled to I / O interface 2270 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0181] In at least one embodiment, memory controller 2280 facilitates data transfer between CPU 2200 and system memory 2290. In at least one embodiment, core complex 2210 and graphics complex 2240 share system memory 2290. In at least one embodiment, CPU 2200 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 2280 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 2200 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 2228 and L3 cache 2230), each cache memory may be component-private or shared among any number of components (e.g., core 2220 and core complex 2210).

[0182] Figure 23 An exemplary accelerator integration slice 2390 according to at least one embodiment is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for multiple graphics processing engines among multiple graphics acceleration modules. Each graphics processing engine may comprise a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0183] The application's effective address space 2382 within system memory 2314 stores process element 2383. In one embodiment, process element 2383 is stored in response to a GPU call 2381 from an application 2380 executing on processor 2307. Process element 2383 contains the processing state of the corresponding application 2380. A job descriptor (WD) 2384 contained in process element 2383 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 2384 is a pointer to a job request queue in the application's effective address space 2382.

[0184] The graphics acceleration module 2346 and / or the various graphics processing engines may be shared by all or some processes in the system. In at least one embodiment, infrastructure may be included for establishing a processing state and sending WD 2384 to the graphics acceleration module 2346 to begin operation in a virtualized environment.

[0185] In at least one embodiment, a dedicated process programming model is used for implementation. In this model, a single process owns the graphics acceleration module 2346 or an individual graphics processing engine. Since the graphics acceleration module 2346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 2346 is allocated.

[0186] During operation, the WD fetch unit 2391 in the accelerator integrated slice 2390 fetches the next WD 2384, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 2346. Data from the WD 2384 can be stored in register 2345 and used by the memory management unit (MMU) 2339, interrupt management circuitry 2347, and / or environment management circuitry 2348, as shown. For example, one embodiment of the MMU 2339 includes segment / page roaming circuitry for accessing segment / page tables 2386 within the OS virtual address space 2385. The interrupt management circuitry 2347 can handle interrupt events (INT) 2392 received from the graphics acceleration module 2346. When performing graph operations, the effective address 2393 generated by the graphics processing engine is translated into an actual address by the MMU 2339.

[0187] In one embodiment, the same register set 2345 is copied for each graphics processing engine and / or graphics acceleration module 2346 and can be initialized by the hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 2390. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0188] Table 1 – Registers for Supervisor Initialization

[0189] 1 Slice Control Register 2 Real Address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restrictions 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilization Record Pointer 9 Storage description register

[0190] Table 2 shows exemplary registers that can be initialized by the operating system.

[0191] Table 2 – Operating System Initialization Registers

[0192] 1 Process and thread identification 2 Valid Address (EA) Environment Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) stores segment table pointers 5 Access Control 6 Job descriptor

[0193] In one embodiment, each WD 2384 is specific to a particular graphics acceleration module 2346 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to perform its work or to do so, or it may be a pointer to a memory location where the application has established a command queue for the work to be done.

[0194] Figures 24A-24B An exemplary graphics processor according to at least one embodiment herein is illustrated. In at least one embodiment, any exemplary graphics processor may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processor / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a System-on-a-Chip (SoC).

[0195] Figure 24A An exemplary graphics processor 2410 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 24B An additional exemplary graphics processor 2440 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 24A The graphics processor 2410 is a low-power graphics processor core. In at least one embodiment, Figure 24B The graphics processor 2440 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2410, 2440 may be... Figure 19 A variant of the 1910 graphics processor.

[0196] In at least one embodiment, the graphics processor 2410 includes a vertex processor 2405 and one or more fragment processors 2415A-2415N (e.g., 2415A, 2415B, 2415C, 2415D to 2415N-1 and 2415N). In at least one embodiment, the graphics processor 2410 can execute different shader programs via separate logic, such that the vertex processor 2405 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2415A-2415N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2405 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, the fragment processors 2415A-2415N use the primitive and vertex data generated by the vertex processor 2405 to generate framebuffers for display on a display device. In at least one embodiment, the fragment processors 2415A-2415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0197] In at least one embodiment, the graphics processor 2410 additionally includes one or more MMUs 2420A-2420B, caches 2425A-2425B, and circuit interconnects 2430A-2430B. In at least one embodiment, one or more MMUs 2420A-2420B provide a virtual-to-physical address mapping for the graphics processor 2410, including for the vertex processor 2405 and / or fragment processors 2415A-2415N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 2425A-2425B. In at least one embodiment, one or more MMUs 2420A-2420B can be synchronized with other MMUs within the system, including with... Figure 19 One or more application processors 1905, graphics processors 1915, and / or video processors 1920 are associated with one or more MMUs, enabling each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2430A-2430B enable the graphics processor 2410 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0198] In at least one embodiment, the graphics processor 2440 includes Figure 24A The graphics processor 2410 includes one or more MMUs 2420A-2420B, caches 2425A-2425B, and circuit interconnects 2430A-2430B. In at least one embodiment, the graphics processor 2440 includes one or more shader cores 2455A-2455N (e.g., 2455A, 2455B, 2455C, 2455D, 2455E, 2455F, to 2455N-1 and 2455N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 2440 includes an inter-core task manager 2445 that acts as a thread dispatcher to assign execution threads to one or more shader cores 2455A-2455N and a tile unit 2458 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0199] Figure 25AA graphics core 2500 according to at least one embodiment is shown. In at least one embodiment, the graphics core 2500 may include... Figure 19 The graphics processor 1910 is located within it. In at least one embodiment, the graphics core 2500 may be... Figure 24B The graphics core 2500 uses a unified shader core 2455A-2455N. In at least one embodiment, the graphics core 2500 includes a shared instruction cache 2502, texture units 2518, and cache / shared memory 2520, which are common to execution resources within the graphics core 2500. In at least one embodiment, the graphics core 2500 may include multiple slices 2501A-2501N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2500. Slices 2501A-2501N may include supporting logic, including local instruction caches 2504A-2504N, thread schedulers 2506A-2506N, thread dispatchers 2508A-2508N, and a set of registers 2510A-2510N. In at least one embodiment, slices 2501A-2501N may include a set of additional functional units (AFU) 2512A-2512N, floating-point units (FPU) 2514A-2514N, integer arithmetic logic units (ALU) 2516A-2516N, address calculation units (ACU) 2513A-2513N, double-precision floating-point units (DPFPU) 2515A-2515N, and matrix processing units (MPU) 2517A-2517N.

[0200] In one embodiment, the FPU 2514A-2514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2515A-2515N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2516A-2516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2517A-2517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2517A-2517N can perform various matrix operations to accelerate CUDA programs, including enabling accelerated Generalized Matrix-to-Matrix Multiplication (GEMM). In at least one embodiment, the AFU 2512A-2512N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0201] Figure 25BA general-purpose graphics processing unit (GPGPU) 2530 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 2530 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 2530 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 2530 can be directly linked to other instances of the GPGPU 2530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 2530 includes a host interface 2532 for connection to a host processor. In at least one embodiment, the host interface 2532 is a PCIe interface. In at least one embodiment, the host interface 2532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2530 receives commands from the host processor and uses a global scheduler 2534 to assign execution threads associated with those commands to a set of compute clusters 2536A-2536H. In at least one embodiment, computing clusters 2536A-2536H share cache memory 2538. In at least one embodiment, cache memory 2538 can be used as an advanced cache of cache memory within computing clusters 2536A-2536H.

[0202] In at least one embodiment, the GPGPU 2530 includes memory 2544A-2544B coupled to computing clusters 2536A-2536H via a set of memory controllers 2542A-2542B. In at least one embodiment, memory 2544A-2544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0203] In at least one embodiment, computing clusters 2536A-2536H each include a set of graphics cores, such as Figure 25A The graphics core 2500 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2536A-2536H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0204] In at least one embodiment, multiple instances of the GPGPU 2530 can be configured to operate as a computing cluster. The computing clusters 2536A-2536H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, the multiple instances of the GPGPU 2530 communicate via a host interface 2532. In at least one embodiment, the GPGPU 2530 includes an I / O hub 2539 that couples the GPGPU 2530 to a GPU link 2540, enabling direct connection to other instances of the GPGPU 2530. In at least one embodiment, the GPU link 2540 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of the GPGPU 2530. In at least one embodiment, the GPU link 2540 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 2530 reside in a separate data processing system and communicate via a network device accessible via the host interface 2532. In at least one embodiment, the GPU link 2540 may be configured to connect to a host processor, supplementing or replacing the host interface 2532. In at least one embodiment, the GPGPU 2530 may be configured to execute CUDA programs.

[0205] Figure 26A A parallel processor 2600 according to at least one embodiment is shown. In at least one embodiment, various components of the parallel processor 2600 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or FPGAs.

[0206] In at least one embodiment, the parallel processor 2600 includes a parallel processing unit 2602. In at least one embodiment, the parallel processing unit 2602 includes an I / O unit 2604 that enables communication with other devices, including other instances of the parallel processing unit 2602. In at least one embodiment, the I / O unit 2604 can be directly connected to other devices. In at least one embodiment, the I / O unit 2604 is connected to other devices using a hub or switch interface (e.g., memory hub 1405). In at least one embodiment, the connection between the memory hub 1405 and the I / O unit 2604 forms a communication link. In at least one embodiment, the I / O unit 2604 is connected to a host interface 2606 and a memory crossbar switch 2616, wherein the host interface 2606 receives commands for performing processing operations, and the memory crossbar switch 2616 receives commands for performing memory operations.

[0207] In at least one embodiment, when host interface 2606 receives a command buffer via I / O unit 2604, host interface 2606 can direct work operations to execute those commands to front end 2608. In at least one embodiment, front end 2608 is coupled to scheduler 2610, which is configured to assign commands or other work items to processing array 2612. In at least one embodiment, scheduler 2610 ensures that processing array 2612 is correctly configured and in an active state before assigning tasks to processing array 2612. In at least one embodiment, scheduler 2610 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2610 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, enabling fast preemption and environment switching of threads executing on processing array 2612. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2612 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2612 by the scheduler 2610 logic within the microcontroller, which includes the scheduler 2610.

[0208] In at least one embodiment, the processing array 2612 may include up to "N" processing clusters (e.g., clusters 2614A, 2614B to 2614N). In at least one embodiment, each cluster 2614A-2614N of the processing array 2612 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2610 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2614A-2614N of the processing array 2612, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2610, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2612. In at least one embodiment, different clusters 2614A-2614N of the processing array 2612 may be assigned to process different types of programs or to perform different types of computations.

[0209] In at least one embodiment, the processing array 2612 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2612 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2612 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0210] In at least one embodiment, the processing array 2612 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2612 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2612 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2602 may transfer data from system memory via I / O unit 2604 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2622) and then written back to system memory.

[0211] In at least one embodiment, when the parallel processing unit 2602 is used to perform graph processing, the scheduler 2610 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2614A-2614N of the processing array 2612. In at least one embodiment, portions of the processing array 2612 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2614A-2614N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2614A-2614N for further processing.

[0212] In at least one embodiment, the processing array 2612 may receive processing tasks to be executed via a scheduler 2610, which receives commands defining the processing tasks from a front end 2608. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2610 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2608. In at least one embodiment, the front end 2608 may be configured to ensure that the processing array 2612 is configured to be active before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0213] In at least one embodiment, each of one or more instances of the parallel processing unit 2602 may be coupled to the parallel processor memory 2622. In at least one embodiment, the parallel processor memory 2622 may be accessed via a memory crossbar switch 2616, which may receive memory requests from the processing array 2612 and the I / O unit 2604. In at least one embodiment, the memory crossbar switch 2616 may be accessed via a memory interface 2618. In at least one embodiment, the memory interface 2618 may include a plurality of partition units (e.g., partition units 2620A, 2620B to 2620N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2622. In at least one embodiment, the plurality of partition units 2620A-2620N are configured to be equal to the number of memory units, such that the first partition unit 2620A has a corresponding first memory unit 2624A, the second partition unit 2620B has a corresponding memory unit 2624B, and the Nth partition unit 2620N has a corresponding Nth memory unit 2624N. In at least one embodiment, the number of partition units 2620A-2620N may not be equal to the number of memory devices.

[0214] In at least one embodiment, memory cells 2624A-2624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2624A-2624N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2624A-2624N, allowing partitioning cells 2620A-2620N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2622. In at least one embodiment, local instances of the parallel processor memory 2622 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0215] In at least one embodiment, any of the clusters 2614A-2614N of the processing array 2612 can process data to be written to any memory cell 2624A-2624N within the parallel processor memory 2622. In at least one embodiment, the memory crossbar switch 2616 can be configured to transfer the output of each cluster 2614A-2614N to any partition cell 2620A-2620N or another cluster 2614A-2614N, and the clusters 2614A-2614N can perform further processing operations on the output. In at least one embodiment, each cluster 2614A-2614N can communicate with the memory interface 2618 via the memory crossbar switch 2616 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2616 has a connection to a memory interface 2618 for communication with I / O unit 2604, and a connection to a local instance of parallel processor memory 2622, thereby enabling processing units within different processing clusters 2614A-2614N to communicate with system memory or other memory not local to parallel processing unit 2602. In at least one embodiment, the memory crossbar switch 2616 may use virtual channels to separate traffic flows between clusters 2614A-2614N and partition units 2620A-2620N.

[0216] In at least one embodiment, multiple instances of the parallel processing unit 2602 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2602 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2602 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2602 or the parallel processor 2600 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0217] Figure 26BA processing cluster 2694 according to at least one embodiment is illustrated. In at least one embodiment, the processing cluster 2694 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2694 is an example of one of the processing clusters 2614A-2614N of FIG. 26. In at least one embodiment, the processing cluster 2694 may be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2694.

[0218] In at least one embodiment, the operation of the processing cluster 2694 can be controlled by a pipeline manager 2632 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2632 receives instructions from the scheduler 2610 of FIG. 26 and manages the execution of these instructions via the graphics multiprocessor 2634 and / or texture unit 2636. In at least one embodiment, the graphics multiprocessor 2634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2694 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2694 may include one or more instances of the graphics multiprocessor 2634. In at least one embodiment, the graphics multiprocessor 2634 can process data, and the data cross switch 2640 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2632 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 2640.

[0219] In at least one embodiment, each graphics multiprocessor 2634 within the processing cluster 2694 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units (LSUs), etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0220] In at least one embodiment, instructions transmitted to the processing cluster 2694 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2634. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2634. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2634. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2634, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2634.

[0221] In at least one embodiment, the graphics multiprocessor 2634 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2634 may forgo the internal cache and use a cache memory within the processing cluster 2694 (e.g., L1 cache 2648). In at least one embodiment, each graphics multiprocessor 2634 may also access partition units (e.g., Figure 26A The L2 cache is located within partition units 2620A-2620N, which are shared among all processing clusters 2694 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2634 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2602 can be used as global memory. In at least one embodiment, the processing cluster 2694 includes multiple instances of the graphics multiprocessor 2634, which can share common instructions and data that can be stored in the L1 cache 2648.

[0222] In at least one embodiment, each processing cluster 2694 may include an MMU 2645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2645 may reside within the memory interface 2618 of FIG. 26. In at least one embodiment, the MMU 2645 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more information about tiles) and optionally to cache line indices. In at least one embodiment, the MMU 2645 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2634, the L1 cache 2648, or the processing cluster 2694. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0223] In at least one embodiment, the processing cluster 2694 may be configured such that each graphics multiprocessor 2634 is coupled to a texture unit 2636 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2634, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2634 outputs a processed task to a data crossbar switch 2640 to provide the processed task to another processing cluster 2694 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2616. In at least one embodiment, the pre-raster operation unit (preROP) 2642 is configured to receive data from the graphics multiprocessor 2634 and direct the data to a ROP unit that may be located together with partitioning units described herein (e.g., partitioning units 2620A-2620N of FIG. 26). In at least one embodiment, the PreROP 2642 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0224] Figure 26C A graphics multiprocessor 2696 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2696 is Figure 26BThe graphics multiprocessor 2634 is included. In at least one embodiment, the graphics multiprocessor 2696 is coupled to the pipeline manager 2632 of the processing cluster 2694. In at least one embodiment, the graphics multiprocessor 2696 has an execution pipeline including, but not limited to, an instruction cache 2652, an instruction unit 2654, an address mapping unit 2656, a register file 2658, one or more GPGPU cores 2662, and one or more LSUs 2666. The GPGPU cores 2662 and LSUs 2666 are coupled to cache memory 2672 and shared memory 2670 via memory and cache interconnect 2668.

[0225] In at least one embodiment, instruction cache 2652 receives a stream of instructions to be executed from pipeline manager 2632. In at least one embodiment, instructions are cached in instruction cache 2652 and dispatched to instruction unit 2654 for execution. In one embodiment, instruction unit 2654 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2662. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2656 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by LSU 2666.

[0226] In at least one embodiment, register file 2658 provides a set of registers for functional units of graphics multiprocessor 2696. In at least one embodiment, register file 2658 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2696 (e.g., GPGPU core 2662, LSU 2666). In at least one embodiment, register file 2658 is partitioned among each functional unit, such that a dedicated portion of register file 2658 is allocated to each functional unit. In at least one embodiment, register file 2658 is partitioned among different thread groups being executed by graphics multiprocessor 2696.

[0227] In at least one embodiment, each of the GPGPU cores 2662 may include an FPU and / or an ALU for executing instructions of the graph multiprocessor 2696. The GPGPU cores 2662 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2662 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2608 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2696 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2662 may also include fixed-function or special-function logic.

[0228] In at least one embodiment, the GPGPU core 2662 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2662 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0229] In at least one embodiment, the memory and cache interconnect 2668 is an interconnect network connecting each functional unit of the graphics multiprocessor 2696 to the register file 2658 and the shared memory 2670. In at least one embodiment, the memory and cache interconnect 2668 is a cross-switch interconnect that allows the LSU 2666 to perform load and store operations between the shared memory 2670 and the register file 2658. In at least one embodiment, the register file 2658 can operate at the same frequency as the GPGPU core 2662, resulting in very low latency for data transfer between the GPGPU core 2662 and the register file 2658. In at least one embodiment, the shared memory 2670 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2696. In at least one embodiment, the cache memory 2672 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2636. In at least one embodiment, the shared memory 2670 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2672, the thread executing on GPGPU core 2662 can also programmatically store data in shared memory.

[0230] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0231] Figure 27A graphics processor 2700 according to at least one embodiment is illustrated. In at least one embodiment, the graphics processor 2700 includes a ring interconnect 2702, a pipeline front end 2704, a media engine 2737, and graphics cores 2780A-2780N. In at least one embodiment, the ring interconnect 2702 couples the graphics processor 2700 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2700 is one of many processors integrated within a multi-core processing system.

[0232] In at least one embodiment, the graphics processor 2700 receives multiple batches of commands via a ring interconnect 2702. In at least one embodiment, the input commands are interpreted by a command stream converter 2703 in a pipeline front-end 2704. In at least one embodiment, the graphics processor 2700 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2780A-2780N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2703 provides commands to the geometry pipeline 2736. In at least one embodiment, for at least some media processing commands, the command stream converter 2703 provides commands to a video front-end 2734, which is coupled to a media engine 2737. In at least one embodiment, the media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2733 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2736 and the media engine 2737 each generate an execution thread for the thread execution resources provided by at least one graphics core 2780A.

[0233] In at least one embodiment, the graphics processor 2700 includes scalable thread execution resources characterized by modular graphics cores 2780A-2780N (sometimes referred to as core slices), each modular core having multiple sub-cores 2750A-2750N, 2760A-2760N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2700 may have any number of graphics cores 2780A to 2780N. In at least one embodiment, the graphics processor 2700 includes a graphics core 2780A having at least a first sub-core 2750A and a second sub-core 2760A. In at least one embodiment, the graphics processor 2700 is a low-power processor having a single sub-core (e.g., 2750A). In at least one embodiment, the graphics processor 2700 includes multiple graphics cores 2780A-2780N, each graphics core including a set of first sub-cores 2750A-2750N and a set of second sub-cores 2760A-2760N. In at least one embodiment, each of the first sub-cores 2750A-2750N includes at least a first set of execution units (EUs) 2752A-2752N and media / texture samplers 2754A-2754N. In at least one embodiment, each of the second sub-cores 2760A-2760N includes at least a second set of execution units 2762A-2762N and samplers 2764A-2764N. In at least one embodiment, each sub-core 2750A-2750N and 2760A-2760N shares a set of shared resources 2770A-2770N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0234] Figure 28 A processor 2800 is illustrated according to at least one embodiment. In at least one embodiment, the processor 2800 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2800 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for ASICs, etc. In at least one embodiment, the processor 2810 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanied by SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2810 can execute instructions to accelerate CUAD programs.

[0235] In at least one embodiment, processor 2800 includes an ordered front end (“front end”) 2801 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2801 may include several units. In at least one embodiment, instruction prefetcher 2826 fetches instructions from memory and provides the instructions to instruction decoder 2828, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2828 decodes the received instructions for execution of one or more so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2828 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operation. In at least one embodiment, trace cache 2830 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2834 for execution. In at least one embodiment, when trace cache 2830 encounters complex instructions, microcode ROM 2832 provides the micro-instructions required to complete the operation.

[0236] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2828 may access the microcode ROM 2832 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2828. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2832. In at least one embodiment, the trace cache 2830 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2832 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2832 has completed the micro-operation ordering of the instructions, the machine front end 2801 may resume fetching micro-operations from the trace cache 2830.

[0237] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2803 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2803 includes, but is not limited to, an allocator / register renamer 2840, a memory microinstruction queue 2842, an integer / floating-point microinstruction queue 2844, a memory scheduler 2846, a fast scheduler 2802, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2804, and a simple floating-point scheduler (“simple FP scheduler”) 2806. In at least one embodiment, the fast scheduler 2802, the slow / general-purpose floating-point scheduler 2804, and the simple floating-point scheduler 2806 are also collectively referred to as “microinstruction schedulers 2802, 2804, 2806”. The allocator / register renamer 2840 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2840 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2840 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2842 for memory operations and integer / floating-point microinstruction queue 2844 for non-memory operations, preceding the memory scheduler 2846 and microinstruction schedulers 2802, 2804, 2806. In at least one embodiment, the microinstruction schedulers 2802, 2804, 2806 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2802 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2804 and the simple floating-point scheduler 2806 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2802, 2804, and 2806 arbitrate the scheduling port to schedule microinstructions for execution.

[0238] In at least one embodiment, execution block 2811 includes, but is not limited to, integer register file / tribute network 2808, floating-point register file / tribute network (“FP register file / tribute network”) 2810, address generation units (“AGU”) 2812 and 2814, fast arithmetic logic units (“fast ALU”) 2816 and 2818, slow ALU 2820, floating-point ALU (“FP”) 2822, and floating-point move unit (“FP move”) 2824. In at least one embodiment, integer register file / tribute network 2808 and floating-point register file / bypass network 2810 are also referred to herein as “register files 2808, 2810”. In at least one embodiment, AGUS 2812 and 2814, fast ALU 2816 and 2818, slow ALU 2820, floating-point ALU 2822, and floating-point movement unit 2824 are also referred to herein as "execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824". In at least one embodiment, the execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0239] In at least one embodiment, register files 2808, 2810 may be arranged between microinstruction schedulers 2802, 2804, 2806 and execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824. In at least one embodiment, integer register file / tribute network 2808 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2810 performs floating-point operations. In at least one embodiment, each of register files 2808, 2810 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2808, 2810 can communicate data with each other. In at least one embodiment, integer register file / tribute network 2808 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2810 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0240] In at least one embodiment, execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824 can execute instructions. In at least one embodiment, register files 2808 and 2810 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2800 may include, but is not limited to, any number of execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824, and combinations thereof. In at least one embodiment, floating-point ALU 2822 and floating-point move unit 2824 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2822 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2816 and 2818. In at least one embodiment, the fast ALUs 2816 and 2818 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2820, because the slow ALU 2820 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by the ALUs 2812 and 2814. In at least one embodiment, the fast ALU 2816, fast ALU 2818, and slow ALU 2820 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2816, fast ALU 2818, and slow ALU 2820 can be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2822 and the floating-point movement unit 2824 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2822 and the floating-point movement unit 2824 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0241] In at least one embodiment, microinstruction schedulers 2802, 2804, and 2806 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2800, processor 2800 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0242] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0243] Figure 29 A processor 2900 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2900 includes, but is not limited to, one or more processor cores (cores) 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908. In at least one embodiment, the processor 2900 may include additional cores up to and including additional processor cores 2902N, indicated by dashed boxes. In at least one embodiment, each processor core 2902A-2902N includes one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core may also access one or more units 2906 of a shared cache.

[0244] In at least one embodiment, internal cache units 2904A-2904N and shared cache unit 2906 represent a cache memory hierarchy within processor 2900. In at least one embodiment, cache memory units 2904A-2904N may include at least one level of instruction and data within each processor core, and one or more levels of cache in a shared intermediate cache, such as L2, L3, L4, or other levels of cache, wherein the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2906 and 2904A-2904N.

[0245] In at least one embodiment, the processor 2900 may further include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2910 provides management functions for various processor components. In at least one embodiment, the system agent core 2910 includes one or more integrated memory controllers 2914 to manage access to various external memory devices (not shown).

[0246] In at least one embodiment, one or more processor cores 2902A-2902N include support for concurrent multithreading. In at least one embodiment, system agent core 2910 includes components for coordinating and operating processor cores 2902A-2902N during multithreaded processing. In at least one embodiment, system agent core 2910 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2902A-2902N and graphics processor 2908.

[0247] In at least one embodiment, processor 2900 further includes graphics processor 2908 to perform graphics processing operations. In at least one embodiment, graphics processor 2908 is coupled to a shared cache unit 2906 and a system agent core 2910 including one or more integrated memory controllers 2914. In at least one embodiment, system agent core 2910 further includes a display controller 2911 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2911 may also be a separate module coupled to graphics processor 2908 via at least one interconnect, or it may be integrated within graphics processor 2908.

[0248] In at least one embodiment, ring-based interconnect unit 2912 is used to couple internal components of processor 2900. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2908 is coupled to ring interconnect 2912 via I / O link 2913.

[0249] In at least one embodiment, I / O link 2913 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2918 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2902A-2902N and graphics processor 2908 uses embedded memory module 2918 as a shared LLC.

[0250] In at least one embodiment, processor cores 2902A-2902N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of the instruction set architecture (ISA), with one or more processor cores 2902A-2902N executing a common instruction set, while one or more other processor cores 2902A-2902N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2900 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0251] Figure 30 A graphics processor core 3000 according to at least one embodiment described is illustrated. In at least one embodiment, the graphics processor core 3000 is included within a graphics core array. In at least one embodiment, the graphics processor core 3000 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 3000 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 3000 may include a fixed-function block 3030, also referred to as a sub-slice, coupled to a plurality of sub-cores 3001A-3001F, which includes modular blocks of general-purpose and fixed-function logic.

[0252] In at least one embodiment, the fixed-function block 3030 includes a geometry / fixed-function pipeline 3036, which, for example, may be shared by all sub-cores of the graphics processor 3000 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 3036 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0253] In at least one embodiment, the fixed functional block 3030 further includes a graphics SoC interface 3037, a graphics microcontroller 3038, and a media pipeline 3039. The graphics SoC interface 3037 provides an interface between the graphics core 3000 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 3038 is a programmable subprocessor configurable to manage various functions of the graphics processor 3000, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 3039 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 3039 implements media operations via requests for computation or sampling logic within subcores 3001-3001F.

[0254] In at least one embodiment, the SoC interface 3037 enables the graphics core 3000 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 3037 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 3000 and the CPU within the SoC. In at least one embodiment, the SoC interface 3037 also implements power management control for the graphics core 3000 and enables interfacing between the clock domain of the graphics core 3000 and other clock domains within the SoC. In at least one embodiment, the SoC interface 3037 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 3039, or when a graph processing operation is to be performed, they can be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 3036 and 3014).

[0255] In at least one embodiment, the graphics microcontroller 3038 can be configured to perform various scheduling and management tasks on the graphics core 3000. In at least one embodiment, the graphics microcontroller 3038 can perform graph and / or computational workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 3002A-3002F, 3004A-3004F in subcores 3001A-3001F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 3000 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 3038 may also facilitate a low-power or idle state of the graphics core 3000, thereby providing the graphics core 3000 with the ability to save and restore registers across low-power state transitions within the graphics core 3000, independent of the operating system and / or the graphics driver software on the system.

[0256] In at least one embodiment, the graphics core 3000 may have more or fewer subcores than the illustrated subcores 3001A-3001F, up to N modular subcores. For each group of N subcores, in at least one embodiment, the graphics core 3000 may further include shared functional logic 3010, shared and / or cache memory 3012, geometry / fixed-function pipeline 3014, and additional fixed-function logic 3016 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 3010 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N subcores within the graphics core 3000. The shared and / or cache memory 3012 may be an LLC of the N subcores 3001A-3001F within the graphics core 3000, and may also be used as shared memory accessible by multiple subcores. In at least one embodiment, a geometry / fixed function pipeline 3014 may be included to replace the geometry / fixed function pipeline 3036 within the fixed function block 3030, and may include the same or similar logic units.

[0257] In at least one embodiment, the graphics core 3000 includes additional fixed-function logic 3016, which may include various fixed-function acceleration logics for use by the graphics core 3000. In at least one embodiment, the additional fixed-function logic 3016 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 3016, 3036, it is an additional geometry pipeline that can be included in the additional fixed-function logic 3016. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 3016 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0258] In at least one embodiment, the additional fixed-function logic 3016 may also include general target processing acceleration logic, such as fixed-function matrix multiplication logic, for implementing a decelerated CUAD program.

[0259] In at least one embodiment, each graphics subcore 3001A-3001F includes a set of execution resources that can be used to perform graph, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 3001A-3001F includes multiple EU arrays 3002A-3002F, 3004A-3004F, thread dispatch and inter-thread communication (TD / IC) logic 3003A-3003F, 3D (e.g., texture) samplers 3005A-3005F, media samplers 3006A-3006F, shader processors 3007A-3007F, and shared local memory (SLM) 3008A-3008F. Each of the EU arrays 3002A-3002F and 3004A-3004F contains multiple execution units, which are GUGPUs capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 3003A-3003F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 3005A-3005F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 3006A-3006F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 3001A-3001F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 3001A-3001F may utilize shared local memory 3008A-3008F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0260] Figure 31A parallel processing unit (“PPU”) 3100 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 3100 is configured with machine-readable code that, if executed by the PPU 3100, causes the PPU 3100 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 3100 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also known as machine-readable instructions or simple instructions) that are executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by the PPU 3100. In at least one embodiment, the PPU 3100 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 3100 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 31 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0261] In at least one embodiment, one or more PPUs 3100 are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 3100 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 3100 includes, but is not limited to, I / O unit 3106, front-end unit 3110, scheduler unit 3112, job allocation unit 3114, hub 3116, crossbar (“Xbar”) 3120, one or more general-purpose processing clusters (“GPC”) 3118, and one or more partitioning units (“memory partitioning units”) 3122. In at least one embodiment, the PPU 3100 is connected to a host processor or other PPU 3100 via one or more high-speed GPU interconnects (“GPU interconnects”) 3108. In at least one embodiment, the PPU 3100 is connected to a host processor or other peripheral devices via a system bus or interconnect 3102. In one embodiment, the PPU 3100 is connected to a local memory including one or more memory devices (“memory”) 3104. In at least one embodiment, the memory device 3104 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high bandwidth memory (“HBM”) subsystem, and multiple DRAM dies are stacked within each device.

[0262] In at least one embodiment, the high-speed GPU interconnect 3108 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 3100 (“CPUs”) coupled with one or more CPUs, supporting cache coherency between the PPUs 3100 and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 3108 transmits data and / or commands to other units of the PPU 3100 via a hub 3116, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components. Figure 31 Other components that may not be explicitly shown.

[0263] In at least one embodiment, I / O unit 3106 is configured to access the host processor via system bus 3102. Figure 31(Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 3106 communicates directly with the host processor via system bus 3102 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 3106 may communicate with one or more other processors (e.g., one or more PPUs 3100) via system bus 3102. In at least one embodiment, I / O unit 3106 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, I / O unit 3106 implements an interface for communication with external devices.

[0264] In at least one embodiment, I / O unit 3106 decodes packets received via system bus 3102. In at least one embodiment, at least some packets represent commands configured to cause PPU 3100 to perform various operations. In at least one embodiment, I / O unit 3106 sends the decoded commands to various other units of PPU 3100 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 3110 and / or to hub 3116 or other units of PPU 3100, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 31 (Not explicitly shown). In at least one embodiment, I / O unit 3106 is configured to route communication between various logical units of PPU 3100.

[0265] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 3100 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 3100—the host interface unit can be configured to access a buffer in system memory connected to the system bus 3102 via memory requests transmitted through the system bus 3102 via the I / O unit 3106. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 3100, such that the front-end unit 3110 receives pointers to one or more command streams and manages one or more command streams, reads commands from the command streams, and forwards the commands to the respective units of the PPU 3100.

[0266] In at least one embodiment, a front-end unit 3110 is coupled to a scheduler unit 3112, which configures various GPCs 3118 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 3112 is configured to track status information related to the various tasks managed by the scheduler unit 3112, wherein the status information may indicate which GPC 3118 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, the scheduler unit 3112 manages multiple tasks executed on one or more GPCs 3118.

[0267] In at least one embodiment, scheduler unit 3112 is coupled to job allocation unit 3114, which is configured to dispatch tasks for execution on GPC 3118. In at least one embodiment, job allocation unit 3114 tracks multiple scheduled tasks received from scheduler unit 3112 and manages a pool of pending tasks and an active task pool for each GPC 3118. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 3118; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 3118, such that as one of the GPCs 3118 completes its execution, that task is evicted from the active task pool of the GPC 3118, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 3118. In at least one embodiment, if an active task is idle on GPC 3118, for example while waiting for data dependency resolution, the active task is evicted from GPC 3118 and returned to the pool of pending tasks, while another task in the pool of pending tasks is selected and scheduled to be executed on GPC 3118.

[0268] In at least one embodiment, the work allocation unit 3114 communicates with one or more GPCs 3118 via XBar 3120. In at least one embodiment, XBar 3120 is an interconnect network that couples a plurality of units of PPU 3100 to other units of PPU 3100, and can be configured to couple the work allocation unit 3114 to a specific GPC 3118. In at least one embodiment, other units of one or more PPUs 3100 can also be connected to XBar 3120 via hub 3116.

[0269] In at least one embodiment, tasks are managed by scheduler unit 3112 and assigned to one of GPCs 3118 by job allocation unit 3114. GPCs 3118 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 3118, routed to different GPCs 3118 via XBar 3120, or stored in memory 3104. In at least one embodiment, results may be written to memory 3104 via partitioning unit 3122, which implements a memory interface for writing data to or reading data from memory 3104. In at least one embodiment, results may be transferred to another PPU 3100 or CPU via high-speed GPU interconnect 3108. In at least one embodiment, PPU 3100 includes, but is not limited to, U partitioning units 3122, which is equal to the number of separate and distinct memory devices 3104 coupled to PPU 3100.

[0270] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 3100. In one embodiment, multiple computing applications are executed concurrently by the PPU 3100, and the PPU 3100 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 3100, and the driver core outputs the tasks to one or more streams processed by the PPU 3100. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory.

[0271] Figure 32 A GPC 3200 according to at least one embodiment is shown. In at least one embodiment, the GPC 3200 is Figure 31The GPC 3118. In at least one embodiment, each GPC 3200 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3200 includes, but is not limited to, a pipeline manager 3202, a pre-raster operation unit (“PROP”) 3204, a raster engine 3208, a work assignment crossbar switch (“WDX”) 3216, a memory management unit (“MMU”) 3218, one or more data processing clusters (“DPC”) 3206, and any suitable combination of components.

[0272] In at least one embodiment, the operation of GPC 3200 is controlled by pipeline manager 3202. In at least one embodiment, pipeline manager 3202 manages the configuration of one or more DPCs 3206 to handle tasks assigned to GPC 3200. In at least one embodiment, pipeline manager 3202 configures at least one of one or more DPCs 3206 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 3206 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 3214. In at least one embodiment, pipeline manager 3202 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 3200, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 3204 and / or raster engine 3208, while other packets may be routed to DPC 3206 for processing by raw engine 3212 or SM 3214. In at least one embodiment, pipeline manager 3202 configures at least one of DPCs 3206 to implement a neural network model and / or computation pipeline. In at least one embodiment, pipeline manager 3202 configures at least one of DPCs 3206 to execute at least a portion of a CUDA program.

[0273] In at least one embodiment, the PROP unit 3204 is configured to route data generated by the raster engine 3208 and DPC 3206 to the raster operation (“ROP”) unit in the partition unit, for example, in conjunction with the above. Figure 31Memory partitioning unit 2522, etc., are described in more detail. In at least one embodiment, PROP unit 3204 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, raster engine 3208 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 3208 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is transmitted to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and transmitted to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the cropped and culled fragments are passed to a fine raster engine to generate properties of pixel fragments based on a planar equation generated by the setting engine. In at least one embodiment, the output of the raster engine 3208 includes fragments that will be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 3206).

[0274] In at least one embodiment, each DPC 3206 included in the GPC 3200 includes, but is not limited to, an M-pipeline controller (“MPC”) 3210; a primitive engine 3212; one or more SMs 3214; and any suitable combination thereof. In at least one embodiment, the MPC 3210 controls the operation of the DPC 3206, routing packets received from the pipeline manager 3202 to the appropriate units within the DPC 3206. In at least one embodiment, packets associated with vertices are routed to the primitive engine 3212, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SMs 3214.

[0275] In at least one embodiment, the SM 3214 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 3214 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process different datasets based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 3214 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process different datasets based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. The following is in conjunction with... Figure 33 At least one embodiment of SM 3214 is described in more detail.

[0276] In at least one embodiment, the MMU 3218 is integrated with the GPC 3200 and memory partitioning unit (e.g., Figure 31 The MMU 3218 provides an interface between partition units 3122 and provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 3218 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0277] Figure 33 A streaming multiprocessor (“SM”) 3300 according to at least one embodiment is illustrated. In at least one embodiment, the SM 3300 is Figure 32SM 3214. In at least one embodiment, SM 3300 includes, but is not limited to, instruction cache 3302; one or more scheduler units 3304; register file 3308; one or more processing cores (“cores”) 3310; one or more special function units (“SFUs”) 3312; one or more load / store units (“LSUs”) 3314; interconnect network 3316; shared memory / Level 1 (“L1”) cache 3318; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 3300. In at least one embodiment, scheduler unit 3304 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks allocated to SM 3300. In at least one embodiment, scheduler unit 3304 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 3304 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 3310, SFU 3312, and LSU 3314) in each clock cycle.

[0278] In at least one embodiment, a "cooperative group" can refer to a programming model used to organize groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, the cooperative startup API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads in a thread block (e.g., the `syncthreads()` function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, the sub-block granularity is as small as that of a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0279] In at least one embodiment, dispatch unit 3306 is configured to send instructions to one or more functional units, and scheduler unit 3304 includes, but is not limited to, two dispatch units 3306 that enable two different instructions from the same thread bundle to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 3304 includes a single dispatch unit 3306 or additional dispatch units 3306.

[0280] In at least one embodiment, each SM 3300 includes, but is not limited to, a register file 3308 that provides a set of registers for functional units of the SM 3300. In at least one embodiment, the register file 3308 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 3308 for each functional unit. In at least one embodiment, the register file 3308 is partitioned between different thread bundles executed by the SM 3300, and the register file 3308 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 3300 includes, but is not limited to, a plurality of L processing cores 3310. In at least one embodiment, the SM 3300 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3310. In at least one embodiment, each processing core 3310 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3310 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0281] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 3310. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0282] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller components. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to efficiently utilize the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 matrix spanning all 32 thread bundle threads.

[0283] In at least one embodiment, each SM 3300 includes, but is not limited to, M SFUs 3312 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFUs 3312 include, but are not limited to, tree traversal units configured to traverse hierarchical tree data structures. In at least one embodiment, the SFUs 3312 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., a 2D array of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by a shader program executed by the SM 3300. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 3318. In at least one embodiment, the texture unit uses mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 3300 includes, but is not limited to, two texture units.

[0284] In at least one embodiment, each SM 3300 includes, but is not limited to, N LSUs 3314 that implement load and store operations between the shared memory / L1 cache 3318 and the register file 3308. In at least one embodiment, each SM 3300 includes, but is not limited to, an interconnect network 3316 that connects each functional unit to the register file 3308, and the LSUs 3314 that connect the register file 3308 and the shared memory / L1 cache 3318. In at least one embodiment, the interconnect network 3316 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3308 and to connect the LSUs 3314 to memory locations in the register file 3308 and the shared memory / L1 cache 3318.

[0285] In at least one embodiment, the shared memory / L1 cache 3318 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 3300 and the primitive engine, as well as between threads within the SM 3300. In at least one embodiment, the shared memory / L1 cache 3318 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 3300 to the partition unit. In at least one embodiment, the shared memory / L1 cache 3318 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 3318, the L2 cache, and the memory are backup storage.

[0286] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache; for example, if shared memory is configured to use half its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 3318 enables the shared memory / L1 cache 3318 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a simpler programming model is created by bypassing fixed-function GPUs. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces a unique result, using an SM 3300 to execute the program and perform computations, using a shared memory / L1 cache 3318 for communication between threads, and using an LSU 3314 to read and write global memory via the shared memory / L1 cache 3318 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM 3300 writes commands to the scheduler unit 3304 that can be used to start new work on the DPC.

[0287] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, RISC CPU, MMU, digital-to-analog converter (“DAC”), etc.).

[0288] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU (“iGPU”) included in the motherboard's chipset.

[0289] Software architecture for general-purpose computing

[0290] The following figure illustrates, but is not limited to, exemplary software constructs for implementing at least one embodiment. In at least one embodiment, one or more software constructs of the following figure can implement, regarding... Figure 1-14 One or more aspects of one or more of the embodiments described, and / or about Figure 8-11 Describes one or more technologies.

[0291] Figure 34 A software stack of a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform is a platform for accelerating computational tasks by utilizing hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler instructions, and / or extensions to programming languages. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Computing Platform (“ROCm”), OpenCL (OpenCL developed by Khronosgroup). TM ), SYCL or Intel One API.

[0292] In at least one embodiment, the software stack 3400 of the programming platform provides an execution environment for the application 3401. In at least one embodiment, the application 3401 may include any computer software capable of being launched on the software stack 3400. In at least one embodiment, the application 3401 may include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”) or data center workloads.

[0293] In at least one embodiment, application 3401 and software stack 3400 run on hardware 3407. In at least one embodiment, hardware 3407 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices supporting a programming platform. In at least one embodiment, such as using CUDA, software stack 3400 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, such as using OpenCL, software stack 3400 may be used with devices from different vendors. In at least one embodiment, hardware 3407 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computational tasks. In at least one embodiment, compared to the host within hardware 3407, which may include, but is not limited to, a CPU (but may also include computing devices) and its memory, devices within hardware 3407 may include, but are not limited to, GPUs, FPGAs, AI engines, or other computing devices (but may also include CPUs) and their memory.

[0294] In at least one embodiment, the software stack 3400 of the programming platform includes, but is not limited to, multiple libraries 3403, a runtime 3405, and a device kernel driver 3406. In at least one embodiment, each library 3403 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, library 3403 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, library 3403 includes functions optimized for execution on one or more types of devices. In at least one embodiment, library 3403 may include, but is not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the device. In at least one embodiment, library 3403 is associated with a corresponding API 3402, which may include one or more APIs that expose functions implemented in library 3403.

[0295] In at least one embodiment, application 3401 is written as source code, which is compiled into executable code, as discussed in more detail below with reference to Figures 49-41. In at least one embodiment, the executable code of application 3401 can run at least partially on an execution environment provided by software stack 3400. In at least one embodiment, during the execution of application 3401, code that needs to run on the device (compared to the host) can be obtained. In this case, in at least one embodiment, runtime 3405 can be invoked to load and start the necessary code on the device. In at least one embodiment, runtime 3405 can include any technically feasible runtime system capable of supporting the execution of application 3401.

[0296] In at least one embodiment, runtime 3405 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 3404). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, dealing with, and copying device memory, as well as functions for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function that can be called from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0297] In at least one embodiment, the runtime library and the corresponding API 3404 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functions for fine-grained control of the device, while another (or any number of) APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs.

[0298] In at least one embodiment, device kernel driver 3406 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 3406 may provide APIs such as API 3404 and / or low-level functions upon which other software depends. In at least one embodiment, device kernel driver 3406 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 3406 may compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code (cached compiled binary code) for a specific target device (sometimes referred to as “final” code) at runtime. In at least one embodiment, doing so allows the final code to run on the target device, which may not exist when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, device source code may be compiled into binary code offline, without requiring device kernel driver 3406 to compile IR code at runtime.

[0299] Figure 35 The illustration shows an embodiment according to at least one of the embodiments. Figure 34 The software stack 3400 is a CUDA implementation. In at least one embodiment, the CUDA software stack 3500 on which an application 3501 can be launched includes a CUDA library 3503, a CUDA runtime 3505, a CUDA driver 3507, and a device kernel driver 3508. In at least one embodiment, the CUDA software stack 3500 executes on hardware 3509, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0300] In at least one embodiment, application 3501, CUDA runtime 3505, and device kernel driver 3508 can respectively perform functions similar to those of application 3401, runtime 3405, and device kernel driver 3406, in combination with the above. Figure 34The CUDA driver 3507 is described in at least one embodiment. In at least one embodiment, the CUDA driver API 3507 includes a library (libcuda.so) implementing the CUDA driver API 3506. In at least one embodiment, similar to the CUDA runtime API 3504 implemented by the CUDA runtime library (cudart), the CUDA driver API 3506 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3506 differs from the CUDA runtime API 3504 in that the CUDA runtime API 3504 simplifies device code management by providing implicit initialization, context (similar to processes) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3504, in at least one embodiment, the CUDA driver API 3506 is a low-level API that provides finer-grained control over the device, particularly regarding context and module loading. In at least one embodiment, the CUDA driver API 3506 may expose functions for context management that are not exposed by the CUDA runtime API 3504. In at least one embodiment, the CUDA driver API 3506 is also language-independent and supports, in addition to the CUDA runtime API 3504, OpenCL, for example. Furthermore, in at least one embodiment, development libraries, including the CUDA runtime 3505, can be considered separate from the driver components, including the user-mode CUDA driver 3507 and the kernel-mode device driver 3508 (sometimes also referred to as the "display" driver).

[0301] In at least one embodiment, CUDA library 3503 may include, but is not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (e.g., application 3501) may utilize. In at least one embodiment, CUDA library 3503 may include mathematical libraries, such as the cuBLAS library, which is an implementation of basic linear algebra subroutines (“BLAS”) for performing linear algebra operations; the cuFFT library for computing the Fast Fourier Transform (“FFT”); and the cuRAND library for generating random numbers, etc. In at least one embodiment, CUDA library 3503 may include deep learning libraries, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0302] Figure 36 The illustration shows an embodiment according to at least one of the embodiments. Figure 34The software stack 3400 is a ROCm implementation. In at least one embodiment, the ROCm software stack 3600 on which the application 3601 can be launched includes a language runtime 3603, a system runtime 3605, a thunk 3607, a ROCm kernel driver 3608, and a device kernel driver. In at least one embodiment, the ROCm software stack 3600 executes on hardware 3609, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0303] In at least one embodiment, application 3601 can perform the above-described combination. Figure 34 The discussed application 3401 has similar functionality. Additionally, in at least one embodiment, the language runtime 3603 and system runtime 3605 can perform functions combined with the above. Figure 34 The runtime 3405 discussed has similar functionality. In at least one embodiment, the language runtime 3603 and the system runtime 3605 differ in that the system runtime 3605 is a language-independent runtime that implements the ROCr System Runtime API 3604 and utilizes the Heterogeneous System Architecture (“HSA”) runtime API. In at least one embodiment, the HSA runtime API is a thin-user mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, kernel execution control dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown, etc. In at least one embodiment, compared to the system runtime 3605, the language runtime 3603 is an implementation of a language-specific runtime API 3602 layered on top of the ROCr System Runtime API 3604. In at least one embodiment, the language runtime API may include, but is not limited to, the Portable Heterogeneous Computing Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. In particular, the HIP language is an extension of the C++ programming language, a functionally similar version with CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes elements combined with the above. Figure 35 The discussion focuses on functions similar to CUDA runtime API 3504, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0304] In at least one embodiment, the thunk (ROCt) 3607 is an interface that can be used to interact with the underlying ROCm driver 3608. In at least one embodiment, the ROCm driver 3608 is a ROCk driver, which is a combination of an AMD GPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMD GPU driver is a device kernel driver for GPUs developed by AMD, which performs the above-described combination. Figure 34 The device kernel driver 3406 discussed has similar functionality. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more efficiently via hardware features.

[0305] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3600 above the language runtime 3603, and provide integration with the above. Figure 35 The discussed CUDA library 3503 has similar functionality. In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and / or other libraries, such as the hipBLAS library which implements functions similar to CUDA cuBLAS, the rocFFT library which is similar to CUDA cuFFT for computing FFT, etc.

[0306] Figure 37 The illustration shows an embodiment according to at least one of the embodiments. Figure 34 The software stack 3400 is an OpenCL implementation. In at least one embodiment, the OpenCL software stack 3700 on which the application 3701 can be launched includes an OpenCL framework 3705, an OpenCL runtime 3706, and a driver 3707. In at least one embodiment, the OpenCL software stack 3700 executes on hardware 3509 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required for interoperability with hardware from such vendors.

[0307] In at least one embodiment, the application 3701, the OpenCL runtime 3706, the device kernel driver 3707, and the hardware 3708 can respectively execute the combination described above. Figure 34 The application 3401, runtime 3405, device kernel driver 3406, and hardware 3407 discussed have similar functionality. In at least one embodiment, application 3701 also includes an OpenCL kernel 3702 with code that will execute on the device.

[0308] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to that host. In at least one embodiment, the OpenCL framework provides a platform-level API and a runtime API, shown as Platform API 3703 and Runtime API 3705. In at least one embodiment, Runtime API 3705 uses a context to manage the execution of the kernel on the device. In at least one embodiment, each identified device can be associated with a respective context, which Runtime API 3705 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, etc. In at least one embodiment, Platform API 3703 discloses functions that allow the device context to select and initialize devices, submit work to devices via command queues, and enable data transfers to and from devices, etc. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0309] In at least one embodiment, compiler 3704 is also included in the OpenCL framework 3710. In at least one embodiment, the source code can be compiled offline before executing the application or online during application execution. Unlike CUDA and ROCm, the OpenCL application in at least one embodiment can be compiled online by compiler 3704, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, the OpenCL application can be compiled offline before executing such an application.

[0310] Figure 38 Software supported by a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform 3804 is configured to support various programming models 3803, middleware and / or libraries 3802, and frameworks 3801 that an application 3800 may depend on. In at least one embodiment, the application 3800 may be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may depend on libraries such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0311] In at least one embodiment, the programming platform 3804 can be a combination of the above-described components. Figure 35 , Figure 36 and Figure 37 One of the described CUDA, ROCm, or OpenCL platforms. In at least one embodiment, the programming platform 3804 supports multiple programming models 3803, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 3803 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3803 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerator (“OpenACC”), and / or Vulcan Compute.

[0312] In at least one embodiment, the library and / or middleware 3802 provides an abstract implementation of the programming model 3804. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those available from the programming platform 3804, such middleware also includes software that provides services to applications. In at least one embodiment, the library and / or middleware 3802 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the library and / or middleware 3802 may include NCCL and ROCm communication collection library (“RCCL”) libraries, which provide communication routines for GPUs, the MIOpen library for deep learning acceleration, and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0313] In at least one embodiment, the application framework 3801 depends on libraries and / or middleware 3802. In at least one embodiment, each application framework 3801 is a software framework for implementing a standard structure of application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0314] Figure 39 Compilation code according to at least one embodiment is shown to be used in Figure 34-37The application is executed on one of the programming platforms. In at least one embodiment, compiler 3901 receives source code 3900, which includes both host code and device code. In at least one embodiment, compiler 3901 is configured to convert source code 3900 into host executable code 3902 for execution on a host and device executable code 3903 for execution on a device. In at least one embodiment, source code 3900 may be compiled offline before executing the application or compiled online during application execution.

[0315] In at least one embodiment, source code 3900 may include code in any programming language supported by compiler 3901, such as C++, C, Fortran, etc. In at least one embodiment, source code 3900 may be included in a single-source file, which has a mixture of host code and device code, and indicates the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3900 may include multiple source code files instead of a single-source file, in which the host code and device code are separate.

[0316] In at least one embodiment, compiler 3901 is configured to compile source code 3900 into host executable code 3902 for execution on a host and device executable code 3903 for execution on a device. In at least one embodiment, compiler 3901 performs operations including resolving source code 3900 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3900 comprises a single source file, compiler 3901 may separate device code and host code within such a single source file, compile the device code and host code into device executable code 3903 and host executable code 3902 respectively, and link device executable code 3903 and host executable code 3902 together in a single file, as described below. Figure 40 To be discussed in more detail.

[0317] In at least one embodiment, the host executable code 3902 and the device executable code 3903 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, the host executable code 3902 may include native object code, while the device executable code 3903 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host executable code 3902 and the device executable code 3903 can include target binary code.

[0318] Figure 40 It is compiled code according to at least one embodiment to be used in Figure 34-37 A more detailed illustration is provided on one of the programming platforms. In at least one embodiment, compiler 4001 is configured to receive source code 4000, compile source code 4000, and output executable file 4010. In at least one embodiment, source code 4000 is a single-source file, such as a .cu file, a .hip.cpp file, or a file of other format, which includes both host code and device code. In at least one embodiment, compiler 4001 may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or an HCC compiler for compiling HIP code in .hip.cpp files.

[0319] In at least one embodiment, compiler 4001 includes compiler front-end 4002, host compiler 4005, device compiler 4006, and linker 4009. In at least one embodiment, compiler front-end 4002 is configured to separate device code 4004 from host code 4003 in source code 4000. In at least one embodiment, device code 4004 is compiled by device compiler 4006 into device executable code 4008, which, as described, may include binary code or IR code. In at least one embodiment, host code 4003 is compiled separately by host compiler 4005 into host executable code 4007. In at least one embodiment, for NVCC, host compiler 4005 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 4006 may be, but is not limited to, a low-level virtual machine (“LLVM”) based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 4005 and the device compiler 4006 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0320] In at least one embodiment, after compiling source code 4000 into host executable code 4007 and device executable code 4008, linker 4009 links the host and device executable codes 4007 and 4008 together in executable file 4010. In at least one embodiment, the native object code of the host and PTX or the binary code of the device can be linked together in an executable and linkable format (“ELF”) file, which is a container format for storing object code.

[0321] Figure 41The illustration shows the transformation of source code prior to compilation, according to at least one embodiment. In at least one embodiment, source code 4100 is passed via a transformation tool 4101, which transforms source code 4100 into transformed source code 4102. In at least one embodiment, a compiler 4103 is used to compile the transformed source code 4102 into host executable code 4104 and device executable code 3405, a process similar to that of compiler 3901 compiling source code 3900 into host executable code 3902 and device executable code 3903, as described above. Figure 39 The subject of discussion.

[0322] In at least one embodiment, the transformation performed by the transformation tool 4101 is used to port source code 4100 to perform in an environment different from where it was originally intended to run. In at least one embodiment, the transformation tool 4101 may include, but is not limited to, a HIP converter for “hipify” CUDA code for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the transformation of source code 4100 may include: parsing source code 4100 and converting calls to APIs provided by one programming model (e.g., CUDA) into corresponding calls to APIs provided by another programming model (e.g., HIP), as combined below. Figure 42A-43 This will be discussed in more detail. Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be translated into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by the translation tool 4101 may sometimes be incomplete, requiring additional manual intervention to fully port the source code 4100.

[0323] Configure GPUs for general-purpose computing

[0324] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computational source code according to at least one embodiment. In at least one embodiment, one or more architectures in the figures below can implement, regarding... Figure 1-14 One or more aspects of one or more of the embodiments described, and / or about Figure 8-11 Describing one or more technologies.

[0325] Figure 42AA system 4200 is shown, configured to compile and execute CUDA source code 4210 using different types of processing units according to at least one embodiment. In at least one embodiment, system 4200 includes, but is not limited to, CUDA source code 4210, CUDA compiler 4250, host executable code 4270(1), host executable code 4270(2), CUDA device executable code 4284, CPU 4290, CUDA-enabled GPU 4294, GPU 4292, CUDA to HIP conversion tool 4220, HIP source code 4230, HIP compiler driver 4240, HCC 4260, and HCC device executable code 4282.

[0326] In at least one embodiment, CUDA source code 4210 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, including but not limited to defining device code and mechanisms for distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 4290, GPU 4292, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host machine after compilation. In at least one embodiment, the host machine is a processor optimized for sequential instruction processing, such as CPU 4290.

[0327] In at least one embodiment, the CUDA source code 4210 includes, but is not limited to, any number (including zero) of global functions 4212, any number (including zero) of device functions 4214, any number (including zero) of host functions 4216, and any number (including zero) of host / device functions 4218. In at least one embodiment, the global functions 4212, device functions 4214, host functions 4216, and host / device functions 4218 can be mixed in the CUDA source code 4210. In at least one embodiment, each global function 4212 is executable on a device and is callable from a host. Therefore, in at least one embodiment, one or more of the global functions 4212 can serve as entry points for a device. In at least one embodiment, each global function 4212 is a kernel. In at least one embodiment, and in a technique called dynamic parallelism, one or more global functions 4212 define a kernel that is executable on a device and is callable from such a device. In at least one embodiment, the kernel is executed in parallel N times (where N is any positive integer) by N different threads on the device during execution.

[0328] In at least one embodiment, each device function 4214 executes on a device and can only be called from such a device. In at least one embodiment, each host function 4216 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 4216 defines both a host version of a function that is executable on a host and can only be called from such a host, and a device version of a function that is executable on a device and can only be called from such a device.

[0329] In at least one embodiment, CUDA source code 4210 may also include, but is not limited to, any number of calls to any number of functions defined by CUDA runtime API 4202. In at least one embodiment, CUDA runtime API 4202 may include, but is not limited to, any number of functions executed on the host for allocating and dealing device memory, transferring data between host memory and device memory, managing a system with multiple devices, etc. In at least one embodiment, CUDA source code 4210 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed to be used by CUDA code. In at least one embodiment, a CUDA API includes, but is not limited to, CUDA runtime API 4202, CUDA driver APIs, APIs for any number of CUDA libraries, etc. In at least one embodiment, and relative to CUDA runtime API 4202, the CUDA driver API is a lower-level API but can provide finer-grained control over devices. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cURAND, cuDNN, etc.

[0330] In at least one embodiment, CUDA compiler 4250 compiles input CUDA code (e.g., CUDA source code 4210) to generate host executable code 4270(1) and CUDA device executable code 4284. In at least one embodiment, CUDA compiler 4250 is an NVCC. In at least one embodiment, host executable code 4270(1) is a compiled version of host code included in input source code executable on CPU 4290. In at least one embodiment, CPU 4290 can be any processor optimized for sequential instruction processing.

[0331] In at least one embodiment, CUDA device executable code 4284 is a compiled version of device code included in input source code executable on a CUDA-enabled GPU 4294. In at least one embodiment, CUDA device executable code 4284 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 4284 includes, but is not limited to, IR code, such as PTX code, which is further compiled at runtime by a device driver into binary code for a specific target device (e.g., the CUDA-enabled GPU 4294). In at least one embodiment, the CUDA-enabled GPU 4294 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 4294 was developed by NVIDIA Corporation of Santa Clara, California.

[0332] In at least one embodiment, the CUDA-to-HIP conversion tool 4220 is configured to convert CUDA source code 4210 into functionally similar HIP source code 4230. In at least one embodiment, the HIP source code 4230 is a collection of human-readable code in a HIP programming language. In at least one embodiment, the HIP code is human-readable code in a HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language, including but not limited to a functionally similar version of the CUDA mechanism, used to define device code and distinguish between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism for defining global functions 4212; however, such a HIP programming language may lack support for dynamic parallelism, therefore, the global function 4212 defined in the HIP code can only be called from the host.

[0333] In at least one embodiment, the HIP source code 4230 includes, but is not limited to, any number (including zero) of global functions 4212, any number (including zero) of device functions 4214, any number (including zero) of host functions 4216, and any number (including zero) of host / device functions 4218. In at least one embodiment, the HIP source code 4230 may also include any number of calls to any number of functions specified in the HIP runtime API 4232. In one embodiment, the HIP runtime API 4232 includes, but is not limited to, functionally similar versions of a subset of functions included in the CUDA runtime API 4202. In at least one embodiment, the HIP source code 4230 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP API includes, but is not limited to, the HIP runtime API 4232, the HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

[0334] In at least one embodiment, the CUDA-to-HIP conversion tool 4220 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA-to-HIP conversion tool 4220 converts any number of calls to functions specified in the CUDA runtime API 4202 into any number of calls to functions specified in the HIP runtime API 4232.

[0335] In at least one embodiment, the CUDA to HIP conversion tool 4220 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 4220 is a tool called hipify-clang, which, compared to hipify-perl, performs a more complex and robust conversion process involving parsing the CUDA code using clang (a compiler front-end) and then converting the resulting symbols. In at least one embodiment, in addition to the modifications performed by the CUDA to HIP conversion tool 4220, correctly converting the CUDA code into HIP code may require further modifications (e.g., manual editing).

[0336] In at least one embodiment, the HIP compiler driver 4240 is a front-end that determines a target device 4246 and then configures a compiler compatible with the target device 4246 to compile the HIP source code 4230. In at least one embodiment, the target device 4246 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 4240 can determine the target device 4246 in any technically feasible manner.

[0337] In at least one embodiment, if the target device 4246 is CUDA compatible (e.g., a CUDA-enabled GPU 4294), the HIP compiler driver 4240 generates HIP / NVCC compilation commands 4242. In at least one embodiment and in conjunction with... Figure 42B In more detail, the HIP / NVCC compilation command 4242 configures the CUDA compiler 4250 to compile the HIP source code 4230 using, but not limited to, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compilation command 4242, the CUDA compiler 4250 generates host executable code 4270(1) and CUDA device executable code 4284.

[0338] In at least one embodiment, if the target device 4246 is incompatible with CUDA, the HIP compiler driver 4240 generates HIP / HCC compilation commands 4244. In at least one embodiment and as in conjunction with... Figure 42C In more detail, HIP / HCC compilation command 4244 configures HCC 4260 to compile HIP source code 4230 using the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 4244, HCC 4260 generates host executable code 4270(2) and HCC device executable code 4282. In at least one embodiment, HCC device executable code 4282 is a compiled version of device code executable on GPU 4292 contained in HIP source code 4230. In at least one embodiment, GPU 4292 may be any processor optimized for parallel instruction processing, CUDA incompatible, and HCC compatible. In at least one embodiment, GPU 4292 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, GPU 4292 is a CUDA-disabled GPU 4292.

[0339] For illustrative purposes only, Figure 42AThe document describes three different processes that, in at least one embodiment, can be implemented to compile CUDA source code 4210 for execution on CPU 4290 and various devices. In at least one embodiment, a direct CUDA process compiles CUDA source code 4210 for execution on CPU 4290 and a CUDA-enabled GPU 4294 without converting CUDA source code 4210 to HIP source code 4230. In at least one embodiment, an indirect CUDA process converts CUDA source code 4210 to HIP source code 4230 and then compiles the HIP source code 4230 for execution on CPU 4290 and a CUDA-enabled GPU 4294. In at least one embodiment, a CUDA / HCC process converts CUDA source code 4210 to HIP source code 4230 and then compiles the HIP source code 4230 for execution on CPU 4290 and GPU 4292.

[0340] The direct CUDA flow, which can be implemented in at least one embodiment, can be depicted by dashed lines and a series of bubble comments A1-A3. In at least one embodiment, and as indicated by bubble comment A1, CUDA compiler 4250 receives CUDA source code 4210 and CUDA compilation command 4248 that configures CUDA compiler 4250 to compile CUDA source code 4210. In at least one embodiment, the CUDA source code 4210 used in the direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to CUDA compilation command 4248, CUDA compiler 4250 generates host executable code 4270(1) and CUDA device executable code 4284 (indicated by bubble comment A2). In at least one embodiment, and as indicated by bubble comment A3, host executable code 4270(1) and CUDA device executable code 4284 can be executed on CPU 4290 and CUDA-enabled GPU 4294, respectively. In at least one embodiment, the CUDA device executable code 4284 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 4284 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0341] The indirect CUDA process, which can be implemented in at least one embodiment, can be described by dashed lines and a series of bubble comments B1-B6. In at least one embodiment, and as shown in bubble comment B1, CUDA to HIP conversion tool 4220 receives CUDA source code 4210. In at least one embodiment, and as shown in bubble comment B2, CUDA to HIP conversion tool 4220 converts CUDA source code 4210 into HIP source code 4230. In at least one embodiment, and as shown in bubble comment B3, HIP compiler driver 4240 receives HIP source code 4230 and determines whether the target device 4246 has CUDA enabled.

[0342] In at least one embodiment and as shown in bubble note B4, the HIP compiler driver 4240 generates HIP / NVCC compilation commands 4242 and sends both the HIP / NVCC compilation commands 4242 and the HIP source code 4230 to the CUDA compiler 4250. In at least one embodiment and as shown in combination Figure 42B In more detail, the HIP / NVCC compilation command 4242 configures the CUDA compiler 4250 to compile the HIP source code 4230 using, but not limited to, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compilation command 4242, the CUDA compiler 4250 generates host executable code 4270(1) and CUDA device executable code 4284 (indicated by bubble comment B5). In at least one embodiment and as shown by bubble comment B6, the host executable code 4270(1) and the CUDA device executable code 4284 can be executed on a CPU 4290 and a CUDA-enabled GPU 4294, respectively. In at least one embodiment, the CUDA device executable code 4284 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 4284 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0343] The CUDA / HCC process, which can be implemented in at least one embodiment, can be described by solid lines and a series of bubble comments C1-C6. In at least one embodiment, and as shown in bubble comment C1, the CUDA to HIP conversion tool 4220 receives CUDA source code 4210. In at least one embodiment, and as shown in bubble comment C2, the CUDA to HIP conversion tool 4220 converts the CUDA source code 4210 into HIP source code 4230. In at least one embodiment, and as shown in bubble comment C3, the HIP compiler driver 4240 receives the HIP source code 4230 and determines that the target device 4246 does not have CUDA enabled.

[0344] In at least one embodiment, the HIP compiler driver 4240 generates HIP / HCC compilation commands 4244 and sends both the HIP / HCC compilation commands 4244 and the HIP source code 4230 to the HCC 4260 (indicated by bubble comment C4). In at least one embodiment and as in combination Figure 42C In more detail, HIP / HCC compilation command 4244 configures HCC 4260 to compile HIP source code 4230 using, but not limited to, the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 4244, HCC 4260 generates host executable code 4270(2) and HCC device executable code 4282 (indicated by bubble comment C5). In at least one embodiment and as shown by bubble comment C6, host executable code 4270(2) and HCC device executable code 4282 can be executed on CPU 4290 and GPU 4292, respectively.

[0345] In at least one embodiment, after converting CUDA source code 4210 to HIP source code 4230, the HIP compiler driver 4240 can then be used to generate executable code for a CUDA-enabled GPU 4294 or GPU 4292 without re-executing CUDA to the HIP conversion tool 4220. In at least one embodiment, the CUDA to HIP conversion tool 4220 converts CUDA source code 4210 to HIP source code 4230 and then stores it in memory. In at least one embodiment, the HIP compiler driver 4240 then configures HCC 4260 to generate host executable code 4270(2) and HCC device executable code 4282 based on the HIP source code 4230. In at least one embodiment, the HIP compiler driver 4240 then configures CUDA compiler 4250 to generate host executable code 4270(1) and CUDA device executable code 4284 based on the stored HIP source code 4230.

[0346] Figure 42B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU 4290 and a CUDA-enabled GPU 4294. Figure 42A The system 4204 includes, but is not limited to, CUDA source code 4210, CUDA to HIP conversion tool 4220, HIP source code 4230, HIP compiler driver 4240, CUDA compiler 4250, host executable code 4270(1), CUDA device executable code 4284, CPU 4290, and CUDA-enabled GPU 4294.

[0347] In at least one embodiment and as previously mentioned herein Figure 42A As described, the CUDA source code 4210 includes, but is not limited to, any number (including zero) of global functions 4212, any number (including zero) of device functions 4214, any number (including zero) of host functions 4216, and any number (including zero) of host / device functions 4218. In at least one embodiment, the CUDA source code 4210 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0348] In at least one embodiment, the CUDA to HIP conversion tool 4220 converts CUDA source code 4210 into HIP source code 4230. In at least one embodiment, the CUDA to HIP conversion tool 4220 converts each kernel call in the CUDA source code 4210 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 4210 into any number of other functionally similar HIP calls.

[0349] In at least one embodiment, the HIP compiler driver 4240 determines that the target device 4246 is CUDA enabled and generates a HIP / NVCC compilation command 4242. In at least one embodiment, the HIP compiler driver 4240 then configures the CUDA compiler 4250 via the HIP / NVCC compilation command 4242 to compile the HIP source code 4230. In at least one embodiment, as part of configuring the CUDA compiler 4250, the HIP compiler driver 4240 provides access to a HIP-to-CUDA translation header 4252. In at least one embodiment, the HIP-to-CUDA translation header 4252 translates an arbitrary number of mechanisms (e.g., functions) specified in an arbitrary number of HIP APIs into an arbitrary number of mechanisms specified in an arbitrary number of CUDA APIs. In at least one embodiment, the CUDA compiler 4250 uses the HIP-to-CUDA translation header 4252 in conjunction with a CUDA runtime library 4254 corresponding to the CUDA runtime API 4202 to generate host executable code 4270(1) and CUDA device executable code 4284. In at least one embodiment, host executable code 4270(1) and CUDA device executable code 4284 can then be executed on CPU 4290 and CUDA-enabled GPU 4294, respectively. In at least one embodiment, CUDA device executable code 4284 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 4284 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0350] Figure 42C A system 4206 according to at least one embodiment is shown, the system 4206 being configured to compile and execute using a CPU 4290 and a GPU 4292 with CUDA disabled. Figure 42A The CUDA source code 4210. In at least one embodiment, the system 4206 includes, but is not limited to, the CUDA source code 4210, the CUDA to HIP conversion tool 4220, the HIP source code 4230, the HIP compiler driver 4240, the HCC 4260, the host executable code 4270(2), the HCC device executable code 4282, the CPU 4290, and the GPU 4292.

[0351] In at least one embodiment, and as previously mentioned herein Figure 42AAs described, the CUDA source code 4210 includes, but is not limited to, any number (including zero) of global functions 4212, any number (including zero) of device functions 4214, any number (including zero) of host functions 4216, and any number (including zero) of host / device functions 4218. In at least one embodiment, the CUDA source code 4210 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0352] In at least one embodiment, the CUDA to HIP conversion tool 4220 converts CUDA source code 4210 into HIP source code 4230. In at least one embodiment, the CUDA to HIP conversion tool 4220 converts each kernel call in the CUDA source code 4210 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 4210 into any number of other functionally similar HIP calls.

[0353] In at least one embodiment, the HIP compiler driver 4240 then determines that the target device 4246 is not CUDA enabled and generates a HIP / HCC compilation command 4244. In at least one embodiment, the HIP compiler driver 4240 then configures the HCC 4260 to execute the HIP / HCC compilation command 4244, thereby compiling the HIP source code 4230. In at least one embodiment, the HIP / HCC compilation command 4244 configures the HCC 4260 to use, but not limited to, the HIP / HCC runtime library 4258 and the HCC header 4256 to generate host executable code 4270(2) and HCC device executable code 4282. In at least one embodiment, the HIP / HCC runtime library 4258 corresponds to the HIP runtime API 4232. In at least one embodiment, the HCC header 4256 includes, but is not limited to, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code 4270(2) and HCC device executable code 4282 can be executed on CPU 4290 and GPU 4292, respectively.

[0354] Figure 43 The diagram illustrates a method according to at least one embodiment. Figure 42CAn exemplary kernel is converted by the CUDA to HIP conversion tool 4220. In at least one embodiment, the CUDA source code 4210 divides the overall problem that a given kernel is designed to solve into relatively coarse subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads. In at least one embodiment, each subproblem is divided into relatively small pieces that can be solved in parallel by the threads within the thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by coordinating memory accesses through synchronized execution.

[0355] In at least one embodiment, CUDA source code 4210 organizes thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0356] In at least one embodiment, the kernel is a function in the device code defined using the "__global__" declaration specifier. In at least one embodiment, CUDA kernel startup syntax 4310 is used to specify the size of the mesh for executing the kernel for a given kernel call and the associated flow. In at least one embodiment, CUDA kernel startup syntax 4310 is specified as "KernelName <<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<<...>>>" construct, which is inserted between the kernel name ("KernelName") and the bracketed list of kernel parameters ("KernelArguments"). In at least one embodiment, the CUDA kernel boot syntax 4310 includes, but is not limited to, the CUDA boot function syntax instead of the execution configuration syntax.

[0357] In at least one embodiment, "GridSize" is of type dim3 and specifies the size and dimensions of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure, which includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the size and dimensions of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel has a unique thread ID, which can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0358] In at least one embodiment, regarding CUDA kernel startup syntax 4310, "SharedMemorySize" is an optional parameter that specifies the number of bytes dynamically allocated for each thread block in shared memory for a given kernel call, excluding statically allocated memory. In at least one embodiment and regarding CUDA kernel startup syntax 4310, SharedMemorySize defaults to zero. In at least one embodiment and regarding CUDA kernel startup syntax 4310, "stream" is an optional parameter that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands executed sequentially (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or simultaneously relative to each other.

[0359] In at least one embodiment, CUDA source code 4210 includes, but is not limited to, kernel definitions and a main function for the exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on the host and includes, but is not limited to, kernel calls that cause the kernel MatAdd to execute on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);”. In at least one embodiment, and in accordance with CUDA kernel startup syntax 4310, a grid of thread blocks of size N / 16 × N / 16 is used to execute the kernel MatAdd, where each thread block is 16 × 16. In at least one embodiment, each thread block comprises 256 threads, creating a grid with enough blocks to have one thread per matrix element, and each thread in the grid executes the kernel MatAdd to perform a pairwise addition.

[0360] In at least one embodiment, while converting CUDA source code 4210 into HIP source code 4230, the CUDA-to-HIP conversion tool 4220 converts each kernel call in the CUDA source code 4210 from CUDA kernel startup syntax 4310 into HIP kernel startup syntax 4320, and converts any number of other CUDA calls in the source code 4210 into any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel startup syntax 4320 is specified as “hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel startup syntax 4320 as it does in the CUDA kernel startup syntax 4310 (as previously described herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in HIP kernel startup syntax 4320, but optional in CUDA kernel startup syntax 4310.

[0361] In at least one embodiment, in addition to the kernel call that causes the kernel MatAdd to execute on the device, Figure 43 The part of HIP source code 4230 described in the text is related to Figure 43 The portion of the CUDA source code 4210 depicted is identical. In at least one embodiment, the kernel MatAdd is defined in the HIP source code 4230, having the same "__global__" declaration specifier as the kernel MatAdd defined in the CUDA source code 4210. In at least one embodiment, the kernel call in the HIP source code 4230 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in the CUDA source code 4210 is "MatAdd <<<numBlocks,threadsPerBlock> >>(A, B, C);”.

[0362] Figure 44 A more detailed description is provided according to at least one embodiment. Figure 42C The GPU 4292 is a CUDA-unenabled GPU. In at least one embodiment, the GPU 4292 was developed by AMD Inc. of Santa Clara City. In at least one embodiment, the GPU 4292 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 4292 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, the GPU 4292 is configured to perform graphics-independent operations. In at least one embodiment, the GPU 4292 is configured to perform both graphics-related and graphics-independent operations. In at least one embodiment, the GPU 4292 can be configured to execute device code included in HIP source code 4230.

[0363] In at least one embodiment, the GPU 4292 includes, but is not limited to, any number of programmable processing units 4420, an command processor 4410, an L2 cache 4422, a memory controller 4470, a DMA engine 4480(1), a system memory controller 4482, a DMA engine 4480(2), and a GPU controller 4484. In at least one embodiment, each programmable processing unit 4420 includes, but is not limited to, a workload manager 4430 and any number of compute units 4440. In at least one embodiment, the command processor 4410 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 4430. In at least one embodiment, for each programmable processing unit 4420, the associated workload manager 4430 distributes work to the compute units 4440 included in the programmable processing unit 4420. In at least one embodiment, each compute unit 4440 can execute any number of thread blocks, but each thread block executes on a single compute unit 4440. In at least one embodiment, the workgroup is a thread block.

[0364] In at least one embodiment, each computing unit 4440 includes, but is not limited to, any number of SIMD units 4450 and shared memory 4460. In at least one embodiment, each SIMD unit 4450 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 4450 includes, but is not limited to, a vector ALU 4452 and a vector register file 4454. In at least one embodiment, each SIMD unit 4450 executes a different thread bundle. In at least one embodiment, a thread bundle is a group of threads (e.g., 16 threads), where each thread in the thread bundle belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a thread bundle. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread bundle. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 4460.

[0365] In at least one embodiment, the programmable processing unit 4420 is referred to as a "shading engine". In at least one embodiment, in addition to the computing unit 4440, each programmable processing unit 4420 also includes, but is not limited to, any number of dedicated graphics hardware. In at least one embodiment, each programmable processing unit 4420 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 4430, and any number of computing units 4440.

[0366] In at least one embodiment, compute units 4440 share an L2 cache 4422. In at least one embodiment, the L2 cache 4422 is partitioned. In at least one embodiment, all compute units 4440 in GPU 4292 have access to GPU memory 4490. In at least one embodiment, memory controller 4470 and system memory controller 4482 facilitate data transfer between GPU 4292 and the host, and DMA engine 4480(1) enables asynchronous memory transfers between GPU 4292 and the host. In at least one embodiment, memory controller 4470 and GPU controller 4484 facilitate data transfers between GPU 4292 and other GPUs 4292, and DMA engine 4480(2) enables asynchronous memory transfers between GPU 4292 and other GPUs 4292.

[0367] In at least one embodiment, GPU 4292 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components, either internal or external to GPU 4292. In at least one embodiment, GPU 4292 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 4292 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 4292 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 4470 and system memory controller 4482) and memory devices dedicated to a component or shared among multiple components (e.g., shared memory 4460). In at least one embodiment, GPU4292 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 4422), each cache memory being either private or shared among any number of components (e.g., SIMD unit 4450, compute unit 4440, and programmable processing unit 4420).

[0368] Figure 45 This illustrates how threads of an exemplary CUDA grid 4520, according to at least one embodiment, are mapped to... Figure 44Different computational units 4440. In at least one embodiment, and for illustrative purposes only, grid 4520 has a GridSize of BX multiplied by BY multiplied by 1 and a BlockSize of TX multiplied by TY multiplied by 1. Therefore, in at least one embodiment, grid 4520 includes, but is not limited to, (BX*BY) thread blocks 4530, each thread block 4530 including, but not limited to, (TX*TY) threads 4540. Threads 4540 in Figure 45 It is depicted as a curved arrow.

[0369] In at least one embodiment, grid 4520 is mapped to programmable processing unit 4420(1), which includes, but is not limited to, computing units 4440(1)-4440(C). In at least one embodiment, and as shown, (BJ*BY) thread block 4530 is mapped to computing unit 4440(1), and the remaining thread blocks 4530 are mapped to computing unit 4440(2). In at least one embodiment, each thread block 4530 may include, but is not limited to, any number of thread bundles, and each thread bundle is mapped to... Figure 44 Different SIMD units 4450.

[0370] In at least one embodiment, the thread bundles in a given thread block 4530 can be synchronized together and communicate via shared memory 4460 included in the associated computing unit 4440. For example, and in at least one embodiment, the thread bundles in thread block 4530(BJ, 1) can be synchronized together and communicate via shared memory 4460(1). For example, and in at least one embodiment, the thread bundles in thread block 4530(BJ+1, 1) can be synchronized together and communicate via shared memory 4460(2).

[0371] At least one embodiment can be described according to at least one of the following terms:

[0372] 1. A processor, comprising:

[0373] One or more circuits are used to generate a third video frame based at least in part on one of a plurality of possible motions of one or more objects from a first video frame to a second video frame.

[0374] 2. The processor according to Clause 1, wherein the one or more circuits are further configured to determine the plurality of possible motions based at least in part on backward motion vectors associated with pixels of the second video frame.

[0375] 3. The processor according to Clause 1 or 2, wherein one or more objects are pixels.

[0376] 4. The processor according to any one of clauses 1-3, wherein the one or more circuits are configured to further generate the third video frame based at least in part on one or more motions of the camera viewpoint.

[0377] 5. The processor according to any one of clauses 1-4, wherein the one or more circuits are configured to select one of the plurality of possible motions based at least in part on depth information.

[0378] 6. The processor according to any one of clauses 1-5, wherein the one or more circuits are configured to generate one or more additional video frames based at least in part on a backward motion vector associated with a pixel of the second video frame and one or more motions of the camera viewpoint.

[0379] 7. The processor according to any one of clauses 1-6, wherein the one or more circuits are configured to generate a third video frame based at least in part on receiving a first video frame, a second video frame, depth information, and a backward motion vector from one or more buffers.

[0380] 8. A machine-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to at least:

[0381] The third video frame is generated based at least in part on one of a number of possible motions of one or more objects from the first video frame to the second video frame.

[0382] 9. The machine-readable medium according to Clause 8, wherein each of the plurality of possible motions corresponds to a backward motion vector from the second video frame to the first video frame in a set of backward motion vectors associated with the pixel depth value of the second video frame, and if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0383] One of the plurality of possible motions is identified at least in part based on a depth value associated with one of the set of backward motion vectors; and

[0384] The third video frame is generated at least in part based on the identified motion.

[0385] 10. The machine-readable medium according to clause 8 or 9, wherein one or more objects are pixels.

[0386] 11. A machine-readable medium according to any one of clauses 8-10, wherein if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0387] Determine the changes in the camera viewpoint matrix between the first and second video frames; and

[0388] The third video frame is generated at least in part based on changes in the determined camera viewpoint matrix.

[0389] 12. A machine-readable medium according to any one of clauses 8-11, wherein if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0390] Determine the location of a set of occluded pixels in the third video frame;

[0391] Determine the locations of a set of demasked pixels in the third video frame; and

[0392] The third video frame is generated at least in part based on the set of occluded pixel locations and the set of deoccluded pixel locations.

[0393] 13. A machine-readable medium according to any one of clauses 8-12, wherein if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0394] At least in part, a set of estimated forward motion vectors from a first video frame to a second video frame are generated based on a set of backward motion vectors, wherein the set of backward motion vectors is from the second video frame to the first video frame; and

[0395] The third video frame is generated at least in part based on a set of estimated forward motion vectors and a set of backward motion vectors.

[0396] 14. A machine-readable medium according to any one of clauses 8-13, wherein if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0397] At least in part, a set of intermediate forward motion vectors from the third video frame to the second video frame are generated based on a set of estimated forward motion vectors.

[0398] Generate a set of intermediate backward motion vectors from the third video frame to the first video frame; and

[0399] The third video frame is generated at least in part based on the set of intermediate forward motion vectors and the set of intermediate backward motion vectors.

[0400] 15. A machine-readable medium according to any one of clauses 8-14, wherein if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0401] The third video frame is generated at least in part based on receiving a first video frame, a second video frame, depth information, and a backward motion vector from one or more buffers.

[0402] 16. A method comprising:

[0403] The third video frame is generated based at least in part on one of a number of possible motions of one or more objects from the first video frame to the second video frame.

[0404] 17. The method according to Clause 16 further includes determining the plurality of possible motions based at least in part on backward motion vectors associated with pixels of the second video frame, wherein each of the plurality of possible motions corresponds to a backward motion vector pointing to the same pixel location in the first video frame.

[0405] 18. The method according to clause 16 or 17, wherein one or more objects are pixels.

[0406] 19. The method according to any one of clauses 16-18 further includes:

[0407] Determine one or more motions of the camera viewpoint between the first and second video frames; and

[0408] The third video frame is generated based at least in part on one or more motions of the determined camera viewpoint.

[0409] 20. The method according to any one of clauses 16-19, wherein the selection of the one of the plurality of possible motions is based at least in part on depth information of pixels in the second video frame.

[0410] 21. The method according to any one of clauses 16-20, further comprising:

[0411] Generate an occlusion mask;

[0412] Generate occlusion removal mask; and

[0413] The third video frame is generated at least in part based on the occlusion mask and the deocclusion mask.

[0414] 22. The method according to any one of clauses 16-21, wherein the generation of the third video frame is based at least in part on receiving the first video frame, the second video frame, depth information, and the backward motion vector from one or more buffers.

[0415] 23. A system comprising:

[0416] One or more processors are configured to generate a third video frame based at least in part on one of a plurality of possible motions of one or more objects from a first video frame to a second video frame; and

[0417] One or more memories are used to store a third video frame.

[0418] 24. The system according to Clause 23, wherein the one or more processors are further configured to:

[0419] The plurality of possible motions are determined at least in part based on backward motion vectors associated with pixels in the second video frame; and

[0420] One of the multiple possible motions is selected, at least in part, based on depth information.

[0421] 25. The system according to clause 23 or 24, wherein one or more objects are pixels.

[0422] 26. The system according to any one of clauses 23-25, wherein said one or more processors are further configured to:

[0423] Determine the camera viewpoint change between the first and second video frames; and

[0424] The third video frame is generated at least in part based on the determined camera viewpoint changes.

[0425] 27. The system according to any one of clauses 23-26, wherein the one or more processors are further configured to:

[0426] Identify the pixel position of the third video frame, which has a corresponding pixel identified using an intermediate motion vector in only one of the first and second video frames; and sample pixel data only for video frames having the corresponding pixel at the identified pixel position.

[0427] 28. The system according to any one of clauses 23-27, wherein one or more processors are configured to generate a third video frame based at least in part on receiving a first video frame, a second video frame, depth information, and a backward motion vector from one or more buffers.

[0428] 29. A processor, comprising:

[0429] One or more circuits are used for:

[0430] Sample the first set of pixel data from the first video frame;

[0431] At least in part, based on a set of forward motion vectors from the first video frame to the second video frame, a second set of pixel data of the second video frame is sampled; and

[0432] An intermediate video frame between the first video frame and the second video frame is generated, at least in part, based on the first set of pixel data and the second set of pixel data.

[0433] 30. The processor according to Clause 29, wherein the one or more circuits are configured to sample the first set of pixel data based at least in part on a set of backward motion vectors from the second video frame to the first video frame.

[0434] 31. The processor according to clause 29 or 30, wherein the one or more circuits are configured to: identify a pixel of an intermediate video frame having a corresponding pixel identified using motion vectors in only one of a first video frame and a second video frame; and sample pixel data of the video frame having the corresponding pixel only for the identified pixel.

[0435] 32. The processor according to any one of clauses 29-31, wherein the one or more circuits are further configured to generate a set of intermediate forward motion vectors from the intermediate video frame to the second video frame, at least in part based on the set of intermediate forward motion vectors, and wherein the one or more circuits are configured to sample the second set of pixel data, at least in part based on the set of intermediate forward motion vectors.

[0436] 33. The processor according to any one of clauses 29-32, wherein said one or more circuits are further configured to:

[0437] Generate a set of intermediate forward motion vectors from the middle video frame to the second video frame;

[0438] Generate a set of intermediate backward motion vectors from the intermediate video frame to the first video frame; and

[0439] Intermediate video frames are generated at least in part based on the set of intermediate forward motion vectors and the set of intermediate backward motion vectors.

[0440] 34. The processor according to any one of clauses 29-33, wherein said one or more circuits are further configured to:

[0441] A set of intermediate forward motion vectors is generated, at least in part, based on the depth values ​​of pixels in the first video frame; and

[0442] A set of intermediate backward motion vectors is generated, at least in part, based on the depth values ​​of pixels in the second video frame.

[0443] 35. The processor according to any one of clauses 29-34, wherein said one or more circuits are further configured to:

[0444] Generate an occlusion mask;

[0445] Generate occlusion removal mask; and

[0446] Intermediate video frames are generated at least in part based on the occlusion mask and the de-occlusion mask.

[0447] 36. The processor according to any one of clauses 29-35, wherein the one or more circuits are configured to generate intermediate frames based at least in part on receiving a first video frame, a second video frame, depth information, a forward motion vector, and a backward motion vector from one or more buffers.

[0448] 37. The processor according to any one of clauses 29-36, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

[0449] 38. A machine-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to at least:

[0450] Sample the first set of pixel data from the first video frame;

[0451] At least in part, a second set of pixel data for the second video frame is sampled based on a set of forward motion vectors from the first video frame to the second video frame; and

[0452] An intermediate video frame between the first video frame and the second video frame is generated, at least in part based on the first set of pixel data and the second set of pixel data.

[0453] 39. The machine-readable medium according to clause 38, wherein if the instructions are executed by said one or more processors, then said one or more processors further cause the following:

[0454] The first set of pixel data is sampled at least in part based on a set of backward motion vectors from the second video frame to the first video frame.

[0455] 40. The machine-readable medium according to clause 38 or 39, wherein the intermediate video frame is a first intermediate video frame, and if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0456] A second intermediate video frame is generated, at least in part, based on the first set of pixel data and the second set of pixel data between the first video frame and the second video frame.

[0457] 41. A machine-readable medium according to any one of clauses 38-40, wherein if the instructions are executed by the one or more processors, the one or more processors further cause the one or more processors to:

[0458] The intermediate video frame is generated at least in part based on a weighted average of pixel color information of pixels for the intermediate video frame from the first set of pixel data and the second set of pixel data, wherein the pixel has a corresponding pixel in the first video frame identified using the first motion vector and in the second video frame identified using the second motion vector.

[0459] 42. The machine-readable medium according to any one of clauses 38-41, wherein the pixel color information is a first set of RGB values ​​from a first set of pixel data and a second set of RGB values ​​from a second set of pixel data.

[0460] 43. A machine-readable medium according to any one of clauses 38-42, wherein if the instructions are executed by said one or more processors, then said one or more processors further cause said one or more processors to:

[0461] Identify a set of occluded pixels;

[0462] Determine a set of de-occluded pixels; and

[0463] Intermediate video frames are generated at least in part based on the set of occluded pixels and the set of deoccluded pixels.

[0464] 44. The machine-readable medium according to any one of clauses 38-43, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

[0465] 45. A method comprising:

[0466] Sample the first set of pixel data from the first video frame;

[0467] At least in part, a second set of pixel data for the second video frame is sampled based on a set of forward motion vectors from the first video frame to the second video frame; and

[0468] Intermediate video frames are generated between the first video frame and the second video frame, based at least in part on the first set of pixel data and the second set of pixel data.

[0469] 46. ​​The method according to clause 45, wherein sampling of the first set of pixel data is based at least in part on a set of backward motion vectors from the second video frame to the first video frame.

[0470] 47. The method described under clause 45 or 46 further comprises:

[0471] Generate a set of intermediate forward motion vectors from the intermediate video frame to the second video frame; and

[0472] Generate a set of intermediate backward motion vectors from the intermediate video frame to the first video frame, wherein sampling of the first set of pixel data is at least partially based on the set of intermediate backward motion vectors.

[0473] 48. The method according to any one of clauses 45-47, wherein generating the set of intermediate forward motion vectors is based at least in part on the depth values ​​of pixels in the first video frame.

[0474] 49. The method according to any one of clauses 45-48 further includes:

[0475] Identify pixels in intermediate video frames that do not have a corresponding pixel in the second video frame identified using forward motion vectors, or do not have a corresponding pixel in the first video frame identified using backward motion vectors.

[0476] The color of the identified pixels in the intermediate video frame is set to that of one of the pixels at the same location as the identified pixels in the first video frame or the second video frame, based at least in part on the depth value of the pixels at the same location as the identified pixels in the first video frame or the second video frame.

[0477] 50. The method according to any one of clauses 45-49 further includes:

[0478] Generate an occlusion mask;

[0479] Generate a de-occlusion mask;

[0480] The first set of pixel data is sampled at least in part based on the occlusion mask; and

[0481] The second set of pixel data is sampled at least in part based on the demasking mask.

[0482] 51. The method according to any one of clauses 45-50, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

[0483] 52. A system comprising:

[0484] One or more processors are used for:

[0485] Sample the first set of pixel data from the first video frame;

[0486] At least in part, a second set of pixel data for the second video frame is sampled based on a set of forward motion vectors from the first video frame to the second video frame; and

[0487] An intermediate video frame is generated, at least in part, based on a first set of pixel data and a second set of pixel data between the first video frame and the second video frame; and

[0488] One or more memories are used to store intermediate video frames.

[0489] 53. The system according to Clause 52, wherein the one or more processors are used for:

[0490] Receive a set of forward motion vectors and a set of backward motion vectors from one or more buffers; and

[0491] The first set of pixel data is sampled at least in part based on a set of backward motion vectors.

[0492] 54. The system according to clause 52 or 53, wherein the one or more processors are used for:

[0493] Receive the first set of depth values ​​from the buffer;

[0494] At least in part based on the set of forward motion vectors and the first set of depth values, a set of intermediate forward motion vectors is generated from the intermediate video frame to the second video frame; and

[0495] Intermediate video frames are generated at least in part based on the set of intermediate forward motion vectors.

[0496] 55. The system according to any one of clauses 52-54, wherein said one or more processors are used for:

[0497] Receive the second set of depth values;

[0498] At least in part, based on a set of backward motion vectors and a second set of depth values, a set of intermediate backward motion vectors is generated from the intermediate video frame to the first video frame; and

[0499] Intermediate video frames are generated at least in part based on the set of intermediate backward motion vectors.

[0500] 56. The system according to any one of clauses 52-55, wherein said one or more processors are used for:

[0501] Generate an occlusion mask;

[0502] Generate occlusion removal mask; and

[0503] Intermediate video frames are generated at least in part based on the occlusion mask and the de-occlusion mask.

[0504] 57. The system according to any one of clauses 52-56, wherein the one or more processors are further configured to:

[0505] One or more additional intermediate video frames are generated between the first video frame and the second video frame, based at least in part on the first video frame, the second video frame, a set of forward motion vectors, a set of backward motion vectors, and a set of depth indicators.

[0506] 58. The system according to any one of clauses 52-57, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

[0507] Other variations are within the spirit of this disclosure. Therefore, although the disclosed technology is readily adaptable to various modifications and alternative constructions, certain embodiments thereof are illustrated in the accompanying drawings and have been described in detail above. However, it should be understood that the disclosure is not intended to be limited to one or more specific forms disclosed, but rather, it is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined in the appended claims.

[0508] Unless otherwise stated or obviously contradicted by the context, the terms “a,” “an,” and “the,” and similar references, used in the context of describing the disclosed embodiments (particularly in the context of the appended claims), should be interpreted as encompassing both singular and plural forms, rather than as definitions of the terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to”). The term “connection” (referring to a physical connection where not modified) should be interpreted as partially or wholly contained, attached to, or joined together, even with some intervention. Unless otherwise indicated herein, references to numerical ranges herein are intended only as a way of abbreviating each individual value falling within that range, and each individual value is incorporated into the specification as if it were separately described herein. Unless otherwise indicated or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by the context, the term “subset” of the corresponding set does not necessarily mean an appropriate subset of the corresponding set, but rather that the subset and the corresponding set can be equal.

[0509] Unless otherwise explicitly stated or clearly contradicted by the context, connective phrases such as “at least one of A, B, and C” or “at least one of A, B, and C” are understood in the context to generally refer to items, terms, etc., which can be A or B or C, or any non-empty subset of the set A, B, and C. For example, in an illustrative example of a set with three members, the connective phrases “at least one of A, B, and C” and “at least one of A, B, and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such connective language is generally not intended to imply that some embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise stated or contradicted by the context, the term “multiple” indicates a plural state (e.g., “multiple items” means multiple items). The number of items in a multiple item is at least two, but may be more if explicitly indicated or indicated by the context. Furthermore, unless otherwise stated or clearly understood from the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0510] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations thereof and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that is executed jointly on one or more processors via hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (i.e., as a result of execution), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media lack all the code, but the multiple non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors; for example, the non-transitory computer-readable storage media store the instructions, and the main central processing unit (“CPU”) executes some instructions while the graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and the different processors execute different subsets of the instructions.

[0511] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that perform the operations of the processes described herein, either individually or collectively, and such a computer system is configured with suitable hardware and / or software to enable the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment it is a distributed computer system comprising multiple devices operating in different ways, such that the distributed computer system performs the operations described herein, and that a single device does not perform all the operations.

[0512] The use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate embodiments of this disclosure and does not constitute a limitation on the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosure.

[0513] All references cited in this article, including publications, patent applications and patents, are incorporated herein by reference as if each reference were individually and specifically indicated to be incorporated herein by reference and the entire contents of which are described herein.

[0514] The terms “coupled” and “connected”, and their derivatives, may be used in the specification and claims. It should be understood that these terms may not be intended to be synonyms with each other. Rather, in certain examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0515] Unless otherwise expressly stated, it will be understood that throughout this specification, terms such as “processing,” “computing,” “determining,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that process and / or convert data represented as physical quantities (e.g., electrons) in the registers and / or memory of the computing system into other data represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0516] In a similar manner, the term "processor" can refer to any device or part of memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a CPU or a GPU. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Similarly, each process can refer to multiple processes that execute instructions sequentially or intermittently, sequentially, or in parallel. The terms "system" and "method" are used interchangeably herein, provided that a system can embody one or more methods, and a method can be considered a system.

[0517] This document refers to the process of acquiring, obtaining, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. The process of acquiring, obtaining, receiving, or inputting analog and digital d...

Claims

1. A processor, comprising: One or more circuits are used for: Sample the first set of pixel data from the first video frame; A second set of pixel data is sampled from the second video frame based at least in part on a set of forward motion vectors of pixel positions from the first video frame to the second video frame, wherein the first video frame and the second video frame are captured at different times; Determine the weighting factor to be applied to the first set of pixel data and the second set of pixel data, a first set of corresponding pixels and a second set of corresponding pixels, wherein the first set of corresponding pixels will include any pixel associated with the first set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame, and the second set of corresponding pixels will include any pixel associated with the second set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame; For any intermediate pixel in the intermediate video frame that corresponds to at least one pixel in the first set of corresponding pixels and at least one pixel in the second set of corresponding pixels, the weighting factor is based at least in part on a first time amount and a second time amount between the intermediate video frame and the first video frame and the second video frame, respectively. For any intermediate pixel in the intermediate video frame that is missing either the first set of corresponding pixels or a corresponding pixel in the second set of corresponding pixels, the weighting factor is selected from a set of predetermined values; and The intermediate video frame is generated by applying the weighting factor to the first set of pixel data and the second set of pixel data.

2. The processor of claim 1, wherein the one or more circuits are configured to sample the first set of pixel data based at least in part on a set of backward motion vectors from the second video frame to the first video frame.

3. The processor of claim 1, wherein the one or more circuits are further configured to: identify pixels of the intermediate video frame that have corresponding pixels identified using intermediate motion vectors only in one of the first video frame and the second video frame; and sample pixel data only from the one video frame that has the corresponding pixels of the identified pixels in the first video frame and the second video frame.

4. The processor of claim 1, wherein the one or more circuits are further configured to generate a set of intermediate forward motion vectors from the intermediate video frame to the second video frame, at least in part based on the set of intermediate forward motion vectors, and wherein the one or more circuits are configured to sample the second set of pixel data, at least in part based on the set of intermediate forward motion vectors.

5. The processor of claim 1, wherein the one or more circuits are further configured to: Generate a set of intermediate forward motion vectors from the intermediate video frame to the second video frame; Generate a set of intermediate backward motion vectors from the intermediate video frame to the first video frame; and The intermediate video frames are generated at least in part based on the set of intermediate forward motion vectors and the set of intermediate backward motion vectors.

6. The processor of claim 5, wherein the one or more circuits are further configured to: The set of intermediate forward motion vectors is generated at least in part based on the depth values ​​of pixels in the first video frame; and The set of intermediate backward motion vectors is generated at least in part based on the depth values ​​of the pixels in the second video frame.

7. The processor of claim 1, wherein the one or more circuits are further configured to: Generate an occlusion mask; Generate occlusion removal mask; and The intermediate video frames are generated at least in part based on the occlusion mask and the de-occlusion mask.

8. The processor of claim 1, wherein the one or more circuits are configured to generate the intermediate video frame based at least in part on receiving from one or more buffers the first video frame, the second video frame, depth information, forward motion vectors, and backward motion vectors associated with pixel data of at least a first portion of the first video frame or a second portion of the second video frame.

9. The processor of claim 1, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

10. The processor of claim 1, wherein the one or more circuits are further configured to transmit the generated intermediate video frames over a network.

11. A non-transitory computer-readable storage medium having a set of instructions stored thereon, which, if executed by one or more processors, causes the one or more processors to at least: Sample the first set of pixel data from the first video frame; A second set of pixel data is sampled from the second video frame based at least in part on a set of forward motion vectors of pixel positions from the first video frame to the second video frame, wherein the first video frame and the second video frame are captured at different times; Determine the weighting factor to be applied to the first set of pixel data and the second set of pixel data, a first set of corresponding pixels and a second set of corresponding pixels, wherein the first set of corresponding pixels will include any pixel associated with the first set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame, and the second set of corresponding pixels will include any pixel associated with the second set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame; For any intermediate pixel in the intermediate video frame that corresponds to at least one pixel in the first set of corresponding pixels and at least one pixel in the second set of corresponding pixels, the weighting factor is based at least in part on a first time amount and a second time amount between the intermediate video frame and the first video frame and the second video frame, respectively. For any intermediate pixel in the intermediate video frame that is missing either the first set of corresponding pixels or a corresponding pixel in the second set of corresponding pixels, the weighting factor is selected from a set of predetermined values; and The intermediate video frame is generated by applying the weighting factor to the first set of pixel data and the second set of pixel data.

12. The non-transitory computer-readable storage medium of claim 11, wherein if the set of instructions is executed by the one or more processors, the one or more processors further cause the one or more processors to: The first set of pixel data is sampled at least in part based on a set of backward motion vectors from the second video frame to the first video frame.

13. The non-transitory computer-readable storage medium of claim 11, wherein the intermediate video frame is a first intermediate video frame, and wherein if the set of instructions is executed by the one or more processors, the one or more processors further cause the one or more processors to: A second intermediate video frame is generated between the first video frame and the second video frame, based at least in part on the first set of pixel data and the second set of pixel data.

14. The non-transitory computer-readable storage medium of claim 11, wherein if the set of instructions is executed by the one or more processors, the one or more processors further cause the one or more processors to: The intermediate video frame is generated at least in part based on a weighted average of pixel color information of pixels for the intermediate video frame from the first set of pixel data and the second set of pixel data, wherein the pixels have corresponding pixels identified using a first intermediate motion vector in the first video frame and corresponding pixels identified using a second intermediate motion vector in the second video frame.

15. The non-transitory computer-readable storage medium of claim 14, wherein the pixel color information is: a first set of RGB values ​​from the first set of pixel data and a second set of RGB values ​​from the second set of pixel data.

16. The non-transitory computer-readable storage medium of claim 11, wherein if the set of instructions is executed by the one or more processors, the one or more processors further cause the one or more processors to: Identify a set of occluded pixels; Determine a set of de-occluded pixels; and The intermediate video frames are generated at least in part based on the set of occluded pixels and the set of deoccluded pixels.

17. The non-transitory computer-readable storage medium of claim 11, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

18. The non-transitory computer-readable storage medium of claim 11, wherein each of the set of forward motion vectors extends from a corresponding pixel position among a plurality of pixel positions in the first video frame to the pixel position in the second video frame.

19. A method comprising: Sample the first set of pixel data from the first video frame; A second set of pixel data is sampled from the second video frame based at least in part on a set of forward motion vectors of pixel positions from the first video frame to the second video frame, wherein the first video frame and the second video frame are captured at different times; Determine the weighting factor to be applied to the first set of pixel data and the second set of pixel data, a first set of corresponding pixels and a second set of corresponding pixels, wherein the first set of corresponding pixels will include any pixel associated with the first set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame, and the second set of corresponding pixels will include any pixel associated with the second set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame; For any intermediate pixel in the intermediate video frame that corresponds to at least one pixel in the first set of corresponding pixels and at least one pixel in the second set of corresponding pixels, the weighting factor is based at least in part on a first time amount and a second time amount between the intermediate video frame and the first video frame and the second video frame, respectively. For any intermediate pixel in the intermediate video frame that is missing either the first set of corresponding pixels or a corresponding pixel in the second set of corresponding pixels, the weighting factor is selected from a set of predetermined values; and The intermediate video frame is generated by applying the weighting factor to the first set of pixel data and the second set of pixel data.

20. The method of claim 19, wherein sampling the first set of pixel data is based at least in part on a set of backward motion vectors from the second video frame to the first video frame.

21. The method of claim 19, further comprising: Generate a set of intermediate forward motion vectors from the intermediate video frame to the second video frame; as well as Generate a set of intermediate backward motion vectors from the intermediate video frame to the first video frame, wherein sampling of the first set of pixel data is at least partially based on the set of intermediate backward motion vectors.

22. The method of claim 21, wherein generating the set of intermediate forward motion vectors is based at least in part on the depth values ​​of pixels in the first video frame.

23. The method of claim 19, further comprising: Identify pixels in the intermediate video frames that do not have a corresponding pixel in the second video frame identified using forward motion vectors, or that do not have a corresponding pixel in the first video frame identified using backward motion vectors; and The color of the identified pixels in the intermediate video frame is set to that of one of the pixels at the same position as the identified pixels in the first video frame or the second video frame, based at least in part on the depth value of the pixels at the same position as the identified pixels in the first video frame and the second video frame.

24. The method of claim 19, further comprising: Generate an occlusion mask; Generate a de-occlusion mask; The first set of pixel data is sampled at least in part based on the occlusion mask; as well as The second set of pixel data is sampled at least in part based on the demasking mask.

25. The method of claim 19, wherein each of the set of forward motion vectors includes a projected vertex movement.

26. The method of claim 19, further comprising displaying the generated intermediate video frames.

27. A system comprising: One or more processors are used for: Sample the first set of pixel data from the first video frame; A second set of pixel data is sampled from the second video frame based at least in part on a set of forward motion vectors of pixel positions from the first video frame to the second video frame, wherein the first video frame and the second video frame are captured at different times; Determine the weighting factor to be applied to the first set of pixel data and the second set of pixel data, a first set of corresponding pixels and a second set of corresponding pixels, wherein the first set of corresponding pixels will include any pixel associated with the first set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame, and the second set of corresponding pixels will include any pixel associated with the second set of pixel data that corresponds to one or more intermediate pixels of the intermediate video frame; For any intermediate pixel in the intermediate video frame that corresponds to at least one pixel in the first set of corresponding pixels and at least one pixel in the second set of corresponding pixels, the weighting factor is based at least in part on a first time amount and a second time amount between the intermediate video frame and the first video frame and the second video frame, respectively. For any intermediate pixel in the intermediate video frame that is missing either the first set of corresponding pixels or a corresponding pixel in the second set of corresponding pixels, the weighting factor is selected from a set of predetermined values; and The intermediate video frame is generated by applying the weighting factor to the first set of pixel data and the second set of pixel data; as well as One or more memories for storing the intermediate video frames.

28. The system of claim 27, wherein the one or more processors are further configured to: Receive the set of forward motion vectors and the set of backward motion vectors from one or more buffers; and The first set of pixel data is sampled at least in part based on the set of backward motion vectors.

29. The system of claim 27, wherein the one or more processors are further configured to: Receive depth information from the buffer, the depth information including a first set of depth values; At least in part based on the set of forward motion vectors and the first set of depth values, a set of intermediate forward motion vectors is generated from the intermediate video frame to the second video frame; and The intermediate video frames are generated at least in part based on the set of intermediate forward motion vectors.

30. The system of claim 29, wherein the one or more processors are further configured to: Receive the second set of depth values; At least in part, based on a set of backward motion vectors and a second set of depth values, a set of intermediate backward motion vectors is generated from the intermediate video frame to the first video frame; and The intermediate video frames are generated at least in part based on the set of intermediate backward motion vectors.

31. The system of claim 30, wherein the one or more processors are further configured to: Generate an occlusion mask; Generate occlusion removal mask; and The intermediate video frames are generated at least in part based on the occlusion mask and the deocclusion mask.

32. The system of claim 27, wherein the one or more processors are further configured to: One or more additional intermediate video frames are generated between the first video frame and the second video frame, based at least in part on the first video frame, the second video frame, the set of forward motion vectors, the set of backward motion vectors, and the set of depth indicators.

33. The system of claim 27, wherein each of the set of forward motion vectors includes a vertex movement of the projection.

34. The system according to claim 27, wherein: The first and second video frames are consecutive video frames; and The intermediate video frame is interpolated between the first and second video frames.

35. The system of claim 28, wherein the one or more processors are configured to: The intermediate video frame is generated by forward warping the set of forward motion vectors and the set of backward motion vectors based at least in part on the sampled first set of pixel data and the sampled second set of pixel data.

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