Device and method for refreshing process when displaying images on LED panel

Abstract

The present teachings relate to methods, systems, media, and implementations for refreshing an LED display. A signal is received that signals a timing for refreshing an LED display. In response to the signal, a bit-based image block is retrieved from one buffer of an alternating buffer pair pointed to by a read buffer pointer, and then the read buffer pointer is switched to point to another buffer of the alternating buffer pair. The bits in the bit-based image block are sequenced according to a connection pattern in which the lights of the LED display are connected to generate sequenced image bits for the bit-based image block, and a control signal is generated for refreshing the lights of the LED display based on the sequenced image bits. The lights of the LED display are refreshed based on the control signal.

Description

[0001] This application claims priority to U.S. patent application No. 16 / 945,130 filed on July 31, 2021, and is related to U.S. patent application No. 16 / 945,011 filed on July 31, 2020 and U.S. patent application No. 16 / 945,093 filed on July 31, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present teachings generally relate to LED displays. More specifically, the present teachings relate to displaying information on LED panels. Background Art

[0003] In a society where electronic products are everywhere, almost every electronic device has a display panel. Light emitting diode (LED) display panel is one of the most popular display panels and is generally a flat display panel formed using a module or matrix of light emitting diodes. LED display panels are bright, large, and have a long life, and are widely used in various public places such as airports, banks, stadiums, and hotels. They are also often used as billboards for displaying advertisements. This industry has grown rapidly in the past 10 years and is still growing.

[0004] An LED display panel includes a display panel (with LED bulbs and panel), (one or more) controllers, and LED drivers. In operation, the LED driver supplies current to cause the LED bulb to emit light, while the controller controls activities related to reading image data from a storage device and coordinates the operation of displaying the image on the LED panel. The controller achieves this by sending control signals to the LED driver at specific timings to turn the LED lights on and off at desired time instances so that the image is properly formed on the display. The controller plays a vital role in the performance and display effect of the LED panel.

[0005] There are different types of LED panels. Some can be single color, i.e., each pixel on the panel has one light that is either on or off (binary). Some can be bi-color, i.e., each pixel on the panel has 2 lights, for example, red and green, resulting in 4 different combinations: (1) red (red light on, green light off), (2) green (red light off, green light on), black (both red and green lights off), and yellow (both red and green lights on). Some LED display panels are full color panels, with each pixel on the panel having three lights, corresponding to red, green, and blue. The number of intensity levels associated with each light determines the color resolution of the panel. The number of intensity levels is controlled by the duration that the light is on. For example, a particular color light can have 256 levels of intensity when it is on and this is achieved by controlling the length of time the light remains on.

[0006] In many applications, large-sized LED display panels are required. For example, LED billboards deployed in stadiums, airports, or stock exchanges need to be very large to ensure visibility from a distance. Therefore, many individual LED panels are usually used to form larger LED display panels of the desired size. An example is shown in FIG. 1A, in which a matrix of unit LED panels (smaller) of K rows and M columns forms a much larger LED display panel. When a plurality of unit panels are used to form a larger panel, the unit panels can be electrically connected in different ways. An exemplary way of connecting 4X8 unit panels is shown in FIG. 1B, in which the LED unit panels in each row are electrically driven from one end to the other by a controller. FIG. 1C shows different panel connections. The controller controls the current to all rows presented in this example. From the perspective of circuit connection, it is also shown in FIG. 1D, in which the electronic connection is along the row direction from one unit panel in the same row to the next unit panel.

[0007] Each unit panel is a matrix of pixels. A picture of an exemplary unit panel 110 with 16x32 pixels is provided in FIG. 1E. As discussed herein, each pixel has one or more lights. Each light associated with each pixel in the unit panel can be individually controlled to turn on or off a certain duration according to the image content at the corresponding position. FIG. 1F illustrates an example 8x8 full-color image block 120, in which each pixel has three color components, corresponding to red (R), green (G) and blue (B). Therefore, as seen in FIG. 1F, the color block 120 actually has three 8x8 matrices, one is an R matrix, one is a G matrix, and one is a B matrix. For example, pixel 00 consists of three values, R (00), G (00) and B (00), corresponding to its red component value, green component value and blue component value, respectively. Each of the color components (R, G, B) can be represented by multiple bits to encode the intensity level of the corresponding color component. For example, if each color component has 3 bits, then it produces 8 intensity levels; if each color component has 8 bits, then it produces 256 intensity levels, etc. These encoded intensity levels will be used to control the timing and duration of the LED lights when displaying image content on the LED display panel.

[0008] When the row signal controlled by the row driver and the column signal controlled by the column driver provide current from two directions, the LED lamp associated with the pixel position of the LED panel is turned on. An example is shown in FIG. 1G, in which each row driver is configured to drive multiple rows of pixels, and the column driver is configured to drive all columns, as shown in the figure. If a specific LED lamp located in a certain row and column is to be turned on, the row signal through the specific row and the column signal through the specific column are controlled to provide current to the position. The column driver is connected in series both inside the unit panel and across different unit panels. Such connection can be determined based on how the unit panel is connected.

[0009] As shown in Figures 1B and 1C, the unit panels that form a larger LED display panel can be connected in different ways. The column drivers on each unit panel can also be connected in different ways. Figure 1H shows an exemplary column connection scheme for linking different column drivers on each unit panel. In Figure 1H, starting from the top column driver [1,1] in the left column, the signal travels from the column driver [1,1] to the column driver [K,1] in the bottom row, then returns to the top row column driver [1,2] of the next column, and then follows the same pattern until it reaches the last column driver [K,M]. Since each unit panel is a matrix of pixels inside, and the column signal can travel within each unit panel.

[0010] There are synchronous and asynchronous operation modes in LED panel displays. In synchronous mode, images are supplied in real time (on-the-fly) (e.g., streaming), so LED displays must be synchronous. In asynchronous mode, images are first stored, and when displayed on the LED display panel, the images are retrieved from the storage device and then displayed accordingly. There are different traditional methods to achieve asynchronous operation. One method is to use a microcontroller unit (MCU), and another method is to use the MCU in combination with a field programmable gate array (FPGA). FIG. 2A illustrates the construction of a traditional controller implementation using an MCU. As shown in the figure, there is an image storage device 205 for storing images to be displayed on the LED display panel, and an MCU 210. In order to display an image on the LED display panel, the MCU 210 reads the image from the storage device 205, processes the image data, transforms the processed data into a suitable form for screen refresh for display, and generates and transmits appropriate control signals (e.g., row / column signals, as a clock signal CLK) to the display panel controller. FIG. 2B provides an exemplary construction of MCU 210. Typically, the MCU 210 includes a flash memory reader module 220 and a central processing unit (CPU) 230. The flash memory reader module 220 is provided for reading relevant information from the storage device 205, which may include image data to be displayed and other peripheral information, such as some operating parameters such as the front-end library 207. Once the image data is read, it is stored in the buffer 215 so that it can be accessed by the CPU 230 for processing. The CPU 230 processes the image data either from 215 or directly from the flash memory reader module 220. This may include any special effects processing and transformation. The CPU 230 may also use the processed image to transform the image data into information that can be used to refresh the LED. This transformed refresh information may be stored in the SRAM storage device 225 within the MCU and then transmitted to the LED display panel via the GPIO interface. In this embodiment, all operations on graphics calculations, data transformations, and screen refreshes are performed by software in the MCU 210 running on the CPU 230. It is known that the processing speed using software is slow. Due to the nature of LED displays, using the solution shown in Figure 2B is so slow that MCU-based solutions are generally only suitable for small LED displays.

[0011] Another conventional solution to the speed problem is shown in Fig. 2C, with a solution of an asynchronous LED display using a combination of an MCU 240 and a field programmable gate array (FPGA) 250. In this embodiment, the MCU 240 is generally used to read data and perform graphic calculations. The data prepared by the MCU 240 is subsequently transferred to the FPGA 250, which is responsible for data conversion and screen refresh. As shown, each of the MCU 240 and the FPGA 250 has its own SDRAM 245 and 255, respectively, for storing image data. The LCD interface or other interfaces with GPIO are used to transmit data between the MCU 240 and the FPGA 250.

[0012] Although the solution of combining MCU and FPGA can alleviate the speed problem associated with the MCU-only solution, there are other defects associated with these traditional solutions of LED displays. First, both methods require a large amount of memory resources. The MCU in both methods needs to read one or more complete images and store them in SRAM. For most MCUs, this calls for a large amount of SRAM resources. Therefore, the size or number of LED lights applied to the LED screen needs to be limited by the SRAM capacity of the MCU. For large screens or full-color LED screens with a large number of pixels, a solution of combining MCU with FPGA can be adopted to increase the speed by making the FPGA perform data transformation and screen refresh. However, additional disadvantages still exist. The typical problem is the cost associated with FPGA. In order to achieve the same logical function, the cost associated with FPGA is much higher than other solutions.

[0013] Therefore, there is a need for methods and systems that address the shortcomings associated with conventional solutions for LED displays. Summary of the invention

[0014] The teachings disclosed herein relate to methods, systems, and programs for advertising. More specifically, the teachings relate to methods, systems, and programs related to exploring sources of advertising and their utilization.

[0015] In one example, a method for refreshing an LED display implemented on a machine having at least one processor, a storage device, and a communication platform capable of connecting to a network. A signal is received that signals the timing of refreshing the LED display. In response to the signal, a bit-based image block is retrieved from one buffer of an alternating buffer pair pointed to by a read buffer pointer, and then the pointer is switched to another buffer of the alternating buffer pair. The bits in the bit-based image block are sequenced according to a connection pattern in which the lights of the LED display are connected to generate sequenced image bits for the bit-based image block, and a control signal is generated for refreshing the lights of the LED display based on the sequenced image bits. The lights of the LED display are refreshed based on the control signal.

[0016] In a different example, a system for refreshing an LED display includes an image bit sequencer and an LED refresh unit. The image bit sequencer is configured to retrieve a bit-based image block from one of the alternating buffer pairs pointed to by a read buffer pointer in response to a received signal indicating a timing for refreshing the LED display, switch the read buffer pointer to point to another of the alternating buffer pairs, and sequence the bits in the bit-based image block according to a connection pattern in which the lights of the LED display are connected to generate sequenced image bits of the bit-based image block. The LED refresh unit is configured to generate a control signal for refreshing the lights of the LED display based on the sequenced image bits, and refresh the lights of the LED display based on the control signal.

[0017] Other concepts relate to software for implementing the present teachings. A software product according to this concept includes at least one machine-readable non-transitory medium and information carried by the medium. The information carried by the medium may be executable program code data, parameters associated with the executable program code, and / or information related to a user, request, content, or other additional information.

[0018] In one example, a machine-readable, non-transitory, and tangible medium having data recorded thereon for refreshing an LED display. A signal is received that signals the timing of refreshing the LED display. In response to the signal, a bit-based image block is retrieved from one buffer of an alternating buffer pair pointed to by a read buffer pointer, and then a switch is made to point to another buffer of the alternating buffer pair. The bits in the bit-based image block are sequenced according to a connection pattern in which the lights of the LED display are connected to generate sequenced image bits for the bit-based image block, and a control signal is generated for refreshing the lights of the LED display based on the sequenced image bits. The lights of the LED display are refreshed based on the control signal.

[0019] Additional advantages and novel features will be set forth in part in the following description, and in part will become apparent to those skilled in the art upon examination of the following and accompanying drawings, or may be learned by production or operation of the examples. The advantages of the present teachings may be realized and obtained by practice or use of various aspects of the methods, tools, and combinations set forth in the detailed examples discussed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0021] The methods, systems and / or programs described herein are further described according to exemplary embodiments. These exemplary embodiments are described in detail with reference to the accompanying drawings. These embodiments are non-limiting exemplary embodiments, in which the same reference numerals represent similar structures in the several views of the drawings, and in which:

[0022] 1A-1B (Prior Art) illustrate an exemplary array of LED unit panels connected via different panels to form a larger LED display panel;

[0023] FIG. 1C (Prior Art) shows an exemplary manner of connecting a panel of LED units;

[0024] FIG. 1D (Prior Art) illustrates the row connections of a panel of LED units;

[0025] FIG. 1E (Prior Art) shows an exemplary LED unit panel having pixels;

[0026] FIG. 1F (Prior Art) illustrates an exemplary representation of an 8x8 LED unit panel with full color;

[0027] FIG. 1G (Prior Art) shows an exemplary manner of driving pixels in an LED panel;

[0028] FIG. 1H (PRIOR ART) illustrates an exemplary manner of connecting a panel of LED units;

[0029] FIG. 2A (Prior Art) shows an implementation of a conventional MCU-based controller card;

[0030] FIG. 2B illustrates an exemplary configuration of an MCU as a controller card for an LED display;

[0031] FIG. 2C (Prior Art) shows a conventional implementation of a controller card having an MCU and an FPGA;

[0032] Figure 3Adepicts an exemplary high-level system diagram of a controller for an LED display with handshaking according to an embodiment of the present teachings;

[0033] Figure 3B is a flow chart of an exemplary process of a controller for an LED display with handshaking according to an embodiment of the present teachings;

[0034] Figure 3C depicts an exemplary high-level system diagram of a controller for an LED display with a shared clock according to an embodiment of the present teachings;

[0035] Figure 3D is a flow chart of an exemplary process of a controller for an LED display with a shared clock according to an embodiment of the present teachings;

[0036] Figure 4A An exemplary representation of color image data to facilitate LED display according to an embodiment of the present teachings is shown;

[0037] Figure 4B An exemplary scheme for encoding a 1x3 image data block according to an embodiment of the present teachings is shown;

[0038] Figure 4C An exemplary compressed representation of image data according to an embodiment of the present teachings is shown;

[0039] Figure 5 depicts an exemplary high-level system diagram of a data transfer unit according to an embodiment of the present teachings;

[0040] Figure 6 is a flow chart of an exemplary process of a data transfer unit according to an embodiment of the present teachings;

[0041] Figure 7 depicts an exemplary high-level system diagram of a refresh processor according to an embodiment of the present teachings;

[0042] Fig. 8A shows different pixel rows on a single color LED panel driven individually by different column signals according to an embodiment of the present teachings;

[0043] Figure 8B shows a representation of different rows of pixels on a single color LED panel driven individually by different column drivers according to an embodiment of the present teachings;

[0044] Fig. 9A shows column signals for driving different rows of pixels having a single color via a serpentine I connection according to an embodiment of the present teachings;

[0045] Fig. 9Bshows a representation of a column driver in a serpentine I wiring for driving different rows of pixels according to an embodiment of the present teachings;

[0046] Fig. 9C shows the contents of a register when the register is loaded with image data of a single color according to an embodiment of the present teachings;

[0047] Fig.9D shows the results of sequencing bits in a register loaded with image data of a single color to facilitate a serpentine I connection in accordance with an embodiment of the present teachings;

[0048] Fig. 10A shows column signals driving different rows of pixels with a single color via a serpentine II connection according to an embodiment of the present teachings;

[0049] Fig. 10B shows a representation of a column driver for driving different rows of pixels with a single color via serpentine II wiring according to an embodiment of the present teachings;

[0050] Fig. 10C shows the results of sequencing bits in registers loaded with different rows of pixels of a single color to facilitate a Snake II connection in accordance with an embodiment of the present teachings;

[0051] Fig.11A shows column signals driving different rows of pixels with a single color via a serpentine III connection according to an embodiment of the present teachings;

[0052] Fig. 11B shows a representation of a column driver for driving different rows of pixels with a single color via serpentine III wiring according to an embodiment of the present teachings;

[0053] Fig. 11C shows the results of sequencing bits in registers loaded with different rows of pixels of a single color to facilitate a snake III connection in accordance with an embodiment of the present teachings;

[0054] Fig. 12A A two-color pixel row is shown in accordance with an embodiment of the present teachings, wherein each color component is driven separately by a separate column signal;

[0055] Fig. 12B A separate column driver according to an embodiment of the present teachings is shown driving two respective color components of a pixel in dual color;

[0056] Fig.13A A dual color pixel row is shown having two color components driven by the same column signal via a serpentine I connection according to an embodiment of the present teachings;

[0057] Fig. 13Bshows a representation of a column driver according to an embodiment of the present teachings, which drives two color components of a row of pixels in bicolor via a serpentine I connection;

[0058] Fig. 13C shows the contents of a register loaded with a dual-color pixel according to an embodiment of the present teachings;

[0059] Fig.13D shows the results of sequencing bits in a register loaded with two-color pixels to facilitate a Snake II connection in accordance with an embodiment of the present teachings;

[0060] Fig.14A shows a full color pixel row with each of the three color components driven by a separate column signal in accordance with an embodiment of the present teachings;

[0061] Fig. 14B is a representation of three column drivers according to an embodiment of the present teachings, each column driver driving a corresponding color component of a row of pixels in full color;

[0062] Fig. 14C shows the contents of a register for loading a pixel in full color according to an embodiment of the present teachings;

[0063] Fig.14D shows the results of sequencing the bits in a register loaded with a full color pixel to facilitate driving each of the different color components separately in accordance with an embodiment of the present teachings;

[0064] Fig.15A shows a representation of driving each color component individually in a serpentine I connection according to an embodiment of the present teachings;

[0065] Fig. 15B shows the results of sequencing bits in a register loaded with full color pixels to facilitate a Snake II connection in accordance with an embodiment of the present teachings;

[0066] Fig.16 is a flow chart of an exemplary process for refreshing a processor according to an embodiment of the present teachings; and

[0067] Fig.17 is an illustrative diagram of an exemplary computing device architecture that can be used to implement a special purpose system implementing the present teachings in accordance with various embodiments. DETAILED DESCRIPTION

[0068] In the following detailed description, many specific details are set forth by way of example to facilitate a thorough understanding of the relevant teachings. However, it is apparent to those skilled in the art that the present teachings may be practiced without these details. In other cases, well-known methods, processes, components and / or circuit systems have been described at a relatively high level without detailed description to avoid unnecessarily obscuring aspects of the present teachings.

[0069] The present teaching is intended to address the deficiencies of conventional asynchronous LED display methods. As discussed herein, conventional systems either require significant memory resources or require expensive solutions. The present teaching discloses a system and method for an asynchronous LED display that requires little memory resources and is cost effective. Furthermore, the present teaching is directed to a solution that can be flexibly applied to LED screens where LED unit panels are connected in different ways. Furthermore, the disclosed system and method are fast, so they can be used to display on large LED panels.

[0070] Specifically, the present teaching discloses a controller system for an LED display having a data transfer unit and a refresh processor, both of which are clocked by the same clock signal, and a small data storage device bridging the data transfer unit and the refresh processor for buffering image data from the data transfer unit that will be needed by the refresh processor in the near future.

[0071] Figure 3A An exemplary high-level system diagram of an LED display controller 300 with handshake according to an embodiment of the present teaching is depicted. As seen, the LED display controller 300 obtains image data from a storage device 310 and outputs a plurality of signals for controlling the display on the LED display panel. The storage device 310 may be a flash memory or any other form of data storage device that facilitates fast access. The output signals from the controller 300 may include row / column signals, clock signals, etc., wherein the row / column signals are used to drive rows and columns to control the state of the lights associated with each pixel on the LED screen (on / off and / or duration of each state to achieve an intensity determined based on pixel content). Such control signals are appropriately generated based on the image content.

[0072] The LED display controller 300 includes a data transfer unit 320, an SRAM storage device 330, a refresh processor 340, and a handshake manager 307. In this illustrated embodiment, the operations of the data transfer unit 320 and the refresh processor 340 are coordinated via some synchronization signals, such as, for example, a specific handshake protocol managed by the handshake manager 307. Through this coordination, the data transfer unit 320 and the refresh processor 340 are synchronized so that the data transfer unit 320 supplies image data to a smaller buffer 330, and the refresh processor 340 retrieves the image data from the buffer in real time. At each supply of an image data block, the synchronization operation of the refresh processor 340 can follow. Based on this mode of operation, only limited image data needs to be stored in the SRAM, greatly reducing the requirements for memory resources.

[0073] When synchronized via the handshake protocol, once the data transfer unit 320 stores a block of image data in the first of the alternating buffers, it may send a handshake signal to the handshake manager 307 to indicate that it has completed the data transfer to the first buffer and then proceed to transfer the next image block to the alternating buffer. Once completed, the data transfer unit 320 waits until a handshake signal is received from the refresh processor 340 indicating that the image block in the first buffer has been retrieved, so that the first buffer can now be used to load another image data block. For the refresh processor 340, after receiving a handshake signal from the data transfer unit 320 indicating that the image data block is now available in the first buffer, the refresh processor 340 proceeds to retrieve image data blocks from the first buffer for its processing. After retrieving the first image block from the first buffer, the refresh processor 340 sends its handshake signal to the data transfer unit 320 (e.g., via the handshake manager 307) to notify the data transfer unit 320 that the first image block has been retrieved.

[0074] Although synchronized, the data transfer unit 320 and the refresh processor 340 operate on different buffers at each specific time instance. However, as long as the processing speed of the two can be matched, the size of the buffer 330 or the SRAM storage device 330 can be kept very small. In this illustrated embodiment, the SRAM storage device includes two buffers 330-1 and 330-2, which can have the same size, for example, determined by the size of the image data block at each reading. The selection of the size of the buffer can be determined based on different considerations. For example, it can correspond to the width of the image, the height of the image, or the amount of data that the refresh processor 340 obtains in a batch for its processing. If it corresponds to the width of the image to be displayed, then the refresh processor 340 can be promoted to process a row of images at a time. Similarly, a buffer size equal to the length of the image can promote the refresh processor 340 to process a whole column of pixel data per batch. The size of the buffer can also be any size required by the application. Since each buffer has a size read each time, the amount of data to be buffered in 330 is much smaller than the entire image.

[0075] Because at each moment, the data transfer unit 320 and the refresh processor 340 operate on different buffers, another aspect of synchronization can be achieved via pointers. That is, a write pointer pointing to one of the two buffers for loading the image block into that buffer by the data transfer unit 320, and a read pointer pointing to the other alternating buffer for reading by the refresh processor 340 to read from the other alternating buffer for display related processing. The data transfer unit 320 switches the write pointer after loading the image block into one of the buffers and after it receives the next handshake signal from the refresh processor 340 indicating that the previous image block stored therein has been retrieved. Similarly, the refresh processor 340 switches the read pointer after it reads the image block from the buffer pointed to by the read pointer and receives a handshake signal from the data transfer unit 320 indicating that new image data has been loaded into the other alternating buffer.

[0076] Figure 3B305 is a flow chart of an exemplary process for LED display controller 300 with handshake according to an embodiment of the present teaching. At 305, data transfer unit 320 performs graphic calculations on image data stored in image data storage device 310. Such graphic calculations may be optional and processing may include, for example, certain special effects processing of the image. Preprocessing may also include other types of data processing. For example, according to one aspect of the present invention, the original image data may be reorganized. Color images are generally provided with multiple frames, each corresponding to a color component (such as red, green or blue). With this organization, data bits of different colors are stored in different frames. One possible process is to reorganize the image data so that corresponding bits from each color component can be stored together. For example, if a full-color image has an 8-bit color representation in each of the three color frames of red, green and blue. After reorganization, the converted image data has 8 frames, each pixel has three bits, and each bit is a corresponding bit from a corresponding color component. This preprocessed image data is then stored internally in data transfer unit 320.

[0077] In operation, the data transfer unit 320 may then initialize the buffer pointers pointing to the alternating buffers at 315. For example, the initialization may set the write pointer and the read pointer to point to one of the alternating buffers, such as buffer 330-1. To begin the data transfer operation, the data transfer unit 320 then obtains the next read instruction for retrieving the image data block from its internal storage at 325 (discussed in detail below). In some embodiments, the read instruction includes the starting address of the image block to be read from the internal storage and the length of the image block.

[0078] To ensure high-speed reading, the data transfer unit 320 maps the address of the image block directly onto the bus connected to the storage device at 335 to facilitate reading the image block via hardware. It then transfers the read image block to the buffer pointed to by the write pointer at 345. Once the transfer of the first image block to the buffer 330 is completed, the data transfer unit 320 sends a handshake signal to the refresh processor 340 via the handshake manager 307 at 347, which notifies the refresh process 340 that the image data block is now available in the buffer.

[0079] After sending out the handshake signal, the data transfer unit 320 continues to write the next image data block to the alternating buffer. To this end, the data transfer unit 320 switches the write pointer to the alternating buffer at 350, retrieves the next read instruction for reading the next image block at 355, and maps the address of the next image block to the bus to facilitate fast reading. The newly retrieved image block is then transferred to the alternating buffer pointed to by the write pointer at 360. At this time, the data transfer unit 320 checks at 365 whether a handshake signal is received from the refresh processor 340. This handshake signal from the refresh processor 340 indicates that the image data stored in the first buffer has been retrieved, so it can now be used to transfer a new image block. When this happens, the data transfer unit 320 switches the write pointer at 350 to point to the first alternating buffer and loads the next image block by executing steps 355 and 360. The process continues in such a loop, and coordination is achieved via the handshake signal and the buffer pointer.

[0080] The refresh processor 340 also acts based on the handshake signal. With the read pointer initialized to point to one of the two buffers (i.e., 330-1), the refresh processor 340 first checks at 367 whether it has received a handshake signal from the data transfer unit 320 indicating that image data has been sent to the buffer 330-1. When it receives the handshake signal, the refresh processor 340 accesses the first image block stored in the first buffer 330-1 based on the read pointer (pointing to the buffer 330-1) at 370. After retrieving the first image block from the buffer 330-1, the refresh processor 340 switches the read pointer to point to the buffer 330-2 at 375, and then sends a handshake signal to the data transfer unit 320 at 380 indicating that the image data buffered in 330-1 has been retrieved, so it can now be used to transfer new image data.

[0081] Then, the refresh processor 340 continues to perform processing on the retrieved image data, including sequencing the bits in the retrieved image data according to the connection mode of the LED display at 385, generating control signals based on the image content at 390, and then refreshing the LED screen using the control signals at 395. According to the present teaching, in order to transform the accessed image data into control signals, the refresh processor 340 can re-sequence the image data bits in the first image data block if necessary. The sequencing of the image bits depends on the line connection mode. In some cases, the sequencing can be performed using a microcode that is specifically programmed with respect to the connection mode of the drive connection in the unit panel of the LED display panel. Based on the sequenced image data, the refresh processor 340 then generates various control signals for implementing the image content on the LED display panel. After completing the processing of the retrieved image data, the refresh processor 340 checks at 367 whether the data transfer unit 320 sends the next handshake signal indicating that the image data has been transferred to another alternating buffer 330-2. If not, the refresh processor 340 waits until new image data is available in the alternating buffer.

[0082] Figure 3C Another exemplary high-level system diagram of an LED display controller 301 with a shared clock according to an embodiment of the present teachings is depicted. As can be seen, the LED display controller 301 herein is similar in construction to 300, except that the data transfer unit 320 and the refresh processor 340 are now coordinated via a common clock signal generated by a clock signal generator 309 (rather than via handshakes managed by a handshake manager 307, as shown in FIG. 1 ). Figure 3A ). Similarly, the LED display controller 300 includes a data transfer unit 320, an SRAM storage device 330, a refresh processor 340, and a clock signal generator 309. The clock signal generated by the clock signal generator 309 can be used by both the data transfer unit 320 and the refresh processor 340, so that the data transfer unit 320 and the refresh processor 340 are synchronized based on the same clock. As discussed herein, the data transfer unit 320 retrieves image data from the storage device 310, processes the retrieved data, and places it on the SRAM storage device 330. The refresh processor 340 accesses the processed data from the SRAM storage device 330, transforms the accessed image content into control signals that can be used to display the image content on the LED screen, and outputs such control signals to the LED display panel.

[0083] In this embodiment, since both the data transfer unit 320 and the refresh processor 340 are clocked on the same signal, the frequency at which the refresh processor requires new image data also dictates the frequency at which the data transfer unit 320 places processed image data into the SRAM storage device 330. Similarly, since the processing speed of the data transfer unit 320 is synchronized with the processing speed of the refresh processor, the size of the SRAM storage device can be kept very small. In order to operate on a per-clock basis, the data transfer unit 320 can retrieve image data from the storage device 310, for example, based on the rising edge of the first clock signal, process the image data, and save the processed image data in the first buffer 330-1, for example, based on the falling edge of the first clock signal. Then, based on the rising edge of the second clock, the data transfer unit 320 can retrieve the next batch of image data, process the image data, and save the processed image data in the second buffer 330-2, for example, based on the falling edge of the second clock. Acting based on the same clock signal, the refresh processor 340 can access the processed image data stored in the first buffer 330-1 based on, for example, the rising edge of the second clock, transform the processed image data into a control signal, and output the transformed signal based on, for example, the falling edge of the second clock. The refresh processor 340 can then access the processed image data from the second buffer 330-2 based on, for example, the rising edge of the third clock signal, transform the accessed image data into a control signal, and output the control signal. While the refresh processor 340 is accessing the processed image data buffered in the second buffer 330-2, the data transfer unit 320 retrieves the next batch of image data from the storage device 310, processes it, and again alternately saves the processed image data back to the buffer 330-1. In this way, by ensuring that the data transfer unit 320 and the refresh processor 340 can act in unison and synchronously, the SRAM storage device 330 can be kept small.

[0084] Figure 3D301 is a flow chart of an exemplary process for an LED display controller 301 with a shared clock according to an embodiment of the present teachings. At 302, the data transfer unit 320 performs graphic calculations or other types of image preprocessing on the image data stored in the image data storage device 310. As discussed herein, such preprocessed image data can be stored in a memory internal to the data transfer unit 320. In order to facilitate the alternating storage of image data in the buffer 330, the data transfer unit 320 can initialize the write and read buffer pointers at 312 to initially point to, for example, the buffer 330-1. In this embodiment, in order to synchronize operations, the data transfer unit 320 and the refresh processor 340 operate based on the clock signal generated by the clock signal generator 309. First, the data transfer unit 320 receives the next clock signal at 322, and then acts based on the clock signal to retrieve the next read instruction at 332 (discussed in detail below). As discussed herein, the read instruction can be combined with the starting address of the image block to be read and the length of the image block.

[0085] In order to keep up with the speed of the refresh processor 340, the data transfer unit 320 maps the address of the image block directly onto the bus connected to the internal memory, and then transfers the image block to the buffer pointed to by the write pointer (e.g., 330-1) at 342. Once the transfer of the first image block to the buffer 330 is completed, the data transfer unit 320 waits to receive the next clock signal at 352. At the same time, this next clock signal is also received by the refresh processor 340 and the operations of the two can be synchronized from this point onwards based on the clock signal. Based on the next clock signal action, the data transfer unit 320 retrieves the next read instruction for reading the next image block from the internal memory at 354, and maps the address of the next image block to the bus to facilitate fast transfer. In preparation for the next buffering, the buffer pointer is switched to point to an alternate buffer, such as 330-2, at 362. After the write pointer is switched to point to the buffer 330-2, the data transfer unit 320 transfers the next image block to the buffer 330-2 via hardware at 364. The operation of the data transfer unit 320 then repeats the cycle by returning to step 352.

[0086] Also based on the next clock signal operation, the refresh processor 340 takes action by first accessing the first image block pointed to by the current read pointer stored in the buffer 330-1 at 372. Once the image data in the buffer 330-1 is retrieved, the refresh processor 340 switches the read pointer at 374 to point to the alternate buffer 330-2, indicating that the next buffer to read the image data is the buffer 330-2. In order to transform the accessed image data into control signals, if necessary, the refresh processor 340 sequences the bits in the image data via the microcode at 382, ​​and the microcode is specially programmed for the connection mode of the unit panel in the current LED display panel so that the bits in the image data can be sequenced in a manner suitable for the current connection mode. Based on the re-sequenced image data, the refresh processor 340 then generates various control signals at 384 for refreshing the lights of the pixels of the LED display panel at 392 to render the image data on the LED display panel. The operation of the refresh processor 340 is then repeated by returning to step 352.

[0087] Details regarding how the present teachings operate are disclosed below. Figure 4A An exemplary organization of full color image data arranged to facilitate LED display according to an embodiment of the present teachings is shown. A conventional image corresponds to an array of pixels. When in full color, such as 120 in FIG. 1E , the image has three image frames, each corresponding to one color component R, G, and B. Depending on the resolution, each pixel of each color frame is encoded by a number of bits, for example, 8 bits representing 256 intensities in that color component space. To facilitate the present teachings, the bits in the image information are organized as follows: Figure 4A For a full color image with 8 bits per color component, the image (410) is represented by 8 frames (410-1, ..., 410-8), each frame representing one bit from each color frame. For example, in frame 1 410-1, the first pixel 00 is represented by three bits, one bit from each color frame at the corresponding bit position. That is, R00 0 is the least significant bit of the 8-bit representation of the R component for pixel 00, G00 0 is the least significant bit of the 8-bit representation of the G component for pixel 00, and B00 0 is the least significant bit of the 8-bit representation of the B component for pixel 00. In addition, R00 1 is the second lowest bit of the 8-bit representation of the R component for pixel 00, G00 1 is the second lowest bit of the 8-bit representation of the G component for pixel 00, B00 1 is the second lowest bit of the 8-bit representation of the B component for pixel 00 (not shown). 7 is the most significant bit of the 8-bit representation of the R component for pixel 00, G007 is the most significant bit of the 8-bit representation of the R component for pixel 00, B00 7 is the highest bit of the 8-bit representation of the B component for pixel 00. Similarly, for other pixels of the full-color image, the image information can be organized in the same way. For example, Figure 4A It shows how the color information of pixels 01 and 02 is organized.

[0088] With this organization, the same bits of color information for each pixel are now stored together, making it possible to read such information without crossing over different color frames. This is significant because it makes it possible to compress image data and simultaneously facilitate a more efficient way of transforming information to refresh the LED display, as described below. Figure 4B An exemplary scheme for encoding a 1x3 image data block 430 according to an embodiment of the present teaching is shown. As shown, the 1x3 image data block includes pixels 00, 01, and 02 represented by a bit block 420, where 8 rows of bits represent the full color of 3 pixels. 420 has 8 bit blocks, corresponding to block 0BLK0 with a read start address of 0 (relative) and a length (or number of bits) of 9, ..., block 7BLK7 with a start address of 7xL and a length of 9, where L is the length of each frame (see Figure 4A ).

[0089] In an asynchronous LED display, the raw image data may be preprocessed first, and then the processed image data may be stored before display. In some embodiments, the preprocessing may be performed offline. For example, the data transfer unit 320 may read the raw image data from the storage device 310, and perform the following steps: Figures 4A-4B The image data is preprocessed by the bit-based reorganization described in, and this reorganized image data (bit-based) can then be stored internally to the data transfer unit 320 to allow subsequent high-speed data access. In order to facilitate the operation of transferring bit-based image data or called bitCopy, the present teaching discloses an image compression scheme in the form of a bitCopy instruction. This bitCopy instruction controls the data transfer unit 320 in the data transfer operation, and each instruction is encoded with a starting address and the length of each image block to be transferred. For example, BLKi[SAi,Li] corresponds to a general bitCopy instruction, where SAi represents the starting address and Li represents the number of bits to be read. In view of this, the bitCopy instruction BLK2[SA2,L2] is an instruction that instructs the data transfer unit 320 to read the bits of L2 bits starting from address SA2. Based on this representation, in order to traverse the entire image when reading, it can be encoded in a much more compressed form with a series of bitCopy instructions, and when the data transfer unit 320 executes these instructions, the entire bit-based image data will be traversed.

[0090] Figure 4C 1 shows the transformation from raw image data to compressed bitCopy instructions to traverse an image according to an embodiment of the present teachings. As can be seen, starting with an image having a color frame 120, the bits in the image data are reorganized to form bit-based image data 410, and then further converted into a series of bitCopy instructions 440 for traversing the entire image in a bit-based data space. As can be seen, while the original image is organized in a conventional manner to include 3 color frames, Figure 4A The bit-based image depicted in FIG. 1 stores corresponding color bits from different color frames together in the same reorganized frame. The bitCopy instruction is much more compressed than the original image data. Therefore, the data transfer unit 320 reads them quickly. Combined with the design of mapping the address of the bit read to the bus, the reading speed of the data transfer unit 320 is synchronized with the clock cycle of the refresh processor 340.

[0091] Figure 5 An exemplary high-level internal system diagram of a data transfer unit 320 according to an embodiment of the present teachings is depicted. In this illustrated embodiment, the data transfer unit 320 includes an image data partitioning unit 510, an image data preprocessing unit 520, a partition index generator 550, a bitCopy instruction generator 560, and a bitCopy unit 580. Figure 6 is a flow chart of an exemplary process of the data transfer unit 320 according to an embodiment of the present teachings. In some embodiments, there may be a portion of the operation for preprocessing operations and an online portion of the operation, wherein the data transfer unit 320 coordinates with the refresh processor 340 to deliver the LED display in real time. During the preprocessing process, the raw image data may be preprocessed, such as for special effects, converted into bit-based image data, and generate bitCopy instructions. Such preprocessed image data is convenient for online processing. The online portion of the operation is a real-time process, wherein the data transfer unit 320 works in conjunction with the refresh processor 340 to read the entire image by continuously accessing the next bitCopy instruction, reading the next preprocessed bit-based image block according to the bitCopy instruction, and alternately placing the read image block into one of the buffers.

[0092] exist Figure 6, the steps in the left column (steps 600-640) correspond to the preprocessing process, while the steps in the loop on the right column (steps 650-690) correspond to the online process. During the preprocessing stage, the image data partitioning unit 510 first reads and preprocesses the raw image data from the storage device 310 at 600. In some embodiments, the raw image can be partitioned into different raw image blocks at 610, for example, to facilitate repeated partial reading of image data during the online process. Then, at 620, the partitioned image data is processed by the image data preprocessing unit 520 to generate bit-based image blocks (according to Figures 4A-4B ). Such pre-processed bit-based image blocks are stored in the internal SRAM storage device 530. For each bit-based image block stored in the internal SRAM, there is a corresponding starting address to locate the block and a length associated with the bit-based image block. Such information associated with each block can be transmitted to the partition index generator 550 to facilitate the generation of the bitCopy instruction.

[0093] Based on the image data partition information and the starting address and length information associated with each bit-based image block, the partition index generator 550 creates an index for each bit-based image block at 630. Each index for the corresponding bit-based image block may include the ID of the block, the starting address of the block in the storage device 530, and the length or the number of bits occupied in the storage device 530. Based on such indexes, the bitCopy instruction generator 560 generates bitCopy instructions at 640, which can be used in the online process to read the bit-based image block. In some embodiments, each bitCopy instruction can point to a bit-based image block and when it is executed, it enables the bit-based image block to be read out from the storage device 530. In some embodiments, it is also possible to make each bitCopy instruction read more than one bit-based image block. The size of the buffer can be adjusted to accommodate multiple bit-based image blocks. The specific manner in which the image data is encoded via the bitCopy instruction may depend on the application. In the following disclosure, it is assumed that each bitCopy instruction is used to read a bit-based image block. However, this assumption is only for illustration, not limitation, and does not limit the scope of this teaching.

[0094] Although the preprocessing operation is discussed as corresponding to an offline process, i.e., it is completed before the online processing begins, it is also possible that the preprocessing is also performed as part of the online operation, i.e., it is performed in real time. Figures 4A-4BThe content disclosed in the reorganization of the bits in the original image data) and the generation of the bitCopy instruction can also be performed in real time. This mode of operation is also part of the present teaching, but it may require additional coordination and / or clock / handshake management to ensure that the preprocessing and bitCopy instruction generation can keep up with the refresh rate and display speed of the LED screen. The following focuses on the online process involving bitCopy operation, refresh and display. It is only for illustration and not limitation, and should not be interpreted as limiting the scope of the present teaching.

[0095] As discussed herein, the real-time process requires synchronization between the data transfer unit 320 and the refresh processor 340 based on either a handshake protocol or a commonly shared clock. The online process is an iterative process. From the perspective of the data transfer unit 320, in each cycle, the bitCopy unit 580 acts based on each generated bitCopy instruction, maps the start address indicated in each bitCopy instruction onto the bus 540, retrieves the bit-based image block (from the internal SRAM 530) via hardware operations, and places the retrieved bit-based image block in one of the alternating buffers. Figure 6 As shown in , the bitCopy unit 580 first receives the next synchronization signal (handshake signal or clock signal CLK) at 650. Acting on the synchronization signal, the bitCopy unit 580 retrieves the next bitCopy instruction at 660 and maps the starting address and length (from the bitCopy instruction) onto the bus 540. This enables the bitCopy unit 580 to read the bit-based image block from the SRAM 530 via hardware at 670, and then stores the read bit-based image block in one of the two buffers 330 based on the current buffer pointer 570 at 680. Once the bit-based image block is saved in the buffer, the bitCopy unit 580 switches the buffer pointer 570 at 690 so that it now points to the alternate buffer. Once completed, the online process proceeds to step 650 to start the next cycle. This process continues until the entire image is retrieved.

[0096] As discussed herein, during the online process, the refresh processor 340 works in conjunction with the data transfer unit 320 by retrieving bit-based image blocks stored in the alternating buffers 330-1 and 330-2 (see Figure 3) to transform the data in each bit-based image block into signals that can be used to refresh the lights associated with the pixels on the LED screen to achieve the display effect indicated by the image content. Figure 7An exemplary high-level system diagram of a refresh processor 340 according to an embodiment of the present teaching is depicted. In this illustrated exemplary embodiment, the refresh processor 340 interfaces with the buffer 330 via the bus 540 and the LED display panel 770. Internally, the refresh processor 340 includes a connection-based sequencer 700, a special buffer 750, and an LED refresh unit 760. A connection-based sequencer 700 is provided to rearrange the bits in the bit-based image block based on how the unit panel is connected so that the lights associated with the pixels on the LED screen can be properly refreshed in a consistent manner. The special buffer 750 is a list that stores the results from the connection-based sequencer. The input to 750 is provided according to the order of the column signals. The output is arranged in such a way that all columns need to output 1 bit per clock cycle. For example, the order of the bits input from 700 to 750 is: 32 bits of column 0, 32 bits of column 1, 32 bits of column 2, ..., 32 bits of column N. The order of the output of 750 is: bit 31 of all columns, bit 30 of all columns, bit 29 of all columns, ..., bit 0 of all columns. The stored image information can then be used by the LED refresh unit 760 to transform it into a control signal based on the image content (i.e., the color representation of the pixels in the image).

[0097] The connection-based sequencer 700 includes an image bit sequencer 720 that takes bits from a bit-based image block from an alternating buffer (based on a buffer pointer) as input and generates a series of bits appropriately arranged relative to the connection mode. In order to rearrange the bits, the image bit sequencer 720 can sequence the bits, or can execute microcodes retrieved from the storage device 730 for this purpose. The microcode used to sequence the bits can be determined based on information stored in 740 representing the specific connection mode of the current LED display screen. This information is used to select the microcode to be used to sequence the image bits. In some embodiments, the storage device 740 can store different connection profiles. The storage device 730 can store different corresponding microcodes, each of which can be provided to support some connection profiles. In operation, information can be set in the storage device 740 to indicate the current connection mode, and this information can be used to activate a corresponding set of microcodes to appropriately process the image bits from the buffer in a manner consistent with the connection mode. Figures 8A-15B Various example ways of reordering bits in different situations are shown.

[0098] Fig. 8ATwo different rows of single color pixels driven individually by different column signals on an LED panel according to an embodiment of the present teaching are shown. There are two rows of 8 pixels, row 810 has pixels 00-07 and row 820 has pixels 10-17. In this configuration, each row is driven by a separate column signal. That is, column signal 0 830 drives pixels 00-07 in the first row 810 on the LED screen and column signal 1 840 drives pixels 10-17 in the second row 820 on the same display screen. Figure 8B A different representation of the embodiment in which each column signal is driven through each row by a separate column driver according to an embodiment of the present teachings is shown. In this representation, although column driver 850 sends column signal 0 830 to pixels 00-07 via separate lines, such lines may represent pins of a chip and they may be connected internally to the driver so the effect is the same as Fig. 8A 8, i.e., column signal 0 830 flows in a serial manner from pixel 00 to 01 to 02, ..., to 07. Similar can be said about how column driver 860 delivers column signal 1 840 to each of pixels 10, 11, 12, ..., 17. When each row is driven by a separate column signal, such as Fig. 8A and 8B As shown in , the bits read from the alternating buffer do not need to be reordered.

[0099] In most LED display operations, column signals drive through pixels across multiple rows. In order to deliver column signals to pixels across different rows, the column signals need to traverse the pixels in an LED display screen formed by multiple LED unit panels in a manner consistent with how the pixels within each unit panel are linked and how the LED unit panels are connected to form a larger LED display screen. Depending on the connection mode, the column signals will traverse the pixels in different ways. Therefore, the bits of the image data need to be sequenced accordingly to accommodate the connection mode.

[0100] Fig. 9A Column signals for driving two rows of pixels with a single color via a serpentine I connection in accordance with an embodiment of the present teachings are shown. As can be seen, there are two exemplary rows of pixels 910 (pixels 00-03) and 920 (pixels 10-13) and all pixels are of a single color. Column signal 930 is used to drive pixels in two rows in a connection pattern known as serpentine I, with serpentine I column signal 930 starting from the top row and flowing from the first pixel 00 in the first row 910 to the first pixel 10 in the second row 920, then back to the first row to flow to the second pixel 01, then to the second pixel 11 in the second row 11, back to the first row again to drive the third pixel 02, down back to the third pixel 12 in the second row 920, ..., and so on. Fig. 9B1 shows different representations of a serpentine I connection in driving a column signal through two rows of pixels of a single color according to an embodiment of the present teachings. Column signal 930 is driven to the pixels by column driver 940. As can be seen, there are different links from column driver 940 to different pixels. From the leftmost link to the rightmost link of the column driver, the order of traversing the pixels is 00, 10, 01, 11, 02, 12, ... and 13, which is the same as Fig. 9A Exactly the same as presented in .

[0101] To facilitate this traversal order, it may be necessary to reorder the bits in the bit-based image blocks read from the interleaving buffer 330. Fig. 9C and 9D is described in. Fig. 9C The contents of the registers when two rows of bit-based image data of a single color are loaded according to an embodiment of the present teachings are shown. As shown, the first row is P0 950 and the second row is P1 960. In this example, the first row has 32 bits, for example starting from A31 as the most significant bit to A0 as the least significant bit. The second row also has 32 bits, starting from B31 as the most significant bit to B0 as the least significant bit. If the connection pattern is Snake I, then along the traversal path, the bit sequence will be A31, B31, A30, B30, A29, B29,..., A1, B1, A0 and B0. This is derived by starting from the first bit in the first row, moving down to the first bit in the second row, back to the second bit in the first row, to the second bit in the second row,... Therefore, in order to satisfy the traversal path caused by the Snake I connection pattern, the bits in 950 and 960 need to be reordered to generate a reordered bit stream, such as Fig.9D , which shows the result of sequencing the bits in 950 and 960 to facilitate a snake-type I connection according to an embodiment of the present teachings.

[0102] As can be seen below, when the connection mode changes, the bits in the same registers 950 and 960 need to be ordered differently to accommodate the connection mode. Fig. 10A A connection pattern called Snake II according to an embodiment of the present teaching is shown. With this connection pattern, the column signal 1030 traverses the pixels starting from the first pixel 10 in the second row 1020 to the first pixel 00 in the first row 1010, back to the second pixel 11 in the second row 1020 and the second pixel 01 in the first row 1010, then back to the second row 1020 again to the third pixel 12, and back to the third pixel 02 in the first row 1010, ... Fig. 10BA different representation of a column driver 1040 for driving a column signal 1030 via a serpentine II connection is shown in accordance with an embodiment of the present teachings. As shown, for two rows 1010 and 1020, the column driver 1040 is linked to different pixels in different rows. Starting from the leftmost link of the column driver 1040, it delivers the column signal 1030 to pixel 10 in the second row 1020, pixel 00 in the first row 1010, pixel 11 in the second row 1020, pixel 01 in the first row 1010, and so on, with the same Fig. 10A The same traversal order as shown in . When the connection mode changes, the bits are traversed in a different order. To accommodate this, the image bits from the bit-based image blocks also need to be ordered differently.

[0103] Fig. 10C The embodiment of the present teaching shows that when the wiring connection mode is snake type II, based on Fig. 9C The image bits are rearranged according to the image content shown in . Consistent with the traversal order according to the snake-type II connection, Fig. 10C The order of the bits shown in is now B31, A31, B30, A30, B29, A29, ..., B1, A1, B0 and A0. This result can be obtained by rearranging the bits loaded from SRAM 330 in different ways. One is the sequencing performed by the image bit sequencer 720. That is, for each connection type, there are different sequencing operations to rearrange the bits in a manner suitable for the connection type. Another way is to execute a suitable set of microcodes corresponding to the connection type. Still another different way is to combine sequencing and microcode. For example, an image bit sequencer 720 can be provided to sequence the image bits according to a serpentine I connection. If the actual connection type is serpentine II, then microcode can be executed based on the result of the sequencing in the serpentine I connection to rearrange the bits in the serpentine I arrangement to achieve other connection types. As can be seen, in order to convert the serpentine I bit arrangement into a serpentine II arrangement, a simple operation of flipping the order of each pair of bits will achieve the conversion.

[0104] Fig.11A A connection pattern called Serpentine III according to an embodiment of the present teaching is shown. As shown, there are two rows of pixels 1110 and 1120, both driven by the same column signal 1130, which traverses a path through the pixels in the following order: the first pixel 00 in the first row 1110, to the first pixel in the second row 1120, to the second pixel 11 in the same second row 1120, back to the second pixel 01 in the first row 1110, to the third pixel 02 in the same first row 1110, to the third pixel 12 in the second row 1120, to the fourth pixel 13 in the same second row 1120, ..., until all pixels in both rows are traversed in this connection pattern. Fig. 11BDifferent representations of serpentine III connections are shown, with the column driver driving through pixels in different rows in this connection pattern, according to an embodiment of the present teachings. The links from the column driver starting with the leftmost link send column signal 1130 to pixel 00 in the first row 1110, pixel 10 in the second row 1120, pixel 11 in the same second row 1120, then to the second pixel 01 in the first row 1110, then to the third pixel 02 in the same first row 1110, ..., to communicate with the pixel 00 in the first row 1110. Fig.11A The same way as shown in .

[0105] Similarly, for the Snake III connection mode, the bits in the bit-based image blocks from the alternating buffer need to be ordered according to this connection mode as discussed herein. Fig. 11C 9 shows the result of ordering the bits in registers 950 and 960 to facilitate a snake-type III connection according to an embodiment of the present teachings. Fig. 9C As shown in , the original sequence of bits in registers 950 and 960 is now reordered to have the order of A31, B31, B30, A30, A29, B29, B28, A28, A27, ..., A3, B3, B2, A2, A1, B1, B0, A0. As discussed herein, instead of using the image bit sequencer 720 to sequence the bits according to the Serpentine III connection, another alternative implementation is to have the image bit sequencer 720 have a fixed function to sequence the bits according to Serpentine I, and then execute appropriate microcode to convert the bits in the Serpentine I arrangement into a new arrangement suitable for Serpentine III connection. Another possible implementation is to have the microcode rearrange the bits loaded from the buffer 330 into any desired order according to the actual connection type of the LED display panel.

[0106] The above examples are based on pixels of a single color, i.e., one bit per pixel. In most LED display applications, the pixels are colored, some partially colored and some fully colored. As discussed herein, when the pixels are colored, each pixel has different color components and therefore has more than one bit. For example, a picture can be two-color, with a red and a green component. The picture can also be fully colored, so that each pixel has all three color components, i.e., red, green, and blue. Each color component can have its own intensity, represented by a different gray level, which is represented by a bit. Depending on the resolution, the number of bits used to represent each color component can be different. It can be a single bit per color, representing two gray levels, for example, on and off. There can also be more bits, for example, 8 bits in each color component representing 256 intensity levels. In general, each color component is represented as a different image frame, so that a full-color image has three image frames, as shown in FIG. 1E . As discussed herein, according to the present teachings, when there are multiple bits representing each color component, the image data is reorganized so that the corresponding color bits in different color components are stored together, such as Figure 4A and 4B This is to facilitate the teaching of Figure 4C The compression scheme shown in .

[0107] When more than a single color is present, the connection pattern is more complex and how the image bits are ordered is correspondingly different. Fig. 12A A two-color pixel row is shown according to an embodiment of the present teachings, where each color of light is driven individually by a separate column signal. As shown, each pixel has two colors of light, red and green. For example, the first pixel on the left has red bit A31 and green bit A30, the second pixel has red bit A29 and green bit A28, and so on. In this illustration, all red lights are driven by column signal 1230 and all green lights are driven by a different column signal 1240. Fig. 12BDifferent representations of the same connection pattern of separate column drivers 1250 and 1260 driving two corresponding color components of a pixel according to an embodiment of the present teaching are shown. As can be seen, column driver 1250 has various links for delivering column signal 1230 to the red lights of a row of pixels, starting with the leftmost link to send the signal to A31, A29, A27, A25... . ...

[0108] Fig.13A 1 shows how the column signals according to an embodiment of the present teachings are used to drive two color components of a pixel via a serpentine I connection. In this illustration, the same pixel row of dual color has two corresponding color components, one for the red row of pixels and the other for the green row of pixels. Fig. 12A different, Fig.13A A single column signal 1310 in is used to drive both the red and green lights of the pixel. Specifically, the column signal 1310 traverses all the red and green lights of the pixels in 1220 in a serpentine I connection pattern, i.e., first to A31 (red), then to A30 (green), A29 (red), A28 (green), A27 (red), A26 (green), ..., A17 (red) and A16 (green). Fig. 13B A representation of using a column driver 1320 via a serpentine I connection to drive a column signal 1310 through two color lights of all pixels in 1220 is shown in accordance with an embodiment of the present teachings. As can be seen, the various links from the column driver 1320 send the column signal 1310 to all lights in the order of A31, A30, A29, A28, ... starting from the leftmost link, traversing both the red and green lights of all pixels in the row.

[0109] In order to facilitate driving two-color pixels via a serpentine I connection pattern, the bits in the bit-based image blocks need to be reordered. As discussed herein, for an image with two colors, the bit-based image blocks retrieved from the interleaving buffer have corresponding bits from the two colors stored together. For example, if each color is represented using 8 bits, then the image will have 8 frames. The first frame can store the least significant bit of red and green for each pixel. The second frame can store the second least significant bit of red and green for each pixel, ... and the last frame can store the most significant bit of red and green for each pixel. Fig. 13CThe contents of a register with two-color pixels loaded from the interleaving buffer 330 according to an embodiment of the present teachings are shown. As discussed herein, A31 and A30 are the red and green bits from the red and green components of the first pixel, respectively. A29 and A28 are the red bits and the corresponding bits of green from the second pixel, respectively, and so on.

[0110] To promote the snake-type I connection mode, such as Fig. 13C The bits shown in need to be reordered. Fig.13D The embodiment of the present teachings is shown using a two-color pixel pair. Fig. 13C The bits in the register shown in are reordered to facilitate the result of the serpentine I connection. The reordered bits in the top row are now ordered as A31, A29, A27, A25, ..., and the reordered bits in the second row are now A30, A28, A26, A24, .... Therefore, when the column signal is traversed in the serpentine I connection mode, the traversal order of A31, A30, A29, A28, ... will be achieved, which is consistent with Fig.13A If the connection pattern for the two-color pixel is snake II, then the Fig.13A The column signals of the two-color components of all pixels in the array will be traversed in the order of A30, A31, A28, A29, ... (not shown). In order to adapt to the snake II connection mode for two-color pixels, the Fig. 13C The color bits in the first register are arranged to generate bits in the order A30, A28, A26, ... in the first register, and bits in the second row are generated in the new order A31, A29, A27, ..., so when the column signal traverses in the snake II connection, it will deliver the signal in the order A30, A31, A28, A29 ... (not shown). If the connection mode is snake III, the order of the rearranged bits will be A31, A30, A28, A29, A27, A26, A24, A25 ... (now shown).

[0111] As discussed herein, when it is necessary to rearrange the image bits loaded from the buffer 330 to accommodate the connection type of the LED display, there are different ways to achieve the rearrangement appropriate for the connection type. One is the sequencing performed by the image bit sequencer 720, such as Fig.9D and Fig.13D . Another approach is to use the image bit sequencer 720 and microcode in combination. An image bit sequencer 720 may be provided to sequence the image bits according to a serpentine I connection. If the actual connection type is serpentine II or III, then microcode may be executed to rearrange the bits in the serpentine I arrangement to convert to the bit order for the other connection type. For example, to convert from a serpentine I bit arrangement to a serpentine II arrangement, a simple operation of flipping the order of each pair of bits will accomplish the conversion.

[0112] Fig.14A A single row of full color pixels according to an embodiment of the present teaching is shown, where each of the three color components is driven by a separate column signal in a direct connection mode. As discussed herein, when the traversal covers a single color and has direct connections in each color component, it does not require sequencing of the bits in the image block based on the bit. Fig. 14B A serpentine I connection between different rows of pixels of each color according to an embodiment of the present teaching is shown. As shown, there are three column signals, each of which is used to drive a different color, but spans two rows of pixels according to a serpentine I traversal pattern. As marked therein, the pixel in the first row is 1410, and the corresponding pixel in the second row is 1420. Each of these pixels is stored with 3 color bits (red, green, and blue) and arranged together. For example, the first pixel of the first row has a red bit A31, a green bit A30, and a blue bit A29; the first pixel of the second row (stored with the first pixel of the first row) has a red bit A28, a green bit A27, and a blue bit A26. In addition, the second pixel of the first row has bits A25 (red), A24 (green), and A23 (blue); the second pixel of the second row has bits A22 (red), A21 (green), and A20 (blue). The column signal 1430-1 for driving the red bit of the pixel in the serpentine I connection (across rows) is driven to a red light by a column driver 1430-2. Column signal 1440-1 for driving the green bit of pixels across rows in a serpentine I connection is driven to a green light by column driver 1440-2. Column signal 1450-1 for driving the blue bit of pixels across rows in a serpentine I connection is driven to a blue light by column driver 1450-2.

[0113] Fig. 14C The contents of a register according to an embodiment of the present teaching are shown, wherein pixels from two rows are stored together in full color. As can be seen, the first three bits A31, A30, and A29 correspond to the red, green, and blue bits of the first pixel 1410 from the first row, and the next three bits A28, A27, and A26 correspond to the red, green, and blue bits of the first pixel from the second row, and together correspond to 1420. Fig.14DThe result of sequencing these color bits of a pixel to facilitate driving each color component separately on different rows in a serpentine I connection pattern according to an embodiment of the present teachings is shown. As can be seen, through the sequencing operation, the red, green, and blue bits of different pixels are now arranged in a manner so that the bits of each color are driven across different rows in a manner consistent with the serpentine I connection pattern. For example, in red, column signal 1430-1 passes through A31 (red from the first pixel of the first row), A28 (red from the first pixel of the second row), A25 (red from the second pixel of the first row), A22 (red from the second pixel of the second row), A19 (red from the third pixel of the first row), A16 (red from the third pixel of the second row), ... and so on. Similarly, in green, the column signal 1440-1 passes through A30 (green from the first pixel of the first row), A27 (green from the first pixel of the second row), A24 (green from the second pixel of the first row), A21 (green from the second pixel of the second row), A18 (green from the third pixel of the first row), A15 (green from the third pixel of the second row), ... etc. Regarding blue, the column signal 1450-1 is driven through A29 (blue from the first pixel of the first row), A26 (blue from the first pixel of the second row), A23 (blue from the second pixel of the first row), A20 (blue from the second pixel of the second row), A17 (blue from the third pixel of the first row), A14 (blue from the third pixel of the second row), ... and so on.

[0114] Fig.15A A representation of each color component of a full-color pixel driven individually in a serpentine II connection according to an embodiment of the present teaching is shown. As shown, the data is organized in the same way as Fig. 14B is the same as shown in , except that the connection type is serpentine II, where instead of starting with pixels in the first row, it starts with pixels in the second row and then zigzags between the first and second rows. Fig. 15B The embodiment according to the present teaching is shown as follows Fig. 14CThe bits in the registers shown in (pixels are full color) are sequenced to facilitate the results of driving the color bits in a serpentine II connection. As discussed herein, this can be achieved via different means. As previously shown, one is the sequencing performed via an image bit sequencer 720. Another way is to use the image bit sequencer 720 and microcode in combination. An image bit sequencer 720 can be provided to sequence the image bits according to a serpentine I connection. If the actual connection type is serpentine II or III, then microcode can be executed to rearrange the bits in the serpentine I arrangement to convert to the bit order for the other connection type. As shown above, in order to convert from a serpentine I bit arrangement to a serpentine II arrangement, a simple operation of flipping the order of each pair of bits will achieve the conversion.

[0115] The above examples show how to sequence bits in bit-based image data to accommodate different connection types used to link different pixels in an LED display. Figure 7 As shown in , the sequencing operation is performed by the image bit sequencer 720. As discussed herein, depending on the connection of each LED display screen, information related to the connection type can be configured in the connection profile 740 and available to the image bit sequencer 720. As discussed herein, based on the information about the connection type, the image bit sequencer 720 can then activate the appropriate microcode stored in 730 to perform the bit sequencing. Therefore, the refresh processor 340 is able to adapt to different LED display screens that connect the LED unit panels in different ways. The reordered image bits are then sent to a specific buffer 750, which then sends such image content to the LED refresh unit 760 in a first-in, first-out order. Based on such appropriately sequenced image bits, the LED refresh unit 760 transforms the image content into different control signals for controlling how the lights associated with the pixels in the LED panel 770 are refreshed in order to deliver the visual effects of the image content.

[0116] Fig.16 330-1 and 330-2. The refresh processor 340 is a flow chart of an exemplary process of the refresh processor 340 according to an embodiment of the present teachings. Similar to the data transfer unit 320, the refresh processor 340 can also operate in two different phases. In the first phase, the refresh processor 340 will be configured to handle an LED display screen with a certain connection type. This is to deploy microcode suitable for the specific connection type at hand. The second phase is the online phase, and the image content is displayed on the LED display screen based on the bit-based image data stored in the alternating buffers 330-1 and 330-2.

[0117] exist Fig.16In the embodiment of the present invention, steps 1600 and 1610 are for phase one, wherein information about the connection type stored in 740 is accessed at 1600, and the appropriate microcode for the specified connection type is loaded at 1610. The remaining steps form a loop to traverse the entire image for displaying the image content on the LED screen. As discussed herein, during the online phase of displaying the image content on the LED display screen, the refresh processor 340 synchronizes its operation with the data transfer unit 320 based on the commonly shared clock signal CLK. In this process, after receiving the next clock signal at 1620, the image bit sequencer 720 accesses the buffer pointer at 1630 to retrieve the next bit-based image block from one of the alternating buffers pointed to by the buffer pointer at 1640. The image bit sequencer 720 then executes the loaded microcode appropriate for the current connection type at 1650 to sequence the image bits in the loaded bit-based image block. The reordered image bits are then stored to a particular buffer 750 at 1660, from which the LED refresh unit 760 can access the reordered image bits at 1670 to generate various refresh control signals based on the image content at 1680. The LED refresh unit 760 then uses such generated control signals to refresh the lights on the LED panel at 1690.

[0118] As disclosed herein, the LED display framework according to the present teaching organizes the bits in the image in a manner that maximizes processing speed, minimizes required memory resources, and can adapt to LED display screens with different connection types. These features of the present invention effectively solve and make up for the shortcomings of the solutions of traditional LED displays.

[0119] Fig.17 1700 is an illustrative diagram of an exemplary computing device architecture that can be used to implement a dedicated system for implementing the present teaching according to various embodiments. This dedicated system in combination with the present teaching has a functional block diagram description of a hardware platform, which includes a user interface element. The computer can be a general-purpose computer or a special-purpose computer. Both can be used to implement the dedicated system of the present teaching. This computer 1700 can be used to implement any component of the various components, as described herein. For example, the data transfer unit 320 and / or the refresh processor 340 can be implemented on a computer such as computer 1700 via its hardware, software program, firmware or a combination thereof. Although only one such computer is shown for convenience, the computer functions associated with the LED display system described herein can be implemented in a distributed manner on multiple similar platforms to distribute the processing load.

[0120] For example, the computer 1700 includes a COM port 1750, which is connected to a network connected thereto to facilitate data communication. The computer 1700 also includes a central processing unit (CPU) 1720 in the form of one or more processors for executing program instructions. The exemplary computer platform includes an internal communication bus 1710, program storage devices and data storage devices in different forms (e.g., disks 1770, read-only memory (ROM) 1730 or random access memory (RAM) 1740), various data files for processing and / or transmission by the computer 1700, and program instructions that may be executed by the CPU 1720. The computer 1700 also includes an I / O component 1760, thereby supporting input / output flows between the computer and other components therein (such as user interface elements 1780). The computer 1700 can also receive programming and data via network communications.

[0121] Thus, as outlined above, aspects of the methods of dialog management and / or other processes may be implemented in programming. The programmatic aspects of the technology may be considered a "product" or "article of manufacture," typically in the form of executable code and / or associated data carried or implemented in a machine-readable medium. Tangible, non-transitory "storage device" type media include any or all memory or other storage devices for computers, processors, etc., or their associated modules, such as various semiconductor memories, tape drives, disk drives, etc., which may provide storage for software programming at any time.

[0122] All or part of the software may sometimes be transmitted over a network such as the Internet or various other telecommunication networks. For example, such communication may enable software to be loaded from one computer or processor to another computer or processor, for example, with respect to conversation management. Thus, another type of medium that may carry software elements includes optical, electrical, and electromagnetic waves, such as across physical interfaces between local devices, through wired and optical landline networks, and through various air links. Physical elements that carry such waves (such as wired or wireless links, optical links, etc.) may also be considered as media that carry software. As used herein, unless limited to tangible "storage" media, terms such as computer or machine "readable media" refer to any medium that participates in providing instructions to a processor for execution.

[0123] Therefore, machine-readable media can take a variety of forms, including but not limited to tangible storage media, carrier media, or physical transmission media. Non-volatile storage media include, for example, optical or magnetic disks, such as any storage device in (one or more) any computer, etc., which can be used to implement the system or any component thereof, as shown in the figure. Volatile storage media include dynamic memory, such as the main memory of such a computer platform. Tangible transmission media include coaxial cables; copper wires and optical fibers, including wires that form buses within a computer system. Carrier transmission media can take the form of electrical or electromagnetic signals, or sound or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Therefore, common forms of computer-readable media include, for example: floppy disks, floppy disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, DVDs or DVD-ROMs, any other optical media, punched card tapes, any other physical storage media with hole patterns, RAMs, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cassettes, carriers that transport data or instructions, cables or links that transport such carriers, or any other media from which a computer can read programming code and / or data. Many of these forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to a physical processor for execution.

[0124] Those skilled in the art will recognize that the present teachings are susceptible to various modifications and / or enhancements. For example, while the various component embodiments described above may be implemented in a hardware device, it may also be implemented as a pure software solution—for example, installed on an existing server. Furthermore, the fraudulent network detection technology as disclosed herein may be implemented as firmware, a firmware / software combination, a firmware / hardware combination, or a hardware / firmware / software combination.

[0125] Although the above has described what is considered to constitute the present teaching and / or other examples, it should be understood that various modifications may be made thereto and the subject matter disclosed herein may be implemented in various forms and examples, and that the teaching may be applied to many applications, only some of which are described herein. The following claims are intended to claim any and all applications, modifications, and variations that fall within the true scope of the present teaching.

Claims

1. A method for refreshing an LED display implemented on at least one machine including at least one processor, a memory, and a communication platform capable of connecting to a network, the method comprising: receiving a first handshake signal from a handshake manager, the first handshake signal indicating that a bit-based image block is stored in one of the buffers of the alternating buffer pair; receiving a signal from a clock signal generator that signals a timing for refreshing the LED display; as well as In response to this signal: retrieving a bit-based image block from one of the alternating buffer pairs pointed to by the read buffer pointer; When the bit-based image block is retrieved, sending a second handshake signal to the data transfer unit, the second handshake signal indicating that the bit-based image block has been retrieved, so that the data transfer unit loads a subsequent bit-based image block into the one buffer of the alternating buffer pair; switching the read buffer pointer to point to another buffer in the alternating buffer pair; identifying a connection pattern in which lamps of the LED display are connected, the connection pattern comprising a serpentine connection, wherein a column driver sends a signal to each individual pixel according to the connection pattern via the serpentine connection; identifying a specific microcode from a plurality of stored microcodes based on a connection mode for connecting the lights of the LED display, wherein each set of microcodes in the plurality of stored microcodes corresponds to a different connection mode in the plurality of connection modes for connecting the lights of the LED display; Before sending the bit-based image block to the LED display, loading the specific microcode for processing, the specific microcode being selected according to the connection mode; Sequencing bits in the bit-based image block by executing the specific microcode to generate sequenced image bits for the bit-based image block; storing the sequenced image bits in a specific buffer located between the connection-based sequencer and the LED display to obtain stored sequenced image bits; generating control signals for refreshing lights of an LED display based on the stored sequenced image bits; and The lights of the LED display are refreshed based on the control signal.

2. The method of claim 1, wherein the bit-based image block comprises a plurality of pixels, each pixel having one or more color bits, wherein each of the one or more color bits is a corresponding bit of a representation of a respective color. The method of claim 1 , wherein the signal is one of a handshake signal or a clock signal.

4. The method of claim 1, wherein the connection mode comprises at least one of the following: A first mode in which a panel of LED units forming an LED display is connected; and The column drivers in the LED unit panel are connected in a second mode.

5. A machine-readable and non-transitory medium having recorded thereon information for refreshing an LED display, wherein the information, once read by a machine, causes the machine to execute: receiving a first handshake signal indicating that a bit-based image block is stored in one of the alternating buffer pairs; receiving a clock signal that signals a timing for refreshing an LED display; as well as In response to the clock signal, retrieving the bit-based image block from one of the alternating buffer pairs pointed to by a read buffer pointer; When the bit-based image block is retrieved, sending a second handshake signal to the data transfer unit, the second handshake signal indicating that the bit-based image block has been retrieved, so that the data transfer unit loads a subsequent bit-based image block into the one buffer of the alternating buffer pair; switching the read buffer pointer to point to another buffer in the alternating buffer pair; identifying a connection pattern in which lamps of the LED display are connected, the connection pattern comprising a serpentine connection, wherein a column driver sends a signal to each individual pixel according to the connection pattern via the serpentine connection; identifying a specific microcode from a plurality of stored microcodes based on a connection mode for connecting the lights of the LED display, wherein each set of microcodes in the plurality of stored microcodes corresponds to a different connection mode in the plurality of connection modes for connecting the lights of the LED display; Before sending the bit-based image block to the LED display, loading the specific microcode for processing, the specific microcode being selected according to the connection mode; Sequencing bits in the bit-based image block by executing the specific microcode to generate sequenced image bits for the bit-based image block; storing the sequenced image bits in a specific buffer located between the connection-based sequencer and the LED display to obtain stored sequenced image bits; generating control signals for refreshing lights of an LED display based on the stored sequenced image bits; and The lights of the LED display are refreshed based on the control signal.

6. The medium of claim 5, wherein the bit-based image block comprises a plurality of pixels, each pixel having one or more color bits, wherein each color bit of the one or more color bits is a corresponding bit of a representation of a respective color.

7. The medium of claim 5, wherein the connection mode comprises at least one of the following: A first mode in which a panel of LED units forming an LED display is connected; and The column drivers in the LED unit panel are connected in a second mode.

8. A system for refreshing an LED display, comprising: Image bit sequencer, configured to: receiving a first handshake signal from a handshake manager, the first handshake signal indicating that a bit-based image block is stored in one of the buffers of the alternating buffer pair; receiving a clock signal that signals a timing for refreshing an LED display; as well as In response to this signal: retrieving a bit-based image block from said one of the alternating buffer pairs pointed to by the read buffer pointer, When the bit-based image block is retrieved, sending a second handshake signal to the data transfer unit, the second handshake signal indicating that the bit-based image block has been retrieved, so that the data transfer unit loads a subsequent bit-based image block into the one buffer of the alternating buffer pair, switching the read buffer pointer to point to the other buffer in the alternating buffer pair, and identifying a connection pattern in which lamps of the LED display are connected, the connection pattern comprising a serpentine connection, wherein a column driver sends a signal to each individual pixel according to the connection pattern via the serpentine connection; identifying a specific microcode from a plurality of stored microcodes based on a connection mode for connecting the lights of the LED display, wherein each set of microcodes in the plurality of stored microcodes corresponds to a different connection mode in the plurality of connection modes for connecting the lights of the LED display; Before sending the bit-based image block to the LED display, loading the specific microcode for processing, the specific microcode being selected according to the connection mode; Sequencing bits in the bit-based image block by executing the specific microcode to generate sequenced image bits for the bit-based image block; storing the sequenced image bits in a specific buffer located between the connection-based sequencer and the LED display to obtain stored sequenced image bits; and The LED refresh unit is configured to: generating control signals for refreshing lights of the LED display based on the stored sequenced image bits, and The lights of the LED display are refreshed based on the control signal.

9. The system of claim 8, wherein the bit-based image block comprises a plurality of pixels, each pixel having one or more color bits, wherein each of the one or more bits is a corresponding bit of a representation of a respective color.

10. The system of claim 8, wherein the connection mode comprises at least one of the following: A first mode in which a panel of LED units forming an LED display is connected; and The column drivers in the LED unit panel are connected in a second mode.

Images