Memory device and method of operating memory

Abstract

The present disclosure includes apparatuses, methods, and systems for threshold voltage shift cancellation of memory cell programming. Embodiments include a memory having a plurality of memory cells and circuitry configured to program a memory cell of the plurality of memory cells into one of two possible data states by: applying a first voltage pulse to the memory cell, where the first voltage pulse has a first polarity and a first magnitude; and applying a second voltage pulse to the memory cell, where the second voltage pulse has a second polarity opposite the first polarity and a second magnitude that can be greater than the first magnitude.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to memory cell programming that eliminates threshold voltage drift. Background Technology

[0002] Memory devices are typically provided in computers or other electronic devices as internal semiconductor integrated circuits and / or external removable devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

[0003] Memory devices can be used as volatile and non-volatile memory in a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, Memory Sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players and video players such as MP3 players, and other electronic devices.

[0004] A variable resistance memory device may include a variable resistance memory cell that can store data based on the resistance state of a memory element (e.g., a memory element with variable resistance). Thus, the variable resistance memory cell can be programmed to store data corresponding to a target data state by changing the resistance level of the memory element. The variable resistance memory cell can be programmed to a target data state (e.g., corresponding to a specific resistance state) by applying an electric field or energy source (e.g., positive or negative electrical pulses (e.g., positive or negative voltage or current pulses)) to the cell (e.g., to the memory element of the cell) for a specific duration. The state of the variable resistance memory cell can be determined by sensing the current through the cell in response to an applied query voltage or by sensing the voltage through the cell in response to an applied query current. The sensed current or voltage, varying based on the resistance level of the cell, can indicate the state of the cell.

[0005] Various memory arrays can be organized into a crosspoint architecture, where memory cells (e.g., variable-resistance cells) are located at the intersection of a first signal line and a second signal line for accessing the cell (e.g., the intersection of a word line and a bit line). Some variable-resistance memory cells may include a selection element (e.g., a diode, transistor, or other switching device) connected in series with a storage element (e.g., a phase-change material, a metal oxide material, and / or another material programmable to different resistance levels). Some variable-resistance memory cells, which may be referred to as self-selecting memory cells, may include a single material that can serve as both the selection element and the storage element of the memory cell. Attached Figure Description

[0006] Figure 1 This is a three-dimensional view of an example of a memory array according to an embodiment of the present disclosure.

[0007] Figure 2A This describes the threshold voltage distribution associated with the memory state of a memory cell according to embodiments of the present disclosure.

[0008] Figure 2B The embodiments corresponding to this disclosure Figure 2A An example of current versus voltage curves for memory states.

[0009] Figure 2C The embodiments corresponding to this disclosure Figure 2A Another example of current versus voltage curves for a memory state.

[0010] Figure 3A Examples of voltage pulses applied to a memory cell and examples of current flowing through a memory cell according to embodiments of the present disclosure are described.

[0011] Figure 3B Additional examples of voltage pulses applied to memory cells and additional examples of current flowing through said cells according to embodiments of the present disclosure are described.

[0012] Figure 4 This is a block diagram illustration of an example device according to an embodiment of the present disclosure. Detailed Implementation

[0013] This disclosure includes apparatus, methods, and systems for programming memory cells to eliminate threshold voltage drift. Embodiments include a memory having a plurality of memory cells and a circuit system configured to program a memory cell among the plurality of memory cells to one of two possible data states by: applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude; and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity opposite to the first polarity and a second magnitude greater than the first magnitude.

[0014] Compared to prior art memory devices, embodiments of this disclosure can provide benefits such as increased density, reduced cost, increased performance, reduced power consumption, and / or faster and / or more complex operation. For example, after programming a variable-resistance memory cell (e.g., a self-selecting memory cell), the cell's threshold voltage may drift (e.g., change) to a higher value over time. In prior methods, this threshold voltage drift could result in a higher voltage pulse being required during subsequent programming operations to program the memory cell to its target data state, which could consequently increase the amount of power used by the memory device during programming operations.

[0015] However, the memory cell programming embodiments of this disclosure can eliminate such threshold voltage drift by adjusting (e.g., returning) the threshold voltage of the cell to a threshold voltage to which the cell was previously (e.g., initially) programmed before applying a voltage pulse for programming the memory cell to its target data state. With the threshold voltage drift eliminated, the magnitude of the voltage pulse subsequently used to program the cell to its target data state can be lower (e.g., about 0.6 volts lower) than the magnitude of the voltage pulse used to program the cell in previous methods (e.g., when the threshold voltage drift was not eliminated). Therefore, the memory cell programming embodiments of this disclosure can use less power than previous programming methods.

[0016] Furthermore, during programming of a variable-resistance (e.g., self-selected) memory cell, the cell can be selected by applying a voltage to (e.g., selecting) two intersecting signal lines (e.g., intersecting word lines and bit lines) where the memory cell is located in the array. However, due to the higher magnitude voltage pulses used in previous programming methods, other (e.g., unselected) memory cells that are not programmed but coupled to (e.g., on) these two signal lines may experience significant leakage when this voltage is applied to the lines, which could lead to these cells being unintentionally (e.g., incorrectly) selected during previous programming methods.

[0017] To prevent such erroneous selection of unselected memory cells during previous programming methods, an additional bias voltage (e.g., a C-cell bias voltage) can be applied to other (e.g., unselected) word lines of the array when programming the selected cell. However, applying this additional bias voltage may further increase the amount of power used by the memory device during programming operations. Furthermore, applying this additional bias voltage may involve (e.g., requiring) performing snap-back detection on the memory cells (e.g., to identify the word lines for which this additional bias voltage will be applied), which may further increase the amount of power used by the memory device during programming operations, and increase the complexity of the circuitry used by the memory device during programming operations.

[0018] However, because the memory cell programming embodiments of this disclosure eliminate threshold voltage drift and thus use a lower magnitude voltage pulse to program selected memory cells to their target data state than previous methods, it is not necessary to prevent erroneous selection of unselected memory cells during the programming embodiments of this disclosure. Therefore, during the programming embodiments of this disclosure, it is not necessary to apply any additional bias voltage to the unselected word lines of the array, and it is not necessary to perform rushback detection (e.g., no rushback detection circuitry is required). Eliminating additional bias voltage and rushback detection further reduces the amount of power used by the programming embodiments of this disclosure compared to previous methods, and reduces the complexity of the circuitry used by the programming embodiments of this disclosure compared to previous methods.

[0019] As used herein, "a" or "a plurality of" can refer to one or more of something, and "a plurality of" can refer to two or more of such things. For example, a memory device can refer to one or more memory devices, and a plurality of memory devices can refer to two or more memory devices. Additionally, as used herein, particularly with respect to reference numerals in the figures, the designations "N" and "M" indicate that several specific features thus specified may be included in several embodiments of this disclosure.

[0020] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify the elements or components in the figure. Similar elements or components can be identified between different figures by using similar numbers.

[0021] Figure 1This is a three-dimensional view of an example of a memory array 100 (e.g., a cross-point memory array) according to embodiments of the present disclosure. The memory array 100 may include a plurality of first signal lines (e.g., first access lines) that intersect each other (e.g., intersect in different planes), referred to as word lines 110-0 to 110-N, and a plurality of second signal lines (e.g., second access lines) that are referred to as bit lines 120-0 to 120-M. For example, each of the word lines 110-0 to 110-N may intersect with the bit lines 120-0 to 120-M. Memory cells 125 may be located between the bit lines and word lines (e.g., at each bit line / word line intersection).

[0022] For example, memory cell 125 may be a variable-resistance memory cell. Memory cell 125 may contain materials programmable to different data states. In some instances, each of memory cells 125 may contain a single material between a top electrode (e.g., a top plate) and a bottom electrode (e.g., a bottom plate) that can act as both a selection element (e.g., a switching material) and a storage element, such that each memory cell 125 can act as both a selector device and a memory element. Such memory cells may be referred to herein as selectable memory cells. For example, each memory cell may contain a chalcogenide material that can be formed from various doped or undoped materials, may or may not be a phase-change material, and / or may or may not undergo a phase change during reading and / or writing to the memory cell. In some instances, each memory cell 125 may contain: a ternary composition that may contain selenium (Se), arsenic (As), and germanium (Ge), a quaternary composition that may contain silicon (Si), Se, As, and Ge, and so on.

[0023] In various embodiments, the threshold voltage of memory cell 125 may shunt back in response to an applied voltage difference exceeding its threshold voltage. Such a memory cell may be referred to as a shunt memory cell. For example, memory cell 125 may change (e.g., shunt back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., lower impedance) state in response to an applied voltage difference exceeding its threshold voltage. For example, a memory cell shunt back may refer to a memory cell transitioning from a high impedance state to a lower impedance state in response to an applied voltage difference greater than the memory cell's threshold voltage. For example, a memory cell threshold voltage shunt back may be referred to as a shunt event.

[0024] The embodiments disclosed herein are not limited to Figure 1The example memory array architecture described herein. For example, embodiments of this disclosure may include a three-dimensional memory array having a plurality of vertically oriented (e.g., vertical) access lines and a plurality of horizontally oriented (e.g., horizontal) access lines. The vertical access lines may be bit lines arranged in a columnar architecture, and the horizontal access lines may be word lines arranged in a plurality of conductive planes or decks separated (e.g., insulated) from each other by a dielectric material. The chalcogenide material of the respective memory cell of such a memory array may be located at the intersection of the respective vertical bit line and horizontal word line.

[0025] Figure 2A Explanation of embodiments according to this disclosure and, for example Figure 1 The threshold distribution associated with various states of memory cells such as memory cell 125, as described herein. For example, such as Figure 2A As shown, the memory cells can be programmed to one of two possible data states (e.g., state 0 or state 1). That is, Figure 2A This describes the threshold voltage distribution associated with two possible data states that the memory cell can be programmed to.

[0026] exist Figure 2A In this context, the voltage VCELL can correspond to a voltage difference applied to (e.g., on) a memory cell, such as the difference between the bit line voltage (VBL) and the word line voltage (VWL) (e.g., VCELL = VBL - VWL). Threshold voltage distributions (e.g., ranges) 200-1, 200-2, 201-1, and 201-2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a specific state. Figure 2A The distribution described corresponds to the asymmetric return that is further explained in conjunction with the assigned data state. Figure 2B and 2C The described current and voltage curves.

[0027] In some instances, the threshold voltage of memory cell 125 in a particular state may be asymmetrical for different polarities, such as... Figure 2A , 2B As shown in 2C. For example, the threshold voltage of memory cell 125 programmed to a reset state (e.g., state 0) or a set state (e.g., state 1) may have a different value in one polarity than in the opposite polarity. For example, in Figure 2AIn the examples described herein, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2) where the magnitude is larger in negative polarity than in positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 200-1 and 200-2) where the magnitude is larger in positive polarity than in negative polarity. In such examples, for one applied voltage polarity and the other, the applied voltage magnitude for the memory cell 125 may be different (e.g., higher or lower).

[0028] Figure 2A The dividing voltages VDM1 and VDM2 are explained, which can be used to determine the state of a memory cell (e.g., to distinguish between states as part of a read operation). In this example, VDM1 is a positive voltage used to distinguish cells in state 0 (e.g., in threshold voltage distribution 201-2) from cells in state 1 (e.g., threshold voltage distribution 200-2). Similarly, VDM2 is a negative voltage used to distinguish cells in state 1 (e.g., threshold voltage distribution 200-1) from cells in state 0 (e.g., threshold voltage distribution 201-1). Figures 2A to 2C In the example, memory cell 125 in positive state 1 does not abruptly return in response to the application of VDM1; memory cell 125 in positive state 0 abruptly returns in response to the application of VDM1; memory cell 125 in negative state 1 abruptly returns in response to the application of VDM2; and memory cell 125 in negative state 0 does not abruptly return in response to the application of VDM2.

[0029] Figure 2A The voltages VMAXN, VMAXP, VWRTN, VWRTP, VINH, and VINP are also described. One or more of these voltages can be used in the operation of programming memory cells to state 0 or state 1, as will be further described herein.

[0030] Examples are not limited to Figure 2A Examples are shown in the text. For instance, the labels for state 0 and state 1 can be interchanged (e.g., distributions 201-1 and 201-2 can be labeled as state 1 and distributions 200-1 and 200-2 can be labeled as state 0).

[0031] Figure 2B and 2C The embodiments corresponding to this disclosure Figure 2A An example of current versus voltage curves for memory states. Therefore, in this example, Figure 2B and 2CThe curves in the diagram correspond to units where state 1 is labeled as a higher threshold voltage state in a specific polarity (positive polarity direction in this example) and where state 0 is labeled as a higher threshold voltage state in the opposite polarity (negative polarity direction in this example). As mentioned above, the state labels are interchangeable, such that state 0 can correspond to a higher threshold voltage state in the positive polarity direction, and state 1 can correspond to a higher threshold voltage state in the negative polarity direction.

[0032] Figure 2B and 2C This describes the memory cell churn as described herein. VCELL can represent the voltage applied across the memory cell. For example, VCELL can be the voltage applied to the top electrode corresponding to the cell minus the voltage applied to the bottom electrode corresponding to the cell (e.g., via the respective bit line and word line). Figure 2B As shown, in response to an applied positive polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution 200-2) is in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be called a ripple event, which occurs when the voltage applied across the cell (in a particular polarity) exceeds the cell's threshold voltage. Therefore, voltage Vtst02 can be called the ripple voltage. Figure 2B In this context, voltage Vtst01 corresponds to the quick-return voltage of a cell programmed to state 1 (e.g., threshold voltage distribution 200-1). That is, as... Figure 2B As shown, when VCELL crosses Vtst01 in the negative polarity direction, the memory cell transitions (e.g., switches) to a conductive state.

[0033] Similarly, such as Figure 2C As shown, in response to an applied negative polarity voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution 201-1) is in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell abruptly returns to a conductive (e.g., lower resistance) state. Figure 2C In this context, voltage Vtst12 corresponds to the quick-return voltage of a cell programmed to state 0 (e.g., threshold voltage distribution 201-2). That is, as... Figure 2C As shown in the figure, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell abruptly returns from a high-impedance non-conductive state to a lower-impedance conductive state.

[0034] In various situations, a ripple event can cause a memory cell to switch states. For example, if a VCELL greater than Vtst02 is applied to a state 1 cell, the resulting ripple event can reduce the cell's threshold voltage to a level below VDM1, causing the cell to be read as state 0 (e.g., threshold voltage distribution 201-2). Thus, in several embodiments, a ripple event can be used to write a cell to the opposite state (e.g., from state 1 to state 0 and vice versa), and to apply a specific amount of current for a specific duration after the ripple event.

[0035] In embodiments of this disclosure, memory cells (e.g., Figure 1 The memory cell 125 described herein can be programmed into one of two possible data states (e.g., state 0 or state 1). For example, the memory cell can be programmed by applying a first voltage pulse to the memory cell and then subsequently applying a second voltage pulse to the memory cell after applying the first voltage pulse. The first voltage pulse may have a first polarity opposite to the polarity direction of one of the two possible data states to which the cell is programmed, and the second voltage pulse may have a second polarity opposite to the first polarity (e.g., the second polarity is the polarity direction of the data state to which the cell is programmed). Furthermore, the first voltage pulse may have a first magnitude, and the second voltage pulse may have a second magnitude greater than the first magnitude. In addition, after applying the first voltage pulse to the memory cell but before applying the second voltage pulse to the memory cell, the current to the memory cell may be turned off (e.g., suppressed). A current pulse may then be applied to the memory cell when the second voltage pulse is applied to the memory cell.

[0036] For example, to program a memory cell to a set data state (e.g., state 1), the polarity of the first voltage pulse can be positive, and the polarities of the second voltage pulse and current pulse can be negative. As an additional example, to program a memory cell to a reset data state (e.g., state 0), the polarity of the first voltage pulse can be negative, and the polarities of the second voltage pulse and current pulse can be positive. In some instances, a memory cell can be programmed to a reset data state without applying a first (e.g., negative) voltage pulse (e.g., in these instances, the cell can be programmed to a reset data state by applying only the second voltage pulse and current pulse). Examples of such voltage and current pulses will be further described herein (e.g., in combination with...). Figures 3A to 3B ).

[0037] The magnitude of the first voltage pulse (e.g., a first magnitude) may, for example, be the same magnitude as the voltage used to distinguish between memory cell 125 programmed to one of two possible data states and memory cell 125 programmed to the other of two possible data states. For example, the magnitude of the first voltage pulse may be the same as... Figure 2AThe values ​​of the dividing voltages VDM1 and / or VDM2 described herein are the same. As an additional example, in an instance where a memory cell is programmed to a set data state, the value of the first voltage pulse may be less than the value of the voltage used to distinguish between memory cell 125 programmed to one of two possible data states and memory cell 125 programmed to the other of the two possible data states. For example, in such an instance, the value of the first voltage pulse may be the same as... Figure 2A The value of VWRTP is described in the text. The value of VWRTP can be given by, for example, the following formula:

[0038] VWRTP = VMAXN - VWRTN + VINH + VOSP

[0039] VMAXN, VWRTN, and VINH are respectively Figure 2A The values ​​of VMAXN, VWRTN, and VINH are described in the text, and VOSP is the value of the offset voltage caused by the change in polarity from the first voltage pulse to the second voltage pulse.

[0040] The magnitude of the second voltage pulse (e.g., a second magnitude) may be, for example, the maximum voltage magnitude used to program memory cell 125 to one of two possible data states. For instance, in an example where the memory cell is programmed to a set data state, the magnitude of the second voltage pulse could be... Figure 2A The value of VMAXN described herein, and in the example where the memory cell is programmed to the reset data state, the value of the second voltage pulse can be... Figure 2A The value of VMAXP is described in the text. The value of VMAXP can be given by, for example, the following formula:

[0041] VMAXP = VMAXN + VOSP

[0042] The magnitude of the second voltage pulse (e.g., the magnitudes of VMAXN and VMAXP) may be lower than the maximum voltage magnitude used to program the memory cell in the previous programming method (e.g., about 0.6 volts lower).

[0043] For example, applying a first voltage pulse to a memory cell can adjust (e.g., return) the cell's threshold voltage to a threshold voltage previously (e.g., initially) programmed to the cell. Therefore, any threshold voltage drift (e.g., change) that may occur in the memory cell can be eliminated by applying the first voltage pulse to the memory cell. Because threshold voltage drift can be eliminated in this way, the magnitude of the second voltage pulse applied to the cell can be lower than the maximum voltage magnitude used in the previous programming method.

[0044] Furthermore, because the magnitude of the second voltage pulse applied to the memory cell can be lower than the maximum voltage magnitude of the previous programming method, other (e.g., unselected) memory cells coupled to the same signal lines (e.g., the same word line 110 and / or bit line 120) as the memory cell may not experience any leakage when the second voltage is applied to the memory cell (e.g., applied to the signal lines coupled to the memory cell), and therefore may not be unintentionally (e.g., incorrectly) selected during the programming of the memory cell. Thus, the memory cell can be programmed without having to apply an additional bias voltage (e.g., C-cell bias voltage) to other (e.g., unselected) access lines (e.g., unselected word line 110) to prevent unselected memory cells from being unintentionally selected when programming a selected memory cell.

[0045] Furthermore, because memory cells can be programmed without applying an additional bias voltage to the unselected access line, jolt detection is not required during memory cell programming. For example, memory cells can be programmed without determining whether the memory cell jolts in response to a first applied voltage or a second applied voltage. Therefore, memory cells can be programmed without utilizing a jolt detection circuitry system.

[0046] Figure 3A Illustrations show examples of voltage pulses applied to memory cells according to embodiments of the present disclosure, in the form of illustration 330, and examples of current flowing through memory cells, in the form of illustration 331. For example, illustration 330 may illustrate voltage pulses applied to memory cells during an operation of programming memory to a set data state according to the present disclosure, and illustration 331 may illustrate current flowing through memory cells. Memory cells may, for example, be those previously combined... Figure 1 The memory unit 125 described.

[0047] exist Figure 3A At time t1, as shown in the diagram, voltage pulse 332 is applied to the memory cell. Voltage pulse 332 is a positive voltage pulse, such as... Figure 3A As explained in the document, and may have Figure 2A The values ​​of VDM1 or VWRTP described herein are as previously described.

[0048] Applying voltage pulse 332 to a memory cell can eliminate threshold voltage drift that might otherwise occur in the memory cell if the cell was previously programmed to a reset data state. For example, applying voltage pulse 332 to a cell previously programmed to a reset data state and having a high-value reset threshold voltage distribution (e.g., Figure 2A The memory cell with the threshold voltage of the drift, as described in section 201-1, allows for the following: Figure 3AThe time t2 described above occurs at a sudden return event in the memory cell, causing the threshold voltage of the memory cell to appear in a low-value reset threshold voltage distribution (e.g., Figure 2A As described in section 201-2), when a sudden return event occurs at time t2, a positive pulse of current 336 flows through the memory cell, as... Figure 3A As explained in [the document]. The current through the cell is then dissipated after time t2, as [example follows]. Figure 3A As explained in the text.

[0049] exist Figure 3A At time t3, as shown in the diagram, the voltage and current to the memory cell are switched off. For example, voltage pulse 332 ends at time t3, and no current flows through the memory cell at time t3.

[0050] exist Figure 3A At time t4, as shown in the diagram, voltage pulse 334 is applied to the memory cell. Voltage pulse 334 is a negative voltage pulse, as... Figure 3A As explained in the document, and may have Figure 2A The value of VMAXN described herein is as previously described.

[0051] Applying voltage pulse 334 to a memory cell previously programmed to set data states can cause negative current pulse 338 to... Figure 3A The time t5 described herein flows through the memory cell, where a sudden return event can occur, and the threshold voltage of the cell can be maintained at a low value to set the threshold voltage distribution (e.g., Figure 2A The distribution described in section 200-1) is within this range. The current through the cell is then dissipated after time t5, as shown in section 200-1. Figure 3A As explained in the text.

[0052] However, applying voltage pulse 334 to a memory cell previously programmed to a reset data state allows for... Figure 3A The time t6 described above occurs at a time relapse event (e.g., a re-snap) in the memory cell, causing the threshold voltage of the memory cell to appear in the high-value reset threshold voltage distribution (e.g., Figure 2A As described in section 201-1), when a sudden return event occurs at time t6, a negative pulse of current 340 flows through the memory cell, as... Figure 3A As explained in [the document]. The current through the cell is then dissipated after time t6, as [example follows]. Figure 3A As explained in the text.

[0053] exist Figure 3AAt time t7, as shown, a negative (e.g., setting) current pulse 342 is applied to a memory cell. Applying current pulse 342 to a memory cell previously programmed to a reset data state causes the cell to switch to a setting data state, and applying current pulse 342 to a memory cell previously programmed to a setting data state refreshes the setting data state of the cell.

[0054] exist Figure 3A At time t8, as shown in the diagram, the operation of programming the memory cell to the set data state is completed, and the voltage and current to the memory cell are turned off. For example, voltage pulse 334 ends at time t8, and no current flows through the memory cell at time t8.

[0055] Figure 3B Additional examples of voltage pulses applied to a memory cell according to embodiments of the present disclosure are illustrated in the form of Figure 350, and additional examples of current flowing through a memory cell are illustrated in the form of Figure 351. For example, Figure 350 may illustrate a voltage pulse applied to a memory cell during an operation of programming the memory to a reset data state according to the present disclosure, and Figure 351 may illustrate a current flowing through a memory cell. The memory cell may, for example, be a previously combined... Figure 1 The memory unit 125 described.

[0056] exist Figure 3B At time t1, as shown in the diagram, voltage pulse 352 is applied to the memory cell. Voltage pulse 352 is a negative voltage pulse, as... Figure 3A As explained in the document, and may have Figure 2A The value of VDM2 described herein is as previously described. However, in some instances, it may not be necessary to apply voltage pulse 352 to the memory cell to program the cell to the reset data state, as previously described herein.

[0057] Applying voltage pulse 352 to a memory cell can eliminate threshold voltage drift that might otherwise occur in the memory cell if the cell was previously programmed to a set data state. For example, applying voltage pulse 352 to a cell previously programmed to a set data state and having drifted (e.g., Figure 2A The memory cell with the threshold voltage of the distribution 200-1 described herein can make it possible to... Figure 3B The time t2 described above indicates that a cyclic event occurs in the memory cell, causing the threshold voltage of the memory cell to appear at a low value, thus setting the threshold voltage distribution (e.g., ...). Figure 2A Within 200-1) as described in the document. When a sudden return event occurs at time t2, the negative pulse 356 of the current flows through the memory cell, as... Figure 3B As explained in [the document]. The current through the cell is then dissipated after time t2, as [example follows]. Figure 3BAs explained in the text.

[0058] exist Figure 3B At time t3, as shown in the diagram, the voltage and current to the memory cell are switched off. For example, voltage pulse 352 ends at time t3, and no current flows through the memory cell at time t3.

[0059] exist Figure 3B At time t4, as shown in the diagram, voltage pulse 354 is applied to the memory cell. Voltage pulse 354 is a positive voltage pulse, such as... Figure 3B As explained in the document, and may have Figure 2A The value of VMAXP described herein is as previously described.

[0060] Applying voltage pulse 354 to a memory cell previously programmed to a reset data state enables... Figure 3B The time t5 described above occurs at a sudden return event in the memory cell, causing the threshold voltage of the memory cell to appear in a low-value reset threshold voltage distribution (e.g., Figure 2A As described in section 201-2), when a sudden return event occurs at time t5, a positive pulse of current 358 flows through the memory cell, as... Figure 3B As explained in [the document]. The current through the cell is then dissipated after time t5, as [example follows]. Figure 3B As explained in the text.

[0061] Furthermore, applying voltage pulse 354 to a memory cell previously programmed to set data states enables... Figure 3B The time t6 described above occurs at a time retracement event (e.g., another sudden shift) in the memory cell, causing the threshold voltage of the memory cell to appear at a high value, thus setting the threshold voltage distribution (e.g., Figure 2A Within 200-2) as described in the text. When a sudden return event occurs at time t6, a positive pulse of current 360 flows through the memory cell, as... Figure 3B As explained in [the document]. The current through the cell is then dissipated after time t6, as [example follows]. Figure 3B As explained in the text.

[0062] exist Figure 3B At time t7, as shown, a positive (e.g., reset) current pulse 362 is applied to a memory cell. Applying current pulse 362 to a memory cell previously programmed to a set data state causes the cell to switch to a reset data state, and applying current pulse 342 to a memory cell previously programmed to a reset data state refreshes the reset data state of the cell.

[0063] exist Figure 3BAt time t8, as shown in the diagram, the operation of programming the memory cell to the reset data state is completed, and the voltage and current to the memory cell are turned off. For example, voltage pulse 354 ends at time t8, and no current flows through the memory cell at time t8.

[0064] It should be noted that Figure 3A and 3B The polarity of the voltage pulses and currents described herein can correspond to a specific (e.g., negative) polarity of the current used to sense (e.g., read) the data state of a memory cell. If a current of opposite (e.g., positive) polarity is used to sense the data state of a memory cell, the polarity of the voltage pulses and currents can be reversed to achieve the same net programming effect.

[0065] Figure 4 This is a block diagram illustration of an example device, such as an electronic memory system 400, according to an embodiment of the present disclosure. The memory system 400 includes devices, such as a memory device 402, and a controller 404, such as a memory controller (e.g., a host controller). For example, the controller 404 may include a processor. The controller 404 may be coupled to, for example, a host, and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host, and may output data to the host.

[0066] Memory device 402 includes a memory array 406 of memory cells. For example, memory array 406 may include one or more of the memory arrays of memory cells disclosed herein (e.g., cross-point arrays).

[0067] Memory device 402 includes address circuitry 408 to latch address signals provided via I / O circuitry 412 on I / O connection 410. Address signals can be received and decoded via row decoder 414 and column decoder 416 to access memory array 406. For example, row decoder 414 and / or column decoder 416 may include drivers.

[0068] Memory device 402 can sense (e.g., read) data in memory array 406 by sensing voltage and / or current changes in the memory array using a sensing / buffering circuitry system, which in some instances may be a read / latch circuitry system 420. Read / latch circuitry system 420 can read and latch data from memory array 406. I / O circuitry system 412 is included for bidirectional data communication with controller 404 over I / O connection 410. Write circuitry system 422 is included for writing data to memory array 406.

[0069] The control circuitry 424 can decode signals provided from the controller 404 via the control connection 426. These signals may include chip signals, write enable signals, and address latch signals for controlling operations on the memory array 406, including data read and data write operations.

[0070] For example, control circuitry 424 may be included in controller 404. Controller 404 may include other circuitry, firmware, software, etc., individually or in combination. Controller 404 may be an external controller (e.g., in a die that is either wholly or partially separate from memory array 406) or an internal controller (e.g., included in the same die as memory array 406). For example, an internal controller may be a state machine or a memory sequencer. In some instances, controller 404 may be configured to cause memory device 402 to perform at least the methods disclosed herein, such as programming memory cells of array 406 to one of two possible data states.

[0071] As used herein, the term “coupling” may include electrical coupling, direct coupling and / or direct connection without an intermediary element (e.g., through direct physical contact), or indirect coupling and / or connection with an intermediary element. The term coupling may also include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship).

[0072] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 4 The memory system 400. It should be recognized that, reference... Figure 4 The functions of the various block components described do not necessarily need to be divided into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 4 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 4 The functionality of a single block component.

[0073] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of several embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of this disclosure should be determined with reference to the appended claims and the full scope of equivalents to which such claims are given.

[0074] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than are expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. A memory device comprising: A memory, which has multiple memory cells; as well as A circuit system configured to program memory cells among the plurality of memory cells to one of two possible data states in such a way as follows: A first voltage pulse is applied to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude; as well as A second voltage pulse is applied to the memory cell, wherein the second voltage pulse has a second polarity and a second magnitude opposite to the first polarity. The circuitry is configured to program the memory cell to one of the two possible data states without determining whether the memory cell shudders in response to an applied first voltage pulse or an applied second voltage pulse.

2. The memory device of claim 1, wherein the first polarity is opposite to the polarity of one of the two possible data states to which the memory cell is programmed.

3. The memory device of claim 1, wherein each of the plurality of memory cells is a selectable memory cell in which a single material serves as both a selection element and a storage element.

4. The memory device of claim 3, wherein the single material is a chalcogenide material.

5. The memory device according to any one of claims 1 to 4, wherein: The memory includes multiple access lines coupled to the plurality of memory cells; The programmed memory cell is coupled to one of the plurality of access lines; and The circuit system is configured to program the memory cell to one of the two possible data states without applying voltage to the plurality of access lines to which the programmed memory cell is not coupled.

6. The memory device according to any one of claims 1 to 4, wherein the circuitry is configured to program the memory cell to one of the two possible data states by turning off the current to the memory cell after the first voltage pulse is applied to the memory cell and before the second voltage pulse is applied to the memory cell.

7. The memory device according to any one of claims 1 to 4, wherein the second value is greater than the first value.

8. A method of operating a memory, comprising: The memory cell is programmed to one of two possible data states in the following way: A first voltage pulse is applied to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude; as well as A second voltage pulse is applied to the memory cell, wherein: The second voltage pulse has a second polarity opposite to the first polarity, and is the polarity direction of one of the two possible data states to which the memory cell is programmed; and The second voltage pulse has a second magnitude, and A current pulse is applied to the memory cell while the second voltage pulse is applied to the memory cell.

9. The method of claim 8, wherein applying the first voltage pulse to the memory cell adjusts the threshold voltage of the memory cell to a threshold voltage previously programmed to the memory cell.

10. A memory device comprising: A memory, which has multiple memory cells; as well as A circuit system configured to program memory cells among the plurality of memory cells to one of two possible data states in such a way as follows: A first voltage pulse is applied to the memory cell, wherein the first voltage pulse has a positive polarity and a first magnitude, wherein the first magnitude is the same magnitude as the voltage of the memory cell used to distinguish between the memory cell programmed to one of the two possible data states and the memory cell programmed to the other of the two possible data states. as well as A second voltage pulse is applied to the memory cell, wherein the second voltage pulse has a negative polarity and a second magnitude.

11. The memory device of claim 10, wherein the second quantity is the maximum voltage quantity for programming a memory cell among the plurality of memory cells to one of the two possible data states.

12. A method of operating a memory, comprising: The self-selected memory cell is programmed into one of two possible data states by applying a voltage pulse to the self-selected memory cell, wherein: The voltage pulse has a positive polarity and a magnitude that is less than the voltage magnitude used to distinguish between the selectable memory cell programmed into one of the two possible data states and the selectable memory cell programmed into the other of the two possible data states; and The method includes programming the self-selected memory cell without determining whether the self-selected memory cell shudders in response to an applied voltage pulse.

13. The method of claim 12, wherein the method comprises programming the auto-memory cell to one of the two possible data states by applying an additional voltage pulse to the auto-memory cell before applying the voltage pulse to the auto-memory cell, wherein the additional voltage pulse has a negative polarity.

14. The method of claim 13, wherein the additional voltage pulse has the same magnitude as the voltage used to distinguish between a self-selected memory cell in the memory programmed into one of the two possible data states and a self-selected memory cell in the memory programmed into the other of the two possible data states.

15. The method according to any one of claims 12 to 14, wherein the voltage pulse has a magnitude that is the maximum voltage magnitude used to program the selectable memory cell of the memory to one of the two possible data states.

16. A memory device comprising: A memory, which has multiple memory cells; as well as A circuit system configured to program memory cells among the plurality of memory cells to one of two possible data states in such a way as follows: A first voltage pulse is applied to the memory cell, wherein the first voltage pulse has a negative polarity and a first magnitude; as well as A second voltage pulse is applied to the memory cell, wherein the second voltage pulse has a positive polarity and a second magnitude; in: The memory includes multiple access lines coupled to the plurality of memory cells; The programmed memory cell is coupled to one of the plurality of access lines; and The circuit system is configured to program the memory cell to one of the two possible data states without applying voltage to the plurality of access lines to which the programmed memory cell is not coupled.

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