Method of forming a bipolar transistor with vertical collector contact

Abstract

A method of forming a bipolar transistor with vertical collector contacts requires providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate, and providing a bulk substrate. A metal collector contact is patterned on a top surface of the bulk substrate, and the plurality of epitaxial semiconductor layers is transferred from the first substrate to the metal collector contact on the bulk substrate. The first substrate is suitable for a growth substrate for the plurality of epitaxial semiconductor layers. The bulk substrate preferably has a higher thermal conductivity than the first substrate, which improves the heat dissipation characteristics of the transistor and allows it to operate at higher power densities. A plurality of transistors can be transferred to a common bulk substrate to form a multi-finger transistor.

Description

Technical Field

[0001] The present invention relates generally to bipolar transistors, and more specifically to a method for forming a bipolar transistor having vertical collector contacts. Background Technology

[0002] Thermal management is a common problem for integrated bipolar transistors, especially when used as part of a power amplifier. For example, power density (W / cm²) in heterojunction bipolar transistor (HBT) based power amplifiers and mixed-signal circuits. 2 HBT junction temperatures are typically limited by thermal factors; they usually need to be kept below a predetermined temperature in order to operate reliably or meet specified performance standards.

[0003] Conventional HBTs typically employ a structure where the lateral base contacts are located on either side of the emitter contacts, and the lateral collector contacts are located outside the base contacts. This arrangement results in a large footprint, and the active semiconductor device area must be removed to support these lateral contacts. Furthermore, the collector resistance (referred to as the "collector access resistance") from the sub-collector semiconductor layer to the contacts adversely affects the RF performance and efficiency of multi-finger HBTs. Summary of the Invention

[0004] A method for forming bipolar transistors with vertical collector contacts is proposed, which enables operation at higher power densities with a compact device footprint.

[0005] This method requires providing a transistor comprising multiple epitaxial semiconductor layers on a first substrate and providing a body substrate. Metal collector contacts are patterned on the top surface of the body substrate, and then the multiple epitaxial semiconductor layers are transferred from the first substrate to the metal collector contacts on the body substrate. In a preferred embodiment, the multiple epitaxial semiconductor layers form a heterojunction bipolar transistor (HBT).

[0006] The first substrate is suitable for growing multiple epitaxial semiconductor layers. Compared to the first substrate, the host substrate preferably has higher thermal conductivity, which improves the heat dissipation characteristics of the transistor and allows it to operate at higher power densities compared to conventional designs.

[0007] Multiple transistor fingers, consisting of an array of emitter and base contacts, can be transferred onto a common host substrate to form a multi-finger transistor. The transistors can be transferred onto common metal collector contacts already patterned on the top surface of the host substrate.

[0008] In one embodiment, a metal collector contact is embedded in an opening that has been patterned and etched in an electrically insulating dielectric layer on the surface of the body substrate such that the surface of the collector contact is approximately horizontal to the top surface of the dielectric layer. In another embodiment, the opening is etched into the top surface of the body substrate, and the metal collector contact is formed within the opening.

[0009] These and other features, aspects, and advantages of the invention will be better understood with reference to the following figures, description, and claims. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating one possible embodiment of the method.

[0011] Figure 2A It is a cross-sectional view of multiple epitaxial semiconductor layers on the first substrate.

[0012] Figure 2B It is based on this method Figure 2A A cross-sectional view of multiple epitaxial semiconductor layers after they have been transferred to the host substrate.

[0013] Figure 2C Another embodiment of this method will Figure 2A A cross-sectional view of multiple epitaxial semiconductor layers after they have been transferred to the host substrate.

[0014] Figure 3A It is a cross-sectional view of multiple epitaxial semiconductor layers including the sub-collector layer on the first substrate.

[0015] Figure 3B It is based on this method Figure 3A A cross-sectional view of multiple epitaxial semiconductor layers after they have been transferred to the host substrate.

[0016] Figure 4A It is a cross-sectional view of multiple transistors, each comprising multiple epitaxial semiconductor layers after being transferred to a common body substrate having common metal collector contacts.

[0017] Figures 5A to 5H One possible processing sequence according to the method is shown, which can be used to form a multifinite transistor, preferably an HBT. Detailed Implementation

[0018] Figure 1An embodiment of the method for forming a bipolar transistor with vertical collector contacts is illustrated. A transistor is provided comprising a plurality of epitaxial semiconductor layers (also referred to herein as “epitaxial layers”) on a first substrate (step 10). A body substrate is also provided (step 12). Metal collector contacts are patterned on the top surface of the body substrate (step 14), and the plurality of epitaxial semiconductor layers from the first substrate are directly transferred onto the metal collector contacts on the body substrate (step 16). Thus, the metal collector contacts serve as the vertical collector contacts of the transistor.

[0019] This process can be advantageously used to maximize semiconductor utilization on the first substrate. Discrete transistors or multi-finger transistor structures can be fabricated on the first substrate at high packaging density. For a given integrated circuit design, these transistors can be transferred at a reduced density onto a host substrate with patterned metal collector contacts. For circuit designs such as high-frequency RF power amplifiers, the active device array can occupy <1% of the total circuit area. With proper design, multiple host substrates can be filled with transistors from a single starting substrate with an epitaxial layer. Since epitaxial growth and transistor fabrication costs are significant components of integrated circuit manufacturing costs, this approach offers considerable cost savings potential. Furthermore, the performance of the transferred transistors can be improved. For example, if the host substrate is properly selected, heterojunction bipolar transistors (HBTs) transferred onto a host substrate with patterned metal collector contacts on its top surface will have improved thermal performance.

[0020] Several methods exist for forming metal collector contacts on the top surface of the host substrate (step 14), preferably a planar surface. For example, as shown in step 18, an electrically insulating dielectric layer can be formed on the surface of the host substrate. The metal collector contacts can then be embedded in the dielectric layer (step 20), preferably such that the surface of the contacts is substantially horizontal with the top surface of the dielectric layer. Here, it is preferable to pattern and etch the electrically insulating dielectric layer to form openings, and deposit metal into the openings to form the metal collector contacts. Alternatively, the openings can be etched into the top surface of the host substrate (step 22), and the metal collector contacts can be formed in the openings (step 24).

[0021] This method can also be used to form multi-finger transistors. For example, as shown in step 26, multiple transistors can be transferred onto a common metal collector contact that has been patterned on the top surface of the host substrate to form a multi-finger transistor.

[0022] Exemplary devices resulting from various embodiments of this method will now be discussed. For example, in Figure 2AIn this structure, multiple epitaxial semiconductor layers include an emitter layer 30, a base layer 32, and a collector layer 34 on a first substrate 36; electrical contacts, such as contact 38, may also be present on the emitter and base layers. According to this method, the EPI layers 30, 32, and 34 are transferred to a body substrate 40 on which metal collector contacts 42 have been formed; this structure in Figure 2B As shown in the diagram. Note that contact 38 can be formed before or after the epitaxial semiconductor layer is transferred to the host substrate 40.

[0023] exist Figure 2B In the example shown, an electrically insulating dielectric layer 44 is formed on the top surface of the host substrate 40, and a metal collector contact 42 is embedded in the dielectric layer, preferably such that the surface of the contact is approximately horizontal with the top surface of the layer. For this embodiment, the dielectric layer 44 is preferably patterned and etched to form openings, and metal is deposited into the openings to form the metal collector contact 42. Alternatively, as... Figure 2C As shown, an opening can be etched into the top surface of the body substrate 40, and a metal collector contact 42 can be formed in the opening. The collector layer 34 suitably includes N... - The materials, and the arrangement of the collector layer directly on the metal collector contact 42, form a Schottky contact at their interface.

[0024] Figure 3A and Figure 3B Another embodiment is shown in the figure. Figure 3A In this structure, multiple epitaxial semiconductor layers include an emitter layer 50, a base layer 52, a collector layer 54, and a sub-collector layer 56 on a first substrate 58; electrical contacts (such as contact 60) of the emitter and base layers may also be present. According to this method, layers 50, 52, 54, and 56 are transferred to a body substrate 62 on which metal collector contacts 64 have already been formed; this structure in Figure 3B As shown in the figure. In this example, the collector contact 64 is formed in an opening etched into the top surface of the body substrate 62, although the collector contact can alternatively be embedded as described above. Figure 2B In the electrically insulating dielectric layer under discussion, the sub-collector layer 56 suitably includes N... ++ The materials, and the arrangement of the sub-collector layer directly on the metal collector contact 42, form an ohmic contact at their interface.

[0025] The host substrate preferably has higher thermal conductivity than the first substrate, which improves the heat dissipation characteristics of the transistor. Compared to conventional designs, metal collector contacts on a high thermal conductivity substrate can significantly improve near-junction heat dissipation in transistors such as HBTs, thereby allowing for higher power densities (W / cm²). 2This allows devices produced according to this method to have a more compact footprint than existing designs, or to provide higher performance (output power or functionality) in confined areas. Suitable materials for the host substrate include silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), or diamond.

[0026] Figure 1 The plurality of epitaxial semiconductor layers mentioned in step 10 preferably comprise III-V group materials. For example, the plurality of epitaxial semiconductor layers may include: indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), and combinations of indium arsenide (InAs) and gallium antimony arsenide (GaAsSb). The first substrate having such epitaxial layers is typically InP, which has poor thermal properties, although many other materials can be used.

[0027] This method is used to transfer a single transistor from a first substrate to a main substrate, but is more practically used to transfer multiple transistors onto a common main substrate. This technique can be used to form discrete isolation transistors or polyfinite transistors, which is commonly used in power amplifier designs. This can be achieved in several ways. For example, in... Figure 4A In this embodiment, multiple transistors 70, comprising multiple epitaxial semiconductor layers on a first substrate, are transferred onto a common metal collector contact 82. The multiple epitaxial semiconductor layers include an emitter layer 72, a common base layer 74, a common collector layer 76, an emitter contact 78, and a base contact 80. The common metal collector contact 82 is formed in an opening etched into the top surface of a body substrate 84, thereby forming a multi-finger transistor 86. The collector contact thus formed is preferably planarized prior to the transfer. In this example, the collector contact 82 is formed in an opening etched into the top surface of the body substrate 84, although the collector contact can alternatively be embedded as described above. Figure 2B In the electrically insulating dielectric layer under discussion. Similarly, although Figure 4A A transistor 70 with an emitter layer, a base layer, and a collector layer is depicted, but a transistor with a sub-collector layer can also be used.

[0028] Figures 5A to 5H The diagram illustrates a possible processing sequence according to this method, which can be used to form a multifinite transistor, suitably an HBT. Figure 5A The present invention provides or forms a structure comprising a plurality of emitter layers 110, a common base layer 112, and a common collector layer 114 epitaxially grown on a first substrate 116. Emitter contacts 118 are preferably disposed on or formed on the respective emitters 110. A sacrificial etch layer 120 is preferably provided between the first substrate 116 and the common collector layer 114 to simplify subsequent steps for removing the first substrate 116 from layers 110, 112, and 114 (discussed below).

[0029] exist Figure 5B In the middle, the base contact 122 is defined on the common base layer 112, and in Figure 5C If necessary, layer 112 is patterned and etched to provide base mesa isolation.

[0030] exist Figure 5D Typically, a layer such as a BCB dielectric layer 124 will be provided, on which device interconnects 126 can be formed. Then... Figure 5E In the process, the BCB layer 124 can be patterned and mesa etching can be performed, and then the remaining structure (mesa 128) is packaged using, for example, a polymer (polymer tape) 130.

[0031] exist Figure 5F In this process, the imprint 132 is preferably attached to the top surface of the polymer tape 130, and the transistor mesa 128 is preferably separated from the first substrate 116 by performing an etch release using a sacrificial etch layer such as layer 120.

[0032] exist Figure 5G In this process, a body substrate 134 is fabricated, wherein metal collector contacts 136 are formed on the top surface of the body substrate. In the example shown, the collector contacts 136 are embedded in openings formed in a dielectric layer 138 suitably made of SiO2. As mentioned above, the collector contacts 136 can alternatively be formed in openings etched into the top surface of the body substrate 134. It goes without saying that the body substrate can be fabricated independently of other steps in the illustrated process; that is, it is not required that... Figure 5F and Figure 5H The host substrate is prepared between the steps shown.

[0033] exist Figure 5H In this process, the mesa 128 is transferred to the metal collector contact 136 on the body substrate 134, and the polymer package 130 is removed. Assuming the body substrate 134 has higher thermal conductivity than the first substrate 116, the heat dissipation characteristics of the device will be improved. As described above, this allows the transistor to operate at a higher power density (W / cm²) compared to conventional designs. 2 This allows the device to have a more compact footprint than existing designs, or to provide higher performance (output power or functionality) in confined areas.

[0034] This method also eliminates the need for lateral collector contacts when designing multi-finger transistors. This can significantly increase the power density of the battery without penalizing the collector connection resistance, which would otherwise affect efficiency. Furthermore, eliminating lateral collector contacts can significantly reduce the transistor's footprint.

[0035] The transfer of the epitaxial layer from the first substrate to the host substrate can be achieved in several different ways. One method of achieving the transfer is using microtransfer printing. In one example of this process, polydimethylsiloxane (PDMS) imprinting is used to pick up the epitaxial layer. Figure 5F HBT epitaxy is prepared using a method that allows the HBT epitaxy to be placed on a host substrate. The micro-transfer printing process relies on the rate-sensitive adhesion of the imprint head to the device to perform device pick-up and placement. This sensitivity stems from the viscoelastic behavior of the PDMS polymer. Micro-transfer printing can be used to pick up individual HBTs or HBT arrays and eliminates the flatness requirements of whole-wafer bonding processes. This process allows for the efficient use of HBT epitaxy from the donor host substrate during batch manufacturing.

[0036] Patterned collector contacts preferably have substantial thickness. Thick patterned collector contact metal can be achieved using chemical mechanical polishing (CMP) while maintaining wafer flatness. Thick metal is preferred because it improves current handling and heat dissipation. This process is compatible with existing HBT processing flows and epitaxial designs, adding one or more sacrificial etch layers beneath the epitaxial layer.

[0037] This processing can be used, for example, to increase the output power and efficiency of microwave and millimeter-wave power amplifiers. It can also be used to increase transistor density in mixed-signal circuits to improve speed, bandwidth, and dynamic range.

[0038] Note that a transistor can have multiple single-pointed transistors (e.g., as shown in the image). Figure 2B , Figure 2C and Figure 3B (as shown) and multi-finger transistors (e.g., as shown) Figure 4A (As shown in the diagram), they are deposited on a host substrate with individual collector contacts. This can be done in a single transfer step or in multiple steps. Then, by connecting these transistors together, integrated circuits with different functions can be realized.

[0039] The embodiments of the invention described herein are exemplary, and many modifications, variations, and rearrangements can be readily contemplated to achieve substantially equivalent results, all of which are intended to be included within the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming a bipolar transistor having vertical collector contacts, comprising: A transistor is provided, the transistor comprising a plurality of epitaxial semiconductor layers on a first substrate; Provide the host substrate; Metal current collector contacts are patterned on the top surface of the body substrate prior to transfer; and The plurality of epitaxial semiconductor layers are transferred directly from the first substrate to the metal collector contact on the main substrate, such that one of the plurality of epitaxial semiconductor layers is directly disposed on the metal collector contact and in direct contact with the metal collector contact.

2. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers include an emitter layer, a base layer, and a collector layer, wherein the collector layer is located on the metal collector contact, thereby forming a Schottky contact.

3. The method according to claim 2, wherein, The current collector layer includes N - Material.

4. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers include an emitter layer, a base layer, a collector layer, and a sub-collector layer, wherein the sub-collector layer is located on the metal collector contact, thereby forming an ohmic contact.

5. The method according to claim 4, wherein, The sub-collector layer includes N ++ Material.

6. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers form a heterojunction bipolar transistor (HBT).

7. The method according to claim 1, wherein, The transfer includes transferring a localized region of the epitaxial layer from the first substrate to the host substrate.

8. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers on the first substrate further include a sacrificial etch layer between the epitaxial semiconductor layers and the first substrate, the transfer comprising: A dielectric layer is formed on the epitaxial semiconductor layer, and mesa etching is performed through the dielectric layer to define a transistor mesa; The transistor mesa epitaxial semiconductor layer and the sacrificial etched layer are encapsulated in a polymer to form a polymer strip; The embossing is fixed to the top surface of the polymer strip; Etch the sacrificial etch layer to release the transistor mesa epitaxial semiconductor layer from the first substrate; The imprinting is used to move the released polymer-encapsulated transistor mesa epitaxial semiconductor layer onto the metal collector contact on the host substrate; and Remove the polymer encapsulation.

9. The method according to claim 1, wherein, The provision of transistors includes providing a plurality of said transistors, and the transfer includes transferring the plurality of said transistors onto a common host substrate.

10. The method according to claim 9, wherein, Multiple transistors are transferred to a common metal collector contact that has been patterned on the top surface of the body substrate, thereby forming a multi-finger transistor.

11. The method according to claim 9, wherein, Multiple transistors are transferred to individual metal collector contacts that have been patterned on the top surface of the body substrate, thereby forming multi-finger transistors.

12. The method according to claim 1, wherein, The main substrate has higher thermal conductivity than the first substrate.

13. The method according to claim 12, wherein, The main substrate includes silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), or diamond.

14. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers include III-V group materials.

15. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers include a combination of the following: indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), indium arsenide (InAs), and gallium antimonide arsenide (GaAsSb).

16. The method according to claim 1, wherein, The metal current collector contact is embedded in an electrically insulating dielectric layer on the surface of the main substrate, such that the surface of the metal current collector contact is approximately horizontal with the top surface of the electrically insulating dielectric layer.

17. The method of claim 16, further comprising: The electrically insulating dielectric layer is patterned and etched to form openings; Metal is deposited into the opening to form the metal current collector contact.

18. The method of claim 17, further comprising planarizing the metal collector contact using chemical mechanical polishing (CMP) prior to the transfer.

19. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers include an emitter layer, a base layer, and a collector layer, and further includes the fabrication of electrical contacts to the emitter layer and the base layer after the plurality of epitaxial semiconductor layers are transferred from the first substrate to the metal collector contacts on the body substrate.

20. The method according to claim 1, wherein, The plurality of epitaxial semiconductor layers include an emitter layer, a base layer, and a collector layer, and further includes fabricating electrical contacts to the emitter and the base layer before the plurality of epitaxial semiconductor layers are transferred from the first substrate to the metal collector contacts on the body substrate.

21. The method according to claim 1, wherein, The first substrate is a growth substrate for the plurality of epitaxial semiconductor layers.

22. The method of claim 1, further comprising etching an opening into the top surface of the body substrate and forming the metal current collector contact in the opening.

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