Power semiconductor modules and power conversion devices

Abstract

A power semiconductor module is provided, which is a power semiconductor module formed by connecting multiple power semiconductor chips disposed on the same substrate in parallel. This reduces the chip placement area on the substrate while reducing wiring inductance within the module. It is characterized by comprising: a first insulating substrate; multiple semiconductor switching elements disposed on the first insulating substrate; a second insulating substrate disposed opposite to the first insulating substrate, sandwiching the multiple semiconductor switching elements; multiple first spacer conductors and multiple second spacer conductors disposed between the multiple semiconductor switching elements and the second insulating substrate, serving as spacers between the multiple semiconductor switching elements and the second insulating substrate; and wiring portions between the spacer conductors integrally formed with the multiple second spacer conductors, connecting each second spacer conductor... The conductors are electrically connected. Each of the plurality of semiconductor switching elements has a first electrode, a second electrode disposed on the side opposite to the first electrode, and a control electrode. The first electrode is electrically connected to a first conductor layer disposed on the first insulating substrate. The second electrode is electrically connected to a second conductor layer disposed on the second insulating substrate via the first spacer conductor. The control electrode is electrically connected to each other via the second spacer conductor and the wiring portion between the spacer conductors. The wiring portion between the spacer conductors and the second conductor layer are arranged opposite each other with a predetermined distance.

Description

Technical Field

[0001] This invention relates to the construction of power semiconductor modules, and in particular to a technique that is effectively applicable to power semiconductor modules constructed by connecting multiple power semiconductor chips disposed on the same substrate in parallel. Background Technology

[0002] Power semiconductor modules are used in the power control and motor control of industrial equipment, electric railway vehicles, automobiles, and home appliances. These power semiconductor modules are composed of multiple switching elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), as well as freewheeling diodes and other semiconductor components, mounted in one module.

[0003] In recent years, the use of GaN (gallium nitride) and SiC (silicon carbide) in power semiconductor chips has effectively utilized their advantages, such as high switching speed and high operating temperature, compared to semiconductor devices using Si (silicon). Currently, due to the small size of GaN and SiC devices, multiple power semiconductor chips need to be connected in parallel and mounted on an insulating substrate within the module to construct a power semiconductor module that meets the predetermined current capacity.

[0004] As background technology in this field, there is, for example, technology such as Patent Document 1. In Patent Document 1, as a technique for mounting multiple semiconductor elements in parallel on an insulating substrate within a power semiconductor module, a power module is disclosed in which multiple conductive patterns with different potentials are arranged on a substrate and the shapes of the conductive patterns are set to a mirror shape.

[0005] In addition, Patent Document 2 discloses a power module that uses a pair (two) module substrates (insulating substrates) to hold multiple power semiconductor elements and uses the conductive layer of the module substrate to electrically connect the electrodes of the multiple power semiconductor elements to each other.

[0006] In addition, Patent Document 3 discloses a package that includes multiple semiconductor elements whose gate electrodes are connected together by a lead frame and whose gate wiring is routed through a via via the lead frame in an extended manner.

[0007] Existing technical documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2017-208547

[0009] Patent Document 2: International Publication No. 2015 / 128975

[0010] Patent Document 3: U.S. Patent Application Publication No. 2019 / 0122970 Summary of the Invention

[0011] Referring to FIG1 of the aforementioned Patent Document 1, a chip configuration constituting a half-bridge circuit is shown, wherein the inner gate contact region 46 and the outer gate contact region 48, which are wired in parallel to the gates of the semiconductor switch chip, are arranged on the same plane as the inner metallization region 16, the middle metallization region 18, and the outer metallization region 20, which connect the drain of the chip.

[0012] Furthermore, referring to Figures 1 and 2 of Patent Document 2, a plurality of semiconductor chips 6 are disposed on the lower substrate 2, and electrode terminals 11 and source electrodes 36 are formed on the upper surface of the semiconductor chips 6. A connecting member 9 is provided for connecting the electrode terminals 11 of the plurality of semiconductor chips 6 together, and a connecting member 10 is provided for connecting the source electrodes 36 of the plurality of semiconductor chips 6 together.

[0013] Then, regarding the connecting member 9, it is described that by paying attention to the wiring length from the chip group input terminal 8, which is located at the central position between the gate electrodes of the multiple semiconductor chips 6, to the module input terminal 5, the delay time of the gate input signals of the multiple semiconductor chips can be made consistent, which has the effect of suppressing the confusion of the gate input signals.

[0014] Furthermore, referring to the aforementioned patent document 3 Figure 1A as well as Figure 1B In this configuration, multiple semiconductor dies 10 are arranged with their gate electrodes GA and GB facing downwards, and a lead frame 130-2 is connected to both gate electrodes GA and GB. Furthermore, the lead frame 130-2 and the gate freewheeling wiring 124 are connected via a via wiring 126. The gate freewheeling wiring 124 is led out from two semiconductor die groups (10A, 10B) and used for external connections. A lead frame 130-3, connected to the source electrodes of the multiple semiconductor dies 10, is arranged laterally on the lead frame 130-2, with gaps provided to ensure insulation between the lead frames 130-2 and 130-3. The drain electrodes of the multiple semiconductor dies 10 are connected to the external environment via spacers 15.

[0015] By adopting this structure, a submodule 100 can be constructed that uses the gate freewheeling wiring 124, the source lead frame 130-3, and the drain spacer 15 as interfaces, and multiple submodules can be easily configured inside the module.

[0016] However, as an example of the internal structure of a power semiconductor module, in the wiring pattern of Patent Document 3, the distance between two different patterns is often separated by a space of several millimeters (e.g., 1.5 mm) due to the insulation withstand voltage specifications. The inner gate contact region 46 and the outer gate contact region 48 of Patent Document 1 are typical examples of this.

[0017] Therefore, the wiring layer on the insulating substrate, which functions as a wiring pattern, has space between it and multiple adjacent wiring patterns, resulting in a larger substrate area. In particular, for GaN and SiC semiconductor chips, a large number of parallel wirings are required due to the small chip area, thus increasing the area allocated to ensure space between wiring patterns and further increasing the substrate area.

[0018] Furthermore, the gate wiring shown in Patent Documents 1 to 3 runs with low magnetic coupling to lead frames and spacers present in other wirings and their paths, such as those of the source and drain. That is, an inductance proportional to the path length is generated in the gate wiring, resulting in low magnetic coupling with the source wiring, which becomes the return path for the gate current. Therefore, the increased inductance in the gate wiring makes the gate waveform prone to instability during switching control of the power semiconductor chip.

[0019] As illustrated in Patent Documents 2 and 3 above, in the structure of holding multiple power semiconductor chips between two module substrates (insulating substrates), it is obvious that the countermeasures to make assembly easier by using the equal length of the gate wiring of the power semiconductor chips or the sub-module structure are obvious, but at the same time, the countermeasures to reduce the area of ​​the module substrates are not mentioned.

[0020] Furthermore, no measures were mentioned to reduce the inductance generated on the gate wiring path.

[0021] Therefore, the object of the present invention is to provide a power semiconductor module formed by connecting multiple power semiconductor chips arranged on the same substrate in parallel, and a power conversion device using the power semiconductor module, which can reduce the chip arrangement area on the substrate while reducing the wiring inductance within the module.

[0022] To address the aforementioned issues, the present invention is characterized by comprising: a first insulating substrate; a plurality of semiconductor switching elements disposed on the first insulating substrate; a second insulating substrate disposed opposite to the first insulating substrate, sandwiching the plurality of semiconductor switching elements; a plurality of first spacer conductors and a plurality of second spacer conductors disposed between the plurality of semiconductor switching elements and the second insulating substrate, serving as spacers between the plurality of semiconductor switching elements and the second insulating substrate; and a wiring portion between the spacer conductors integrally formed with the plurality of second spacer conductors, thereby connecting the plurality of second spacer conductors. Each of the plurality of semiconductor switching elements is electrically connected to the second spacer conductors. Each of the plurality of semiconductor switching elements has a first electrode and a second electrode and a control electrode disposed on the side opposite to the first electrode. The first electrode is electrically connected to a first conductor layer disposed on the first insulating substrate. The second electrode is electrically connected to a second conductor layer disposed on the second insulating substrate via the first spacer conductor. The control electrode is electrically connected to each other via the second spacer conductor and the wiring portion between the spacer conductors. The wiring portion between the spacer conductors and the second conductor layer are arranged opposite each other with a predetermined distance.

[0023] In addition, the present invention is a power conversion device comprising: a main circuit having a pair or more upper and lower arms; and a drive circuit for driving the upper and lower arms, wherein the power conversion device is characterized in that the upper and lower arms have power semiconductor modules having the above-mentioned features.

[0024] According to the present invention, a power semiconductor module consisting of multiple power semiconductor chips arranged on the same substrate connected in parallel and a power conversion device using the power semiconductor module can be realized, which can reduce the chip arrangement area on the substrate while reducing the wiring inductance within the module.

[0025] This enables the miniaturization, high performance, and high reliability of power semiconductor modules and power conversion devices using these modules.

[0026] Other issues, structures, and effects beyond those described above will become clear through the following description of the implementation methods. Attached Figure Description

[0027] Figure 1A These are plan views and cross-sectional views of the power semiconductor module involved in Embodiment 1 of the present invention.

[0028] Figure 1B yes Figure 1A A floor plan of the main parts.

[0029] Figure 2A This is a plan view of a traditional power semiconductor module.

[0030] Figure 2B yes Figure 2A A floor plan of the main parts.

[0031] Figure 3A These are plan and cross-sectional views of traditional power semiconductor modules.

[0032] Figure 3B yes Figure 3A A floor plan of the main parts.

[0033] Figure 4 This is a diagram illustrating one example of the effects of the present invention.

[0034] Figure 5A This is a diagram that conceptually illustrates the effect of the power semiconductor module involved in Embodiment 1 of the present invention.

[0035] Figure 5B This is a diagram that conceptually illustrates the function of a conventional power semiconductor module.

[0036] Figure 6A These are plan views and cross-sectional views of the power semiconductor module involved in Embodiment 2 of the present invention.

[0037] Figure 6B yes Figure 6A A floor plan of the main parts.

[0038] Figure 7A These are plan views and cross-sectional views of the power semiconductor module involved in Embodiment 3 of the present invention.

[0039] Figure 7B yes Figure 7A A floor plan of the main parts.

[0040] Figure 8 This is a block diagram illustrating the circuit structure of the power conversion device according to Embodiment 4 of the present invention. Detailed Implementation

[0041] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. Furthermore, in the drawings, the same reference numerals are used for the same structures or structures having similar functions, and detailed descriptions of repeated parts are omitted.

[0042] Example 1

[0043] Reference Figures 1A to 5B This section describes a power semiconductor module according to Embodiment 1 of the present invention. In this embodiment, countermeasures for reducing the size, i.e. the area occupied, of a power semiconductor module constructed using two insulating substrates are shown, and the effect of stabilizing gate controllability by reducing the inductance generated in the gate wiring inside the module is explained.

[0044] Outline Structure

[0045] Figure 1A A schematic structure of the power semiconductor module 1 in this embodiment is shown. Furthermore, in Figure 1A In the text, the configuration of lower-level components that are not normally visible is explicitly indicated by dashed lines for convenience. Figure 1A The diagram shows a plan view of the power semiconductor module 1 viewed from above, and two cross-sectional views at section lines A-A' and B-B' shown in the plan view.

[0046] Sectional Structure

[0047] In this embodiment, the power semiconductor module 1 is constructed using two insulating substrates 10 and 20 arranged vertically.

[0048] The construction is illustrated using cross-sectional view A-A'. Gaps in components not shown are filled with insulating resin. In subsequent descriptions, gaps will be omitted unless absolutely necessary.

[0049] Regarding the insulating substrate 10 disposed on the lower side of the power semiconductor module 1, a conductor layer 11 is provided on the upper surface of the insulating layer 12, and a conductor layer 13 is provided on the lower surface. Regarding the insulating substrate 20 disposed on the upper side of the power semiconductor module 1, a conductor layer 21 is provided on the upper surface of the insulating layer 22, and a conductor layer 23 is provided on the lower surface. The insulating substrate 20 is disposed opposite to the insulating substrate 10, sandwiching a plurality of semiconductor switching elements 5.

[0050] In the semiconductor switching element 5, an electrode 6 is arranged on one plane, and an electrode 7 and a control electrode 8 are arranged on another plane. Current flows longitudinally from electrode 6 toward electrode 7. The on / off state of the current is controlled based on the potential of electrode 7 and the voltage applied to the control electrode 8. In the case where the semiconductor switching element 5 is a MOSFET type device, electrode 6 is the drain electrode, electrode 7 is the source electrode, and control electrode 8 is the gate electrode.

[0051] In order to meet the predetermined rated current of the power semiconductor module 1, it includes a plurality of semiconductor switching elements 5, which are configured to electrically connect electrodes 6 to the conductor layer 11 of the insulating substrate 10.

[0052] The spacer conductor 31 has a conductor shape with a height in a direction perpendicular to the plane of the insulating substrate 10, and electrically connects the electrode 7 of the semiconductor switching element 5 to the conductor layer 23 on the lower surface of the insulating substrate 20. The spacer conductor 31, acting as a mechanical spacer, determines the distance of the gap from the electrode 7 of the semiconductor switching element 5 to the conductor layer 23 on the lower surface of the insulating substrate 20. The electrical connection between the spacer conductor 31, the electrode 7, and the conductor layer 23 utilizes a bonding technique using solder or sintering materials. The same applies to the spacer conductor 32, which will be described later.

[0053] Like the spacer conductor 31, the spacer conductor 32 has a conductor shape with a height in a direction perpendicular to the plane of the insulating substrate 10, and electrically connects the control electrode 8 of the semiconductor switching element 5 to the conductor layer 23 on the lower surface of the insulating substrate 20.

[0054] The conductor patterns of the conductor layers 23 to which the spacer conductors 31 and 32 are connected are independent, mechanically separated, and electrically insulated. Here, the conductor pattern of the conductor layer 23 to which the spacer conductor 31 is connected is designated as 23a, and the conductor pattern of the conductor layer 23 to which the spacer conductor 32 is connected is designated as 23b. The spacer conductor 32 also acts as a mechanical spacer, determining the distance of the gap from the control electrode 8 of the semiconductor switching element 5 to the conductor layer 23 on the lower surface of the insulating substrate 20.

[0055] Methods for handling insulation distances

[0056] like Figure 1A As shown, the power semiconductor module 1 includes a plurality of spacer conductors 32, which are connected by a spacer conductor wiring section 33. The spacer conductor wiring section 33 is disposed opposite to the conductor pattern 23a and is separated from the conductor pattern 23a by a predetermined insulation distance in a direction perpendicular to the plane of the insulating substrate 20. The spacer conductor wiring section 33 is also separated from the electrode 7 of the semiconductor switching element 5 by a predetermined insulation distance in a direction perpendicular to the plane of the insulating substrate 20.

[0057] Furthermore, the spacer conductor 31 and the spacer conductor 32 are separated by a predetermined insulating distance in the direction of the plane of the insulating substrate 20. In order to ensure the above-mentioned insulating distance, the wiring portion 33 between the spacer conductors is drawn out from the middle of the height of the spacer conductor 32 (the length in the direction perpendicular to the plane of the insulating substrate 20) rather than from the lower limit or the upper limit.

[0058] Regarding the potential of the control electrode 8, the switching control is performed with the potential of the electrode 7 as the reference potential. Since the maximum potential difference between the control electrode 8 and the electrode 7 is limited to tens of volts, the insulation distance between the electrodes and the wiring can be set to be relatively small. Based on this feature, the wiring portion 33 between the spacer conductors is led out from the upper part (the part closer to the insulating substrate 20 than the insulating substrate 10) of the height (length in the direction perpendicular to the plane direction of the insulating substrate 20) of the spacer conductor 32, close to the conductor pattern 23a electrically connected to the electrode 7.

[0059] Therefore, the absolute value of the magnetic coupling coefficient between the spacer conductor wiring section 33 and the conductor pattern 23a can be set to be relatively large. In other words, it is possible to configure a structure with a large magnetic coupling between the wiring electrically connected to the control electrode 8 and the wiring electrically connected to the electrode 7.

[0060] Planar Structures

[0061] Figure 1A The plan view is a top view of the power semiconductor module 1. For ease of explanation, the insulating substrate 20 is not shown. Furthermore, the insulating layer 12 within the insulating substrate 10 and the conductor layer 13 on its lower surface are also not shown.

[0062] exist Figure 1A In this example, as a configuration of multiple semiconductor switching elements 5, a total of 16 elements are configured. For example, a group of switching elements 9 is formed by arranging four semiconductor switching elements 5 with their respective control electrodes 8 positioned at the center, and a total of four switching element groups 9a, 9b, 9c, and 9d are disposed on the conductor layer 11 of the insulating substrate 10.

[0063] The spacer conductor 31 has a shape that converges to the shape of connecting the electrodes 7 of the four semiconductor switching elements 5. Furthermore, the illustrated example shows the electrodes 7 of the four semiconductor switching elements 5 connected by a single spacer conductor 31, but a separate spacer conductor 31 may also be provided for each of the individual semiconductor switching elements 5.

[0064] The spacer conductor 32 has a conductor shape that spans the control electrodes 8 of the four semiconductor switching elements 5. Furthermore, it is connected to the conductor pattern 23b provided on the lower surface of the insulating substrate 20, thus serving as a mechanical spacer.

[0065] Conductor pattern 23b is a conductor pattern mechanically connected to spacer conductor 32 via solder or sintering material. A control voltage is applied from outside the power semiconductor module 1 and reaches spacer conductor 32 via spacer conductor wiring portion 33, and then the control voltage is transmitted to control electrode 8 of semiconductor switching element 5. Control current (gate current in the case of MOSFET) also flows in and out of control electrode 8 of semiconductor switching element 5 along the same path.

[0066] As described above, when the semiconductor switching element 5 is a MOSFET, conductor pattern 23a has the same potential as the source electrode (electrode 7), and conductor pattern 23b has the same potential as the gate electrode (control electrode 8). These conductor patterns with different potentials are mechanically separated and electrically insulated from each other.

[0067] Figure 1B A configuration diagram defining conductor pattern 23 is shown. The conductor pattern 23b connecting the spacer conductor 32 is arranged in an island shape according to the arrangement of the four switching element groups 9 (9a, 9b, 9c, 9d). Conductor pattern 23a adopts a gap shape that maintains an insulating distance from conductor pattern 23b. Although conductor pattern 23b is formed in an island shape, conductor pattern 23a is not divided, resulting in a wide pattern. The shapes of the spacer conductor 32 and the wiring portion 33 between the spacer conductors corresponding to conductor patterns 23a and 23b are shown with dashed lines. Furthermore, Figure 1B The symbol 51 indicates the traveling structure of the control wiring (gate wiring) of the present invention. Regarding its cross-sectional structure, the symbol 51 is used... Figure 5A That will be described later.

[0068] As explained above, in the power semiconductor module 1 of this embodiment, the electrode 6 (drain electrode: first electrode) of the semiconductor switching element 5 is connected to the conductor pattern of the conductor layer 11 of the insulating substrate 10 using bonding methods such as soldering, metal bonding, and sintering. Similarly, the electrode 7 (source electrode: second electrode) is connected to the conductor pattern 23a of the conductor layer 23 of the insulating substrate 20 using the same connection method. The control terminal 8 (gate electrode) is connected to the wiring portion 33 between the spacer conductors using the same connection method. Regarding the control terminal 8 (gate electrode), for example, it is connected to the conductor pattern near the edge of the insulating substrates 10 and 20, such as the gate lead-out portion 4.

[0069] "Effect"

[0070] This example illustrates two effects achieved through this embodiment.

[0071] By introducing spacer conductors 32 to form a wiring path for control electrode 8, the spacer conductor wiring portion 33 is positioned in the middle of two upper and lower insulating substrates 10 and 20. This ensures, in the vertical direction, the insulation distance between the spacer conductor wiring portion 33 and the surrounding conductors (conductor pattern 23a, electrode 7 of semiconductor switching element 5, conductor layer 11) required for the spacer conductor wiring portion 33 to move.

[0072] Based on this configuration, the planar insulation distance (distance between semiconductor switching elements 5) of the insulating substrates 10 and 20 can be made to the minimum required (e.g., the minimum space between semiconductor switching elements 5). As a result, the area of ​​the insulating substrates 10 and 20 occupied by a predetermined number of semiconductor switching elements 5 can be designed to be smaller. Thus, the size (area) of the power semiconductor module itself can be reduced.

[0073] For comparison, in Figure 2A , Figure 2B as well as Figure 3A , Figure 3B The diagram shows an example of a conventional configuration of a semiconductor switching element 5. The dimensions of the semiconductor switching element 5 and the construction of its electrodes are shown in the diagram. Figure 1A , Figure 1B same.

[0074] Figure 2A as well as Figure 2B This diagram is a drawing obtained by plotting the wiring on the insulating substrate connected to the control electrode 8, with reference to Patent Document 1. Furthermore, Figure 2B A configuration diagram is shown that defines the conductor layer 23 and the conductor patterns 11a, 11b.

[0075] Figure 2A This is a configuration diagram showing 16 semiconductor switching elements 5 connected in parallel. The control electrode (gate electrode) 8 of each semiconductor switching element 5 is connected to the conductor pattern 11b of the insulating substrate 10 via bonding wire 35. The electrode 6 (drain electrode: first electrode) of the semiconductor switching element 5 is connected to the conductor pattern 11a of the insulating substrate 10, and the electrode 7 (source electrode: second electrode) of the semiconductor switching element 5 is connected to the conductor layer 23 of the insulating substrate 20.

[0076] As from Figure 2A as well as Figure 2B As is clearly stated, regarding conductor pattern 11, in order to ensure the area of ​​conductor patterns 11a and 11b themselves, and to maintain a space in the plane between conductor patterns 11a and 11b at different potentials to ensure an insulating distance, it is known that the area required for conductor pattern 11 (11a and 11b and their space) is greater than that shown in the embodiment of FIG1.

[0077] For example, in the case where the semiconductor switching element 5 is a MOSFET type element, electrode 6 is the drain electrode, electrode 7 is the source electrode, and control electrode 8 is the gate electrode. That is, the conductor pattern 11a is applied with a high potential of the drain electrode, and the conductor pattern 11b is applied with a relatively low potential of the gate electrode. Therefore, regarding the space between conductor pattern 11a and conductor pattern 11b, a predetermined distance needs to be set from the viewpoint of ensuring insulation characteristics. When filling the space around it with an insulator, for example, for a potential difference of up to 1.2kV, a space of 1.0mm or more is required.

[0078] Figure 3A This demonstrates that when using two insulating substrates 10 and 20 to construct a power semiconductor module, without introducing [the following]... Figure 1A as well as Figure 1B The spacer conductor shown is an example of a wiring structure when 16 semiconductor switching elements 5 are arranged using a conductor layer of an insulating substrate. This wiring structure is a structure obtained by drawing with reference to Patent Document 2. Figure 3A as well as Figure 3B symbols and Figure 1A as well as Figure 1B same.

[0079] exist Figure 3A In this process, the conductor layer 23 of the insulating substrate 20 is used to connect the electrode 7 (source electrode: second electrode) and the control electrode (gate electrode) 8 of the semiconductor switching element 5. The same conductor layer 23 is divided, with conductor pattern 23a assigned to the electrode 7 (source electrode: second electrode) and conductor pattern 23b assigned to the control electrode (gate electrode) 8. To facilitate the routing of wiring electrically connected to the control electrode (gate electrode) 8, such as... Figure 3A As shown, it is necessary to ensure an insulating distance between the substrate and the electrode 7 (source electrode: second electrode) of the semiconductor switching element 5 in the planar direction. This is because the lower surface of the conductor pattern 23b is at the same height as the upper surface of the electrode 7 (source electrode: second electrode) of the semiconductor switching element 5. Therefore, if the conductor pattern 23a and the conductor pattern 23b are close together, they will either contact each other or the insulating distance will be insufficient.

[0080] Since there is no space in the vertical direction of the insulating substrate to ensure the insulation distance, the insulation distance must be ensured in the planar direction of the insulating substrate. Therefore, it is necessary to widen the spacing between some of the 16 semiconductor switching elements 5. Therefore, it can be seen that... Figure 3A The required area of ​​the insulating substrate shown is larger than that of the embodiment shown in Figure 1.

[0081] Figure 3BThe shape of the conductor pattern of conductor layer 23 is shown. Conductor pattern 23a is distributed in a segmented manner to the electrode 7 (source electrode: second electrode) of semiconductor switching element 5, and conductor pattern 23b is distributed in a segmented manner to the control electrode (gate electrode) 8. As a result, conductor pattern 23a is significantly segmented by conductor pattern 23b.

[0082] Therefore, the electrodes 7 (source electrode: second electrode) of the multiple semiconductor switching elements 5 are electrically connected via the conductor pattern 23a with increased self-inductance after being split, resulting in a timing deviation between the multiple semiconductor switching elements 5. For example, when switching is performed, the following problem occurs: an imbalance of the switching current of each semiconductor switching element 5.

[0083] Figure 4 Show Figure 1A as well as Figure 1B This embodiment illustrates one effect. Figure 4 In this example, 16 semiconductor switching elements 5 are configured under the same conditions, and the area occupied by the semiconductor switching elements 5 (chips) is summed up according to the ratio.

[0084] Regarding the configuration conditions, the chip size of the semiconductor switching element 5 is set to 5mm square, the configuration space between chips is set to 1mm, the width of the control wiring trace is set to 1mm, the insulation distance is set to 1mm, and the coverage distance of the conductor pattern connected to the semiconductor switching element 5 is set to 0.5mm.

[0085] Will Figure 1A as well as Figure 1B The configuration shown in this embodiment is set to "Invention". Figure 2A as well as Figure 2B The configuration concept is set to "Previous 1". Figure 3A as well as Figure 3B The configuration concept is set as "Conventional 2". Regarding the area ratio of the chip occupied by the plane, if "Conventional 1" is set as a baseline of 100%, then "Conventional 2" is 102% and there is almost no change. In contrast, in "This Invention", it is 80%, which can reduce the area by 20%.

[0086] The above is an example of quantitative discussion. The obvious effect of the invention in this embodiment is that, based on the feature of ensuring the insulation distance between the spacer conductors and surrounding conductors required for the movement of the wiring portion 33 in the vertical direction, the planar area of ​​the insulating substrate having the semiconductor switching element 5 and its wiring structure can be reduced.

[0087] Figure 5A as well as Figure 5B This is a diagram used to illustrate another effect of this embodiment. Figure 5AThe diagram uses a perspective view to illustrate the wiring portion 33 between the spacer conductors of this embodiment, and the arrangement of the conductor pattern 23a and conductor layer 11 disposed around it. It shows... Figure 1B The main part of the cross-sectional structure of region 51. The spacer conductor wiring section 33 is a wiring section that is connected to the control electrode (gate electrode) 8 of the semiconductor switching element 5 via the spacer conductor 32. In the case that the semiconductor switching element 5 is a MOSFET, it becomes the gate wiring section.

[0088] Furthermore, conductor pattern 23a is a wiring that is electrically connected to the electrode 7 (second electrode), i.e., the source electrode, of the semiconductor switching element 5 via the aforementioned spacer conductor 31. Therefore, it is obvious that it is in a relationship with the main wiring (A) of the gate drive current and the return current wiring (B).

[0089] The potential difference between the gate wiring and the source wiring is at most within tens of volts, thus shortening the insulation distance between the wirings. When the wirings are sealed around an insulator, the insulation distance can be reduced to approximately 0.3 mm. The spacer conductor wiring portion 33 can be led out from any point within the height of the spacer conductor 32. Therefore, for the conductor pattern 23a, the spacer conductor wiring portion 33 can be configured to ensure the minimum insulation distance, thereby maximizing the magnetic coupling between these wirings.

[0090] The mutual inductance can be calculated by multiplying the self-inductance by the coupling coefficient K. Therefore, when calculating the coupling coefficient, KA-B = -0.83. The conditions for calculating the absolute value of the mutual inductance are set as follows: the space between the spacer conductor wiring portion 33 and the conductor pattern 23a is 0.8 mm, the width of the spacer conductor wiring portion 33 is 1 mm, and the thickness of the spacer conductor wiring portion 33 is 0.4 mm.

[0091] Figure 5B It is focused on Figure 3A as well as Figure 3B The previous configuration concept shown will Figure 3B A perspective view of the wiring section 23b (wiring A') connecting the control electrode (gate electrode) 8 and the wiring section 23a (wiring B') connecting the electrode 7 (source electrode: second electrode). (The image shows...) Figure 3B The main part of the cross-sectional structure of region 52 is as follows: relative to the conductor pattern 23b that becomes the gate wiring portion, the conductor pattern 23a that becomes the source wiring portion is arranged side by side in the planar direction with an insulating space between them.

[0092] Regarding the calculation conditions, let's assume the space between conductor pattern 23a and conductor pattern 23b is 1mm, the width of conductor pattern 23b is 1mm, and the thickness of conductor pattern 23b is 0.3mm. When calculating the coupling coefficient under these conditions, KA'-B' = -0.68. Therefore, in the construction of this embodiment ( Figure 5A When the absolute value of the coupling coefficient is larger and negative, mutual inductance occurs more significantly. This gives us the advantage of being able to set a smaller loop inductance for the gate wiring path.

[0093] As described above, the power semiconductor module of this embodiment includes: a first insulating substrate 10; a plurality of semiconductor switching elements 5 disposed on the first insulating substrate 10; a second insulating substrate 20 disposed opposite to the first insulating substrate 10, sandwiching the plurality of semiconductor switching elements 5; a plurality of first spacer conductors 31 and a plurality of second spacer conductors 32 disposed between the plurality of semiconductor switching elements 5 and the second insulating substrate 20, serving as spacers between the plurality of semiconductor switching elements 5 and the second insulating substrate 20; and a spacer conductor wiring portion 33 integrally formed with the plurality of second spacer conductors 32, connecting the plurality of second spacer conductors 5. The spacer conductors 32 are electrically connected to each other. Each of the multiple semiconductor switching elements 5 has a first electrode 6 and a second electrode 7 and a control electrode 8 disposed on the side opposite to the first electrode 6. The first electrode 6 is electrically connected to the first conductor layer 11 disposed on the first insulating substrate 10. The second electrode 7 is electrically connected to the second conductor layer 23a disposed on the second insulating substrate 20 via the first spacer conductor 31. The control electrode 8 is electrically connected to each other via the second spacer conductor 32 and the spacer conductor wiring portion 33. The spacer conductor wiring portion 33 and the second conductor layer 23a are arranged opposite each other with a predetermined distance.

[0094] In addition, the control electrode 8 is electrically connected to each other through the second spacer conductor 32 and the wiring portion 33 between the spacer conductors, and is electrically connected to the third conductor layer 23b disposed on the second insulating substrate 20 through the second spacer conductor 32.

[0095] Furthermore, the aforementioned predetermined distance is the insulation distance between the spacer conductor wiring portion 33 and the second conductor layer 23a, which enables electrical insulation.

[0096] In addition, the wiring section 33 between the spacer conductors forms a mutual inductance between the wiring and the second conductor layer 23a, which is determined by a negative coupling coefficient.

[0097] Furthermore, the spacer conductor wiring section 33 and the second conductor layer 23a are configured such that the coupling coefficient between the spacer conductor wiring section 33 and the second conductor layer 23a is greater than -1.0 and less than -0.8.

[0098] Therefore, it has the following two advantages:

[0099] (1) It can improve the surface mounting efficiency of semiconductor switching elements;

[0100] (2) It can reduce the inductance of the control wiring (gate wiring) in the power semiconductor module.

[0101] Therefore, it is possible to provide small power semiconductor modules with excellent gate control stability.

[0102] Furthermore, when using MOSFET-type SiC elements (SiC-MOSFET) in the semiconductor switching element 5, the chip area is small as described above. Therefore, in order to ensure the rated current of the power semiconductor module, it is necessary to connect multiple semiconductor switching elements 5 in parallel. However, by adopting the wandering structure of the control wiring (gate wiring) of this embodiment, miniaturization can be achieved while ensuring the desired rated current of the power semiconductor module, which is particularly effective.

[0103] Example 2

[0104] Reference Figure 6A as well as Figure 6B This describes the power semiconductor module of Embodiment 2 of the present invention.

[0105] Outline Structure

[0106] Figure 6A The schematic structure of the power semiconductor module 1 in this embodiment is shown. Figure 6A A plan view of the power semiconductor module 1 viewed from above is shown, along with two cross-sectional views along sections A-A' and B-B' as depicted in the plan view. Furthermore, for ease of explanation, the insulating substrate 20 is not shown in the plan view. Additionally, the insulating layer 12 and its conductor layer 13 within the insulating substrate 10 are also not shown.

[0107] Sectional Structure

[0108] The power semiconductor module 1 in this embodiment is similar to that in Embodiment 1, constructed using two insulating substrates 10 and 20 arranged vertically. The difference between this embodiment and Embodiment 1 lies in the construction of the spacer conductor 32 and the shape of the conductor pattern on the conductor layer 23 of the insulating substrate 20. The differences will be primarily illustrated using cross-sectional view A-A'.

[0109] This embodiment is constructed as follows: the control electrodes 8 of multiple semiconductor switching elements 5 are connected to each other by multiple spacer conductors 32, and the wiring from the control electrodes 8 is made to flow using the wiring portion 33 between the spacer conductors. The difference from Embodiment 1 is that the height of the spacer conductors 32 is reduced, and an insulator 34 is disposed between the spacer conductors 32 and the conductor layer 23 on the lower side of the insulating substrate 20.

[0110] Here, the structure formed by the spacer conductor 32 and the insulator 34 is configured to perform the mechanical function of a spacer. With the introduction of the insulator 34, the conductor layer 23 is only supplied with the potential of the electrode 7 (source electrode: second electrode) of the semiconductor switching element 5, therefore, it is not necessary to... Figure 1B The conductor layer 23 is shown to be separated into conductor patterns 23a and 23b.

[0111] Therefore, the conductor pattern of the conductor layer 23 in this embodiment is as follows: Figure 6B As shown, it can become a completely undivided plane. Therefore, by adopting the structure of this embodiment, the following effects can be obtained compared to Embodiment 1.

[0112] The first effect is as follows: when current flows through the semiconductor switching element 5 (conduction current flows), the resistance and inductance of the path through which current flows from the electrodes 7 (source electrodes: second electrodes) of the multiple semiconductor switching elements 5 to the conductor layer 23 via the spacer conductor 31 can be reduced. This is because, as Figure 6B As shown, the area of ​​the pattern in conductor layer 23a increases.

[0113] The second effect is improved ease of module assembly. In Embodiment 1, alignment of the spacer conductor 32 with the conductor pattern 23b is required for the conductor layer 23. Furthermore, unforeseen exposure of solder, sintering materials, etc., can lead to insulation defects. In this embodiment, since the alignment of the spacer conductor 32 with the conductor layer 23 is not required, the possibility of assembly defects is reduced, resulting in an improved module manufacturing yield.

[0114] Furthermore, regarding other advantages of this embodiment, the advantages described in Embodiment 1 can be obtained as is.

[0115] Furthermore, the power semiconductor module according to this embodiment, in addition to the advantages of Embodiment 1, also has the advantage of being able to reduce the resistance and inductance of the current path (conductor layer 23a).

[0116] Therefore, it is possible to provide power semiconductor modules that are not only small and have excellent control stability, but also reduce the path of large current flow and have high yield.

[0117] Example 3

[0118] Reference Figure 7A as well as Figure 7B This describes the power semiconductor module of Embodiment 3 of the present invention.

[0119] Outline Structure

[0120] Figure 7A The schematic structure of the power semiconductor module 1 in this embodiment is shown. Figure 7A A plan view of the power semiconductor module 1 viewed from above is shown, along with two cross-sectional views along sections A-A' and B-B' as depicted in the plan view. Furthermore, for ease of explanation, the insulating substrate 20 is not shown in the plan view. Additionally, the insulating layer 12 and its conductor layer 13 within the insulating substrate 10 are also not shown.

[0121] Sectional Structure

[0122] The power semiconductor module 1 in this embodiment is similar to that in Embodiment 1, constructed using two insulating substrates 10 and 20 arranged vertically. The differences between this embodiment and Embodiments 1 and 2 lie in the construction of the spacer conductor 32 (32a), the shape of the conductor patterns (11a, 11b) of the conductor layer 11 on the insulating substrate 10, and the electrical connection to the control electrode 8 of the semiconductor switching element 5 via bonding wire 35. The description will primarily focus on these differences using cross-sectional view A-A'.

[0123] In this embodiment, the control electrodes 8 of the plurality of semiconductor switching elements 5 are electrically connected to the conductor pattern 11b, which serves as the upper conductor of the insulating substrate 10, via a plurality of bonding wires 35. As shown in the plan view, the conductor pattern 11b adopts a plurality of island-shaped patterns and is surrounded by the conductor pattern 11a. A spacer conductor 32a is mechanically and electrically connected between the conductor pattern 11b and the conductor pattern 23b of the insulating substrate 20.

[0124] The spacer conductor 32a is electrically connected to the spacer conductor wiring section 33, which is a structure that is separated from the conductor pattern 23a by a predetermined insulating distance in a direction perpendicular to the plane of the insulating substrate 20.

[0125] Therefore, the wiring structure of the spacer conductor wiring portion 33 and the conductor pattern 23a is the same as in Embodiment 1, which provides the advantage of reducing the inductance of the control wiring within the power semiconductor module. Furthermore, in this embodiment, the control electrodes 8 of each semiconductor switching element 5 are electrically connected via bonding wires 35, thereby achieving the aforementioned effects of the present invention regardless of the position of the control electrodes 8 in the semiconductor switching element 5.

[0126] like Figure 7A As shown, the bonding wire 35 is a component that can easily realize a three-dimensional wiring structure, and its electrical connection can also be realized when the control electrode 8 of the semiconductor switching element 5 is arranged at the center of the edge of the element.

[0127] Another advantage of this embodiment is that the electrical distance from each semiconductor switching element 5 to the gate lead-out portion 4 of the power semiconductor module 1 can be designed to be equal.

[0128] exist Figure 7B The diagram above representatively shows the wiring characteristics of conductor patterns 23a and 23b, and the spacer conductor wiring portion 33 (illustrated with dashed lines). For every four semiconductor switching elements 5, conductor pattern 23b is set as an island shape, and the spacer conductor wiring 33 is set as an H-shape from here, thereby achieving the effect of setting the electrical length (resistance and inductance) of the wiring of the control electrode 8 to be approximately equal.

[0129] In addition, Figure 7B In the figure below, only the shapes of the conductor patterns 11 (11a, 11b), which serve as the upper conductors of the insulating substrate 10, are shown. By arranging the conductor patterns 11b of the control electrodes 8 connecting the semiconductor switching element 5 into a four-island configuration, the following effect is achieved: the shape of the conductor pattern 11a is compared to... Figure 2B The degree of segmentation of the conductor pattern 11a shown in the lower part is reduced, thereby reducing the inductance value between the semiconductor switching elements 5 in the conductor pattern 11a.

[0130] As explained above, although the power semiconductor module according to this embodiment does not achieve the miniaturization effect of the power semiconductor module in Embodiment 1, it has the following two advantages by introducing bonding wires 35 in the electrical connection with the control electrode 8 and using spacer conductors 32a and spacer conductor wiring portions 33 in the path of the control electrode 8:

[0131] (1) The inductance of the control wiring (11a) in the power semiconductor module 1 can be reduced without depending on the position of the control electrode 8 in the semiconductor switching element 5.

[0132] (2) The electrical length (resistance and inductance) of the wiring of the control electrode 8 in the power semiconductor module 1 can be set to be approximately equal.

[0133] Therefore, it is a highly versatile module structure for the configuration of control electrodes of semiconductor switching elements mounted in a power semiconductor module, and a power semiconductor module that can provide excellent uniform operation of the multiple semiconductor switching elements mounted thereon.

[0134] Example 4

[0135] Reference Figure 8 This describes the power conversion device of Embodiment 4 of the present invention. Figure 8 This is a block diagram illustrating the circuit structure of the power conversion device in this embodiment.

[0136] exist Figure 8 The image shows an example of a three-phase AC motor that drives the axle of an electric vehicle, consisting of a battery 110, a power conversion device 150, and an electric motor 140 as a load.

[0137] The power conversion device 150 of this embodiment includes: three branch circuits with one phase, each consisting of an upper and lower arm composed of two power semiconductor modules 1 (1a and 1b, 1c and 1d, 1e and 1f); a capacitor 160; and a control circuit 170. Furthermore, the power conversion device 150 includes three branch circuits 100a, 100c, and 100e, with the same number of phases as the AC circuit.

[0138] The power conversion device 150 maintains the main voltage (Vcc) through the capacitor 160, and generates control signals for the gate drive circuits 3a, 3c, and 3e that drive the gates of the semiconductor switching elements 5 in each power semiconductor module 1 through the control circuit 170, and inputs them to the gate drive circuits 3a, 3c, and 3e respectively.

[0139] Branch circuits 100a, 100c, and 100e constitute the inverter branch for phase 1, phase 2, and phase 3, respectively. The output of each inverter branch is connected to the motor 140.

[0140] In this embodiment, branch circuits 100a, 100c, and 100e have the same circuit structure. Therefore, the circuit structure will be described using branch circuit 100a as an example.

[0141] Branch circuit 100a includes a pair of upper and lower arms consisting of power semiconductor modules 1a and 1b connected in series, and a gate drive circuit 3a for controlling the on / off state of power semiconductor modules 1a and 1b.

[0142] According to this embodiment, the power semiconductor module described in any one of Embodiments 1 to 3 is used in the power semiconductor module 1 (1a, 1b, 1c, 1d, 1e, 1f) mounted on the power conversion device 150. In the cases of Embodiments 1 and 2, the power conversion device 150 and the electric vehicle motor drive system including the power conversion device 150 can be miniaturized.

[0143] In addition, the parasitic inductance of the gate wiring built into the power semiconductor module 1 can be reduced. Therefore, compared with the conventional module structure, the power semiconductor module 1 can be driven while keeping the gate drive waveform stable.

[0144] Therefore, the power conversion device 150 and the electric vehicle motor drive system configured to include the power conversion device 150 can be miniaturized or prevented from malfunctioning.

[0145] Furthermore, the present invention is not limited to the above-described embodiments, but includes various modifications.

[0146] For example, the above embodiments are examples described in detail to aid in understanding the present invention and are not intended to limit the implementation to all the described structures. Furthermore, a portion of the structure of one embodiment can be replaced with the structure of another embodiment, and the structure of another embodiment can be added to the structure of one embodiment. Additionally, for a portion of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0147] For example, the size and insulation distance of the components constituting the power semiconductor module 1 can be arbitrary depending on the application. Moreover, the chip configuration of the semiconductor switching elements constituting the power semiconductor module 1 is not limited to the form shown in the figure.

[0148] Furthermore, the power semiconductor module 1 constituting the upper and lower arms can be any device other than a MOSFET, such as a JFET (Junction Field Effect Transistor) or an IGBT (Bipolar Transistor). Additionally, depending on the device, the main terminals are referred to as the "drain" and "source" as described above, as well as the "collector" and "emitter".

[0149] In addition, regarding the configuration of the power semiconductor module, besides the one-in-one (1-in-1) and two-in-one (2-in-1) power semiconductor modules 1 shown in the embodiments, it can also be a three-phase full-bridge circuit using more than 6 power semiconductor modules 1.

[0150] In addition, the power conversion device using this power semiconductor module 1 can be applied not only to motor drive systems for electric vehicles, but also to PCS (Power Conditioning System) in solar power generation devices, electrical systems for railway vehicles, and so on.

[0151] Explanation of symbols

[0152] 1, 1a, 1b, 1c, 1d, 1e, 1f: Power semiconductor module; 3, 3a, 3c, 3e: Gate drive circuit; 4: Gate lead-out; 5: Semiconductor switching element; 6: Electrode (drain electrode); 7: Electrode (source electrode); 8: Control electrode (gate electrode); 9, 9a, 9b, 9c, 9d: Semiconductor switching element group; 10: Insulating substrate; 11: Conductor layer; 11a: Conductor pattern (for connecting the drain electrode of the upper conductor of the lower insulating substrate); 11b: Conductor pattern (for connecting the gate electrode of the upper conductor of the lower insulating substrate); 12: Insulating layer; 13: Conductor layer; 20: Insulating substrate; 21: Conductor layer; 22: Insulating layer; 23: Conductor layer; 23a: (Upper insulating substrate) 23b: Conductor pattern for connecting the source electrode of the lower conductor of the board; 31: (for the source electrode) spacer conductor; 32, 32a: (for the gate electrode) spacer conductor; 33: (for the gate electrode) wiring between spacer conductors; 34: (for the spacer conductor) insulator; 35: bonding wire; 51: wandering structure of the control wiring of the present invention; 52: wandering structure of the control wiring of a conventional example; 53: gate wiring current; 54: source wiring return current; 100, 100a, 100c, 100e: branch circuit; 110: battery; 140: motor; 150: power conversion device; 160: capacitor; 170: control circuit.

Claims

1. A power semiconductor module, characterized in that, have: First insulating substrate; Multiple semiconductor switching elements are disposed on the first insulating substrate; The second insulating substrate, which sandwiches the plurality of semiconductor switching elements, is disposed opposite to the first insulating substrate; A plurality of first spacer conductors and a plurality of second spacer conductors are disposed between the plurality of semiconductor switching elements and the second insulating substrate, forming spacers between the plurality of semiconductor switching elements and the second insulating substrate; as well as The wiring portion between the spacer conductors is integrally formed with the plurality of second spacer conductors, and electrically connects each of the plurality of second spacer conductors. Each of the plurality of semiconductor switching elements has a first electrode, a second electrode disposed on the side opposite to the first electrode, and a control electrode. The first electrode is electrically connected to the first conductor layer disposed on the first insulating substrate. The second electrode is electrically connected to the second conductor layer disposed on the second insulating substrate via the first spacer conductor. The control electrodes are electrically connected to each other through the second spacer conductor and the wiring portion between the spacer conductors. The spacer conductor wiring portion is disposed opposite the second conductor layer at a predetermined distance in a direction perpendicular to the plane of the second insulating substrate.

2. The power semiconductor module according to claim 1, characterized in that, The control electrodes are electrically connected to each other through the second spacer conductor and the wiring portion between the spacer conductors, and are electrically connected to the third conductor layer disposed on the second insulating substrate via the second spacer conductor.

3. The power semiconductor module according to claim 1, characterized in that, Between the plurality of second spacer conductors and the second conductor layer, there is an insulating layer that, together with the plurality of second spacer conductors, forms a spacer between the plurality of semiconductor switching elements and the second insulating substrate.

4. The power semiconductor module according to claim 1, characterized in that, The predetermined distance is an insulation distance that enables electrical insulation between the wiring portion between the spacer conductors and the second conductor layer.

5. The power semiconductor module according to claim 1, characterized in that, The control electrode is electrically connected to the second spacer conductor via a bonding wire.

6. The power semiconductor module according to claim 1, characterized in that, The spacer conductor wiring section forms a mutual inductance between the wiring and the second conductor layer, which is determined by a negative coupling coefficient.

7. The power semiconductor module according to claim 6, characterized in that, The coupling coefficient between the wiring portion between the spacer conductors and the second conductor layer is greater than -1.0 and less than -0.

8.

8. The power semiconductor module according to claim 1, characterized in that, The plurality of semiconductor switching elements are MOSFET type elements. The first electrode is the drain electrode, the second electrode is the source electrode, and the control electrode is the gate electrode.

9. The power semiconductor module according to claim 8, characterized in that, The plurality of semiconductor switching elements are SiC-MOSFETs.

10. A power conversion device, comprising: The main circuit has one or more upper and lower arms; and The driving circuit drives the upper and lower arms. The power conversion device is characterized in that... The upper and lower arms have a power semiconductor module as described in any one of claims 1 to 9.

Images