Fault detection in shunt capacitor banks

Abstract

Fault detection in a shunt capacitor bank connected to a power system is described. Voltage measurements and current measurements are obtained at one terminal of the shunt capacitor bank. An electrical parameter is calculated based on the voltage measurements and current measurements, wherein the electrical parameter is an impedance angle or an active power. A difference between a first value and a second value of the electrical parameter is calculated, and a fault is detected based on the difference.

Description

Technical Field

[0001] This topic generally relates to fault detection in power systems. Specifically, it relates to fault detection in shunt capacitor banks. Background Technology

[0002] Parallel capacitor banks (SCBs) are used for reactive power compensation in power systems. Typically, an SCB comprises capacitor elements, which are groups of capacitors connected in series and parallel. Reactive power compensation in power systems provides reactive power support, which increases power system capacity, improves the system's power factor, and provides better voltage stability. However, power systems are frequently subjected to internal or external faults and disturbances, which can lead to arcing faults in the SCB. If an arcing fault occurring in a parallel capacitor bank goes undetected, it can damage the entire capacitor bank. Attached Figure Description

[0003] The features, aspects, and advantages of this subject matter will be better understood with reference to the following description and accompanying drawings. The same reference numerals are used in the different drawings to indicate similar or identical features and parts.

[0004] Figure 1 An example arrangement of capacitor cells in an SCB is shown.

[0005] Figure 2 An example of an embodiment of this subject is illustrated: a power system including a device for fault detection in an SCB.

[0006] Figure 3 The trajectory of the impedance angle is illustrated according to this topic when a phase arc fault occurs between phase A and phase B.

[0007] Figure 4 A method for detecting faults in a parallel capacitor bank according to one embodiment of this subject is illustrated. Summary of the Invention

[0008] Embodiments of the present invention relate to a method for detecting faults in a parallel capacitor bank connected to a power system, an apparatus for fault detection, and a computer-readable storage medium including instructions for fault detection. An objective of embodiments of the present invention is to identify phase arcing faults in the capacitor bank within a short time interval, thereby preventing damage to the capacitor bank through early detection of cascading faults in the detection unit.

[0009] According to a first aspect, a method for detecting faults in a parallel capacitor bank connected in a power system is provided. The method includes obtaining voltage and current measurements at one terminal of the parallel capacitor bank. Electrical parameters are calculated based on the voltage and current measurements. The calculated electrical parameters are either impedance angle or active power. Furthermore, a difference between a first and a second value of the electrical parameters is calculated, and a fault is detected based on the difference.

[0010] According to a second aspect, an apparatus for detecting faults in a parallel capacitor bank connected to a power system is provided. The apparatus includes a processor and a fault detection module executable by the processor. The fault detection module is configured to obtain voltage and current measurements at the terminals of the parallel capacitor bank. The fault detection module is configured to calculate electrical parameters based on the voltage and current measurements. The calculated electrical parameters are impedance angle or active power. Furthermore, a difference between a first and a second value of the electrical parameters is calculated, and a fault is detected based on the difference.

[0011] According to a third aspect, a non-transitory computer-readable medium is provided, the non-transitory computer-readable medium containing program instructions that, when executed, cause a device to detect a fault in a parallel capacitor bank connected to a power system.

[0012] According to one embodiment, voltage and current measurements are obtained at the terminals of the parallel capacitor bank in each phase.

[0013] According to another embodiment, the first and second values ​​of the electrical parameter are continuous with each other.

[0014] According to another embodiment, detecting the fault includes determining whether a predefined criterion is met. The predefined criterion includes that the absolute value of the sum of the difference between a first and a second value of the electrical parameter of a first phase and the difference between the first and a second value of the electrical parameter of a second phase is greater than the difference between the first and a second value of the electrical parameter of a third phase, and that the absolute values ​​of the differences between the first and second values ​​of the electrical parameter of the first phase and the absolute values ​​of the differences between the first and second values ​​of the electrical parameter of the second phase are each greater than a corresponding threshold.

[0015] According to another embodiment, the fault is detected as an interphase fault between the first phase and the second phase of the phase.

[0016] According to another embodiment, the corresponding threshold of the electrical parameter is set based on the accuracy of the measuring equipment.

[0017] According to another embodiment, the parallel capacitor bank is connected to the three-phase transmission line in a double-Y configuration.

[0018] According to another embodiment, the fault is detected before the cascaded fault of the parallel capacitor bank.

[0019] According to another implementation, the arc resistance is calculated based on the Warrington formula to determine the electrical parameters. Detailed Implementation

[0020] This topic relates to fault detection in parallel capacitor banks connected to a power system. The fault can be an arc-over within the capacitor bank, occurring between phases.

[0021] During a phase arcing fault in an SCB (such as a capacitor element failure or a rack flashover caused by a short circuit on the same single or multiple series-connected units), a protection scheme can activate an alarm to notify the operator of a potential parallel capacitor bank failure. Tripping of this bank helps minimize damage and prevents the possible rapid cascading of faults caused by other faulty components / units. Therefore, it is desirable to detect phase arcing faults for a short duration to avoid cascading faults in the SCB.

[0022] Typically, in one technique, the magnitude and peak value of the current are used to detect arcing faults in parallel capacitor banks. This current-magnitude-based method may fail during system disturbances that may occur near the capacitor bank. Another technique detects ground-to-ground arcing faults based on the third harmonic present in the voltage signal. However, this technique cannot detect phase arcing faults. Yet another technique uses the magnitude of the negative-sequence current to detect arcing faults. However, this technique is sensitive to external disturbances and requires coordination with other protection systems in the power system, which introduces a delay of 15-20 power cycles. Furthermore, setting up the operational level of a negative-sequence current-based detection technique is complex.

[0023] The most effective protection against arcing within a capacitor bank is provided by fast unbalanced relays. While unbalanced trip relays are the most effective protection for arc detection in series sections, neutral voltage type unbalanced relays cannot be relied upon for rack fault protection on capacitor banks (where all three phases are not well separated). In this embodiment, a single ungrounded Y-type capacitor bank with two series groups per phase is considered, where all three phases are mounted on a single steel structure. The phases are stacked on top of each other, allowing an initial fault to occur as an inter-rack phase fault. If grounded, this fault will not cause an imbalance in neutral voltage or neutral current, which would prevent the neutral unbalanced relay from responding. The initial fault may propagate until it becomes severe enough to trigger a time-of-use or transient overcurrent relay. However, considerable damage involving all three phases may exist before the bank trips.

[0024] By constructing parallel capacitor banks so that the phases are well separated in a discrete structure, arcing within the capacitor bank will begin as arcing of a single series group. Such a fault produces very little phase overcurrent. If the unbalanced relay protection scheme fails to operate, increasingly more of the same series group can be involved until the group overcurrent relay trips the group or the fuse blows. This fault is accompanied by severe damage to the group, including numerous blown fuses and broken capacitor cells. Instantaneous overcurrent relays are generally not effective for rack faults due to their high required settings.

[0025] For example, based on the magnitudes of voltage and current, the performance of various protection schemes for a 10MVAr, 52kV externally fuse-grounded double Y-connected capacitor bank with parameters as described in Table 1 is analyzed.

[0026] Table 1: Parameters of SCB used for fault analysis

[0027]

[0028] Figure 1 An exemplary arrangement of capacitor cell 101 in the SCB is illustrated, and the results of the analysis are shown in Table 2, where the fault location for each unit value is represented by 'm'. The value of 'm' can vary between '0' and '1', where '0' indicates the fault location of a phase arc fault at the top of SCB 102, and '1' indicates the fault location of a phase arc fault at the bottom of SCB 104. In this embodiment, phase arc faults at different fault locations (m) are considered. The main protection scheme adopted to trip the relay is to set the overvoltage (0V) to 110% of the rated voltage and the overcurrent (OC) to 135% of the rated current.

[0029] As can be observed from Table 2 below, when a phase arc fault occurs toward the bottom of the SCB (m = 0.875), a voltage rise and fault current magnitude less than the preset values ​​for the detected OV and OC are observed. As a result, the voltage values ​​across the healthy units of the group continue to rise until they reach 110% of the rated voltage before the protective relay trips, which may subsequently lead to cascading faults in the SCB.

[0030] Table 2: Simulation results for interphase arc faults at different fault locations

[0031]

[0032] Furthermore, since the fault is a phase arcing fault, there will be no neutral current due to the imbalance, and therefore, protection schemes based on neutral current will not respond. Additionally, negative-sequence-based protection will introduce a time delay of 15-20 power cycles to allow sufficient coordination between other protection devices for external faults in the power system. Arcing faults between different phases generate very small phase currents and phase overvoltages, and this fault leads to an increase in the voltage of healthy cells. Therefore, it is necessary to protect the capacitor bank from phase arcing faults as early as possible to minimize damage.

[0033] This topic provides a fast and reliable protection scheme for parallel capacitor banks connected to a power system against phase arcing faults. Fault detection is based on the values ​​of three-phase voltage and three-phase current measured at the terminals of the SCB. An example method involves using measuring equipment to obtain the three-phase voltage and three-phase current measurements at the SCB terminals as voltage signals or current signals, respectively. These signals are continuously measured to calculate electrical parameters, such as impedance angle or active power at each phase, or both. Furthermore, the difference between a first and a second value of these electrical parameters is calculated, and this difference is tested against predefined criteria to detect the fault.

[0034] The proposed method and apparatus identify phase arcing faults, also known as inter-rack faults, within a capacitor bank within a short time interval, thereby preventing damage to the capacitor bank through early detection of cascading faults in the unit. The proposed method is insensitive to external system interference, thus improving response time. Furthermore, no additional sensors or hardware are required for arcing fault detection.

[0035] The above and other features, aspects, and advantages of this subject matter will be better explained with reference to the following description and accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the following description to refer to the same or similar parts. Although several embodiments have been described, modifications, adaptations, and other implementations are possible.

[0036] Figure 2 An embodiment of this subject matter is illustrated, including a device for fault detection in an SCB. The power system 200, as shown in the figure, includes three-phase transmission lines, which may be part of a transmission and distribution network. Although the SCB is shown connected to the power transmission lines for discussion purposes, it should be understood that the teachings of this subject matter can also be applied to SCBs connected to other power transmission lines. A parallel capacitor bank 202 may be connected to the power system 200 to provide reactive power support. In one embodiment, the SCB may be a double-Y configuration of the three phases connected to the transmission lines. However, the SCB 202 may have various configurations depending on how the capacitor units can be connected.

[0037] It should be understood that the power system 200 for fault detection may include multiple additional components or devices for monitoring, sensing, and controlling various parameters. These additional components or devices may be associated with parallel capacitor banks and the power system, but are not shown for simplicity. For example, components—such as circuit breakers, sensors, current transformers, voltage transformers, loads connected to the power system, parallel reactors, intelligent electronic devices (IEDs), protective relays, etc.—may be connected.

[0038] The techniques of this subject can be implemented using one or more devices associated with a power system. These devices may include current transformers, voltage transformers, circuit breakers, and devices for detecting fault locations. For example... Figure 2 As shown, device 204 can be configured to receive voltage and current measurements at the terminals of the parallel capacitor bank. Device 204 can be configured to detect faults in the SCB caused by internal interference (such as capacitor element failure or flashover within the rack) and external interference (such as increased harmonic levels or sustained overvoltage). In response to device 204 detecting a fault in the SCB, device 204 can be configured to send a trip signal to the circuit breaker of the parallel capacitor bank 202. In one embodiment, device 204 can be a smart electronic device (IED). In another embodiment, device 204 can be any computing device that can receive measurement results from an IED, such as a server, desktop device, laptop computer, etc.

[0039] In one embodiment, this subject matter may be implemented by one or more modules. The modules may be implemented as instructions stored in a non-transitory computer-readable medium and executable by one or more processors. For example, in an embodiment where the method is performed by device 204, the modules are executed by the processor of device 204. Where the method is implemented partly by device 204 and partly by a server, the modules (depending on the steps) will be distributed accordingly across device 204 and the server.

[0040] In one embodiment, device 204 may be configured to receive input measurement signals from various measuring devices (such as current transformers, voltage transformers, Rogowski coils, or other measuring sensors) connected to a parallel capacitor bank. Device 204 may process the acquired measurement results with the assistance of processor 220. Processor 220 may be implemented as a dedicated processor, a shared processor, or multiple separate processors, some of which may be shared. Device 204 may include memory 226, which may be communicatively connected to processor 220. Among other capabilities, processor 220 may retrieve and execute computer-readable instructions stored in memory 226. In one embodiment, memory 226 may store fault detection module 222. In other embodiments, fault detection module 222 may be external to memory 226. Memory 226 may include any non-transitory computer-readable medium—including, for example, volatile memory (such as RAM) or non-volatile memory (such as EPROM, flash memory, etc.).

[0041] Furthermore, device 204 may include an output interface 224 to transmit results obtained from fault detection module 222 to, for example, a server. In one embodiment, when the method is implemented at a server, device 204 may transmit current and voltage measurement results to the server via output interface 224. Output interface 224 may include a variety of computer-readable instruction-based interfaces and hardware interfaces that allow interaction with other communication, storage, and computing devices such as network entities, web servers, databases and external repositories, and peripheral devices. In one embodiment, fault detection parameters, current and voltage measurement results, etc., may be viewed on a display connected to output interface 224 or integrated with device 204.

[0042] In operation, to detect a phase arcing fault in a parallel capacitor bank 202 connected to the power system 200, the processor 220 of device 204 executes the fault detection module 222 to obtain voltage and current measurements at one terminal of the parallel capacitor bank 202. In one embodiment, the voltage and current measurements are obtained at each phase at the terminal of the parallel capacitor bank 202. As will be understood, one or more measuring devices associated with the terminal can be used to obtain the voltage and current measurements. Based on the voltage and current measurements, the processor 220 can calculate electrical parameters. In one embodiment, the electrical parameter may be active power. In another embodiment, the electrical parameter may be impedance angle. Faults can be detected based on the calculated active power, impedance angle, or both. In one embodiment, the detected fault may be a phase arcing fault.

[0043] In one embodiment, the apparent power flow during a phase arc fault, which is a combination of active and reactive power, and the arc resistance can be calculated first. In one embodiment, the arc resistance during the arc fault can be considered zero. In another embodiment, the arc resistance during the arc fault can be calculated, as will be discussed later. For discussion purposes, a fault between phases A and B is considered as one embodiment, and the apparent power at the time of the fault can be calculated as explained below. Equations (1) and (2) depict the apparent power in phases A and B.

[0044]

[0045]

[0046] in,

[0047] S A It is the apparent power of phase A, and

[0048] S B It is the apparent power of phase B.

[0049] V A The voltage measured at phase A

[0050] I A The current is measured at phase A.

[0051] V B The voltage measured at phase B

[0052] I B The current is measured at phase B.

[0053] In addition, V A and I A The phase angle between them can be expressed as And V B and I B The phase angle between them can be expressed as Consider a phase arc fault located at the m-th small portion of a capacitor cell between phases A and B, where 'm' represents the fault location. A and I B The value can be calculated by processor 220 using the superposition theorem, a method known in the art, to give equations (3) and (4):

[0054]

[0055]

[0056] in,

[0057] m is the fault location, and

[0058] X is the reactance of each phase of the capacitor bank.

[0059] In addition, in V A =V<0 0 and V B =V<120 0 —where V is the RMS value of the phase-to-ground voltage—and when Ia and Ib are substituted into equations 1 and 2 respectively, we obtain equations (5) and (6) as shown below.

[0060]

[0061]

[0062] Similarly, if a phase arc fault between phases B and C is considered, the apparent power in phases B and C is calculated using equations (7) and (8) respectively, as shown below:

[0063]

[0064]

[0065] From the above equations, it can be understood that during the normal operation of the power system 200, i.e., when the value m = 1, the active power will be 0, and only the expression (-V) can be used. 2 The reactive power calculated by / X) flows into the power system 200. Unless there is an internal resistance in the SCB, the SCB only supplies reactive power to the power system 200. During any fault, i.e., when the value of m is less than 1, an active power flow between phases can be observed. Based on this active power flow, predefined criteria can be set to detect phase arcing faults. In one embodiment, the predefined criteria can be stored in memory 226, and processor 220 can execute fault detection module 222 to detect phase arcing faults between the first phase and the second phase of the phase based on the predefined criteria.

[0066] An ideal capacitor bank consumes no active power and only supplies reactive power to the power system 200. In one embodiment, under practical conditions, the SCB may consume a negligible amount of active power due to contact resistance or leakage current through the capacitor. However, when the SCB has a phase arcing fault, the amount of active power flowing through the SCB will no longer be negligible. In one embodiment, the fault detection module 222 can calculate the active power flow during the pre-fault condition and at the time of the fault to detect the fault. In another embodiment, the fault detection module 222 can calculate the impedance angle during the pre-fault condition and at the time of the fault to detect the fault. In yet another embodiment, the fault detection module 222 can calculate both the active power flow and the impedance angle for fault detection.

[0067] In one example method, the change in active power flow can be calculated by determining the difference between two consecutive active power calculations, based on each voltage and current measurement in each phase. In one embodiment, the difference between a first and a second value of the active power calculation can be represented as 'ΔP'. The value of ΔP can be calculated for all three phases and verified using predefined criteria as depicted in Table 3 to detect phase arcing faults.

[0068] Table 3: Predefined standards for fault detection

[0069]

[0070] As can be understood from the table above, when the absolute value of the sum of the differences between the first and second active power calculation values ​​of each phase in the first and second phases of the phase is greater than or equal to the difference between the first and second active power calculation values ​​of the third phase of the phase, and the absolute value of the difference between the first and second active power calculation values ​​of each phase in the first and second phases of the phase is greater than a threshold, the fault detection module 222 determines that a phase arc fault has been detected between the first and second phases of the phase. The first phase of the phase can be any one of phases A, B, and C; the second phase of the phase can be a different phase among phases A, B, and C; and the third phase of the phase can be the third phase among phases A, B, and C. The threshold can be set based on the accuracy of the measuring equipment used.

[0071] Similarly, the fault detection module 222 can be configured to detect faults based on the impedance angle. When the SCB only supplies reactive power to the system, the impedance angle is always close to 90 degrees under normal operation. Figure 3 The diagram illustrates the impedance angle trajectory according to this topic when a phase arcing fault occurs between phases A and B. However, when a phase arcing fault occurs between capacitor cells within a capacitor bank, the impedance angle will no longer be 90 degrees. Continuing on... Figure 2 In the discussion, the processor 220 can calculate the impedance angle based on Equation (9) or (10) shown below:

[0072]

[0073]

[0074] where

[0075] <Vph and <Iph are the phase angles of the voltage measurement result and the current measurement result respectively, and

[0076] P Ph and Q Ph are the phase angles of the measured active power and reactive power.

[0077] Based on each voltage measurement result and current measurement result in each phase, the change in the impedance angle between the fault condition and the pre-fault condition can be calculated by calculating the difference between the first value and the second value of the impedance angle. In one embodiment, the difference between the first value and the second value of the impedance angle can be expressed as The value of can be calculated for all three phases and the value can be verified using the predefined criteria depicted in Table 4 to detect an internal arc fault.

[0078] Table 4: Predefined Criteria for Fault Detection

[0079]

[0080] As can be understood from the above table, when the absolute value of the sum of the difference between the first value and the second value of the impedance angle of the first phase in the phase and the difference between the first value and the second value of the impedance angle of the second phase in the phase is greater than or equal to the difference between the first value and the second value of the impedance angle of the third phase in the phase and the absolute value of the difference between the first value and the second value of the impedance angle of each of the first phase and the second phase in the phase is greater than the threshold, the fault detection module 222 determines that a phase arc fault between the first phase and the second phase in the phase has been detected. The first phase in the phase can be any one of phases A, B, and C, the second phase in the phase can be a different one of phases A, B, and C, and the third phase in the phase can be the third phase of phases A, B, and C. The threshold can be set based on the accuracy of the measurement equipment used.

[0081] Although the above calculations can be performed with zero arc resistance, arc faults are usually accompanied by some resistance, and the Warrington formula can be used to determine the arc resistance for performing the above calculations, as discussed below. The arc resistance value can be derived from the Warrington formula, as depicted in equation (11).

[0082]

[0083] in,

[0084] L is the length of the arc, which is the distance between the faulty racks of phase A and phase B, or phase B and phase C.

[0085] I is the root mean square (RMS) value of the current flowing through the electric arc.

[0086] Considering that a phase arc fault has occurred between phases AB or BC, the current flowing through the arc can be calculated using equation (12) shown below:

[0087]

[0088] in,

[0089] X is the capacitive reactance of each phase.

[0090] In addition, in the examination And when we substitute it into equation (12), we get:

[0091]

[0092] Substituting equation (13) into equation (11), we obtain:

[0093]

[0094] Consider Q as the rated MVAR of a dual Y-connected capacitor bank, where Q is described by the following expression:

[0095]

[0096] Furthermore, when substituting the above expression into equation (14), we obtain:

[0097]

[0098] The calculated arc resistance can then be used to determine reactance and calculate fault location, as discussed above.

[0099] Therefore, this topic provides efficient phase arc fault detection in parallel capacitor banks connected to a power system. The proposed fault determination technique can be implemented to detect phase arc faults between phases of the SCB for a short duration before the cascading fault of the capacitor cell begins.

[0100] Figure 4 A method for detecting faults in a parallel capacitor bank according to one embodiment of this subject matter is illustrated. The order in which methods 400 are described is not intended to be construed as limiting, and some of the method blocks described may be performed in a different order to implement method 400 or an alternative method. Furthermore, method 400 can be implemented in any suitable hardware, computer-readable instructions, firmware, or a combination thereof. For discussion, see references. Figure 2 The method 400 is described using the embodiments illustrated herein.

[0101] In method 400, at block 402, voltage and current measurements are obtained at one terminal of a parallel capacitor bank. The voltage and current measurements are obtained in each phase at the terminal of the parallel capacitor bank. The voltage and current measurements are obtained using one or more measuring devices associated with the terminal of the parallel capacitor bank. In one embodiment, the voltage and current measurements are fed to device 204.

[0102] At box 404, electrical parameters are calculated based on the voltage and current measurements. These electrical parameters correspond to either the impedance angle or active power. The electrical parameters are calculated for each new voltage and current measurement.

[0103] At block 406, the difference between a first value and a second value of the electrical parameter can be calculated. In one embodiment, the first and second values ​​of the electrical parameter are continuous with each other. The difference between the first and second values ​​of the electrical parameter for each voltage measurement and current measurement in each phase can be calculated, and the difference is stored in memory 226.

[0104] At block 408, a fault is detected based on the difference between a first value and a second value of the electrical parameter. In one embodiment, the fault detection may be based on a predefined standard. In one embodiment, the predefined standard may be based on the difference between a first value and a second value of the electrical parameter for each voltage measurement and current measurement in each phase, and the predefined standard may be stored in memory 226.

[0105] In one embodiment, the predefined standard may be that a fault can be detected when the absolute value of the sum of the difference between the first and second values ​​of the electrical parameters of the first phase and the difference between the first and second values ​​of the electrical parameters of the second phase is greater than the difference between the first and second values ​​of the electrical parameters of the third phase, and the absolute values ​​of the differences between the first and second values ​​of the electrical parameters of the first phase and the second phase are each greater than a corresponding threshold.

[0106] The thresholds for the predefined criteria can be set based on the accuracy of the measuring equipment. Furthermore, upon detecting a fault in the SCB, device 204 can employ a protection scheme to trip the SCB for a short period to prevent cascading failures of the capacitor cells.

[0107] The methods discussed above can be used to detect phase arcing faults even at lower cells of the capacitor bank, thereby preventing the initiation of cascading faults in the SCB. Simulation results are provided below for a system with L = 471 mm, VL-L = 52 kV, and Q = 10 MVAr, as considered in Table 1 above, and these results are compared with those provided in Table 2. It should be understood that these simulations are provided only as embodiments for verifying this technology and not as limitations.

[0108] Example 1

[0109] In the first embodiment, the fault detection technology was tested using active power as an electrical parameter. The active power flow in different phases was tested for a phase arc fault between phases A and B at different fault locations.

[0110] Considering zero arc resistance, the active power flow in different phases with phase A-phase B type arc faults was simulated, and the active power flow is tabulated in Table 5 as shown below:

[0111] Table 5: Arc faults of phase A-phase B type at different fault locations (with R...) ARC The active power flow in different phases of (=0).

[0112]

[0113] However, since arc faults are usually accompanied by some resistance, the actual arc can be calculated according to equation (15), and the arc resistance and different fault locations can be calculated. Table 6 depicts the arc resistance at different fault locations with an arc length of 471 mm, the system having a line-to-line voltage of 52 kV and a reactive power of 10 MVAr.

[0114] Table 6: Calculation of arc resistance at different fault locations.

[0115]

[0116] Furthermore, for phase arc faults between phases A and B, with arc resistances as depicted in Table 6, fault detection techniques were tested for active power flows in different phases. Active power flows in different phases with phase A-phase B type arc faults and a single arc resistance are tabulated in Table 7 below:

[0117] Table 7: Arc faults in phase A-phase B at different fault locations (according to Warrington's formula, R...) ARC The active power flow in different phases.

[0118]

[0119] As can be observed from Tables 5 and 7, for arc faults in phase A-phase B at different fault locations, the predefined standard |ΔP A +ΔP B |=>ΔP C &&(|ΔP A |>P Set )&&(|ΔP B |>P Set The active power-based method, even at lower fault locations opposite to those in Table 2, helps to accurately detect faults. For this embodiment, the threshold P... Set It was set to 2%.

[0120] Example 2

[0121] In the second embodiment, the fault detection technique was tested using the impedance angle as an electrical parameter. The impedance angle in different phases was tested for rack-type faults between phases A and B at different fault locations.

[0122] Considering zero arc resistance, the impedance angles in different phases with phase A-phase B type arc faults have been tabulated in Table 8 below:

[0123] Table 8: Arc faults of phase A-phase B type at different fault locations (with R...) ARC The impedance angles of different phases of (=0).

[0124]

[0125] Fault detection was also simulated based on the calculated arc resistance depicted in Table 6 above. Furthermore, the impedance angles for fault detection for different phases with arc resistances depicted in Table 6 for arc faults of phase A-phase B type have been tabulated in Table 9 below:

[0126] Table 9: Arc faults of phase A-phase B type at different fault locations (according to Warrington's formula, R...) ARC The impedance angle for different phases.

[0127]

[0128]

[0129] As can be observed from Tables 8 and 9, for arc faults in phase A-phase B at different fault locations, a predefined standard is used. The impedance angle-based method helps to accurately detect faults, even at lower fault locations, contrary to those in Table 2. For this embodiment, the threshold... It was set to 1 degree.

[0130] When comparing the results of Examples 1 and 2 for phase arc faults at different fault locations with the results of protection schemes based on voltage and current values ​​as shown in Table 2, it can be observed that when a fault occurs at the lower cell of the capacitor bank (m = 0.875), it can trigger cascading faults when overcurrent or overvoltage is used. However, cascading faults can be avoided using active power-based methods, impedance angle-based methods, or both for fault detection.

[0131] Therefore, the methods and apparatus of this subject matter can detect phase arcing faults in parallel capacitor banks within a short time interval and can be reliably implemented to avoid cascading failures of capacitor units and subsequent damage to the power system.

Claims

1. A method for detecting faults in a parallel capacitor bank connected in a power system, the method comprising: Voltage and current measurements were obtained at the terminals of the parallel capacitor bank. Electrical parameters are calculated based on the voltage measurement results and the current measurement results, wherein the electrical parameters are impedance angle or active power; Calculate the difference between the first and second values ​​of the electrical parameters of the multiple phases; as well as The fault is detected based on the difference, wherein detecting the fault includes determining whether a predefined criterion is met, wherein the predefined criterion includes: The absolute value of the sum of the difference between the first and second values ​​of the electrical parameters of the first phase and the difference between the first and second values ​​of the electrical parameters of the second phase is greater than the difference between the first and second values ​​of the electrical parameters of the third phase; and The absolute value of the difference between the first and second values ​​of the electrical parameters of the first phase in the phase and the absolute value of the difference between the first and second values ​​of the electrical parameters of the second phase in the phase are each greater than a corresponding threshold.

2. The method according to claim 1, wherein, Voltage and current measurements are obtained at each phase of the parallel capacitor bank at its terminals.

3. The method according to claim 1 or 2, wherein, The first and second values ​​of the electrical parameter are continuous with each other.

4. The method according to claim 1, wherein, The fault was detected as an interphase fault between the first phase and the second phase of the phase.

5. The method according to claim 1, wherein, The corresponding threshold for the electrical parameter is set based on the accuracy of the measuring equipment.

6. The method according to claim 1, wherein, The parallel capacitor bank is connected to the three-phase transmission line in a double Y configuration.

7. The method according to claim 1, wherein, The fault is detected before the cascaded fault of the parallel capacitor bank.

8. The method according to claim 1, wherein, The arc resistance is calculated based on the Warrington formula to determine the electrical parameters.

9. An apparatus for detecting faults in a parallel capacitor bank connected to a power system, the apparatus comprising: processor; as well as A fault detection module, which can be executed by the processor, to: Voltage and current measurements were obtained at the terminals of the parallel capacitor bank. Electrical parameters are calculated based on the voltage measurement results and the current measurement results, wherein the electrical parameters are impedance angle or active power; Calculate the difference between the first and second values ​​of the electrical parameters of the multiple phases; as well as The fault is detected based on the difference, wherein the fault detection module is operable to detect the fault based on meeting predefined criteria, wherein the predefined criteria include: The absolute value of the sum of the difference between the first and second values ​​of the electrical parameters of the first phase and the difference between the first and second values ​​of the electrical parameters of the second phase is greater than the difference between the first and second values ​​of the electrical parameters of the third phase; and The absolute value of the difference between the first and second values ​​of the electrical parameters of the first phase in the phase and the absolute value of the difference between the first and second values ​​of the electrical parameters of the second phase in the phase are each greater than a corresponding threshold.

10. The device according to claim 9, wherein, Voltage and current measurements are obtained at each phase of the parallel capacitor bank at its terminals.

11. The device according to claim 9 or 10, wherein, The first and second values ​​of the electrical parameter are continuous with each other.

12. The device according to claim 9, wherein, The fault was detected as an interphase fault between the first phase and the second phase of the phase.

13. The device according to claim 9, wherein, The corresponding threshold for the electrical parameter is set based on the accuracy of the measuring equipment.

14. The device according to claim 9, wherein, The parallel capacitor bank is connected to the three-phase transmission line in a double Y configuration.

15. The device according to claim 9, wherein, The fault detection module is configured to detect the fault before a cascade fault occurs in the parallel capacitor bank.

16. The device according to claim 9, wherein, The fault detection module is configured to calculate the arc resistance based on the Warrington formula in order to determine the electrical parameters.

17. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 8.

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