Isolated dc-dc power converter with low emission

Abstract

An example DC-DC power converter circuit includes an H-bridge switching circuit (103) operatively coupled with a transformer (T1). The switching circuit (103) is compensated to account for parasitic differences between the high side (power supply) and the low side (ground). For example, PMOS transistors (Q1 and Q2) connected to the high side are sized larger to substantially match the on-resistance of NMOS transistors (Q3 and Q4) connected to the low side (e.g., such that the on-resistances are both within tolerance of each other), and the NMOS transistors (Q3 and Q4) include additional gate-drain capacitances (C1 and C2) to substantially match the gate-drain capacitances of the larger PMOS transistors (e.g., such that the gate-drain capacitances are both within tolerance of each other, or within tolerance of a target gate-drain capacitance value). Additionally, the transformer (T1) is configured with physical symmetry such that the inductance and capacitance midpoints of the transformer are substantially co-located.

Description

Technical Field

[0001] This specification relates to isolated DC-DC power converters, and more specifically to techniques for reducing radiated emissions in integrated isolated DC-DC power converters. Background Technology

[0002] Electromagnetic compatibility (EMC) standards set limits on electromagnetic interference (EMI) in electrical and electronic equipment. For example, these standards define the frequency range and maximum permissible amplitude of accidental radiated emissions to prevent such emissions from interfering with the intended operation or emissions of other equipment and systems, such as communication equipment that uses allocated frequency ranges for radio frequency communication. While there are many EMC standards across various industries, one widely recognized standard is known as the International Special Committee on Radio Interference (CISPR), which is part of the broader International Electrotechnical Commission (IEC).

[0003] Commercial products and technologies must comply with relevant EMC standards. Such compliance can be particularly challenging as form factors continue to shrink proportionally. For example, a relatively new area of ​​electronics involves integrating transformers and supporting circuitry into integrated circuit packages. On the one hand, integrating a given transformer and its associated circuitry into an integrated circuit package can result in significant space savings on the printed circuit board (PCB) that houses the integrated transformer. On the other hand, such integrated transformers often introduce higher radiated emissions. One possible way to reduce radiated emissions is to connect so-called stitched capacitors between the primary and secondary windings. This allows common-mode currents to couple across the transformer's current barrier, thus reducing radiated emission levels. Stitched capacitors can be discrete components packed onto the PCB or interlayer capacitors embedded within the PCB itself. Unfortunately, stitched capacitors are prone to reliability issues, especially in applications subjected to electrostatic discharge and other potentially high-voltage transients. Therefore, technologies for reducing radiated emissions are needed. Summary of the Invention

[0004] An integrated isolated DC-DC power converter architecture is described.

[0005] In one example, an integrated circuit includes a transformer and an H-bridge switching circuit. The transformer includes a primary-side inductor and a secondary-side inductor. Each of the primary-side and secondary-side inductors includes a first half-cell portion and a second half-cell portion, the second half-cell portion being a replica of the first half-cell portion except for rotation about an axis. The two half-cell portions are connected to each other to provide corresponding inductance. The H-bridge switching circuit is operatively coupled to the primary-side inductor. The H-bridge switching circuit includes a first transistor and a second transistor of a first polarity, and a third transistor and a fourth transistor of a second polarity. The first transistor, the second transistor, the third transistor, and the fourth transistor have substantially the same on-resistance and substantially the same gate-drain capacitance.

[0006] In another example, an integrated circuit includes a transformer and an H-bridge switching circuit. The transformer includes a primary-side inductor and a secondary-side inductor. Each of the primary-side and secondary-side inductors includes a first portion and a second portion, the second portion being a replica of the first portion except for rotation about an axis. The two portions are connected to each other to provide a corresponding inductance. A fictitious line of symmetry divides each of the primary-side and secondary-side inductors into a corresponding first and second portion. The H-bridge switching circuit is operatively coupled to the primary-side inductor. The H-bridge switching circuit includes a first transistor and a second transistor of a first polarity, and a third transistor and a fourth transistor of a second polarity. The first, second, third, and fourth transistors each have an on-resistance within a 10% tolerance of the same target on-resistance, and a gate-drain capacitance within a 10% tolerance of the same target gate-drain capacitance.

[0007] In another example, an integrated circuit includes a transformer, a rectifier, a supply network, and an H-bridge switching circuit. The transformer includes a primary-side inductor and a secondary-side inductor, wherein a fictitious line of symmetry divides each of the primary-side and secondary-side inductors into a first portion and a second portion. The rectifier is operatively coupled to the secondary side of the transformer and includes a plurality of diodes arranged and connected symmetrically about the line of symmetry. The supply network includes a voltage supply portion and a ground portion, wherein the voltage supply portion is symmetrical to the ground portion about the line of symmetry. The H-bridge switching circuit is operatively coupled to the primary-side inductor. The H-bridge switching circuit includes a first p-type metal-oxide-semiconductor field-effect transistor (MOSFET) and a second p-type MOSFET connected to the voltage supply portion of the supply network, and a third n-type MOSFET and a fourth n-type MOSFET connected to the ground portion of the supply network. The first, second, third, and fourth MOSFETs each have an on-resistance within a 10% tolerance of the same target on-resistance and a gate-drain capacitance within a 10% tolerance of the same target gate-drain capacitance. Furthermore, the first and second portions of the primary-side inductor each have a primary-side feed point, and are symmetrical about the line of symmetry except for portions attributable to the following: the primary-side feed point of one portion of the primary-side inductor is moved to a feed point physically closer to the primary-side feed point of the other portion of the primary-side inductor. Similarly, the first and second portions of the secondary-side inductor each have a secondary-side feed point, and are symmetrical about the line of symmetry except for portions attributable to the following: the secondary-side feed point of one portion of the secondary-side inductor is moved to a feed point physically closer to the other portion of the secondary-side inductor. Attached Figure Description

[0008] Figure 1 An example DC-DC power converter configured with an H-bridge switching circuit and a transformer architecture according to an embodiment of this specification is schematically illustrated.

[0009] Figures 2a-2d The illustrations together depict operational details of H-bridge switching circuits and transformer architectures according to some embodiments of this specification.

[0010] Figure 2e The illustrations show improvements in radiative emissions that can be achieved using H-bridge switching circuits and transformer architectures according to some embodiments of this specification.

[0011] Figures 3a-3b The diagram illustrates an embodiment of this specification with an R configuration between NMOS and PMOS transistors. ds A matching example H-bridge switch circuit.

[0012] Figures 4a-4bThe diagram illustrates a configuration of NMOS and PMOS transistors according to an embodiment of this specification, with C between them. gd A matching example H-bridge switch circuit.

[0013] Figures 5a-5b The diagram illustrates an embodiment of this specification with an R configuration between NMOS and PMOS transistors. ds and C gd An example H-bridge switch circuit that matches the two.

[0014] Figures 6a-6b The diagrams together illustrate a transformer configured according to an embodiment of this specification.

[0015] Figures 6c-6d Each illustration shows an example layout of the primary or secondary inductor of a transformer configured according to an embodiment of this specification.

[0016] Figures 7a-7d The illustrations together depict an example half-cell formation process and layout of the primary inductor of a transformer configured according to an embodiment of this specification.

[0017] Figures 8a-8d The illustrations together depict an example half-cell formation process and layout of a transformer's secondary inductor configured according to an embodiment of this specification.

[0018] Figure 9 The illustration shows an H-bridge switching circuit and transformer architecture according to another embodiment of this specification. Detailed Implementation

[0019] This document provides techniques for reducing radiated emissions in integrated isolated DC-DC power converters. In embodiments, the isolated power converter includes a driver circuit and a transformer. The driver circuit is implemented on a semiconductor die included in an integrated circuit package, which may also include a transformer. For example, in some such cases, the transformer is a laminated transformer also included within the package and wire-bonded to the connection points of the die. The transformer's current barrier provides electrical isolation between the primary side of the converter and the secondary side ground. The driver circuit includes an H-bridge switching circuit and a control block operatively coupled to the transformer. The H-bridge switching circuit is compensated to account for parasitic differences between the high side (power supply) and the low side (ground), which allows for symmetrical drive and a stable common-mode voltage across the primary side of the transformer. For example, in some example embodiments, the H-bridge switching circuit is implemented using power MOS transistors, wherein the PMOS transistor connected to the high side is sized larger to match the on-resistance of the NMOS transistor connected to the low side, and the NMOS transistor includes an additional gate-drain capacitance to match the gate-drain capacitance of the PMOS transistor. Furthermore, the transformer is configured with physical symmetry such that the midpoints of the transformer's inductance and capacitance are aligned, which allows for a reduction in common-mode switching current flowing between the two isolated grounds via parasitic capacitances present between the primary and secondary windings of the transformer. The physical symmetry of the power converter can be further applied to the control block and / or supply voltage path to further reduce common-mode voltage peaks and currents. For example, according to some embodiments, the NMOS and PMOS transistors of the H-bridge switching circuit can be driven in a non-overlapping manner by symmetrical drive signals from the control block. In this case, given the physical layout symmetry of their respective signal paths, the drive signals are symmetrical (e.g., physically symmetrical paths experience substantially the same parasitic delay); and given non-overlapping drive circuitry, the drive signals are non-overlapping (e.g., they cannot be high simultaneously). Note that symmetry about the axis relative to the physical layout of the circuit system allows for symmetry relative to the electrical characteristics of the signaling generated by that circuit system (e.g., signal delay, signal rise / fall time, etc.). Thus, for example, if the first signal path of the first drive signal is physically symmetrical to the second signal path of the second drive signal, these first and second drive signals can be considered symmetrical to each other. In any such embodiment, note that having a relatively stable common mode allows for reduced charge transfer across the two grounds, and thus reduced radiative emissions. Numerous example embodiments and configurations will be appreciated in accordance with this specification.

[0020] General Overview As mentioned earlier, there is a need for technologies to reduce radiated emissions, particularly regarding integrated transformers. More specifically, an important and often misunderstood aspect of good industrial system design is proper grounding without ground loops. Depending on the system, ground isolators in the signal path can be used to eliminate ground loops. For example, in the context of a DC-DC converter, the transformer's current barrier electrically isolates the primary-side input voltage and ground from the secondary-side output voltage and ground. However, this arrangement allows common-mode current to be injected across the two isolated grounds via parasitic capacitances present between the primary and secondary windings of the transformer. This current can become asymmetrical due to asymmetry in the signal path, allowing it to manifest at (or multiples of) the switching frequency. Complicating this phenomenon is that the ground plane on the printed circuit board (PCB) on which the integrated circuit, including the transformer, is filled can act as a dipole antenna. This antenna, combined with the behavior of the current flowing between grounds, generates radiated emissions at (or multiples of) the converter's switching frequency. Given the relatively small feature size of an integrated transformer, the associated inductance and capacitance values ​​are relatively low, which in turn allows for relatively high switching frequencies (e.g., tens to hundreds of MHz) to transfer power from the primary to the secondary. Such radiated emissions may conflict with EMC standards or otherwise cause undesirable interference.

[0021] To this end, a DC-DC power converter architecture is provided herein, configured to maintain a relatively stable common-mode voltage across the primary inductor of the converter. In an embodiment, this architecture includes a parasitic compensated H-bridge switching circuit operably coupled to a transformer that is physically symmetrical about the axis (although a relatively small degree of asymmetry attributable to feed point alignment and / or feed line differences, such as reference...). Figures 6c-6d , Figures 7a-7d and Figures 8a-8d (Further described). This architecture is particularly useful in reducing charge transfer between the current barrier across the transformer and the isolation ground plane, which in turn reduces radiated emissions from the converter. Because the architecture is implemented at a local level (e.g., the integrated circuit package and / or die level) rather than a global level (e.g., the system level), it is system-independent. Therefore, this architecture allows for reduction of radiated emissions at the source without requiring a system-level solution.

[0022] In example embodiments, the integrated circuit including the DC-DC power converter is configured with a metal-oxide-semiconductor (MOS) H-bridge switching circuit operatively coupled to a transformer. The H-bridge switching circuit can be implemented on a semiconductor die included within a package of the integrated circuit. In some such cases, the transformer is a laminated transformer included within the integrated circuit package and wire-bonded or otherwise interconnected to connection points on the die. In other cases, the transformer can be part of the die or external to the integrated circuit package, such as on and / or within a PCB to which the integrated circuit package is attached. In any such case, the transformer is symmetrical because the midpoints of the transformer's inductance and capacitance are co-located or otherwise substantially located in the same geometric position (meaning the midpoints coincide spatially in all three dimensions, although perfect co-location is not required), rather than being spaced apart as in asymmetrical transformer designs. One example of a symmetrical configuration includes a case where the primary and secondary windings are each implemented with figure-eight inductors placed on opposite sides of an intermediate laminate (a dielectric material used to electrically isolate the primary side from the secondary side). When the midpoints of the inductor and capacitor are not aligned (as in the case of a spiral inductor), unbalanced current flows across the parasitic capacitance between the primary and secondary windings, and thus flows between the two isolated grounds, resulting in radiative emissions.

[0023] For example, an H-bridge switching circuit can be implemented using power MOS field-effect transistors (MOSFETs), although it would be understandable that other suitable transistor technologies (e.g., bipolar junction transistors, BJTs) may be used depending on the specific requirements of a given application. In any such case, the H-bridge switching circuit is parasitic compensated. More specifically, and according to some such embodiments, the connection to the high side (primary-side power supply, such as V) is... CC The size of the P-channel MOS (PMOS) transistor is set to be larger (e.g., 3.3 times) to match the on-resistance (R0) of the N-channel MOS (NMOS) transistor connected to the low side (primary side ground). ds In addition, the low-side NMOS transistor includes an additional gate-drain capacitor to match the gate-drain capacitance (C) of the high-side PMOS transistor. gdThis parasitic matching between the PMOS and NMOS power transistors in the H-bridge switching circuit helps reduce the common-mode voltage peaks appearing across the transformer at the switching frequency or its multiples. Furthermore, since the drive signals applied to the parasitic-compensated H-bridge switching circuit are non-overlapping (not both high), the resulting drive signals applied to the primary side of the transformer are also non-overlapping. Specifically, the drive signals applied to the transformer rise and fall differentially, ensuring that the two drive signals are never in the same state (both high or both low). As a result of the parasitic-compensated H-bridge switching circuit, when the converter switches at the switching frequency to transfer power from the primary side to the secondary side, the common-mode voltage of the transformer does not change or remains relatively stable in other ways (such as reference voltage). Figure 5b The example described is where the common-mode peak voltage is within the desired threshold. For example, this contrasts with a cross-coupled driver, in which the drive signal applied to the transformer can be high simultaneously, albeit briefly, which in turn generates an asymmetrical current through the parasitic capacitance between the primary and secondary windings, which in turn produces radiated emissions at or multiples of the switching frequency.

[0024] In some embodiments, physical symmetry can be applied to other parts of the signal chain of the power converter to maintain a more stable common-mode voltage even in noisy environments. For example, in one such embodiment, the power converter also includes a control block operatively coupled to the H-bridge switching circuit, a diode rectifier operatively coupled to the secondary side of the transformer and used to provide the converter's output, and a hysteresis comparator operatively coupled across the output. In some such embodiments, the control block includes digital controls, non-overlapping drivers, and pre-drivers, all of which can be implemented in a half-cell manner to be physically symmetrical about a given axis. The digital controls are programmed or otherwise configured to control the switching of the H-bridge switching circuit to drive the transformer based on feedback from the hysteresis comparator on the rectifier side. The non-overlapping driver generates NMOS and PMOS drive signals from the control signals generated by the digital controls. The pre-driver buffers the drive signals from the non-overlapping driver and drives the gates of the NMOS and PMOS power FETs of the H-bridge switching circuit with optimized or otherwise sufficient drive strength. Given a non-overlapping driver, the drive signals are non-overlapping (e.g., they cannot be high simultaneously). Furthermore, given the layout symmetry of the corresponding signal paths of the drive signals (e.g., the two paths experience substantially the same parasitic delay), the drive signals can be considered symmetrical. For this purpose, control blocks can be laid out symmetrically (e.g., using half-cell design principles) to provide substantially equal delays in the two polarity drive signals. In any such case, and as previously mentioned, reducing common-mode variation helps reduce charge transfer across the isolation ground plane and radiated emissions. In some such example embodiments of this specification, symmetry can be maintained throughout the entire signal chain of the power converter, starting with the digital controls and non-overlapping drivers, and continuing to the pre-driver, H-bridge switching circuit, laminated transformer, and rectifier.

[0025] Further embodiments may include further symmetry features. For example, the bond wire and trace lengths of the voltage supply and ground paths may be arranged symmetrically to provide symmetrical feed paths to the inverter and rectifier circuitry. This symmetry helps to reduce out-of-phase noise (e.g., (V... CC+GND) / 2) remains at a constant level. Similarly, the rectifier can be arranged symmetrically. Furthermore, decoupling capacitors can be symmetrically connected between the power supply and ground on one or both of the primary and secondary sides to help reduce power supply noise. As will be understood with reference to this specification, lower power supply noise is desirable because any power supply noise can couple to the transformer if an asymmetry exists in the power converter design, resulting in higher radiated emissions. Therefore, decoupling capacitors can be used, for example, in cases where the input and / or output power supplies are relatively noisy. Additionally, some embodiments include compensation to counteract parasitics introduced by asymmetry. For example, some configurations may experience parasitic capacitances associated with the primary and secondary die attachment pads (priDAP and secDAP). For example, this parasitic capacitance can manifest between two isolation grounds. In this case, an additional capacitor can be added between the isolation voltage supplies as a symmetrical balance to this parasitic capacitance.

[0026] As will be understood, the term "half-cell section" or "layout" as used herein refers to the layout of half of a given circuit or cell. For example, a given cell can be a single component such as an inductor, a multi-part component such as a transformer, or an entire circuit or sub-circuit such as a digital control block. In a more general sense, a cell can be any circuit that can be halved during the design and layout phases of that particular circuit using circuit layout tools. Once the half-cell is laid out, the other half of the cell is a mirror image that can be automatically generated by the layout tool used to generate the first half of the cell. As will be further understood with reference to this specification, the reason for using half-cell layouts is, for example, to maintain similar parasitics (e.g., routing resistance, routing inductance, and routing capacitance) for the two drive branches of a transformer, and to reduce the common-mode switching current passing between the two isolation grounds via parasitic capacitances present between the primary and secondary sides of the transformer. Of course, in the real world, a perfect match between one half-cell and the other is not necessary. Therefore, the use of "half-cell," "half-cell section," "replica," or "copy" herein does not limit this specification to two perfectly matched halves. Rather, reasonable similarity-tolerance can be used to accommodate real-world process constraints. For example, minor differences may arise between two half-cell inductor sections or two half-cell circuit sections formed by the same process, and these minor differences have a negligible impact on radiated emissions, or otherwise remain within acceptable limits for a given EMC standard. Similarly, as will be understood from this specification, deliberate deviations from similarity can be used to accommodate layout preferences and design constraints that result in relatively small asymmetries between half-cells. For example, a relatively small degree of asymmetry between half-cell sections of a transformer inductor can be achieved by moving one of the inductor's feed points to allow the inductor's feed points to be on the same side and to allow for symmetry in the feed lines to those feed points (e.g., as will be referenced). Figures 7a-7d and Figures 8a-8d As described herein, the degree of matching between one half-unit and the other half-unit may vary slightly for a given component or circuit, but still allows for a relatively high degree of symmetry, which in turn reduces radiative emissions to acceptable limits for a given EMC standard, as described differently in this paper.

[0027] Circuit architecture Figure 1 An example power converter with a symmetrical switching bridge and transformer architecture configured according to an embodiment of this specification is schematically illustrated. It can be seen that the power converter in this example case is a DC-DC converter and includes a control block 101, an H-bridge switching circuit 103, a rectifier 105, and a hysteresis comparator 107. A transformer T is operatively coupled between the H-bridge switching circuit 103 and the rectifier 105. The control block 101 includes digital controls 102, non-overlapping drivers 104a and 104b, and a pre-driver 106. Further, it can be seen that the H-bridge switching circuit 103 in this example is implemented using power MOS technology and includes two P-channel MOSFETs (Q1 and Q2) connected to the high side (V) and two N-channel MOSFETs (Q3 and Q4) connected to the low side (GND). The H-bridge switching circuit 103 is also configured with additional features including capacitors C1-C6 and capacitor CP. The rectifier 105 includes diodes D1-D4 and capacitor CS. In other embodiments, these capacitors may be integrated with the transformer T1. Capacitor C7 is connected in the feedback path between hysteresis comparator 107 and control block 101. Each of these components will be described further in turn. The power converter can be implemented as an integrated circuit, wherein at least some portions of the power converter circuitry (e.g., 101, 103, 105, and 107) are formed on a semiconductor die using standard or proprietary process technologies and materials, as will be understood. As previously mentioned, transformer T1 can be separate from the die and operatively coupled to it. In this case, both the chip and the transformer can be bonded to the integrated circuit package.

[0028] In operation, the power converter converts the input voltage (V) to the output voltage (VISO). Note that the input voltage V is referenced to a first ground (GND), and the output voltage VISO is referenced to a second ground (GISO). The first and second grounds are isolated from each other via a current barrier of transformer T1. An example embodiment includes converting a 5-volt input to an isolated 5-volt output (5Vin 5Vout), although any input / output voltage scheme can be used, as will be understood. In this particular example, digital control 102 reacts based on feedback received from a hysteresis comparator 107 operably coupled across the output of rectifier 105 and is configured to generate control signals that control the switching of H-bridge switching circuit 103 to drive transformer T1. Non-overlapping drivers 104a and 104b derive symmetrical drive signals (pulses) from the control signals generated by digital control 102, and pre-drivers 106a-106d amplify or otherwise buffer these symmetrical drive signals to drive the respective gates of the MOSFETs (Q1, Q2, Q3, and Q4) of H-bridge switching circuit 103 with sufficient drive strength. Hysteresis comparator 107 senses the converter output and load conditions and generates feedback, which digital control 102 can respond to when generating control signals.

[0029] According to some embodiments of this specification, each of the control block 101, rectifier 105, and hysteresis comparator 107 can be implemented using either standard or proprietary technology, except that they can also be implemented with a degree of layout symmetry. For example, in some such embodiments: digital control 102 is a standard 2-state (on-off) architecture driving the power stage (H-bridge switching circuit and transformer T1); non-overlapping drivers 104a-104b are standard circuits that generate 180-degree phase-separated clock signals in response to control signals from digital control 102; and pre-driver 106 is a standard driver. In this case, control block 101, H-bridge switching circuit 103, transformer T1, rectifier 105, and hysteresis comparator 107 operate together to provide a hysteresis DC-DC converter that uses a standard 2-state digital control architecture to drive the power stage. Various configurations can be used, and this specification is not limited to any particular control block, as will be understood.

[0030] According to embodiments of this specification, the components and conductive lines of control block 101 are arranged in a half-cell manner to ensure equal delays in the two drive signals. This symmetrical arrangement can also be applied to the components and conductive lines constituting each of 103, 105, and 107. Depending on the requirements of a given application, different embodiments may have varying degrees of symmetry when used in conjunction with the parasitic-compensated H-bridge switching circuit 103. For example, with respect to control block 101, fictitious lines of symmetry passing through the circuit (such as...) Figure 1(Represented by a dashed line passing through control block 101), such that the component portions and conductive lines constituting the non-overlapping drivers 104a and pre-drivers 106a-106b are above the line of symmetry in a specific layout configuration. This configuration provides a first half-unit of the symmetrical control block 101. The second half-unit can be a flipped version of the same layout configuration (flipped about the line of symmetry) to provide the non-overlapping drivers 104b and pre-drivers 106c-106d. The corresponding conductive lines from digital control 102 to the corresponding non-overlapping drivers 104a-104b can also be laid out symmetrically about the line of symmetry in a balanced manner, just like the circuit system constituting digital control 102 itself, to be substantially perfectly symmetrical.

[0031] The H-bridge switching circuit 103 is parasitic compensated to adjust for polarity-based parasitic differences between p-type and n-type transistors, as shown in the reference. Figures 2a-5b Further description. Transformer T1 has a physically symmetrical configuration such that the midpoints of its capacitance and inductance are substantially congruent. In some example cases, each of the primary and secondary inductors includes a first half-cell portion and a second half-cell portion, the second half-cell portion being a replica of the first half-cell portion except that it rotates about an axis, and the two half-cell portions are connected at the point that serves as the midpoint of the capacitance and inductance of the inductor (e.g., reference...). Figures 6c-6d , Figures 7a-7d and Figures 8a-8d The example inductor and transformer configuration shown is further described. Any asymmetry in this inductor is relatively small and can be attributed to, for example, real-world process limitations or feeder differences (such as...). Figures 6c-6d (such as) or the movement of the feeder point (e.g. Figures 7a-7d and Figures 8a-8d The situation will be described sequentially. Therefore, the degree of symmetry between the capacitance and inductance midpoints of transformer T1 can vary within a tolerance attributable to a relatively small asymmetry. Furthermore, note that larger inductors can have a larger tolerance regarding symmetry, which is understandable (the larger the symmetrical portion of the inductor, the less relevant the asymmetrical portion becomes). Note that the feed point refers to the point of the transformer inductor coupled to the feed line, and the feed line refers to the conductive path (or at least a portion of that path) to which the excitation is applied to the feed point of the inductor.

[0032] In some such embodiments, transformer T1 is implemented as an integrated laminated transformer, with the primary and secondary windings printed or otherwise formed on opposite sides of the laminated structure (e.g., bismaleimide triazine (BT) resin or other suitable dielectric material). Any number of turns ratios can be used depending on the given application. In this example case, diodes D1-D4 of rectifier 105 are symmetrically arranged in the full-wave rectifier to convert the AC output of transformer T1 back to DC. As will be understood, diodes D1-D4 can be implemented using any number of diode techniques, such as rectifier diodes, Schottky diodes, or MOSFET diodes (also known as diode-connected MOSFETs), to name just a few. In any such case, layout symmetry can be maintained. As will be further understood, hysteresis comparator 107 provides a feedback control loop for the power converter to maintain a stable output voltage VISO (e.g., low overshoot and undershoot) during load changes or transients. Capacitor C7 blocks or otherwise reduces low-frequency noise and DC components on the feedback path between comparator 107 and control 102.

[0033] Figures 2a-2d The illustrations together depict the operational details of the H-bridge switching circuit 103 and the transformer T1 according to some embodiments of this specification. It can be seen that the circuit is balanced about a fictitious line of symmetry. While the degree of symmetry can vary from one embodiment to the next, in this particular example embodiment, each of the H-bridge switching circuit 103, the transformer T1, and the rectifier 105 connected to the secondary winding of the transformer T1 can be arranged in a symmetrical half-cell manner to be substantially balanced about the line of symmetry.

[0034] As can be seen, the line of symmetry passes through the center of transformer T1, dividing each of the primary and secondary inductors (LP and LS, respectively) into two essentially equal parts. Therefore, any high-frequency common-mode switching current flowing from the primary to the secondary (via the parasitic capacitance Cps) will be canceled out by the mirrored common-mode current from the other side, such as... Figure 2b The dashed line in the diagram depicts the entirety of the symmetrical zero-voltage switch (ZVS). The switch is activated by using a leakage inductance (on both the primary and secondary sides, such as...) Figure 2b The common-mode current is achieved by using resonant capacitors CP and CS connected in parallel (as shown). The resulting LC energy storage circuit (tank circuit) (CP connected in parallel with the leakage inductance on the primary side and CS connected in parallel with the leakage inductance on the secondary side, combined with parasitic Cps) establishes a switching differential, which in turn greatly reduces the common-mode current. The ZVS turn-off time (dead time) is half a cycle of the resonant frequency of the leakage inductance, CP, and CS. The ZVS turn-on time is extended, allowing for higher peak current and thus a larger output current.

[0035] As will be understood with reference to this specification, this architecture allows for symmetrical switching. More detailed, as in... Figure 2c As can be seen in the timing diagram, the drive signals DRV0 and DRV1 output by the H-bridge switching circuit 103 are essentially differential, and they cannot be high simultaneously. At time t1, the drive signals... φ 1 is low, and the drive signal φ 2 transitions from high to low, which in turn causes DRV0 to begin its high-to-low transition, and DRV1 to begin its low-to-high transition. Specifically, when the drive signal... φ 1 and φ When both LP and LS are low, inductor LP has a limited current flow, and capacitor CP is charged to a certain voltage. At this time, capacitor Cp and the effective inductance from inductors LP and LS together form an LC energy storage circuit. This LC energy storage circuit resonates at its resonant frequency. This resonance drives the DRV1 signal to high and the DRV0 signal to low. At time t2, the drive signal... φ 1. The signal transitions from low to high, and ZVS conduction occurs when dv / dt approaches zero (therefore, ZVS conduction). At time t3, the drive signal... φ The transition from high to low causes DRV0 to begin its transition from low to high, and DRV1 to begin its transition from high to low, and this continues until the transformer peak current (I) is reached. LP ZVS shutdown occurs at time t4. The drive signal... φ 2. The frequency transitions from low to high, and this process repeats after the dead time ends. The dead time is half a cycle of the resonant frequency of the LC energy storage circuit.

[0036] Note that the resonant frequency is a function of the primary inductance and the net capacitance across the primary inductor. Depending on the implementation, the resonant frequency and / or amplitude may not match the desired turn-off time. The amplitude of the resulting sine wave will be the peak current (I0) through the primary inductor. LP The function of ). Figure 2d In the example case where the amplitude of the resulting sine wave is much larger than the power supply value (V-GND), ZVS can be achieved by timing the turn-on of H-bridge 103 when DRV0 and DRV1 are sufficiently close to their final stable values. As will be understood, this helps to maintain charge and symmetry in the driver and effectively behaves as a compromise between no ZVS and proper ZVS.

[0037] drive signal φ 1 and φ 2 and their symmetrical complementary counterparts and It can be generated, for example, from a high-frequency clock included in digital control 102 or in non-overlapping drivers 104a-104b, or otherwise accessible by control block 101, and digitally down-divided to achieve the desired ZVS turn-on. Figure 2c As shown in the optimal configuration, the ZVS on-time is extended, thus enabling a higher peak current (IV) through the primary inductor. LP This results in a higher output current Iout. This tradeoff allows the converter to operate at a frequency lower than the resonant frequency of the LC energy storage circuit. Therefore, this converter can be called a quasi-resonant converter. As will be understood, compared to a cross-coupled PMOS stage, the ZVS topology allows the LC energy storage to resonate by reversing charges on the capacitors (CP and CS) at both nodes without using power from the supply, which in turn helps to maintain higher converter efficiency by compensating for the additional power required to drive the higher-resistance PMOS FET.

[0038] In any such case, note that in some embodiments, capacitor CP may be part of transformer T1 (e.g., on a laminate), or in other embodiments may be part of H-bridge switching circuit 103, or in still other embodiments may be deployed independently of both 103 and T1. Similarly, note that capacitor CS may be part of transformer T1 (e.g., on a laminate), or part of rectifier 105, or deployed independently of both T1 and 105. Further note that one or both of CP and CS may be discrete capacitors, or parasitic capacitances sufficient to allow ZVS or resonant operation, or a combination of both discrete and parasitic capacitances. In any such case, the net resulting capacitances CP and CS (whether parasitic, intentionally discrete, or a combination thereof) are sufficient to enable ZVS and resonant converter operation at a given operating frequency. Many such embodiments and variations will be apparent from this specification.

[0039] Further reference Figure 2a The H-bridge switching circuit 103 is parasitic compensated. More specifically, the high-side PMOS transistors Q1 and Q2 are made larger, resulting in a higher on-resistance (R0). ds The on-resistance (R) of the low-side NMOS transistors Q3 and Q4 ds Basic matching. Typically, due to the lower mobility of p-type devices, PMOS transistors have a higher R-value than NMOS transistors of similar size. ds A much larger R ds Therefore, the size of a PMOS transistor can be increased to approximately 3.3 times that of an NMOS transistor, allowing the PMOS transistor to have essentially the same R0. dsFurthermore, the low-side NMOS transistors Q3 and Q4 are implemented using additional capacitors (C1 and C2, respectively) between their gate and drain, such that their gate-drain capacitance (C... gd ) and the gate-drain capacitance (C) of the larger PMOS transistors Q1 and Q2 on the high side gd Basic matching. Note the Ri of PMOS and NMOS transistors. ds and C gd The values ​​do not need to be exactly the same; rather, they only need to be within acceptable tolerances of each other. Therefore, for example, in some exemplary cases, the R values ​​of PMOS and NMOS transistors... ds The values ​​are essentially the same or otherwise largely matched, which is in R ds Values ​​are within tolerances of 25%, 20%, 15%, 10%, 5%, or 2% or 1% of each other, or within the same target R. ds Within tolerances of 10%, 5%, 2.5%, 2%, 1%, or 0.5% or 0.25% for values; similarly, the C values ​​for PMOS and NMOS transistors... gd The values ​​are essentially the same or otherwise largely matched, which is in C gd The values ​​are within tolerances of 25%, 20%, 15%, 10%, 5%, or 2% or 1% of each other, or within the same target C. gd The values ​​are within tolerances of 10%, 5%, 2.5%, 2%, 1%, or 0.5% or 0.25%. Depending on the requirements of a given application, the tolerance can vary from one embodiment to the next. Further note that C... gd The tolerance can be different from R. ds The tolerance. Further note, R ds and C gd The absolute value of R can vary from one embodiment to the next, and this specification is not limited to any particular range of values. In any such case, the R value between PMOS and NMOS transistors... ds and C gd The mismatch is essentially compensated within acceptable tolerances for a given application and accompanying EMI performance targets. To this end, as will be understood, according to some embodiments, the mismatch between PMOS and NMOS transistors is related to R... ds and C gd The greater the degree of matching, the greater the performance regarding radiation emissions.

[0040] For example, according to some embodiments, some reduction in radiative emissions is achieved when a 25% matching threshold is used (whether for matching between matching devices or for target tolerance), while a further reduction in radiative emissions is achieved when a 20% matching threshold is used, and a further reduction in radiative emissions is achieved when a 10% matching threshold is used, and a further reduction in radiative emissions is achieved when a 5% matching threshold is used, and a further reduction in radiative emissions is achieved when a 2% matching threshold is used. Note that regarding R... ds and C gd A tighter matching threshold can allow for relaxation of other parameters while still maintaining desired EMI performance. For example, in some example embodiments, the ratio of R between PMOS and NMOS transistors is... ds and C gd A tighter matching threshold can allow for a higher degree of physical asymmetry with respect to the transformer (such as asymmetry caused by moving the feed point, etc.). Figure 7d and Figure 8d (as described in the example embodiments).

[0041] According to some embodiments, in addition to this R ds and C gd In addition to compensation, the H-bridge switching circuit 103 may also include capacitors C3, C4, C5, and C6. It can be seen that C3 and C4 reference the input voltage V (such as V0). CC C3 is connected to the first node of the primary-side inductor of T1, and C4 is connected to the second node of the primary-side inductor of T1. Similarly, C5 and C6 are referenced to primary-side ground (GND), with C5 connected to the first node of the primary-side inductor of T1 and C6 connected to the second node of the primary-side inductor of T1. As will be understood, capacitors C3, C4, C5, and C6 effectively operate to maintain the common mode at V / 2 during transitions. Through capacitive voltage division, these capacitors also help reduce any stray charge injected into the driving power MOSFETs Q1-Q4.

[0042] Figure 2e The illustrations depict improvements in radiated emissions that can be achieved using H-bridge switching circuits and transformer architectures according to some embodiments of this specification. Specifically, it can be seen that the symmetrical switch itself can produce an improvement (reduction) in radiated emissions of approximately 5%-10%. Furthermore, combining the symmetrical switch with the R... ds Value matching in target R ds Within a 20% tolerance, radiation emissions can be improved by more than 10%, while the R value of PMOS and NMOS transistors can be adjusted. ds Value matching in target R dsWithin a 10% tolerance of the value, emissions can be improved by more than 15%. Furthermore, combining symmetrical switches and R... ds Matching the C of PMOS transistors and NMOS transistors gd Value matching in target C gd Within a 20% tolerance, radiation emissions can be further improved by more than 18%, while the C values ​​of PMOS and NMOS transistors can be adjusted. gd Value matching in target C gd A 10% tolerance in the value can improve emissions by more than 20%. As will be further understood, R... ds and / or C gd A 5% match in the value will further improve radiation emissions. At this point, note the symmetrical switch, R... ds Matching and C gd The degree of each in the match can be tuned to achieve the desired performance improvement regarding radiation emissions.

[0043] H-bridge switching circuit As mentioned earlier, PMOS and NMOS are asymmetrical in design, especially in terms of on-resistance R. ds and gate-drain capacitance C gd In this regard, the H-bridge switching circuit can be modified to provide better, more symmetrical performance. Figures 3a-5b Together, they illustrate the effects of each of these parasitic compensations, both individually and in combination.

[0044] More in detail, Figure 3a The diagram illustrates an embodiment of this specification with an R configuration between an NMOS transistor and a PMOS transistor. ds A matching example H-bridge switching circuit. It can be seen that the PMOS transistors Q1 and Q2 are 3.3 times the size of the NMOS transistors Q1 and Q2, making all four transistors have essentially the same on-resistance R. ds The above description regarding precise matching without on-resistance also applies here (a substantial match within tolerances is sufficient). As will be understood, absolute and relative dimensions can vary from one embodiment to the next, and this specification is not limited to any particular one or set of dimensional schemes. Conversely, dimensional schemes can be customized for any opposite polarity (n-type and p-type) transistors, which can be matched in terms of on-resistance. In any such case, as Figure 3b As shown, the matching R of NMOS (Q3 and Q4) and PMOS (Q1 and Q2) is... ds This produces a common-mode peak (peak-to-peak) voltage of approximately 1.2 volts. This performance is largely due to the asymmetric C... gd Charge injection (C of larger PMOS transistors Q1 and Q2) gdWith the smaller NMOS transistors Q3 and Q4, C gd (Mismatch).

[0045] Figure 4a The illustration shows a configuration with only C-type NMOS and PMOS transistors between NMOS and PMOS transistors according to an embodiment of this specification. gd A matching example H-bridge switching circuit. It can be seen that transistors Q1 and Q2 are essentially the same size as transistors Q3 and Q4, therefore the Ci of all four transistors is... gd They are essentially a match. However, due to the lower carrier mobility in p-type semiconductors (e.g., in silicon, the mobility of holes is lower than that of electrons), the on-resistance R of transistors Q1 and Q2 is... ds The on-resistance R of transistors Q3 and Q4 is relatively higher. ds .like Figure 4b As shown, the C values ​​of Q3 and Q4 are... gd C with Q1 and Q2 gd Match, but not match R ds This produces approximately 250 mV common-mode peak (peak-to-peak) at twice the switching frequency. The above description regarding the lack of precise matching of gate-drain capacitors also applies here (a near-perfect match within tolerances is sufficient).

[0046] Figure 5a The diagram illustrates an R-type transistor configured between an NMOS transistor and a PMOS transistor. ds and C gd An example H-bridge switching circuit matching the two. It can be seen that transistors Q1 and Q2 are 3.3 times larger than transistors Q3 and Q4, making all four transistors have essentially the same R0. ds Furthermore, transistors Q3 and Q4 are respectively coupled with transistors Q1 and Q2 via C. gd Matching, so that all four transistors have essentially the same C gd Regarding not needing R ds and C gd The above description of an exact match also applies here (RM is essentially a match within tolerance). ds and C gd (Okay). Specifically, Q3 has an additional capacitor C1 configured across its gate-drain junction, and Q4 has an additional capacitor C2 configured across its gate-drain junction. As will be understood, capacitors C1 and C2, as well as any other capacitors provided herein, can be implemented using any number of capacitor techniques, such as metal-insulator-metal capacitors, metal-oxide-metal capacitors, or MOSFET capacitors, to name just a few. Figure 5aThe example MOSFET capacitor configuration for C1 is shown in dashed lines (a similar configuration will apply to C2 to maintain symmetry). As will be further understood, the absolute values ​​of capacitors C1 and C2 can vary from one embodiment to the next, depending on the semiconductor process technology and materials used, and this specification is not limited to any particular range of capacitance values. Conversely, capacitors C1 and C2 can be customized for any opposite polarity (n-type and p-type) transistors, which can be matched in this capacitance. Figure 5b As shown, R of Q3 and Q4 ds and C gd Both and R of Q1 and Q2 ds and C gd This matching produces a relatively low (approximately 90 mV) common-mode peak (peak-to-peak) at twice the switching frequency. As will be understood, this particular configuration provides minimal EMI at the cost of some switching losses (slower switching speed). It is further noted that complete elimination of common-mode voltage variations is not required. Instead, relatively small common-mode voltage peaks can be tolerated within tolerances suitable for a given application. For example, in some cases, a peak-to-peak common-mode voltage of less than 200 mV is acceptable for 5Vin 5Vout or 3.3Vin 3.3Vout isolated DC-DC power converters, or less than 150 mV or less than 100 mV, or otherwise less than an acceptable percentage of the input or output voltage of the isolated DC-DC power converter.

[0047] transformer Figures 6a-6b A symmetrical transformer T1 configured according to an embodiment of this specification is illustrated. It can be seen that the transformer T1 generally includes a primary inductor LP and a secondary inductor LS. In this example case, the primary inductor LP includes Lp1, Lp2, and Lp3, and the secondary inductor LS includes Ls1, Ls2, and Ls3. Furthermore, parasitic capacitance exists between Lp1 and Ls2, which is depicted entirely by dashed lines. (The remaining text appears to be a fragment and requires further context for accurate translation.) Figures 6c-6d Described sequentially, Lp1 and Lp2 are symmetrical half-unit portions of LP, and Lp3 is a relatively small asymmetrical portion of LP, which is attributed to the difference in feed line structure to the corresponding feed points of Lp1 and LP2. Similarly, Ls1 and Ls2 are symmetrical half-unit portions of LS, and Ls3 is a relatively small asymmetrical portion of LS, which is attributed to the difference in feed line structure to the corresponding feed points of Ls1 and Ls2.

[0048] As in Figure 6bAs can be seen in the example embodiment, transformer T1 is an integrated laminated transformer comprising inductors LP and LS printed on or otherwise formed on opposite sides of the laminated structure. As can be further seen, wire bonding is used to connect LP to the H-bridge switching circuit 103 and LS to the rectifier 105, although other interconnection mechanisms may be used. As will be understood, each of 103 and 105 may be formed on a semiconductor die. As will be understood, standard or proprietary process technologies and materials may be used.

[0049] Figure 6c The illustration shows an example inductor layout configured according to an embodiment of this specification for either the LP (where x=P) or LS (where x=S) of transformer T1. Of course, the LP and LS of a given transformer T1 design can have different numbers of turns depending on the desired turns ratio. In any case, as can be seen, the inductor in this example embodiment is figure-eight shaped and includes portions 601 and 602 connected together at the center point 603 of the inductor, and portion 602 is a copy (replica) of portion 601 that has been rotated 180 degrees about the z-axis (off-page); therefore, they are symmetrical half-cell portions. Note that the center point 603 is both the inductance midpoint and capacitance midpoint of the figure-eight inductor. The above description regarding substantially in-situ alignment, and the lack of precise in-situ alignment, also applies here. The feed to feed point 604 includes portions 606 and 607, and the feed to feed point 605 includes portions 608 and 609. Each of these parts 601-609 can be implemented with any suitable conductive material such as copper.

[0050] Furthermore, there is a slight asymmetry between the two feeds, which in turn provides a slight difference in inductance. This slight difference in... Figure 6aThe inductors are denoted as Lp3 or Ls3. More specifically, some of the feeder segments are symmetrical because they are common to both feeders and therefore can be attributed to the main inductance fed into them. In this example case, segment 606B corresponds to segment 608, and segment 607E corresponds to segment 609. Therefore, the inductances of segments 606B and 607E can be grouped with the inductance of L601; similarly, the inductances of segments 608 and 609 can be grouped with the inductance of L602. The only remaining feeder segments not yet considered are 606A, 606C, and 607D. Therefore, the inductances of these segments can be denoted as Lx3, which can be either Lp3 or Ls3. Nevertheless, the inductors exhibit a high degree of symmetry. For example, in some exemplary embodiments, the inductance of each of L601 (including segments 606B and 607E) and L602 (including segments 608 and 609) is 5 times or more, or 10 times or more, or 20 times or more, or 50 times or more, or 100 times or more, the inductance of segments 606A, 606C, and 607D. The connection point at 610 allows connections (e.g., wire bonding or other interconnections) to 103 (if x=P) or 105 (if x=S) of the semiconductor die. This interconnection can also be implemented symmetrically.

[0051] Figure 6d The illustration shows another example inductor layout configured according to embodiments of this specification for use with LP (where x=P) or LS (where x=S) of transformer T1. (The preceding text is about...) Figure 6cThe relevant description also applies here. In this example case, the inductor is O-type and includes portions 651 and 652 connected together at the center point 653 of the inductor, and portion 652 is a copy (replica) of portion 651 that has been rotated 180 degrees about the x-axis; therefore, they are symmetrical half-unit portions. Note that the center point 653 is both the inductance midpoint and capacitance midpoint of the O-type inductor. The description above regarding the lack of precise alignment also applies here. The feed to feed point 654 includes portions 656 and 657, and the feed to feed point 655 includes portions 658 and 659. As can be seen further, segment 656A corresponds to segment 658, and segment 657D corresponds to segment 659. Therefore, the inductors of segments 656A and 657D can be grouped with the inductor of L651; similarly, the inductors of segments 658 and 659 can be grouped with the inductor of L652. The only remaining feeder segments not yet considered are 656B and 657C. Therefore, the inductance of these segments can be represented as Lx3, which can be Lp3 or Ls3. Nevertheless, the inductors exhibit a high degree of symmetry. For example, in some example embodiments, the inductance of each of L651 (including segments 656A and 657D) and L652 (including segments 658 and 659) is 5 times or more, or 10 times or more, or 20 times or more, or 50 times or more, or 100 times or more, than the inductance of segments 656B and 657C. The connection point at 660 allows connections (e.g., wire bonding or other interconnections) to 103 (if x=P) or 105 (if x=S) of the semiconductor die. This interconnection can also be implemented symmetrically.

[0052] Figures 7a-7d The primary inductor of a symmetrical transformer according to another embodiment of this specification is also illustrated. More specifically, Figure 7a A half-cell portion 701 of the inductor is shown, which includes a feed point 704. Figure 7b The other half of the inductor, cell 702, is shown, which includes a feed point 705. It can be seen that half cell 702 is a copy of half cell 701 that has been rotated 180 degrees about the z-axis (away from the page). Figure 7c The half-cell portions 701 and 702 connected at 703 are shown to provide a symmetrical figure-eight inductor. Note that this example inductor has 2 turns, and point 703 is the location of both the midpoint of the capacitor and the midpoint of the inductor. The above description regarding the unnecessary precise alignment of these midpoints also applies here. In some embodiments, it is desirable for the feed points to be on the same side (for easier connection). For this purpose, as... Figure 7dAs shown, feed point 705 is extended or otherwise moved to feed point 707 by adding extension 706 to align with feed point 704. Therefore, feed lines 708 and 709 can be more easily attached to the corresponding feed points 704 and 707. Since the voltage difference at exactly the center of the coil is relatively small, the slight difference in symmetry results in negligible voltage across extension 706. Therefore, the feed point can be moved to the desired location without sacrificing symmetry. Half-unit portion 701, half-unit portion 702, and extension 706 can be respectively considered as... Figure 6a Lp1, Lp2, and Lp3. Because 706 is much smaller than 701 and 702 (for example, the combined inductance of 701 and 702 is at least 5 times, or at least 10 times or more, or at least 20 times or more, or at least 50 times or more, or at least 100 times or more), the voltage across 706 is relatively small or negligible.

[0053] Figures 8a-8d The accompanying diagram illustrates the secondary inductor of a symmetrical transformer according to another embodiment of this specification. More specifically, Figure 8a A half-cell portion 801 of the inductor is shown, which includes a feed point 804. Figure 8b The other half of the inductor, cell portion 802, is shown, which includes a feed point 805. It can be seen that half cell portion 802 is a copy of half cell portion 801 that has been rotated 180 degrees about the z-axis (away from the page). Figure 8c The half-cell portions 801 and 802 connected at 803 are shown to provide a symmetrical figure-eight inductor. Note that this example inductor has 3 turns, and point 803 is the location of both the midpoint of the capacitor and the midpoint of the inductor. The above description regarding the unnecessary precise alignment of these midpoints also applies here. In some embodiments, it is desirable for the feed points to be on the same side (for easier connection). For this purpose, as... Figure 8d As shown, by removing (or simply not forming) the corresponding portion of 801, feed point 804 is shortened or otherwise moved to feed point 807 to align with feed point 805. Therefore, feed lines 808 and 809 can be more easily attached to the corresponding feed points 805 and 807. The missing portions of half-unit portions 801, 802, and 801 can be respectively considered as... Figure 6a Ls1, Ls2, and Ls3. Because the missing portion of 801 is much smaller than 801 and 802 (for example, the combined inductance of 801 and 802 is at least 5 times larger, or at least 10 times larger, or at least 20 times larger, or at least 50 times larger, or at least 100 times larger), the resulting asymmetry is relatively small or negligible.

[0054] Notice, Figures 7a-7dThe primary inductor can be with Figures 8a-8d The secondary inductors are used in combination to provide a transformer with a 2 / 3 turns ratio. In some such examples, the transformer has capacitor midpoints and inductor midpoints that at least partially overlap each other (e.g., point 703 is co-located with point 803, or in cases where there is an acceptable tolerance at that point), and a line of symmetry passes through at least one of the capacitor midpoint and inductor midpoint. Many other configurations will be recognized.

[0055] As described above, this symmetry in the H-bridge switching circuit 103 and transformer T1 significantly reduces the peak common-mode voltage across the transformer. For example, considering the example case where the converter is a DC-DC converter (e.g., 5Vin 5Vout or 3.3Vin 3.3Vout), the symmetrical drive transformer with symmetrical figure-eight primary and secondary windings produces approximately 6 dB or more of common-mode current reduction compared to other comparable DC-DC converters with asymmetrical transformers (e.g., spiral inductors). Furthermore, the R between the NMOS and PMOS power FETs (Q1-Q4) using the H-bridge switching circuit 103... ds and C gd With proper matching, the peak common-mode voltage across the primary winding of the transformer is less than 100 millivolts, which is significantly lower than the peak common-mode voltage attributable to the uncompensated H-bridge switching circuit. As will be understood, other embodiments may yield different results.

[0056] Supply Network As previously mentioned, the power converter's supply network can also include symmetrical features. For example, the bond wire and trace lengths of the voltage supply (V) and ground path (GND) can be arranged symmetrically to provide symmetrical feed paths to the H-bridge switching circuit 103 and rectifier 105. This symmetry helps to reduce out-of-phase noise (e.g., (V) CC +GND) / 2) remains at a constant level. Similarly, rectifier 105 can be arranged in a symmetrical half-cell configuration. Furthermore, decoupling capacitors can be connected between the power supply and ground on both the primary and secondary sides to help reduce power supply noise. Additionally, extra capacitors can be added to compensate for parasitic capacitances associated with the primary and secondary die attachment pads (priDAP and secDAP). These features are... Figure 9 It is described in the text as being similar to Figure 2a The architecture shown is the same as described herein. Furthermore, the architecture has been modified to include symmetrical supply networks on both the primary and secondary sides, and compensation for the parasitic capacitance of priDAP / secDAP.

[0057] As can be seen, the primary-side supply network 970 is arranged symmetrically and includes a voltage supply section 970a, a ground section 970b, and a decoupling capacitor C8. Similarly, the secondary-side supply network 975 is arranged symmetrically and includes a voltage supply section 975a, a ground section 975b, and a decoupling capacitor C9. Note that in some embodiments, capacitors C3-C6 may also be included in supply network 970, and / or diodes D1-D4 or rectifier 905 may be included in supply network 975. In any case, supply networks 970 and 975 are symmetrical about a line of symmetry to provide symmetrical feed paths to the inverter and rectifier circuitry.

[0058] Therefore, for example, the supply network 970 can be implemented with two half-cell portions, wherein the upper half-cell portion includes a voltage supply portion 970a, which in this example embodiment includes a voltage supply V routing trace and any bond wire or element portions above and up to the line of symmetry, including the upper half of C8 (and in some such embodiments, including C3 and C4). In this case, the lower half-cell portion can be a copy (replica) of the upper half-cell portion rotated 180 degrees about the x-axis to provide a ground portion 970b, which in this example includes a first ground (GND) routing trace and any bond wire or element portions below and up to the line of symmetry, including the lower half of C8 (and in some such embodiments, including C5 and C6).

[0059] Similarly, the supply network 975 can be implemented with two half-cell portions, wherein the upper half-cell portion includes a voltage supply portion 975a, which in this example embodiment includes an output voltage VISO routing trace and any bond wire or element portions above and up to the line of symmetry, including the upper half of C9 (and in some such embodiments, including D1 and D2). In this case, the lower half-cell portion can be a copy of the upper half-cell portion rotated 180 degrees about the x-axis to provide a ground portion 975b, which in this example includes a second ground (GISO, which is isolated from GND) routing trace and any bond wire or element portions below and up to the line of symmetry, including the lower half of C9 (and in some such embodiments, including D3 and D4). As previously mentioned, the rectifier 905 can also be arranged in a half-cell manner around the line of symmetry, as can other components in the signal chain (e.g., CS, T1, CP, and 903). Any half-cell portion can include element portions from any combination of these, as long as the isolation barrier is ultimately maintained.

[0060] As will be understood, decoupling capacitors C8 and C9 can be used, for example, in situations where the input supply V and / or output supply VISO are relatively noisy. Consider, for instance, the case where the power-to-ground parasitic inductance (from the bond wires and lead fingers) contributes 3Vp-p to the 5Vin-5Vout supply noise. In typical designs, the ground route is stronger (more robust or asymmetrical) than the power route, which leads to common-mode peaks when driving the transformer. Therefore, by making the power and ground paths symmetrical (on one or both of the primary and secondary sides), and by providing different levels of symmetry in the drivers, transformers, and rectifiers, the common-mode noise can be reduced or otherwise tuned below the desired threshold.

[0061] As in Figure 9 As can be further seen in the example embodiments, the parasitic capacitance (C) associated with the primary and secondary die attachment pads priDAP-secDAP This effectively couples the primary-side GND to the secondary-side GISO. Parasitic capacitance can be compensated for by a matching capacitor (C10) coupled between the primary-side V and the secondary-side VISO. For example, consider C... priDAP-secDAP An example case provides a parasitic capacitance of approximately 900F, which can lead to unbalanced common-mode currents. To address this, a capacitor of a similar value, C10, can be added symmetrically, for example, on the laminate of a transformer, to balance this parasitic capacitance. Other parasitic effects introducing asymmetrical common-mode currents can be similarly compensated for to further increase the symmetry of the configuration.

[0062] The variations will be understood. For example, a p-type transistor is shown connected to the high side of the converter, and an n-type transistor is shown connected to the low side of the converter. In other embodiments, this arrangement can be reversed, such that an n-type transistor is connected to the high side of the converter, and a p-type transistor is connected to the low side of the converter. For this purpose, the first and second polarities of the transistors constituting the H-bridge switching circuit can be switched between the high and low sides.

[0063] Further example embodiments Example 1 is an integrated circuit comprising: a transformer having a primary-side inductor and a secondary-side inductor, each of the primary-side inductor and the secondary-side inductor including a first half-cell portion and a second half-cell portion, the second half-cell portion being a replica of the first half-cell portion except for rotation about an axis, and the two half-cell portions being connected to each other to provide a corresponding inductor; and an H-bridge switching circuit operatively coupled to the primary-side inductor, the H-bridge switching circuit including a first transistor and a second transistor of a first polarity, and a third transistor and a fourth transistor of a second polarity, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have substantially the same on-resistance and substantially the same gate-drain capacitance.

[0064] Example 2 includes the subject of Example 1, wherein a fictitious line of symmetry divides the secondary-side inductor of the transformer into corresponding first half-cell portions and second half-cell portions. The integrated circuit also includes a rectifier operatively coupled to the secondary side of the transformer and includes a plurality of diodes arranged and connected symmetrically about the line of symmetry.

[0065] Example 3 includes the subject of Example 1 or 2, wherein a fictitious line of symmetry divides the primary side of the transformer into corresponding first half-unit portions and second half-unit portions. The integrated circuit also includes a control block for providing drive signals to drive the first, second, third, and fourth transistors of the H-bridge switching circuit. The control block is arranged and connected symmetrically about the line of symmetry.

[0066] Example 4 includes the subject of Example 3, and also includes: a hysteresis comparator, which is used to provide feedback signals to the control block.

[0067] Example 5 includes the subject matter of Example 3 or 4, wherein the control block includes: a digital control circuit for generating control signals; a first non-overlapping drive circuit for generating a first pair of complementary non-overlapping drive signals to drive one of a first transistor and a second transistor of a first polarity and one of a third transistor and a fourth transistor of a second polarity; and a second non-overlapping drive circuit for generating a second pair of complementary non-overlapping drive signals to drive the other of the first transistor and the second transistor of the first polarity and the other of the third transistor and the fourth transistor of the second polarity.

[0068] Example 6 includes the subject of Example 5, wherein the control block further includes: a first driver, a second driver, a third driver, and a fourth driver, each driver receiving a corresponding one of the non-overlapping drive signals and driving the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively.

[0069] Example 7 includes the subject of any one of Examples 1 to 6, wherein the transformer has a capacitor midpoint and an inductor midpoint, and the capacitor midpoint and the inductor midpoint are in the same position.

[0070] Example 8 includes the subject of any one of Examples 1 to 7, wherein the on-resistance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 10% tolerance of the same target value, and the gate-drain capacitance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 10% tolerance of the same target value.

[0071] Example 9 includes the subject matter of any one of Examples 1 through 8, wherein the on-resistance of each of the first, second, third, and fourth transistors is within a 5% tolerance of the same target value, and the gate-drain capacitance of each of the first, second, third, and fourth transistors is within a 5% tolerance of the same target value. In other such examples, the on-resistance of each of the first, second, third, and fourth transistors is within a 5% tolerance of the same target value, and the gate-drain capacitance of each of the first, second, third, and fourth transistors is within a 10% tolerance of the same target value. In other such examples, the on-resistance of each of the first, second, third, and fourth transistors is within a 10% tolerance of the same target value, and the gate-drain capacitance of each of the first, second, third, and fourth transistors is within a 5% tolerance of the same target value.

[0072] Example 10 includes the subject of any one of Examples 1 to 9, and also includes a supply network comprising a voltage supply section and a ground section, wherein the corresponding trace lengths of the voltage supply section and the ground section are arranged in a symmetrical manner, so that the voltage supply section is symmetrical to the ground section.

[0073] Example 11 is an integrated circuit comprising: a transformer having a primary-side inductor and a secondary-side inductor, each of the primary-side and secondary-side inductors comprising a first portion and a second portion, the second portion being a copy of the first portion except for rotation about an axis, and the two portions being connected to each other to provide a corresponding inductor, wherein a fictitious line of symmetry divides each of the primary-side and secondary-side inductors into a respective first portion and second portion; and an H-bridge switching circuit operatively coupled to the primary-side inductor, the H-bridge switching circuit comprising a first transistor and a second transistor of a first polarity, and a third transistor and a fourth transistor of a second polarity, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each have an on-resistance within a 10% tolerance of the same target on-resistance and a gate-drain capacitance within a 10% tolerance of the same target gate-drain capacitance. Thus, for example, if the target on-resistance is 100 ohms, then the first transistor, the second transistor, the third transistor, and the fourth transistor each have an on-resistance in the range of 90 to 110 ohms.

[0074] Example 12 includes the subject matter of Example 11, and further includes: a rectifier operatively coupled to the secondary side of a transformer, and includes a plurality of diodes arranged and connected symmetrically about a line of symmetry.

[0075] Example 13 includes the subject matter of Example 11 or 12, and further includes: a control block for providing drive signals to drive the first, second, third, and fourth transistors of the H-bridge switching circuit, the control block being arranged and connected symmetrically about a line of symmetry; and / or a hysteresis comparator for providing feedback signals to the control block.

[0076] Example 14 includes the subject matter of Example 13, wherein the control block includes: a digital control circuit for generating control signals; a first non-overlapping drive circuit for generating a first pair of complementary non-overlapping drive signals to drive one of a first transistor and a second transistor of a first polarity and one of a third transistor and a fourth transistor of a second polarity; and a second non-overlapping drive circuit for generating a second pair of complementary non-overlapping drive signals to drive the other of the first transistor and the second transistor of the first polarity and the other of the third transistor and the fourth transistor of the second polarity.

[0077] Example 15 includes the subject matter of any one of Examples 11 through 14, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each have an on-resistance within a 2.5% tolerance of the same target on-resistance and a gate-drain capacitance within a 2.5% tolerance of the same target gate-drain capacitance. In other such examples, the on-resistance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 1% tolerance of the same target value, and the gate-drain capacitance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 2.5% tolerance of the same target value. In other such examples, the on-resistance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 2.5% tolerance of the same target value, and the gate-drain capacitance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 1% tolerance of the same target value.

[0078] Example 16 includes the subject of any of Examples 11 to 15, and also includes a supply network comprising a voltage supply section and a grounding section, wherein the voltage supply section is symmetrical about a line of symmetry to the grounding section.

[0079] Example 17 is an integrated circuit comprising: a transformer having a primary-side inductor and a secondary-side inductor, wherein a fictitious line of symmetry divides each of the primary-side inductor and the secondary-side inductor into a first portion and a second portion; a rectifier operatively coupled to the secondary side of the transformer and including a plurality of diodes arranged and connected symmetrically about the line of symmetry; a supply network including a voltage supply portion and a ground portion, wherein the voltage supply portion is symmetrical to the ground portion about the line of symmetry; and an H-bridge switching circuit operatively coupled to the primary-side inductor, the H-bridge switching circuit including a first p-type metal-oxide-semiconductor field-effect transistor (MOSFET) and a second p-type metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the voltage supply portion of the supply network, and a third n-type MOSFET and a fourth n-type MOSFET connected to the ground portion of the supply network, wherein the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET each have an on-resistance within a 10% tolerance of the same target on-resistance and a gate-drain capacitance within a 10% tolerance of the same target gate-drain capacitance. The first and second portions of the primary-side inductor each have a primary-side feed point, and are symmetrical about a line of symmetry except for portions attributable to the following: the primary-side feed point of one portion of the primary-side inductor is moved to a feed point physically closer to the primary-side feed point of the other portion of the primary-side inductor. Furthermore, the first and second portions of the secondary-side inductor each have a secondary-side feed point, and are symmetrical about a line of symmetry except for portions attributable to the following: the secondary-side feed point of one portion of the secondary-side inductor is moved to a feed point physically closer to the other portion of the secondary-side inductor.

[0080] Example 18 includes the subject matter of Example 17, and also includes a control block for providing drive signals to drive the first MOSFET, second MOSFET, third MOSFET and fourth MOSFET of the H-bridge switching circuit; and / or a hysteresis comparator operatively coupled to the rectifier and providing feedback signals to the control block.

[0081] Example 19 includes the subject matter of Example 18, wherein the control block includes: a digital control circuit for generating control signals; a first non-overlapping drive circuit for generating a first pair of complementary non-overlapping drive signals to drive one of a first transistor and a second transistor of a first polarity and one of a third transistor and a fourth transistor of a second polarity; and a second non-overlapping drive circuit for generating a second pair of complementary non-overlapping drive signals to drive the other of the first transistor and the second transistor of the first polarity and the other of the third transistor and the fourth transistor of the second polarity.

[0082] Example 20 includes the subject of any of Examples 17 to 19, wherein the transformer has a capacitor midpoint and an inductor midpoint, and the capacitor midpoint and the inductor midpoint are in the same position.

[0083] The above description of exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit this specification to the precise forms described. Many modifications and variations are possible according to this specification. The scope of this specification is not limited by this detailed description, but by the claims appended herein.

Claims

1. An integrated circuit, comprising: A transformer having a primary-side inductor and a secondary-side inductor, each of the primary-side inductor and the secondary-side inductor comprising a first half-unit portion and a second half-unit portion, the second half-unit portion being a copy of the first half-unit portion except for rotation about an axis, and the two half-unit portions being connected to each other to provide a corresponding inductor. as well as An H-bridge switching circuit operatively coupled to the primary-side inductor, the H-bridge switching circuit including a first transistor and a second transistor of a first polarity, and a third transistor and a fourth transistor of a second polarity, wherein the first transistor, the second transistor, the third transistor and the fourth transistor have substantially the same on-resistance and substantially the same gate-drain capacitance.

2. The integrated circuit of claim 1, wherein a fictitious symmetry line divides the secondary-side inductor of the transformer into corresponding first half-cell portions and second half-cell portions, the integrated circuit further comprising: A rectifier, operably coupled to the secondary-side inductor of the transformer, and comprising a plurality of diodes arranged and connected symmetrically about the line of symmetry.

3. The integrated circuit of claim 1, wherein a fictitious symmetry line divides the primary side of the transformer into corresponding first half-unit portions and second half-unit portions, the integrated circuit further comprising: A control block, which provides drive signals to drive the first transistor, the second transistor, the third transistor, and the fourth transistor of the H-bridge switching circuit, is arranged and connected symmetrically about the line of symmetry.

4. The integrated circuit according to claim 3, further comprising: A hysteresis comparator is used to provide feedback signals to the control block.

5. The integrated circuit according to claim 3, wherein the control block comprises: Digital control circuits, used to generate control signals; A first non-overlapping driving circuit is configured to generate a first pair of complementary non-overlapping driving signals to drive one of the first transistor and the second transistor of the first polarity, and one of the third transistor and the fourth transistor of the second polarity; as well as A second non-overlapping drive circuit is used to generate a second pair of complementary non-overlapping drive signals to drive the other of the first transistor and the second transistor of the first polarity, as well as the other of the third transistor and the fourth transistor of the second polarity.

6. The integrated circuit according to claim 5, wherein the control block further comprises: The first driver, the second driver, the third driver, and the fourth driver each receive a corresponding one of the non-overlapping drive signals and drive the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively.

7. The integrated circuit of claim 1, wherein the transformer has a capacitor midpoint and an inductor midpoint, and the capacitor midpoint and the inductor midpoint are located at the same position.

8. The integrated circuit of claim 1, wherein the on-resistance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 10% tolerance of the same target value, and the gate-drain capacitance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 10% tolerance of the same target value.

9. The integrated circuit of claim 1, wherein the on-resistance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 5% tolerance of the same target value, and the gate-drain capacitance of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is within a 5% tolerance of the same target value.

10. The integrated circuit of claim 1, further comprising a supply network including a voltage supply portion and a ground portion, wherein the corresponding trace lengths of the voltage supply portion and the ground portion are arranged symmetrically, so that the voltage supply portion is symmetrical to the ground portion.

11. An integrated circuit, comprising: A transformer having a primary-side inductor and a secondary-side inductor, each of the primary-side inductor and the secondary-side inductor comprising a first portion and a second portion, the second portion being a copy of the first portion except for rotation about an axis, and the two portions being connected to each other to provide a corresponding inductor, wherein a fictitious line of symmetry divides each of the primary-side inductor and the secondary-side inductor into a corresponding first portion and a second portion; as well as An H-bridge switching circuit operatively coupled to the primary-side inductor, the H-bridge switching circuit including a first transistor and a second transistor of a first polarity, and a third transistor and a fourth transistor of a second polarity, wherein the first transistor, the second transistor, the third transistor and the fourth transistor each have an on-resistance within a 10% tolerance of the same target on-resistance and a gate-drain capacitance within a 10% tolerance of the same target gate-drain capacitance.

12. The integrated circuit according to claim 11, further comprising: A rectifier, operably coupled to the secondary-side inductor of the transformer, and comprising a plurality of diodes arranged and connected symmetrically about the line of symmetry.

13. The integrated circuit according to claim 11, further comprising: A control block for providing drive signals to drive the first transistor, the second transistor, the third transistor and the fourth transistor of the H-bridge switching circuit, the control block being arranged and connected symmetrically about the line of symmetry; as well as A hysteresis comparator is used to provide feedback signals to the control block.

14. The integrated circuit of claim 13, wherein the control block comprises: Digital control circuits, used to generate control signals; A first non-overlapping driving circuit is configured to generate a first pair of complementary non-overlapping driving signals to drive one of the first transistor and the second transistor of the first polarity, and one of the third transistor and the fourth transistor of the second polarity; as well as A second non-overlapping drive circuit is used to generate a second pair of complementary non-overlapping drive signals to drive the other of the first transistor and the second transistor of the first polarity, as well as the other of the third transistor and the fourth transistor of the second polarity.

15. The integrated circuit of claim 11, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each have an on-resistance within a 2.5% tolerance of the same target on-resistance and a gate-drain capacitance within a 2.5% tolerance of the same target gate-drain capacitance.

16. The integrated circuit of claim 11, further comprising a supply network including a voltage supply portion and a ground portion, wherein the voltage supply portion is symmetrical to the ground portion about the line of symmetry.

17. An integrated circuit, comprising: A transformer having a primary-side inductor and a secondary-side inductor, wherein a fictitious line of symmetry divides each of the primary-side inductor and the secondary-side inductor into a first part and a second part; A rectifier operably coupled to the secondary-side inductor of the transformer, and comprising a plurality of diodes arranged and connected symmetrically about the line of symmetry; A power supply network comprising a voltage supply section and a grounding section, wherein the voltage supply section is symmetrical to the grounding section about the line of symmetry; as well as H-bridge switching circuit, operably coupled to the primary-side inductor, the H-bridge switching circuit including a first p-type metal-oxide-semiconductor field-effect transistor, i.e., a first p-type MOSFET and a second p-type MOSFET connected to the voltage supply portion of the supply network, and a third n-type MOSFET and a fourth n-type MOSFET connected to the ground portion of the supply network, wherein the first p-type MOSFET, the second p-type MOSFET, the third n-type MOSFET and the fourth n-type MOSFET each have an on-resistance within a 10% tolerance of the same target on-resistance and a gate-drain capacitance within a 10% tolerance of the same target gate-drain capacitance; The first and second portions of the primary-side inductor each have a primary-side feed point, and are symmetrical about the line of symmetry except for portions attributable to the following: the primary-side feed point of one of the portions of the primary-side inductor is moved to be physically closer to the primary-side feed point of the other of the portions of the primary-side inductor; and The first and second portions of the secondary-side inductor each have a secondary-side feed point and are symmetrical about the line of symmetry except for portions attributable to the following: the secondary-side feed point of one of the portions of the secondary-side inductor is moved to be physically closer to the feed point of the other of the portions of the secondary-side inductor.

18. The integrated circuit according to claim 17, further comprising: A control block is used to provide drive signals to drive the first p-type MOSFET, the second p-type MOSFET, the third n-type MOSFET, and the fourth n-type MOSFET of the H-bridge switching circuit; as well as A hysteresis comparator is operatively coupled to the rectifier and provides a feedback signal to the control block.

19. The integrated circuit of claim 18, wherein the control block comprises: Digital control circuits, used to generate control signals; A first non-overlapping drive circuit is used to generate a first pair of complementary non-overlapping drive signals to drive one of the first p-type MOSFET and the second p-type MOSFET, as well as one of the third n-type MOSFET and the fourth n-type MOSFET; as well as The second non-overlapping drive circuit is used to generate a second pair of complementary non-overlapping drive signals to drive the other of the first p-type MOSFET and the second p-type MOSFET, as well as the other of the third n-type MOSFET and the fourth n-type MOSFET.

20. The integrated circuit of claim 17, wherein the transformer has a capacitor midpoint and an inductor midpoint, and the capacitor midpoint and the inductor midpoint are co-located.

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