Techniques for pdsch / pusch processing for multi-trp

Abstract

Techniques are disclosed for physical downlink shared channel (PDSCH) and physical uplink shared channel (PUSCH) processing for multi-transmission and reception point (multi-TRP). In some embodiments, determining PDSCH hybrid automatic repeat request acknowledgement (HARQ-ACK) processing timing can include determining that a user equipment (UE) is configured for single downlink control information (single-DCI) multi-TRP PDSCH operation, determining a first PDSCH and a second PDSCH within a slot, where the first PDSCH and the second PDSCH are used in the single-DCI multi-TRP PDSCH operation, and determining a minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

Description

Technical Field

[0001] This application relates to wireless communication systems in general. Background Technology

[0002] Wireless mobile communication technologies use various standards and protocols to transmit data between base stations and wireless mobile devices. Wireless communication system standards and protocols may include 3GPP Long Term Evolution (LTE) (e.g., 4G) or New Radio (NR) (e.g., 5G); the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard, commonly referred to by the industry organization as WiMAX; and the IEEE 802.11 standard for Wireless Local Area Networks (WLANs), commonly referred to by the industry organization as Wi-Fi. In the 3GPP Radio Access Network (RAN) of an LTE system, a base station may include RAN nodes such as an Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (also commonly referred to as Evolved Node B, Enhanced Node B, eNodeB, or eNB) and / or a Radio Network Controller (RNC) in the E-UTRAN, which communicates with wireless communication equipment called User Equipment (UE). In the fifth generation (5G) wireless RAN, RAN nodes may include 5G nodes and NR nodes (also known as next-generation node B or g NodeB (gNB)).

[0003] The RAN uses Radio Access Technology (RAT) to communicate between RAN nodes and UEs. The RAN can include Global System for Mobile Communications (GSM), Enhanced Data Rate GSM Evolution (EDGE) RAN (GERAN), Universal Terrestrial Radio Access Network (UTRAN), and / or E-UTRAN, which provides access to communication services through the core network. Each RAN operates according to a specific 3GPP RAT. For example, GERAN implements the GSM and / or EDGE RAT, UTRAN implements the Universal System for Mobile Communications (UMTS) RAT or other 3GPP RATs, E-UTRAN implements the LTE RAT, and NG-RAN implements the 5G RAT. In some deployments, E-UTRAN may also implement the 5G RAT.

[0004] 5G NR frequency bands can be divided into two distinct frequency ranges. Frequency range 1 (FR1) includes bands below 6 GHz, some of which may be used by previous standards but could potentially be extended to cover new spectrum offerings from 410 MHz to 7125 MHz. Frequency range 2 (FR2) includes bands from 24.25 GHz to 52.6 GHz. The millimeter wave (mmWave) bands in FR2 have a shorter range but higher available bandwidth than those in FR1. Those skilled in the art will recognize that these frequency ranges, presented by way of example, may vary over time or in different regions. Attached Figure Description

[0005] To facilitate identification of any particular element or action being discussed, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element was first introduced.

[0006] Figure 1 The capability reporting process is illustrated according to some implementation schemes.

[0007] Figure 2 A diagram illustrating a Physical Downlink Shared Channel (PDSCH) according to TDMS scheme A is shown according to some implementation schemes.

[0008] Figure 3 The process for PDSCH processing according to some implementation schemes is shown.

[0009] Figure 4 Another illustration of PDSCH according to TDMSchemeA is shown according to some implementation schemes.

[0010] Figure 5 The process for determining the overall minimum HARQ-ACK processing time according to some implementation schemes is shown.

[0011] Figure 6 The system architecture according to some implementation schemes is shown.

[0012] Figure 7 The infrastructure equipment is shown according to some implementation schemes.

[0013] Figure 8 The platform is shown according to some implementation schemes.

[0014] Figure 9 System components according to some implementation schemes are shown.

[0015] Figure 10 An exemplary system for multiple transmit and receive points (multiple TRPs) operation is shown according to some implementation schemes. Detailed Implementation

[0016] Multiple Transmitter and Receiver Points (Multiple TRPs) is one of the five agendas in Rel-16 eMIMO. For multiple TRPs in NR Rel-16, two operating modes have been agreed upon: multiple downlink control information (multiple DCI) operation (e.g., where multiple DCIs can be used to schedule and / or control transmissions between the UE and the gNB) and single DCI operation (e.g., where a single DCI can be used to schedule and / or control transmissions between the UE and the gNB). For example, in multiple DCI multiple TRPs, multiple physical downlink control channels (PDCCHs) can be received by the UE from multiple TRPs (e.g., multiple gNBs). Each PDCCH can correspond to a different TRP and can schedule physical downlink shared channel (PDSCH) transmissions from its corresponding TRP to the UE. For example, in single DCI multiple TRPs, a single PDCCH can be received by the UE from one of the multiple TRPs (e.g., one gNB). A single PDCCH from one TRP can schedule PDSCH transmissions from each of the multiple TRPs to the UE.

[0017] In a multi-TRP multi-DCI solution, each TRP can be scheduled by a control resource set (CORESET) with a corresponding CORESETPoolIndex from {0,1}. When a CORESETPoolIndex is not configured, it can be assumed to be zero. Up to three CORESETs (BWPs) per bandwidth portion can be configured for each CORESETPoolIndex. Up to a total of five CORESETs can be configured per BWP. In a multi-TRP multi-DCI solution, fully overlapping, partially overlapping, or non-overlapping physical downlink shared channels (PDSCHs) are allowed. Additionally, hybrid automatic repeat request (HARQ) acknowledgment (ACK) feedback supports both "individual" and "joint" feedback modes. Up to two codewords (CWs) and 16 HARQ processes are supported, identical to Rel-15.

[0018] Figure 10An exemplary system 1000 for multiple TRP operations according to some embodiments is shown. In the illustrated embodiment, system 1000 includes gNB 1002, gNB 1004, and UE 1006. UE 1006, as well as one or both of gNB 1002 and gNB 1004, can communicate with other user equipment using signals 1008, 1012, 1016, and 1020. For example, gNB 1002 and / or gNB 1004 are transmit and receive points (TRPs) in system 1000, and UE 1006 supports multiple TRP operations. For example, gNB 1002 transmits signal 1010 of signal 1008 to UE 1006, and UE 1006 transmits signal 1014 of signal 1012 to gNB 1002. For example, gNB 1004 transmits signal 1022 in signal 1020 to UE 1006, and UE 1006 transmits signal 1018 in signal 1016 to gNB 1004.

[0019] Figure 10 The diagram illustrates multi-TRP operation based on a multi-DCI mode. For example, UE 1006 simultaneously receives signals (e.g., signal 1010 and signal 1022) from multiple TRPs (e.g., gNB 1002 and gNB 1004), where signal 1010 and signal 1022 are scheduled by multiple physical downlink control channels (PDCCHs). PDCCHs from different TRPs (e.g., gNB 1002, gNB 1004) can be transmitted from different control resource sets (CORESETs) of each TRP with different CORESET-poolIndex values. For example, signal 1010 and / or signal 1014 used for communication between UE 1006 and gNB 1002 use a PDCCH from CORESET 1, which has a CORESET-poolIndex value of 0. For example, signals 1018 and / or 1022 used for communication between UE 1006 and gNB 1004 use a PDCCH from CORESET 2 with a CORESET-poolIndex value of 1. In some implementations, the network of system 1000 with multiple DCI modes (e.g., gNB 1002 and gNB 1004) may be deployed with ideal or non-ideal backhaul. For example, a system with ideal backhaul may have a latency of less than or approximately 2.5 microseconds and a throughput of up to or approximately 10 Gbps. A system with non-ideal backhaul may have latency and throughput beyond what is provided for ideal backhaul.

[0020] In Rel-15, 3GPP Technical Specification (TS) 38.214 defines two processing capabilities for PDSCH and Physical Uplink Shared Channel (PUSCH). For PDSCH, regarding the timing offset between PDSCH and HARQ-ACK, PDSCH processing capability 1 has regular HARQ-ACK feedback; PDSCH processing capability 2 has low-latency HARQ-ACK feedback. For PUSCH, regarding the timing offset between PDCCH and PUSCH, PUSCH processing capability 1 has regular PUSCH processing; PUSCH processing capability 2 has low-latency PUSCH processing.

[0021] Some embodiments of this disclosure address PDSCH / PUSCH processing capabilities for multi-TRP. Some embodiments provide capability reports for PDSCH / PUSCH processing capabilities. Some embodiments provide PDSCH processing capabilities for the TDMSchemeA single-DCI multi-TRP scheme. Some embodiments provide PDSCH processing capabilities for other single-DCI multi-TRP schemes. Some embodiments of this disclosure implement one or more of the following solutions.

[0022] Solutions 1.1 through 1.9 relate to capability reporting for PDSCH / PUSCH processing.

[0023] Solution 1.1

[0024] In some implementations, PDSCH processing capability 2 is not applicable to multi-DCI multi-TRP operations. For example, when a UE is configured for multi-DCI multi-TRP operation, PDSCH processing capability 2 is not available for the UE. In another example, when all UEs are configured for multi-DCI multi-TRP operation, PDSCH processing capability 2 is not available for any UE.

[0025] Solution 1.2

[0026] In some implementations, PDSCH processing capability 2 is not applicable to single-DCI multi-TRP. For example, when a UE is configured for single-DCI multi-TRP operation, PDSCH processing capability 2 is not available for the UE. In another example, when all UEs are configured for single-DCI multi-TRP operation, PDSCH processing capability 2 is not available for any UE.

[0027] Solution 1.3

[0028] In some implementations, PUSCH processing capability 2 is not applicable to multi-DCI multi-TRP. For example, when a UE is configured for multi-DCI multi-TRP operation, PUSCH processing capability 2 is not available for the UE. In another example, when all UEs are configured for multi-DCI multi-TRP operation, PUSCH processing capability 2 is not available for any UE.

[0029] Solution 1.4

[0030] In some implementations, the UE may indicate support for PDSCH capability 2 for multiple DCI multiple TRP. For example, the UE may issue a report indicating support. This report may be issued by the UE by feature set per component carrier (FSPC) (component carriers (CC) per band combined per band) or by feature set (FS) or by band.

[0031] Solution 1.5

[0032] In some implementations, the UE may indicate support for PUSCH capability 2 for multiple DCI multiple TRP. For example, the UE may issue a report indicating support. This report may be issued by the UE per FSPC (CC per band per band combination), per FS (band per band combination), or per band.

[0033] Solution 1.6

[0034] In some implementations, the UE may indicate support for PDSCH capability 2 for single DCI multiple TRP. For example, the UE may issue a report indicating support. This report may be in bitmap format to cover all five different single DCI multiple TRP schemes (e.g., SDM, FDMSchemeA, FDMSchemeB, TDMSchemeA, Scheme 4). The report may be issued by the UE by FSPC (CC per band per band combination), by FS (band per band combination), or by band.

[0035] For example, in SDM (Spatial Domain Multiplexing), spatial domain multiplexing of a single PDSCH occurs. Each TRP can be mapped to a TCI (Transmission Configuration Indicator) and a demodulation reference signal (DMRS) code division multiplexing (CDM) group.

[0036] For example, in FDMSchemeA (Frequency Domain Multiplexing SchemeA), frequency domain multiplexing of a single PDSCH occurs. Each TRP can be mapped to a TCI and half of the resource elements (REs).

[0037] For example, in FDMSchemeB (Frequency Domain Multiplexing SchemeB), frequency domain multiplexing occurs between two PDSCHs of the same transport block (TB). Each TRP can be mapped to a TCI and half of the RE.

[0038] For example, in TDMSchemeA (Time Domain Multiplexing SchemeA), time domain multiplexing occurs between two PDSCHs of the same TB. Each TRP can be mapped to a TCI with an in-slot TDM.

[0039] For example, in Scheme 4, time-domain multiplexing of multiple PDSCHs occurring within the same TB is possible. Each TRP can be mapped to a TCI or the same TCI with inter-slot TDM.

[0040] Solution 1.7

[0041] In some implementations, the UE may support PUSCH capability 2 for multiple DCI multiple TRP under certain conditions. For example, when there is no out-of-order (OOO) PDCCH to PUSCH scheduling, the UE may support PUSCH capability 2 for multiple DCI multiple TRP.

[0042] Solution 1.8

[0043] In some implementations, the UE may support PDSCH capability 2 for multiple DCI multiple TRP only under certain conditions. For example, the UE may support PDSCH capability 2 for multiple DCI multiple TRP when one, a subset, or all of the following conditions are met: no PDCCH to PDSCH out-of-order (OOO) scheduling, no PDSCH to HARQ-ACK out-of-order (OOO) scheduling, no joint HARQ-ACK feedback, no overlap in time-domain scheduling, no overlap in frequency-domain scheduling, or no cross-carrier scheduling.

[0044] Solution 1.9

[0045] In some implementations, the UE may only support PDSCH / PUSCH capabilities with processing timeline relaxation.2 For example, processing timeline relaxation may be based on UE reports or hard-coded in the specification. For example, in each of the five schemes (e.g., SDM, FDMSchemeA, FDMSchemeB, TDMSchemeA, Scheme 4), processing timeline relaxation may be used independently or jointly for multi-DCI multi-TRP PDSCH, multi-DCI multi-TRP PUSCH, and single-DCI multi-TRP PDSCH.

[0046] Solutions 2.1 through 2.4 relate to PDSCH processing capabilities for TDMScheme A. For example, for TDMScheme A, two PDSCHs can be in a time slot, each PDSCH can be provided with the same duration and frequency resource allocation, the same transport block (TB) can be transmitted twice, and the offset between the first PDSCH and the second PDSCH can be configured via Radio Resource Configuration (RRC) signaling.

[0047] 3GPP TS 38.214 describes the current processing timeline for PDSCH in TDMScheme A. As described in 3GPP TS 38.314, if the first uplink symbol of the PUCCH carrying HARQ-ACK information, as defined by the assigned HARQ-ACK timing K1 and the PUCCH resources to be used and including the effect of timing advance, does not begin earlier than symbol L1, where L1 is defined as the next uplink symbol, and the CP of the PDSCH carrying TB is confirmed after the end of the last symbol of the PDSCH carrying TB, T... proc,1 =(N1+d 1,1 +d2)(2048+144)·κ2 -μ ·T C +T ext Then, the UE will provide a valid HARQ-ACK message.

[0048] For UE processing capability 1: If the PDSCH is mapping type B as given in clause 7.4.1.1 of [4, 3GPP TS 38.211], and

[0049] - If the number of allocated PDSCH symbols is L≥7, then d 1,1 =0,

[0050] - If the number of assigned PDSCH symbols is L≥4 and L≤6, then d 1,1 =7-L.

[0051] -If the number of allocated PDSCH symbols is L = 3, then d 1,1 =3+min(d,1),

[0052] Where d is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0053] - If the number of allocated PDSCH symbols is 2, then d 1,1 =3+d, where d is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0054] For UE processing capability 2: If PDSCH is mapping type B as given in clause 7.4.1.1 of [4, TS 38.211],

[0055] - If the number of allocated PDSCH symbols is L≥7, then d 1,1 =0,

[0056] - If the number of allocated PDSCH symbols is L≥3 and L≤6, then d 1,1 It is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0057] -If the number of PDSCH symbols allocated is 2,

[0058] - If the scheduled PDCCH is in a 3-symbol CORESET, and the CORESET and PDSCH have the same start symbol, then d 1,1 =3,

[0059] -otherwise d 1,1 It is the number of overlapping symbols between the scheduled PDCCH and the scheduled PDSCH.

[0060] The embodiments of this disclosure can determine how to determine the HARQ-ACK processing timing (also referred to as a timeline or time), such as, for example, a minimum HARQ-ACK timeline K1. For example, for a first PDSCH (e.g., PDSCH 1) and a second PDSCH (e.g., PDSCH 2) in a time slot, the minimum HARQ-ACK processing timeline or timing K1 up to the end of PDSCH 2 can be defined as the timing or duration between PDSCH 2 and the corresponding HARQ-ACK in the PUCCH. The timing or duration can be defined by the last symbol of PDSCH 2 (e.g., the last PDSCH repeat) and the first symbol of the PUCCH carrying the corresponding HARQ-ACK. This timing or duration can provide the UE with the time to process the PDSCH. The embodiments of this disclosure can provide a solution for determining this minimum HARQ-ACK processing timeline or timing K1 up to the end of PDSCH 2.

[0061] Solution 2.1

[0062] In some implementations, the minimum HARQ-ACK processing timeline up to the end of PDSCH 2 may be based solely on PDSCH 1. For example, only symbols from PDSCH 1 may be considered.

[0063] Solution 2.2

[0064] In some implementations, the minimum HARQ-ACK processing timeline to the end of PDSCH 2 can consider all symbols from the beginning of PDSCH 1 to the end of PDSCH 2, where blank symbols between PDSCH 1 and PDSCH 2 are counted. For example, all symbols from the first symbol of PDSCH 1 to the last symbol of PDSCH 2 (inclusive) can be considered as PDSCH transmissions. The duration L can correspond to the number of overlapping symbols with the CORESET / schedule PDCCH. For example, if PDSCH 1 has 4 symbols, followed by a 2-symbol gap (e.g., 2 blank symbols), followed by PDSCH 2 with 4 symbols, then all symbols are considered for PDSCH 1, PDSCH 2, and the gap. Therefore, the duration L = 4 symbols of PDSCH 1 + 2 symbols of the gap + 4 symbols of PDSCH 2 = 10.

[0065] Solution 2.3

[0066] In some implementations, the minimum HARQ-ACK processing timeline to the end of PDSCH 2 may consider all symbols in both PDSCH 1 and PDSCH 2. For example, all symbols in PDSCH 1 and PDSCH 2 as a whole may be considered, but blank symbols between PDSCH 1 and PDSCH 2 may not be counted. The duration L may correspond to the number of overlapping symbols with the CORESET / schedule PDCCH. For example, if PDSCH 1 has 4 symbols, followed by a 2-symbol gap (e.g., 2 blank symbols), followed by PDSCH 2 with 4 symbols, then only the symbols used for PDSCH 1 and PDSCH 2 are considered. The symbols in the gap are not considered. Therefore, the duration L = 4 symbols of PDSCH 1 + 4 symbols of PDSCH 2 = 8.

[0067] Solution 2.4

[0068] In some implementations, the minimum HARQ-ACK processing timeline K1 up to the end of PDSCH 2 may be jointly based on PDSCH 1 and PDSCH 2. For example, for PDSCH 1, the minimum HARQ-ACK processing time k1_1 may be calculated, and for PDSCH 2, the minimum HARQ-ACK processing time k1_2 may be calculated.

[0069] For example, the actual minimum HARQ-ACK processing time K1 can be equal to one of the following alternative forms: 1) max(k1_1-Offset,0)+k1_2+C; 2) max(k1_1,k1_2)+C; or 3) k1_1+k1_2+C. For example, C can be zero, or used to provide additional timeline relaxation.

[0070] In some implementations, PDSCH processing capabilities for multiple DCI and multiple TRP can be provided.

[0071] Solution 3.1

[0072] In some implementations, for multi-DCI-based multi-TRP, the minimum HARQ-ACK timeline to the end of PDSCH 2 is based on the same design as TDMSchemeA. For example, it may be based on solutions 2.1, 2.2, 2.3 and / or 2.4 discussed above.

[0073] In some implementations, PDSCH processing capabilities can be provided for other single DCI multi-TRPs.

[0074] Solution 4.1

[0075] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS38.214, discussed above) can be used for the SDMSDCI MTRP scheme, since the two PDSCHs overlap. Additional relaxation may be included to account for the UE interference handling timeline.

[0076] Solution 4.2

[0077] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS 38.214, discussed above) can be used for the FDMSchemeA SDCI MTRP scheme.

[0078] Solution 4.3

[0079] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS 38.214, discussed above) can be used for the FDMSchemeB SDCI MTRP scheme, and relaxation may be included, for example, when the UE supports CW soft combining.

[0080] Solution 4.4

[0081] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS 38.214, discussed above) can be used for the Scheme 4SDCI MTRP scheme based on the timing of the first PDSCH transmission.

[0082] Figure 1 A capability reporting process 100 according to some implementation schemes is shown.

[0083] At box 102, UE configurations for multi-DCI multi-TRP operation and single-DCI multi-TRP operation are determined. In some embodiments, a UE configuration for multi-DCI multi-TRP only is determined. In some embodiments, a UE configuration for single-DCI multi-TRP only is determined. In some embodiments, a UE configuration for both multi-DCI multi-TRP operation and single-DCI multi-TRP operation is determined.

[0084] At box 104, the PDSCH processing capability for the timing offset between PDSCH and HARQ-ACK is determined for the identified multi-DCI multi-TRP operation and / or single-DCI multi-TRP operation. In some embodiments, PDSCH processing capability 1 uses conventional HARQ-ACK feedback for the timing offset between PDSCH and HARQ-ACK. In some embodiments, PDSCH processing capability 2 uses low-latency HARQ-ACK feedback for the timing offset between PDSCH and HARQ-ACK.

[0085] In some implementations, the PDSCH processing capability is designated as PDSCH processing capability 1. In some implementations, the PDSCH processing capability is designated as PDSCH processing capability 2.

[0086] In some implementations, PDSCH processing capability 2 is not applicable to multi-DCI multi-TRP operations. For example, when a UE is configured for multi-DCI multi-TRP operations, PDSCH processing capability 2 is not available for the UE. In another example, when all UEs are configured for multi-DCI multi-TRP operations, PDSCH processing capability 2 is not available for any UE.

[0087] In some implementations, PDSCH processing capability 2 is applicable to multi-DCI multi-TRP operations. For example, when a UE is configured for multi-DCI multi-TRP operations, the UE can operate using PDSCH processing capability 2. In another example, when all UEs are configured for multi-DCI multi-TRP operations, all UEs can operate using PDSCH processing capability 2.

[0088] In some implementations, the UE may support PDSCH capability 2 for multiple DCI multiple TRP only under certain conditions. For example, the UE may support PDSCH capability 2 for multiple DCI multiple TRP when one, a subset, or all of the following conditions are met: no PDCCH to PDSCH out-of-order (OOO) scheduling, no PDSCH to HARQ-ACK out-of-order (OOO) scheduling, no joint HARQ-ACK feedback, no overlap in time-domain scheduling, no overlap in frequency-domain scheduling, or no cross-carrier scheduling.

[0089] In some implementations, PDSCH processing capability 2 is not applicable to single-DCI multi-TRP. For example, when a UE is configured for single-DCI multi-TRP operation, PDSCH processing capability 2 is not available for the UE. In another example, when all UEs are configured for single-DCI multi-TRP operation, PDSCH processing capability 2 is not available for any UE.

[0090] In some implementations, PDSCH processing capability 2 is applicable to single DCI multiple TRP. For example, when a UE is configured for single DCI multiple TRP operation, the UE can operate using PDSCH processing capability 2. In another example, when all UEs are configured for single DCI multiple TRP operation, all UEs can operate using PDSCH processing capability 2.

[0091] At box 106, support for the determined PDSCH processing capability is indicated. In some implementations, the UE may indicate support for PDSCH capability 2 for multiple DCI multiple TRPs. For example, the UE may generate a report to indicate support and issue or transmit the report. This report may be issued by the UE by feature set per component carrier (FSPC) (CC per band per band combination) or by feature set (FS) or by band. In some implementations, the UE may indicate support for PDSCH capability 2 for single DCI multiple TRPs. For example, the UE may issue a report to indicate support. This report may be in bitmap format to cover all five different single DCI multiple TRP schemes (e.g., SDM, FDMSchemeA, FDMSchemeB, TDMSchemeA, Scheme 4). This report may be issued by the UE by FSPC (CC per band per band combination) or by FS (band per band combination) or by band.

[0092] At box 108, the PUSCH processing capability for the timing offset between the PDCCH and PUSCH is determined for the identified multi-DCI multi-TRP operation and / or single-DCI multi-TRP operation. In some embodiments, PUSCH processing capability 1 uses regular PUSCH processing for the timing offset between the PDCCH and PUSCH. In some embodiments, PUSCH processing capability 2 uses low-latency PUSCH processing for the timing offset between the PDCCH and PUSCH.

[0093] In some implementations, the PUSCH processing capability is designated as PUSCH processing capability 1. In some implementations, the PUSCH processing capability is designated as PUSCH processing capability 2.

[0094] In some implementations, PUSCH processing capability 2 is not applicable to multi-DCI multi-TRP. For example, when a UE is configured for multi-DCI multi-TRP operation, PUSCH processing capability 2 is not available for the UE. In another example, when all UEs are configured for multi-DCI multi-TRP operation, PUSCH processing capability 2 is not available for any UE.

[0095] In some implementations, the UE may support PUSCH capability 2 for multiple DCI multiple TRP under certain conditions. For example, when there is no out-of-order (OOO) PDCCH to PUSCH scheduling, the UE may support PUSCH capability 2 for multiple DCI multiple TRP.

[0096] At box 110, support for the determined PUSCH processing capability is indicated. In some implementations, the UE may indicate support for PUSCH capability 2 for multiple DCI multiple TRP. For example, the UE may generate a report to indicate support and issue or transmit the report. The report may be issued by the UE per FSPC (CC per band per band combination), per FS (band per band combination), or per band.

[0097] In some implementations, the reports of boxes 106 and 110 can be combined to generate a combined report that includes the reports of boxes 106 and 110 and then issue or transmit the combined report.

[0098] Regarding boxes 104 and 108, in some implementations, the UE may only support PDSCH and / or PUSCH capabilities with processing timeline relaxation. For example, processing timeline relaxation may be based on UE reports or hard-coded in the specification. For example, in each of the five schemes (e.g., SDM, FDMSchemeA, FDMSchemeB, TDMSchemeA, Scheme 4), processing timeline relaxation may be used independently or jointly for multi-DCI multi-TRP PDSCH, multi-DCI multi-TRP PUSCH, and single-DCI multi-TRP PDSCH.

[0099] Figure 2 A diagram 200 illustrating a PDSCH according to TDMScheme A is shown according to some embodiments. Here, two PDSCHs, namely PDSCH 1 (202) and PDSCH 2 (204), are located in time slot 208. PDSCH 1 (202) and PDSCH 2 (204) are separated within time slot 208 by offset 206. For example, offset 206 is between the last symbol of PDSCH 1 and the first symbol of PDSCH 2. In some embodiments, PDSCH 1 and PDSCH 2 have the same duration and frequency resource allocation. In some embodiments, PDSCH 1 and PDSCH 2 have different durations and / or frequency resource allocations. In some embodiments, a transport block (TB) is transmitted twice by the UE within this time slot. In some embodiments, offset 206 between PDSCH 1 (202) and PDSCH 2 (204) is configured via RRC.

[0100] In some embodiments, PDSCH 1 (202) and PDSCH 2 (204) each include a set of symbols describing their payloads. In some embodiments, the region represented by offset 206 between the end of PDSCH 1 (202) (e.g., the last symbol of PDSCH 1) and the beginning of PDSCH 2 (204) (e.g., the first symbol of PDSCH 2) includes one or more blank symbols corresponding to the duration of offset 206.

[0101] As discussed above, 3GPP TS 38.214 describes the processing timeline for PDSCH in TDMScheme A. As described in 3GPP TS 38.314, if the first uplink symbol of the PUCCH carrying HARQ-ACK information, as defined by the assigned HARQ-ACK timing K1 and the PUCCH resources to be used and including the effect of timing advance, does not begin earlier than symbol L1, where L1 is defined as the next uplink symbol, and the CP of the PDSCH carrying the TB is confirmed after the end of the last symbol of the PDSCH carrying the TB, then...proc,1 =(N1+d 1,1 +d2)(2048+144)·κ2 -μ ·T C +T ext Then, the UE will provide a valid HARQ-ACK message. The parameters of this equation are defined below.

[0102] For UE processing capability 1: If PDSCH is the mapping type B given in clause 7.4.1.1 of [4, TS 38.211], and

[0103] - If the number of allocated PDSCH symbols is L≥7, then d 1,1 =0,

[0104] - If the number of assigned PDSCH symbols is L≥4 and L≤6, then d 1,1 =7-L.

[0105] -If the number of allocated PDSCH symbols is L = 3, then d 1,1 =3+min(d,1), where d is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0106] - If the number of allocated PDSCH symbols is 2, then d 1,1 =3+d, where d is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0107] For UE processing capability 2: If PDSCH is mapping type B as given in clause 7.4.1.1 of [4, TS 38.211],

[0108] - If the number of allocated PDSCH symbols is L≥7, then d 1,1 =0,

[0109] - If the number of allocated PDSCH symbols is L≥3 and L≤6, then d 1,1 It is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0110] -If the number of PDSCH symbols allocated is 2,

[0111] - If the scheduled PDCCH is in a 3-symbol CORESET, and the CORESET and PDSCH have the same start symbol, then d 1,1 =3,

[0112] -otherwise d 1,1 It is the number of overlapping symbols between the scheduled PDCCH and the scheduled PDSCH.

[0113] In some implementations, the HARQ-ACK processing timing K1 is determined, as shown in the reference. Figures 3 to 5 As described. In some implementations, a minimum HARQ-ACK timing K1 is determined.

[0114] Figure 3 A process 300 for PDSCH processing according to some implementation schemes is shown.

[0115] At box 302, a single DCI multiple TRP PDSCH operation is determined. In some embodiments, the single DCI multiple TRP PDSCH operation is a TDMScheme A operation. In some embodiments, this determination includes determining that the UE is configured for a single DCI multiple TRP PDSCH operation. In some embodiments, this determination includes determining that the UE is configured for a TDMScheme A operation.

[0116] At block 304, the first and second PDSCHs (e.g., PDSCH 1 (202) and PDSCH 2 (204)) within a time slot (e.g., time slot 208) are determined according to the determined single-DCI multi-TRP PDSCH operation. For example, the first and second PDSCHs can be used in the determined single-DCI multi-TRP PDSCH operation. In some embodiments, the duration and / or frequency resource allocation for each PDSCH is determined. In some embodiments, for example when the single-DCI multi-TRP PDSCH operation is TDMScheme A, the duration and / or frequency resource allocation for the first and second PDSCHs are the same.

[0117] At block 306, the HARQ-ACK timing for the first PDSCH and the second PDSCH is determined. In some embodiments, the determined HARQ-ACK timing is a minimum HARQ-ACK timing. In some embodiments, one or more symbols of the first PDSCH are used to determine the minimum HARQ-ACK timing. In some embodiments, one or more symbols of the first PDSCH and the second PDSCH are used to determine the minimum HARQ-ACK timing.

[0118] In some implementations, the minimum HARQ-ACK timing is until the end of the second PDSCH. Here, for example, for the first and second PDSCHs in a time slot, the minimum HARQ-ACK processing timeline or timing K1 until the end of the second PDSCH can be defined as the timing or duration between the corresponding HARQ-ACK in the second PDSCH and the PUCCH. The timing or duration can be defined by the last symbol of the second PDSCH (e.g., the last PDSCH repeats) and the first symbol of the PUCCH carrying the corresponding HARQ-ACK. This timing or duration provides the UE with time to process the PDSCH.

[0119] In some implementations, the minimum HARQ-ACK timing to the end of the second PDSCH may be determined based solely on the first PDSCH. For example, only symbols from the first symbol of the first PDSCH (e.g., PDSCH 1 (202)) to the last symbol of the first PDSCH are considered for PDSCH transmission and the minimum HARQ-ACK timing is determined.

[0120] In some implementations, the minimum HARQ-ACK processing timing up to the end of the second PDSCH may consider all symbols from the beginning of the first PDSCH to the end of the second PDSCH, where blank symbols between the first and second PDSCHs are counted. For example, for PDSCH transmission and to determine the minimum HARQ-ACK timing, all symbols from the first symbol of the first PDSCH to the last symbol of the second PDSCH (inclusive) may be considered. For example, the duration L may correspond to the number of overlapping symbols with the CORESET / schedule PDSCH. For example, if the first PDSCH has 4 symbols, followed by a 2-symbol gap (e.g., 2 blank symbols), followed by a second PDSCH with 4 symbols, then all symbols are considered for the first PDSCH, the second PDSCH, and the gap. Therefore, the duration L = 4 symbols of the first PDSCH + 2 symbols of the gap + 4 symbols of the second PDSCH = 10.

[0121] In some implementations, the minimum HARQ-ACK processing timeline up to the end of the second PDSCH may consider all symbols in both the first and second PDSCHs. For example, for PDSCH transmission and to determine the minimum HARQ-ACK timing, all symbols in both the first and second PDSCHs may be considered as a whole, but blank symbols between the first and second PDSCHs (e.g., in the offset region between them) may not be counted. For example, the duration L may correspond to the number of overlapping symbols with the CORESET / schedule PDSCH. For example, if the first PDSCH has 4 symbols, followed by a 2-symbol gap (e.g., 2 blank symbols), followed by a second PDSCH with 4 symbols, then only the symbols used for the first and second PDSCHs are considered. The symbols for the gap are not considered. Therefore, the duration L = 4 symbols of the first PDSCH + 4 symbols of the second PDSCH = 8.

[0122] Figure 4 A diagram 400 illustrating a PDSCH according to TDMScheme A is shown according to some embodiments. Here, two PDSCHs, namely a first PDSCH (PDSCH 1 (402)) and a second PDSCH (PDSCH 2 (404)), are separated by an offset 406. In some embodiments, the first PDSCH and the second PDSCH have the same duration and frequency resource allocation. In some embodiments, the first PDSCH and the second PDSCH have different durations and / or frequency resource allocations. In some embodiments, a transport block (TB) is transmitted twice by the UE within this time slot. In some embodiments, the offset 406 between the first PDSCH 402 and the second PDSCH 404 is configured via RRC.

[0123] As shown in Figure 400, the initial minimum HARQ-ACK processing timing k1_1 is shown in item 408, and the initial minimum HARQ-ACK processing timing k1_2 is shown in item 410. k1_1 and k1_2 are described below regarding... Figure 5 The method discussed is used to determine the overall minimum HARQ-ACK processing time K1.

[0124] In fact, Figure 5 A process 500 is shown for determining the overall minimum HARQ-ACK processing time K1 using values ​​k1_1 and k1_2. Therefore, here, the minimum HARQ-ACK processing timeline to the end of the second PDSCH is jointly based on the first PDSCH (PDSCH 1 (402)) and the second PDSCH (PDSCH 2 (404)). In some embodiments, process 500 reflects... Figure 3The exemplary blocks 304 and 306 of process 300 are shown.

[0125] At box 502, the minimum HARQ-ACK processing timing k1_1 is determined for the first PDSCH.

[0126] At box 504, the minimum HARQ-ACK processing timing k1_2 is determined for the second PDSCH.

[0127] At box 506, k1_1 and k1_2 are used to determine the overall minimum HARQ-ACK processing timing (also called time) K1 for the first PDSCH and the second PDSCH. In some embodiments, the overall minimum HARQ-ACK processing time K1 = max(k1_1 - Offset, 0) + k1_2 + C. In some embodiments, the overall minimum HARQ-ACK processing time K1 = max(k1_1, k1_2) + C. In some embodiments, the overall minimum HARQ-ACK processing time K1 = k1_1 + k1_2 + C. For example, Offset can be the offset between the first PDSCH and the second PDSCH (e.g., offset 406). For example, Offset can be the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH. For example, C can be a constant and can be zero, or can be set to provide a value for additional timeline relaxation. For example, "max(X,Y)" means selecting the maximum value of a series of values ​​X and Y within the parentheses. Therefore, if X is greater than Y, then max(X,Y) = X.

[0128] It should be noted that in some implementations, for multi-DCI-based multi-TRP, the minimum HARQ-ACK timeline to the end of the second PDSCH (PDSCH 2 (404)) uses the same process described above for TDMScheme A. For example, it can be used Figures 2 to 5 One or more of the techniques described herein are used to perform the determination of minimum HARQ-ACK for multi-TRP based on multi-DCI.

[0129] In some implementations, PDSCH processing capabilities for other single DCI MTRPs can also be provided.

[0130] The processing timeline for PDSCH for TDMScheme A described in 3GPP TS 38.214 can also be used in the following implementation. As described in 38.214, if the first uplink symbol of the PUCCH carrying HARQ-ACK information, as defined by the assigned HARQ-ACK timing K1 and the PUCCH resources to be used and including the effect of timing advance, does not begin earlier than at symbol L1, where L1 is defined as the next uplink symbol, and the CP of the PDSCH carrying TB is confirmed after the end of the last symbol of the PDSCH carrying TB, T proc,1 =(N1+d 1,1 +d2)(2048+144)·κ2 -μ ·T C +T ext Then, the UE will provide a valid HARQ-ACK message. The parameters of this equation are defined below.

[0131] For UE processing capability 1: If PDSCH is the mapping type B given in clause 7.4.1.1 of [4, TS 38.211], and

[0132] - If the number of allocated PDSCH symbols is L≥7, then d 1,1 =0,

[0133] - If the number of assigned PDSCH symbols is L≥4 and L≤6, then d 1,1 =7-L.

[0134] -If the number of allocated PDSCH symbols is L = 3, then d 1,1 =3+min(d,1),

[0135] Where d is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0136] - If the number of allocated PDSCH symbols is 2, then d 1,1 =3+d, where d is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0137] For UE processing capability 2: If PDSCH is mapping type B as given in clause 7.4.1.1 of [4, TS 38.211],

[0138] - If the number of allocated PDSCH symbols is L≥7, then d 1,1 =0,

[0139] - If the number of allocated PDSCH symbols is L≥3 and L≤6, then d 1,1It is the number of overlapping symbols between the scheduling PDCCH and the scheduled PDSCH.

[0140] -If the number of PDSCH symbols allocated is 2,

[0141] - If the scheduled PDCCH is in a 3-symbol CORESET, and the CORESET and PDSCH have the same start symbol, then d 1,1 =3,

[0142] -otherwise d 1,1 It is the number of overlapping symbols between the scheduled PDCCH and the scheduled PDSCH.

[0143] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS38.214, discussed above) can be used for the SDMSDCI MTRP scheme, since the two PDSCHs overlap. Additional relaxation may be included to account for the UE interference handling timeline.

[0144] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS 38.214, discussed above) can be used for the FDMSchemeA SDCI MTRP scheme.

[0145] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS 38.214, discussed above) can be used for the FDMSchemeB SDCI MTRP scheme, and relaxation may be included, for example, when the UE supports CW soft combining.

[0146] In some implementations, to determine the minimum HARQ-ACK timeline to the end of PDSCH 2, the same scheme as Rel-15 (3GPP TS 38.214, discussed above) can be used for the Scheme 4SDCI MTRP scheme based on the timing of the first PDSCH transmission.

[0147] Figure 6Exemplary architectures of network system 600 according to various implementations are shown. The following description is provided for example system 600 operating in combination with LTE system standards and 5G or NR system standards provided by 3GPP technical specifications. However, the exemplary implementations are not limited in this respect, and the implementations can be applied to other networks that benefit from the principles described herein, such as future 3GPP systems (e.g., sixth generation (6G)) systems, IEEE 802.16 protocols (e.g., WMAN, WiMAX, etc.), etc.

[0148] like Figure 6 As shown, system 600 includes UE 622 and UE 620. In this example, UE 622 and UE 620 are shown as smartphones (e.g., handheld touchscreen mobile computing devices that can connect to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as consumer electronics devices, mobile phones, smartphones, feature phones, tablets, wearable computing devices, personal digital assistants (PDAs), pagers, wireless handheld devices, desktop computers, laptops, in-vehicle infotainment (IVI), in-vehicle entertainment (ICE) devices, instrument cluster (IC), head-up display (HUD) devices, onboard diagnostic (OBD) devices, dashboard mobile equipment (DME), mobile data terminal (MDT), electronic engine management system (EEMS), electronic / engine electronic control unit (ECU), electronic / engine electronic control module (ECM), embedded systems, microcontrollers, control modules, engine management system (EMS), connected or “smart” appliances, MTC devices, M2M, IoT devices, etc.

[0149] In some implementations, UE 622 and / or UE 620 may be IoT UEs, which may include a network access layer designed to utilize low-power IoT applications with short-lived UE connections. IoT UEs may utilize technologies such as M2M or MTC to exchange data with MTC servers or devices via PLMN, ProSe, or D2D communication, sensor networks, or IoT networks. M2M or MTC data exchange may be machine-initiated data exchange. An IoT network describes interconnected IoT UEs, which may include uniquely identifiable embedded computing devices (within the internet infrastructure) with short-lived connections. IoT UEs may execute background applications (e.g., keeping track of activity messages, status updates, etc.) to facilitate connectivity within the IoT network.

[0150] UE 622 and UE 620 can be configured to connect to an access node or radio access node (shown as (R)AN 608), for example, communicatively coupled. In embodiments, (R)AN 608 can be an NG RAN or SG RAN, E-UTRAN, or a legacy RAN such as UTRAN or GERAN. As used herein, the term "NG RAN," etc., can refer to (R)AN 608 operating in an NR or SG system, and the term "E-UTRAN," etc., can refer to (R)AN 608 operating in an LTE or 4G system. UE 622 and UE 620 utilize connections (or channels) (shown as connection 604 and connection 602, respectively), each connection including a physical communication interface or layer (discussed in further detail below).

[0151] In this example, connections 604 and 602 are air interfaces for communication coupling and are compatible with cellular communication protocols such as GSM, CDMA, PTT, POC, UMTS, 3GPP LTE, SG, NR, and / or any other communication protocols discussed herein. In an implementation, UE 622 and UE 620 may also exchange communication data directly via ProSe interface 610. ProSe interface 610 may alternatively be referred to as sidelink (SL) interface 110 and may include one or more logical channels, including but not limited to PSCCH, PSSCH, PSDCH, and PSBCH.

[0152] UE 620 is shown configured to access AP 612 (also known as a "WLAN node", "WLAN", "WLAN terminal", "WT", etc.) via connection 624. Connection 624 may include a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where AP 612 will include Wireless Fibre. Router. In this example, AP 612 may connect to the Internet but not to the core network of the wireless system (described in further detail below). In various implementations, UE 620, (R)AN 608, and AP 612 may be configured to utilize LWA operation and / or LWIP operation. LWA operation may involve UE 620 in RRC_CONNECTED being configured by RAN node 614 or RAN node 616 to utilize the radio resources of LTE and WLAN. LWIP operation may involve UE 620 using WLAN radio resources (e.g., connection 624) via IPsec protocol tunneling to authenticate and encrypt packets (e.g., IP packets) transmitted through connection 624. IPsec tunneling may include encapsulating the entire original IP packet and adding a new packet header to protect the original header of the IP packet.

[0153] (R)AN 608 may include one or more AN nodes, such as RAN node 614 and RAN node 616, that implement connection 604 and connection 602. As used herein, the terms “access node,” “access point,” etc., can describe equipment that provides radio baseband functionality for data and / or voice connections between the network and one or more users. These access nodes may be referred to as BS, gNB, RAN node, eNB, NodeB, RSU, TRxP, or TRP, etc., and may include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., a cell). As used herein, the terms “NG RAN node,” etc., can refer to a RAN node (e.g., gNB) operating in an NR or SG system, while the terms “E-UT RAN node,” etc., can refer to a RAN node (e.g., eNB) operating in an LTE or 4G system 600. According to various implementation schemes, RAN node 614 or RAN node 616 may be implemented as one or more of dedicated physical devices such as macro cell base stations and / or low-power (LP) base stations for providing smaller coverage areas, smaller user capacity or higher bandwidth compared to macro cells.

[0154] In some implementations, all or part of RAN node 614 or RAN node 616 may be implemented as one or more software entities running on a server computer as part of a virtual network, which may be referred to as CRAN and / or Virtual Baseband Unit Pool (vBBUP). In these implementations, CRAN or vBBUP may implement RAN function partitioning, such as PDCP partitioning, where the RRC and PDCP layers are operated by CRAN / vBBUP, while other L2 protocol entities are operated by individual RAN nodes (e.g., RAN node 614 or RAN node 616); MAC / PHY partitioning, where the RRC, PDCP, RLC, and MAC layers are operated by CRAN / vBBUP, and the PHY layer is operated by individual RAN nodes (e.g., RAN node 614 or RAN node 616); or “lower PHY” partitioning, where the upper portion of the RRC, PDCP, RLC, MAC, and PHY layers is operated by CRAN / vBBUP, and the lower portion of the PHY layer is operated by individual RAN nodes. This virtualization framework allows idle processor cores of RAN node 614 or RAN node 616 to execute other virtualized applications. In some specific implementations, each RAN node can represent a connection via each F1 interface ( Figure 6(Not shown) Individual gNB-DUs connected to the gNB-CU. In these specific implementations, the gNB-DU may include one or more remote radio head units or RFEMs, and the gNB-CU may be operated by a server (not shown) located in (R)AN 608 or by a server pool in a manner similar to CRAN / vBBUP. Additionally or alternatively, one or more of RAN node 614 or RAN node 616 may be a next-generation eNB (ng-eNB), which is a RAN node that provides E-UTRA user plane and control plane protocol termination to UE 622 and UE 620 and is connected to the SGC via the NG interface (discussed below). In V2X scenarios, one or more of RAN nodes 614 or RAN node 616 may be an RSU or act as an RSU.

[0155] The term "roadside unit" or "RSU" can refer to any traffic infrastructure entity used for V2X communication. An RSU can be implemented in or by a suitable RAN node or a stationary (or relatively stationary) UE, wherein an RSU implemented in or by a UE can be referred to as a "UE-type RSU," an RSU implemented in or by an eNB can be referred to as an "eNB-type RSU," an RSU implemented in or by a gNB can be referred to as a "gNB-type RSU," and so on. In one example, an RSU is a computing device coupled to radio frequency circuitry located on the roadside that provides connectivity support to passing vehicle UEs (vUEs). An RSU may also include internal data storage circuitry for storing intersection map geometry, traffic statistics, media, and applications / software for sensing and controlling ongoing vehicle and pedestrian traffic. An RSU can operate on the 5.9 GHz Direct Near Range Communication (DSRC) band to provide extremely low-latency communication required for high-speed events, such as collision avoidance and traffic warnings. Alternatively or in addition to this, the RSU may operate on a cellular V2X band to provide the aforementioned low-latency communications and other cellular communication services. Alternatively or in addition to this, the RSU may operate as a Wi-Fi hotspot (2.4 GHz band) and / or provide connectivity to one or more cellular networks to provide uplink and downlink communications. Some or all of the computing device and the RSU's radio frequency circuitry may be packaged in a weather-resistant package suitable for outdoor installation and may include a network interface controller to provide wired connectivity (e.g., Ethernet) to traffic signal controllers and / or backhaul networks.

[0156] RAN node 614 and / or RAN node 616 may terminate the air interface protocol and may be the first point of contact for UE 622 and UE 620. In some implementations, RAN node 614 and / or RAN node 616 may perform various logical functions of (R)AN 608, including but not limited to Radio Network Controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0157] In the implementation, UE 622 and UE 620 may be configured to communicate with each other or with RAN node 614 and / or RAN node 616 on a multi-carrier communication channel using OFDM communication signals according to various communication technologies, such as, but not limited to, OFDMA communication technology (e.g., for downlink communication) or SC-FDMA communication technology (e.g., for uplink and ProSe or sidelink communication), although the scope of the implementation is not limited in this respect. The OFDM signal may include multiple orthogonal subcarriers.

[0158] In some implementations, the downlink resource grid can be used for downlink transmissions from RAN node 614 and / or RAN node 616 to UE 622 and UE 620, while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, referred to as a resource grid or time-frequency resource grid, which represents the physical resources in the downlink within each time slot. This time-frequency plane representation is common practice for OFDM systems, making radio resource allocation intuitive. Each column and row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to a time slot in a radio frame. The smallest time-frequency unit in the resource grid is represented as a resource element. Each resource grid comprises multiple resource blocks that describe the mapping of certain physical channels to resource elements. Each resource block comprises a set of resource elements; in the frequency domain, this can represent the minimum amount of resources currently available for allocation. Such resource blocks are used to transmit several different physical downlink channels.

[0159] According to various implementations, UE 622 and UE 620, as well as RAN node 614 and / or RAN node 616, transmit (e.g., transmit and receive) data via licensed media (also referred to as “licensed spectrum” and / or “licensed band”) and unlicensed shared media (also referred to as “unlicensed spectrum” and / or “unlicensed band”). Licensed spectrum may include channels operating in the frequency range of approximately 400 MHz to approximately 3.8 GHz, while unlicensed spectrum may include a 5 GHz band.

[0160] To operate in unlicensed spectrum, UEs 622 and 620, along with RAN node 614 or RAN node 616, may use LAA, eLAA, and / or feLAA mechanisms. In these specific implementations, UEs 622 and 620, along with RAN node 614 or RAN node 616, may perform one or more known media sensing and / or carrier sensing operations to determine whether one or more channels in the unlicensed spectrum are unavailable or otherwise occupied before transmission in the unlicensed spectrum. Media / carrier sensing operations may be performed according to a Listen-After-Speak (LBT) protocol.

[0161] LBT is a mechanism by which equipment (e.g., UE 622 and UE 620, RAN node 614 or RAN node 616, etc.) senses a medium (e.g., a channel or carrier frequency) and transmits when that medium is sensed to be idle (or when a specific channel in that medium is sensed to be unoccupied). The medium sensing operation may include CCA, which utilizes at least ED to determine the presence of other signals on the channel in order to determine whether the channel is occupied or idle. This LBT mechanism allows cellular / LAA networks to coexist with existing systems in unlicensed spectrum and with other LAA networks. ED may include sensing RF energy in the intended transmission band over a period of time and comparing the sensed RF energy with a predefined or configured threshold.

[0162] Typically, existing systems in the 5GHz band are WLANs based on IEEE 802.11 technology. WLANs employ a contention-based channel access mechanism called CSMA / CA. Here, when a WLAN node (e.g., a mobile station (MS) such as UE 622, AP612, etc.) intends to transmit, the WLAN node can first perform CCA before transmitting. Additionally, in cases where more than one WLAN node senses the channel as idle and transmits simultaneously, a backoff mechanism is used to avoid collisions. This backoff mechanism can be a counter randomly introduced within the CWS, which increases exponentially upon collision and resets to a minimum value upon successful transmission. The LBT mechanism designed for LAA is somewhat similar to WLAN's CSMA / CA. In some specific implementations, the LBT process for DL ​​or UL transmission bursts (including PDSCH or PUSCH transmissions) can have a variable-length LAA contention window between the X and Y ECCA time slots, where X and Y are the minimum and maximum values ​​of the LAA's CWS. In one example, the minimum CWS for LAA transmission can be 9 microseconds (μs); however, the size of the CWS and MCOT (e.g., transmission burst) can be based on government regulatory requirements.

[0163] The LAA mechanism is built upon the CA technology of LTE-Advanced systems. In CA, each aggregated carrier is called a CC. A CC can have a bandwidth of 1.4, 3, 5, 10, 15, or 20 MHz, and a maximum of five CCs can be aggregated, thus the maximum aggregated bandwidth is 100 MHz. In FDD systems, the number of aggregated carriers can differ for DL ​​and UL, where the number of UL CCs is equal to or less than the number of DL component carriers. In some cases, individual CCs can have different bandwidths than the other CCs. In TDD systems, the number of CCs and the bandwidth of each CC are usually the same for DL ​​and UL.

[0164] The CA also includes individual serving cells to provide individual CCs. The coverage of serving cells can differ, for example, because CCs on different frequency bands will experience different path losses. The primary serving cell, or PCell, provides PCCs for both UL and DL and handles activities related to RRC and NAS. Other serving cells are called SCells, and each SCell provides individual SCCs for both UL and DL. SCCs can be added and removed as needed, while changing the PCC may require the UE to undergo a handover. In LAA, eLAA, and feLAA, some or all of the SCells can operate in unlicensed spectrum (referred to as "LAA SCells"), and LAA SCells are assisted by PCells operating in licensed spectrum. When a UE is configured to have more than one LAA SCell, the UE can receive UL grants on the configured LAA SCells, indicating different PUSCH start positions within the same subframe.

[0165] The PDSCH carries user data and higher-layer signaling to UEs 622 and 620. Among other information, the PDCCH carries information about the transmission format and resource allocation related to the PDSCH channel. It can also inform UEs 622 and 620 about the transmission format, resource allocation, and HARQ information related to the uplink shared channel. Typically, downlink scheduling (allocating control and shared channel resource blocks to UEs 620 within the cell) can be performed at either RAN node 614 or RAN node 616 based on channel quality information fed back from either UE 622 or UE 620. Downlink resource allocation information can be transmitted on the PDCCH used (e.g., allocated to) each of UEs 622 and UE 620.

[0166] PDCCH uses CCEs to transmit control information. Before being mapped to resource elements, the complex-valued symbols of the PDCCH can first be organized into quadruplets, which can then be arranged using a sub-block interleaver for rate matching. One or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to nine sets, called REGs, each with four physical resource elements. Four Quadrature Phase Shift Keying (QPSK) symbols can be mapped to each REG. Depending on the DCI size and channel conditions, one or more CCEs can be used to transmit the PDCCH. Four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation levels, L = 1, 2, 4, or 8) can exist.

[0167] Some implementations may use the concept of resource allocation for control channel information, which is an extension of the above concept. For example, some implementations may utilize EPDCCH, which uses PDSCH resources for control information transmission. One or more ECCEs may be used to transmit EPDCCH. Similarly, each ECCE may correspond to a set of nine, each consisting of four physical resource elements, called EREG. In some cases, an ECCE may have a different number of EREGs.

[0168] RAN node 614 or RAN node 616 may be configured to communicate with each other via interface 630. In embodiments where system 600 is an LTE system (e.g., when CN 606 is an EPC), interface 630 may be an X2 interface. The X2 interface may be defined between two or more RAN nodes connected to the EPC (e.g., two or more eNBs, etc.), and / or between two eNBs connected to the EPC. In some specific implementations, the X2 interface may include an X2 user plane interface (X2-U) and an X2 control plane interface (X2-C). X2-U may provide flow control mechanisms for user packets transmitted via the X2 interface and may be used to transmit information about the delivery of user data between eNBs. For example, X2-U may provide specific sequence number information about user data transmitted from MeNB to SeNB; information about the successful in-order delivery of PDCP PDUs from SeNB to UE 622 for user data; information about PDCP PDUs not delivered to UE 622; information about the current minimum expected buffer size at SeNB for transmitting user data to the UE; and so on. The X2-C provides LTE intra-eNB access mobility functions, including context transmission from the source eNB to the destination eNB, user plane transmission control, load management functions, and inter-cell interference coordination functions.

[0169] In implementations where system 600 is an SG or NR system (e.g., when CN 606 is an SGC), interface 630 may be an Xn interface. The Xn interface is defined between two or more RAN nodes connected to the SGC (e.g., two or more gNBs, etc.), between a RAN node 614 (e.g., a gNB) connected to the SGC and an eNB, and / or between two eNBs connected to the 5GC (e.g., CN 606). In some specific implementations, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. Xn-U provides non-guaranteed delivery of user plane PDUs and supports / provides data forwarding and flow control functions. Xn-C provides management and error handling functions for managing the functionality of the Xn-C interface; mobility support for UE 622 in connected modes (e.g., CM-CONNECTED) includes functions for managing UE mobility in connected modes between one or more RAN nodes 614 or RAN nodes 616. Mobility support may include context transfer from the old (source) serving RAN node 614 to the new (destination) serving RAN node 616; and control of the user plane tunnel between the old (source) serving RAN node 614 and the new (destination) serving RAN node 616. The Xn-U protocol stack may include a transport network layer built on top of the Internet Protocol (IP) transport layer, and a GTP-U layer on top of the UDP and / or IP layers for carrying user plane PDUs. The Xn-C protocol stack may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on top of SCTP. SCTP may be on top of the IP layer and provides guaranteed delivery of application layer messages. In the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In other specific implementations, the Xn-U protocol stack and / or the Xn-C protocol stack may be the same as or similar to the user plane and / or control plane protocol stacks shown and described herein.

[0170] (R)AN 608 is shown as a communication-coupled ground to the core network—in this embodiment, communication-coupled to CN 606. CN 606 may include one or more network elements 632 configured to provide various data and telecommunications services to customers / subscribers (e.g., users of UE 622 and UE 620) connected to CN 606 via (R)AN 608. Components of CN 606 may be implemented in a single physical node or in separate physical nodes, including components for reading and executing instructions from machine-readable or computer-readable media (e.g., non-transitory machine-readable storage media). In some embodiments, NFV may be used to virtualize any or all of the aforementioned network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). A logical instance of CN 606 may be referred to as a network slice, and a logical instance of a portion of CN 606 may be referred to as a network subslice. NFV architectures and infrastructure may be used to virtualize one or more network functions onto physical resources comprising a combination of industry-standard server hardware, storage hardware, or switches (or alternatively, performed by proprietary hardware). In other words, an NFV system can be used to perform a virtual or reconfigurable concrete implementation of one or more EPC components / functions.

[0171] Generally, application server 618 can be a component that provides IP bearer resources for applications to use with the core network (e.g., UMTS PS domain, LTE PS data service, etc.). Application server 618 can also be configured to support one or more communication services for UE 622 and UE 620 via EPC (e.g., VoIP sessions, PTT sessions, group communication sessions, social networking services, etc.). Application server 618 can communicate with CN 606 via IP communication interface 636.

[0172] In this implementation, CN 606 may be an SGC, and (R)AN 116 may be connected to CN 634 via NG interface 606. In this implementation, NG interface 634 may be divided into two parts: an NG user plane (NG-U) interface 626, which carries traffic data between RAN node 614 or RAN node 616 and the UPF; and an S1 control plane (NG-C) interface 628, which is the signaling interface between RAN node 614 or RAN node 616 and the AMF.

[0173] In one implementation, CN 606 may be an SG CN, while in other implementations, CN 606 may be an EPC. When CN 606 is an EPC, (R)AN 116 may be connected to CN 606 via S1 interface 634. In one implementation, S1 interface 634 may be divided into two parts: an S1 user plane (S1-U) interface 626, which carries traffic data between RAN node 614 or RAN node 616 and the S-GW; and an S1-MME interface 628, which is the signaling interface between RAN node 614 or RAN node 616 and the MME.

[0174] Figure 7 Examples of infrastructure equipment 700 according to various implementation schemes are shown. Infrastructure equipment 700 may be implemented as a base station, radio head unit, RAN node, AN, application server, and / or any other element / device discussed herein. In other examples, infrastructure equipment 700 may be in or implemented by a UE.

[0175] Infrastructure equipment 700 includes application circuitry 702, baseband circuitry 704, one or more radio front-end modules 706 (RFEM), memory circuitry 708, a power management integrated circuit (shown as PMIC 710), a power tee circuitry 712, network controller circuitry 714, a network interface connector 720, satellite positioning circuitry 716, and user interface circuitry 718. In some embodiments, infrastructure equipment 700 may include additional components such as memory / storage devices, displays, cameras, sensors, or input / output (I / O) interfaces. In other embodiments, these components may be included in more than one device. For example, the circuitry may be individually included in more than one device for CRAN, vBBU, or other similar specific implementations. Application circuitry 702 includes, but is not limited to, one or more processors (or processor cores), cache memory, and one or more low-dropout regulators (LDOs), an interrupt controller, and serial interfaces such as SPI, I... 2The application circuit 702 may include a C or general-purpose programmable serial interface module, a real-time clock (RTC), a timer-counter including an interval timer and a watchdog timer, general-purpose input / output (I / O or IO), a memory card controller such as a Secure Digital (SD) Multimedia Card (MMC) or similar, a Universal Serial Bus (USB) interface, a Mobile Industry Processor Interface (MIPI) interface, and a Joint Test Access Group (JTAG) test access port. The processor (or core) of the application circuit 702 may be coupled to or may include a memory / storage element and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on the infrastructure apparatus 700. In some specific implementations, the memory / storage element may be on-chip memory circuitry that may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0176] The processor of application circuit 702 may include, for example, one or more processor cores (CPUs), one or more application processors, one or more graphics processing units (GPUs), one or more Reduced Instruction Set Computing (RISC) processors, one or more Acorn RISC machine (ARM) processors, one or more Complex Instruction Set Computing (CISC) processors, one or more digital signal processors (DSPs), one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, or any suitable combination thereof. In some embodiments, application circuit 702 may include or may be a dedicated processor / controller for operation according to the various embodiments herein. As an example, the processor of application circuit 702 may include one or more Intel processors. or Processor; Advanced Micro Devices (AMD) Processor, Accelerated Processing Unit (APU) or Processors; ARM-based processors licensed by ARM Holdings, Ltd., such as the ARM Cortex-A series processors provided by Cavium™, Inc. MIPS-based designs from MIPS Technologies, Inc., such as the MIPS Warrior P-class processor; etc. In some implementations, the infrastructure equipment 700 may not utilize the application circuitry 702 and may instead include a dedicated processor / controller to process, for example, IP data received from the EPC or 5GC.

[0177] In some embodiments, application circuitry 702 may include one or more hardware accelerators, which may be microprocessors, programmable processing devices, etc. These hardware accelerators may include, for example, computer vision (CV) and / or deep learning (DL) accelerators. For example, programmable processing devices may be one or more field-programmable devices (FPDs), such as field-programmable gate arrays (FPGAs); programmable logic devices (PLDs), such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs); ASICs, such as structured ASICs; programmable SoCs (PSoCs); and so on. In such embodiments, the circuitry of application circuitry 702 may include logic blocks or logic architectures, and other interconnect resources that can be programmed to perform various functions such as processes, methods, functions, etc., as discussed in the various embodiments herein. In such embodiments, the circuitry of application circuitry 702 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), fuses, etc.)) for storing logic blocks, logic architectures, data, etc., in lookup tables (LUTs). Baseband circuitry 704 may be implemented, for example, as a soldered substrate comprising one or more integrated circuits, a single-package integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits.

[0178] User interface circuitry 718 may include one or more user interfaces designed to enable a user to interact with infrastructure equipment 700 or peripheral component interfaces, wherein the peripheral component interfaces are designed to enable peripheral components to interact with infrastructure equipment 700. User interfaces may include, but are not limited to, one or more physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., light-emitting diodes (LEDs)), a physical keyboard or keypad, a mouse, a touchpad, a touchscreen, a speaker or other audio transmitting device, a microphone, a printer, a scanner, a headset, a display screen or display device, etc. Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, universal serial bus (USB) ports, audio jacks, power interfaces, etc.

[0179] The radio front-end module 706 may include a millimeter-wave (mmWave) radio front-end module (RFEM) and one or more sub-millimeter-wave radio frequency integrated circuits (RFICs). In some embodiments, the one or more sub-millimeter-wave RFICs may be physically separated from the millimeter-wave RFEM. The RFIC may include connectors to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In another embodiment, the radio functions of both millimeter-wave and sub-millimeter-wave technologies are implemented in the same physical radio front-end module 706 that combines both millimeter-wave and sub-millimeter-wave technologies.

[0180] The memory circuit 708 may include one or more of the following: volatile memory, including dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM); and non-volatile memory (NVM), including high-speed electrically erasable memory (commonly referred to as "flash memory"), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc., and may be combined with... and A three-dimensional (3D) XPOINT memory. The memory circuit 708 can be implemented as one or more of the following: a solder-in packaged integrated circuit, a socket memory module, and an insert memory card.

[0181] The PMIC 710 may include a voltage regulator, surge protector, power alarm detection circuitry, and one or more backup power sources, such as batteries or capacitors. The power alarm detection circuitry can detect one or more of a power outage (undervoltage) and a power surge (overvoltage) condition. The power tee circuit 712 can provide power drawn from the network cable to provide both power and data connectivity to the infrastructure equipment 700 using a single cable.

[0182] Network controller circuitry 714 can provide connectivity to a network using standard network interface protocols such as Ethernet, GRE-tunneled Ethernet, Multiprotocol Label Switching (MPLS)-based Ethernet, or some other suitable protocol. Network connectivity can be provided to / from infrastructure equipment 700 via a physical connection via network interface connector 720; this physical connection can be an electrical connection (typically referred to as a "copper interconnect"), an optical connection, or a wireless connection. Network controller circuitry 714 may include one or more dedicated processors and / or FPGAs for communicating using one or more of the aforementioned protocols. In some implementations, network controller circuitry 714 may include multiple controllers for providing connectivity to other networks using the same or different protocols.

[0183] Positioning circuit 716 includes circuitry for receiving and decoding signals transmitted / broadcast by a positioning network of a Global Navigation Satellite System (GNSS). Examples of navigation satellite constellations (or GNSS) include the U.S. Global Positioning System (GPS), Russia's Global Navigation System (GLONASS), the European Union's Galileo system, China's BeiDou Navigation Satellite System, regional navigation systems, or GNSS augmentation systems (e.g., using the Indian constellation (NAVIC), Japan's Quasi-Zenith Satellite System (QZSS), France's Doppler orbit charts and satellite integrated radio positioning (DORIS), etc.). Positioning circuit 716 includes various hardware components (e.g., hardware devices such as switches, filters, amplifiers, antenna elements, etc.) for facilitating OTA communication to communicate with components of the positioning network, such as navigation satellite constellation nodes. In some embodiments, positioning circuit 716 may include a micro-technology (micro PNT) IC for positioning, navigation, and timing, which performs position tracking / estimation using a master timing clock in the absence of GNSS assistance. The positioning circuit 716 may also be part of or interact with the baseband circuit 704 and / or the radio front-end module 706 to communicate with nodes and components of the positioning network. The positioning circuit 716 may also provide location data and / or time data to the application circuit 702, which can use the data to synchronize operations with various infrastructures, etc. Figure 7 The components shown can communicate with each other using interface circuitry, which may include any number of bus and / or interconnect (IX) technologies, such as Industry Standard Architecture (ISA), Extended ISA (EISA), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Extended (PCix), PCI Express (PCie), or any number of other technologies. The bus / IX may be a proprietary bus, for example, used in a SoC-based system. Other bus / IX systems, such as I... 2 Interfaces include C-type interface, SPI interface, point-to-point interface, and power bus, etc.

[0184] Figure 8 Examples of platform 800 according to various embodiments are shown. In embodiments, computer platform 800 may be adapted to function as a UE, application server, and / or any other element / device discussed herein. Platform 800 may include any combination of the components shown in the examples. Components of platform 800 may be implemented as integrated circuits (ICs), portions of ICs, discrete electronic devices, or other modules, logic, hardware, software, firmware, or combinations thereof adapted in computer platform 800, or may be implemented as components otherwise integrated within the chassis of a larger system. Figure 8 The block diagram is intended to show a high-level view of the components of the computer platform 800. However, some of the components shown may be omitted, additional components may be present, and different arrangements of the components shown may occur in other specific implementations.

[0185] Application circuit 802 includes circuitry such as, but not limited to, one or more processors (or processor cores), cache memory, and LDOs, interrupt controllers, serial interfaces (such as SPI), and I / O pins. 2 The application circuit 802 may include one or more of the following: a C or general-purpose programmable serial interface module, an RTC, timers (including interval timers and watchdog timers), general-purpose I / O, a memory card controller (such as an SD MMC or similar controller), a USB interface, a MIPI interface, and a JTAG test access port. The processor (or core) of the application circuit 802 may be coupled to or may include a memory / storage element, and may be configured to execute instructions stored in the memory / storage element to enable various applications or operating systems to run on platform 800. In some specific implementations, the memory / storage element may be on-chip memory circuitry that may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0186] The processor of application circuit 802 may include, for example, one or more processor cores, one or more application processors, one or more GPUs, one or more RISC processors, one or more ARM processors, one or more CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, multi-threaded processors, ultra-low voltage processors, embedded processors, some other known processing elements, or any suitable combination thereof. In some embodiments, application circuit 802 may include or may be a dedicated processor / controller for operation according to various embodiments herein.

[0187] As an example, the processor of application circuit 802 may include a processor based on... Architecture TM processors, such as Quark TM Atom TM i3, i5, i7 or MCU-level processors, or available from Another processor of this type from the company. The processor for Application Circuit 802 can also be one or more of the following: Advanced Micro Devices (AMD). Processor or Accelerated Processing Unit (APU); from Inc.'s AS-A9 processor, from Snapdragon by Technologies, Inc.TM Processor, Texas Instruments OpenMultimedia Applications Platform(OMAP) TM Processors; MIPS-based designs from MIPS Technologies, Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings, Ltd., such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; etc. In some specific implementations, application circuitry 802 may be part of a system-on-a-chip (SoC), where application circuitry 802 and other components are formed as a single integrated circuit or a single package, such as those from... Edison of the Corporation TM Or Galileo TM SoC board.

[0188] In addition to or alternatively, application circuitry 802 may include circuitry such as, but not limited to, one or more field-programmable devices (FPDs) such as FPGAs; programmable logic devices (PLDs) such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs); ASICs such as structured ASICs; programmable SoCs (PSoCs); and so on. In such embodiments, the circuitry of application circuitry 802 may include logic blocks or logic architectures, and other interconnect resources that can be programmed to perform various functions such as processes, methods, functions, etc., as discussed in the various embodiments herein. In such embodiments, the circuitry of application circuitry 802 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), fuses, etc.)) for storing logic blocks, logic architectures, data, etc., in lookup tables (LUTs), etc.

[0189] The baseband circuit 804 can be implemented, for example, as a soldered substrate, which includes one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits.

[0190] The radio front-end module 806 may include a millimeter-wave (mmWave) radio front-end module (RFEM) and one or more sub-millimeter-wave radio frequency integrated circuits (RFICs). In some embodiments, the one or more sub-millimeter-wave RFICs may be physically separated from the millimeter-wave RFEM. The RFIC may include connectors to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In another embodiment, both millimeter-wave and sub-millimeter-wave radio functions may be implemented in the same physical radio front-end module 806 that combines both millimeter-wave antennas and sub-millimeter-wave components.

[0191] Memory circuitry 808 may include any number and type of memory devices for providing a fixed amount of system memory. For example, memory circuitry 808 may include one or more of the following: volatile memory, including random access memory (RAM), dynamic RAM (DRAM), and / or synchronous dynamic RAM (SD RAM); and non-volatile memory (NVM), including high-speed electrically erasable memory (commonly referred to as flash memory), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc. Memory circuitry 808 may be developed according to the Joint Electronic Equipment Committee (JEDEC) design based on low-power double data rate (LPDDR), such as LPDDR2, LPDDR3, LPDDR4, etc. Memory circuitry 808 may be implemented as one or more of the following: solder-in packaged integrated circuits, single-die package (SDP), dual-die package (DDP), or quad-die package (Q17P), socket memory modules, dual in-line memory modules (DIMMs) (including micro DIMMs or mini DIMMs, and / or soldered to a motherboard via a ball grid array (BGA)). In a low-power implementation, memory circuitry 808 may be an on-chip memory or register associated with application circuitry 802. To provide persistent storage for information such as data, applications, operating systems, etc., memory circuitry 808 may include one or more mass storage devices, which may include, in particular, solid-state drives (SSDDs), hard disk drives (HDDs), micro HDDs, resistance-changing memories, phase-change memories, holographic memories, or chemical memories. For example, computer platform 800 may be integrated with... and 3D XPOINT memory.

[0192] The removable storage circuitry 826 may include devices, circuitry, enclosures / housings, ports, or sockets for coupling portable data storage devices to the platform 800. These portable data storage devices may be used for mass storage and may include, for example, flash memory cards (e.g., Secure Digital (SD) cards, Micro SD cards, xD picture cards, etc.), as well as USB flash drives, optical discs, external HDDs, etc.

[0193] Platform 800 may also include interface circuitry (not shown) for connecting external devices to platform 800. External devices connected to platform 800 via this interface circuitry include sensor 822 and electromechanical components (shown as EMC 824), as well as a removable memory device coupled to removable memory 826.

[0194] Sensor 822 includes devices, modules, or subsystems designed to detect events or changes in their environment and transmit information about the detected events (sensor data) to other devices, modules, subsystems, etc. Examples of such sensors include, in particular: inertial measurement units (IMUs) including accelerometers, gyroscopes, and / or magnetometers; microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) including triaxial accelerometers, triaxial gyroscopes, and / or magnetometers; level sensors; flow sensors; temperature sensors (e.g., thermistors); pressure sensors; barometric pressure sensors; gravimeters; altimeters; image capture devices (e.g., cameras or lensless aperture sensors); light detection and ranging (LiDAR) sensors; proximity sensors (e.g., infrared radiation detectors, etc.), depth sensors, ambient light sensors, ultrasonic transceivers; microphones or other similar audio capture devices; etc.

[0195] EMC 824 includes devices, modules, or subsystems intended to enable platform 800 to change its state, position, and / or orientation, or to move or control mechanisms or (sub)systems. Additionally, EMC 824 can be configured to generate messages / signaling and send messages / signaling to other components of platform 800 to indicate the current state of EMC 824. Examples of EMC 824 include one or more power switches, relays (including electromechanical relays (EMRs) and / or solid-state relays (SSRs)), actuators (e.g., valve actuators, etc.), audible generators, visual warning devices, motors (e.g., DC motors, stepper motors, etc.), wheels, propellers, pawls, clamps, hooks, and / or other similar electromechanical components. In embodiments, platform 800 is configured to operate one or more EMC 824s based on one or more captured events and / or commands or control signals received from a service provider and / or various clients. In some specific implementations, interface circuitry may connect platform 800 to positioning circuitry 816. Positioning circuit 816 includes circuitry for receiving and decoding signals transmitted / broadcast by a GNSS positioning network. Examples of navigation satellite constellations (or GNSS) may include the US GPS, Russia's GLONASS, the EU's Galileo system, China's BeiDou Navigation Satellite System, regional navigation systems, or GNSS augmentation systems (e.g., NAVIC, Japan's QZSS, France's DORIS, etc.). Positioning circuit 816 includes various hardware components (e.g., hardware devices such as switches, filters, amplifiers, antenna elements, etc.) for facilitating OTA communication to communicate with components of the positioning network, such as navigation satellite constellation nodes. In some embodiments, positioning circuit 816 may include a miniature PNT IC that performs position tracking / estimation using a master timing clock without GNSS assistance. Positioning circuit 816 may also be part of or interact with baseband circuitry 804 and / or radio front-end module 806 to communicate with nodes and components of the positioning network. The positioning circuit 816 can also provide location data and / or time data to the application circuit 802, which can use the data to synchronize operations with various infrastructures (e.g., radio base stations) for use in turn-by-turn navigation applications, etc.

[0196] In some implementations, this interface circuitry can connect platform 800 to a near-field communication circuitry (shown as NFC circuitry 812). NFC circuitry 812 is configured to provide contactless short-range communication based on a radio frequency identification (RFID) standard, where a magnetic field sensor is used to enable communication between NFC circuitry 812 and NFC-enabled devices (e.g., “NFC contacts”) external to platform 800. NFC circuitry 812 includes an NFC controller coupled to an antenna element and a processor coupled to the NFC controller. The NFC controller may be a chip / IC that provides NFC functionality to NFC circuitry 812 by executing NFC controller firmware and an NFC stack. The NFC stack may be executed by the processor to control the NFC controller, and the NFC controller firmware may be executed by the NFC controller to control the antenna element to transmit short-range RF signals. The RF signals may power passive NFC tags (e.g., microchips embedded in stickers or wristbands) to transmit stored data to NFC circuitry 812, or initiate data transfer between NFC circuitry 812 and another active NFC device (e.g., a smartphone or an NFC-enabled POS terminal) located near platform 800.

[0197] The drive circuit 818 may include software and hardware elements for controlling specific devices embedded in, attached to, or otherwise communicatively coupled to the platform 800. The drive circuit 818 may include various drivers that allow other components of the platform 800 to interact with or control various input / output (I / O) devices that may exist within or be connected to the platform. For example, the drive circuit 818 may include a display driver for controlling and allowing access to a display device, a touchscreen driver for controlling and allowing access to a touchscreen interface of the platform 800, a sensor driver for obtaining sensor readings of sensor 822 and controlling and allowing access to sensor 822, an EMC driver for obtaining actuator position of EMC 824 and / or controlling and allowing access to EMC 824, a camera driver for controlling and allowing access to an embedded image capture device, and an audio driver for controlling and allowing access to one or more audio devices.

[0198] A power management integrated circuit (shown as PMIC 810) (also referred to as a "power management circuit") manages the power supplied to various components of platform 800. Specifically, relative to baseband circuit 804, PMIC 810 controls power selection, voltage scaling, battery charging, or DC-DC conversion. PMIC 810 is typically included when platform 800 can be powered by battery 814, for example, when the device is included in a UE.

[0199] In some implementations, the PMIC 810 can be controlled or otherwise integrated into various power-saving mechanisms of the platform 800. For example, if the platform 800 is in the RRC_Connected state, where it remains connected to the RAN node as it anticipates receiving traffic soon, it can enter a state known as Discontinuous Receive Mode (DRX) after a period of inactivity. During this state, the platform 800 can power down for short intervals to conserve power. If there is no data traffic activity over an extended period, the platform 800 can transition to the RRC_Idle state, in which it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The platform 800 enters a very low-power state and performs paging, where it periodically wakes up to listen to the network and then power down again. The platform 800 may not receive data in this state; to receive data, the platform must transition back to the RRC_Connected state. Additional power-saving modes can allow the device to be unavailable from the network for longer than the paging interval (ranging from a few seconds to several hours). During this period, the device is completely unable to connect to the network and can be completely powered off. Any data sent during this time will result in significant latency, which is assumed to be acceptable.

[0200] Battery 814 can power platform 800, but in some examples, platform 800 may be mounted in a fixed location and may have a power source coupled to the grid. Battery 814 may be a lithium-ion battery, a metal-air battery such as a zinc-air battery, an aluminum-air battery, a lithium-air battery, etc. In some specific implementations, such as in V2X applications, battery 814 may be a typical lead-acid automotive battery.

[0201] In some implementations, battery 814 may be a "smart battery," which includes or is coupled to a battery management system (BMS) or battery monitoring integrated circuit. The BMS may be included in platform 800 to track the state of charge (SoCh) of battery 814. The BMS can be used to monitor other parameters of battery 814, such as the state of health (SoH) and state of function (SoF) of battery 814, to provide fault prediction. The BMS can transmit information about battery 814 to application circuitry 802 or other components of platform 800. The BMS may also include an analog-to-digital converter (ADC) that allows application circuitry 802 to directly monitor the voltage of battery 814 or the current from battery 814. Battery parameters can be used to determine actions that platform 800 can perform, such as transmission frequency, network operation, sensing frequency, etc.

[0202] A power block coupled to the power grid or other power source can be coupled to the BMS to charge battery 814. In some examples, a wireless power receiver can replace the power block to obtain power wirelessly, for example, via a loop antenna in computer platform 800. In these examples, wireless battery charging circuitry can be included in the BMS. The specific charging circuitry chosen may depend on the size of battery 814 and therefore on the required current. Charging can be performed using aviation fuel standards published by the Aviation Fuel Alliance, the Qi wireless charging standard published by the Radio Power Alliance, or the Rezence charging standard published by the Radio Power Alliance.

[0203] User interface circuitry 820 includes various input / output (I / O) devices present within or connected to platform 800, and includes one or more user interfaces designed to enable user interaction with platform 800 and / or peripheral component interfaces designed to enable interaction with peripheral components of platform 800. User interface circuitry 820 includes input device circuitry and output device circuitry. Input device circuitry includes any physical or virtual device for accepting input, particularly including one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, a keypad, a mouse, a touchpad, a touchscreen, a microphone, a scanner, a headset, etc. Output device circuitry includes any physical or virtual device for displaying information or otherwise conveying information (such as sensor readings, actuator positions, or other similar information). Output device circuitry may include any number and / or combination of audio or visual displays, particularly one or more simple visual outputs / indicators such as binary status indicators (e.g., light-emitting diodes (LEDs) and multi-character visual outputs), or more complex outputs such as display devices or touchscreens (e.g., liquid crystal displays (LCDs), LED displays, quantum dot displays, projectors, etc.), wherein the output of characters, graphics, multimedia objects, etc., is generated or produced by the operation of platform 800. Output device circuitry may also include speakers or other audio transmitting devices, printers, etc. In some embodiments, sensor 822 may be used as input device circuitry (e.g., image capture devices, motion capture devices, etc.) and one or more EMCs may be used as output device circuitry (e.g., actuators for providing haptic feedback, etc.). In another example, NFC circuitry may be included for reading electronic tags and / or connecting to another NFC-enabled device, the NFC circuitry including an NFC controller and processing device coupled to an antenna element. Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power interfaces, etc.

[0204] Although not shown, components of Platform 800 may communicate with each other using suitable bus or interconnect (IX) technologies, which may include any number of technologies, including ISA, EISA, PCI, PCix, PCie, Time Triggered Protocol (TTP) systems, FlexRay systems, or any number of other technologies. The bus / IX may be a proprietary bus / IX, for example, used in a SoC-based system. Other bus / IX systems, such as I... 2 Interfaces include C-type interface, SPI interface, point-to-point interface, and power bus, etc.

[0205] Figure 9 This is a block diagram illustrating a component 900, according to some exemplary embodiments, capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and capable of executing any or more of the methods discussed herein. Specifically, Figure 9 A schematic diagram of hardware resource 902 is shown, which includes one or more processors 906 (or processor cores), one or more memory / storage devices 914, and one or more communication resources 924, each of which is communicatively coupled via bus 916. In an implementation utilizing node virtualization (e.g., NFV), an executable hypervisor 922 provides an execution environment for one or more network slices / subslices to utilize hardware resource 902.

[0206] Processor 906 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) (such as a baseband processor), an application-specific integrated circuit (ASIC), a radio frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processor 908 and processor 910.

[0207] The memory / storage device 914 may include main memory, disk storage, or any suitable combination thereof. The memory / storage device 914 may include, but is not limited to, any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage devices, etc.

[0208] Communication resource 924 may include interconnect or network interface components or other suitable devices for communicating with one or more peripheral devices 904 or one or more databases 920 via network 918. For example, communication resource 924 may include wired communication components (e.g., for coupling via Universal Serial Bus (USB), cellular communication components, NFC components, etc. Components (e.g.) (low power consumption) Components and other communication components.

[0209] Instruction 912 may include software, programs, applications, applets, or other executable code for causing at least one processor in processor 906 to perform any or more of the methods discussed herein. Instruction 912 may reside wholly or partially in processor 906 (e.g., within the processor's cache), memory / storage device 914, or at least one of any suitable combination thereof. Furthermore, any portion of instruction 912 may be transferred from peripheral device 904 or database 920 to hardware resource 902. Therefore, the memory of processor 906, memory / storage device 914, peripheral device 904, and database 920 are examples of computer-readable and machine-readable media.

[0210] For one or more embodiments, at least one of the components shown in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes, and / or methods described in the Embodiments section below. For example, the baseband circuitry described above in conjunction with one or more of the foregoing figures may be configured to operate according to one or more of the examples below. As another example, circuitry associated with the UE, base station, network element, etc., described above in conjunction with one or more of the foregoing figures may be configured to operate according to one or more of the examples shown in the Examples section below.

[0211] Example Section

[0212] The following examples relate to other implementation schemes.

[0213] Example 1 may include a method for determining the timing of Hybrid Automatic Repeat Request Acknowledgment (HARQ-ACK) processing for Physical Downlink Shared Channel (PDSCH). The method may include: determining that a User Equipment (UE) is configured for Single Downlink Control Information (Single DCI) Multiple Transmit and Receive Points (Multiple TRPs) PDSCH operation; determining a first PDSCH and a second PDSCH within a time slot, wherein the first PDSCH and the second PDSCH are used in the Single DCI Multiple TRP PDSCH operation; and determining a minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

[0214] Example 2 may include the method according to Example 1, wherein the single DCI multiple TRP PDSCH operation is a TDMSchemeA operation.

[0215] Example 3 may include the method according to Example 1, wherein the first PDSCH and the second PDSCH have the same duration.

[0216] Example 4 may include the method according to Example 3, wherein the first PDSCH and the second PDSCH have the same frequency resource allocation.

[0217] Example 5 may include the method according to Example 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH uses only the one or more symbols of the first PDSCH.

[0218] Example 6 may include the method according to Example 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH uses one or more symbols of both the first PDSCH and the second PDSCH, and one or more blank symbols located between the first PDSCH and the second PDSCH.

[0219] Example 7 may include the method according to Example 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH uses one or more symbols of both the first PDSCH and the second PDSCH, and does not use any blank symbols located between the first PDSCH and the second PDSCH.

[0220] Example 8 may include the method according to Example 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is to determine the overall HARQ-ACK processing timing, and further includes: determining the initial minimum HARQ-ACK processing timing (k1_1) for the first PDSCH; determining the initial minimum HARQ-ACK processing timing (k1_2) for the second PDSCH; and using the first minimum HARQ-ACK processing timing and the second minimum HARQ-ACK processing timing to determine the overall HARQ-ACK processing timing (K1).

[0221] Example 9 may include the method according to Example 8, wherein the overall HARQ-ACK processing timing (K1) is equal to max(k1_1-Offset,0)+k1_2+C, wherein the Offset value is the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH, and the C value is a constant.

[0222] Example 10 may include the method according to Example 8, wherein the overall HARQ-ACK processing timing (K1) is equal to max(k1_1,k1_2)+C, where the value of C is a constant.

[0223] Example 11 may include the method according to Example 8, wherein the overall HARQ-ACK processing timing (K1) is equal to k1_1+k1_2+C, where the value of C is a constant.

[0224] Example 12 may include a non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to: determine that a user equipment (UE) is configured for single downlink control information (single DCI) multiple transmission and receive (multiple TRP) PDSCH operation; determine a first PDSCH and a second PDSCH within a time slot, wherein the first PDSCH and the second PDSCH are used in the single DCI multiple TRP PDSCH operation; and determine a minimum hybrid automatic repeat request acknowledgment (HARQ-ACK) processing timing for the first PDSCH and the second PDSCH using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

[0225] Example 13 may include the non-transitory computer-readable storage medium according to Example 12, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is to determine the overall HARQ-ACK processing timing, and the instruction, when executed by the processor, also causes the processor to: determine the initial minimum HARQ-ACK processing timing (k1_1) for the first PDSCH; determine the initial minimum HARQ-ACK processing timing (k1_2) for the second PDSCH; and determine the overall HARQ-ACK processing timing (K1) using the first minimum HARQ-ACK processing timing and the second minimum HARQ-ACK processing timing.

[0226] Example 14 may include the non-transitory computer-readable storage medium according to Example 13, wherein the overall HARQ-ACK processing timing (K1) is equal to max(k1_1-Offset,0)+k1_2+C, wherein the Offset value is the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH, and the C value is a constant.

[0227] Example 15 may include the non-transitory computer-readable storage medium according to Example 13, wherein the overall HARQ-ACK processing timing (K1) is equal to max(k1_1,k1_2)+C, where the value of C is a constant.

[0228] Example 16 may include the non-transitory computer-readable storage medium according to Example 13, wherein the overall HARQ-ACK processing timing (K1) is equal to k1_1+k1_2+C, where the value of C is a constant.

[0229] Example 17 may include a computing device for determining the timing of a Physical Downlink Shared Channel (PDSCH) Hybrid Automatic Repeat Request Acknowledgment (HARQ-ACK) processing, the computing device comprising: a processor; and a memory storing instructions that, when executed by the processor, configure the device to: determine that a User Equipment (UE) is configured for Single Downlink Control Information (Single DCI) Multiple Transmission and Receive (Multiple TRP) PDSCH operation; determine a first PDSCH and a second PDSCH within a time slot, wherein the first PDSCH and the second PDSCH are used in the Single DCI Multiple TRP PDSCH operation; and determine a minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

[0230] Example 18 may include the computing device according to Example 17, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is to determine the overall HARQ-ACK processing timing, and wherein the instruction, when executed by the processor, also configures the device to: determine the initial minimum HARQ-ACK processing timing (k1_1) for the first PDSCH; determine the initial minimum HARQ-ACK processing timing (k1_2) for the second PDSCH; and determine the overall HARQ-ACK processing timing (K1) using the first minimum HARQ-ACK processing timing and the second minimum HARQ-ACK processing timing.

[0231] Example 19 may include the computing device according to Example 18, wherein the overall HARQ-ACK processing timing (K1) is equal to max(k1_1-Offset,0)+k1_2+C, wherein the Offset value is the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH, and the C value is a constant.

[0232] Example 20 may include the computing device according to Example 18, wherein the overall HARQ-ACK processing timing (K1) is equal to max(k1_1,k1_2)+C, where the value of C is a constant.

[0233] Example 21 may include the computing device according to Example 18, wherein the overall HARQ-ACK processing timing (K1) is equal to k1_1+k1_2+C, where the value of C is a constant.

[0234] Example 22 may include a method for reporting User Equipment (UE) capabilities, the method comprising: determining a UE configuration for one or both of a Multiple Downlink Control Information (Multiple DCI) Multiple Transmission and Receive (Multiple TRP) operation and a Single DCI Multiple TRP operation; for one or both of the Multiple DCI Multiple TRP operation and the Single DCI Multiple TRP operation, determining a PDSCH processing capability for a timing offset between the Physical Downlink Shared Channel (PDSCH) and HARQ-ACK; for one or both of the Multiple DCI Multiple TRP operation and the Single DCI Multiple TRP operation, determining a PUSCH processing capability for a timing offset between the Physical Downlink Control Channel (PDCCH) and the Physical Uplink Shared Channel (PUSCH); and generating one or more reports indicating support for the determined PDSCH processing capability and the determined PUSCH processing capability.

[0235] Example 23 may include the method according to Example 22, wherein the UE transmits the one or more reports based on a feature set per component carrier.

[0236] Example 24 may include the method according to Example 22, wherein the determined UE configuration is for multiple DCI multiple TRP, and the determined PDSCH processing capability is not PDSCH processing capability 2, wherein the PDSCH processing capability 2 uses low-latency HARQ-ACK feedback.

[0237] Example 25 may include the method according to Example 22, wherein the determined UE configuration is for single DCI multiple TRP, and the determined PDSCH processing capability is not PDSCH processing capability 2, wherein the PDSCH processing capability 2 uses low-latency HARQ-ACK feedback.

[0238] Example 26 may include the method according to Example 22, wherein the determined UE configuration is for multiple DCI multiple TRP, and the determined PUSCH processing capability is not PUSCH processing capability 2, wherein the PUSCH processing capability 2 uses low-latency PUSCH processing.

[0239] Example 27 may include an apparatus comprising one or more elements for performing any of the methods described or associated with any of the above embodiments or any other methods or processes described herein.

[0240] Example 28 may include one or more non-transitory computer-readable media, the one or more non-transitory computer-readable media including instructions that, when executed by one or more processors of an electronic device, cause the electronic device to perform one or more elements of the method or any other method or process described herein as described or associated with any of the above embodiments.

[0241] Example 29 may include an apparatus comprising logic components, modules, or circuitry for performing one or more elements of the methods described or associated with any of the above embodiments or any other methods or processes described herein.

[0242] Example 30 may include any of the methods, techniques, or processes described or related to any of the above examples, or a portion or component thereof.

[0243] Example 31 may include an apparatus comprising: one or more processors and one or more computer-readable media, the one or more computer-readable media including instructions that, when executed by the one or more processors, cause the one or more processors to perform any of the methods, techniques or processes or portions thereof described or associated with any of the above embodiments.

[0244] Example 32 may include any of the signals or parts or components described or associated with any of the above examples.

[0245] Example 33 may include any datagram, packet, frame, segment, protocol data unit (PDU) or message or part or component thereof described or associated with any of the above examples, or otherwise described in this disclosure.

[0246] Example 34 may include a data-encoded signal or part or component thereof described or associated with any of the above examples, or otherwise described in this disclosure.

[0247] Example 35 may include a signal or part or component thereof encoded as a datagram, packet, frame, segment, PDU or message as described or associated with any of the above examples, or otherwise described in this disclosure.

[0248] Example 36 may include an electromagnetic signal carrying computer-readable instructions, wherein execution of the computer-readable instructions by one or more processors will cause the one or more processors to perform any of the methods, techniques or processes or portions thereof described or associated with any of the above embodiments.

[0249] Example 37 may include a computer program comprising instructions, wherein execution of the program by a processing element causes the processing element to perform any of the methods, techniques, or processes or portions thereof described or associated with any of the above embodiments.

[0250] Example 38 may include signals in a wireless network as shown and described herein.

[0251] Example 39 may include methods for communicating in a wireless network as shown and described herein.

[0252] Example 40 may include a system for providing wireless communication as shown and described herein.

[0253] Example 41 may include a device for providing wireless communication as shown and described herein.

[0254] Unless otherwise expressly stated, any of the above embodiments may be combined with any other embodiment (or combination of embodiments). The foregoing description of one or more specific embodiments provides illustration and description, but is not intended to be exhaustive or to limit the scope of the embodiments to the precise forms disclosed. In view of the teachings above, modifications and variations are possible, or modifications and variations may be obtained from the practice of various embodiments.

[0255] Implementations and specific embodiments of the systems and methods described herein may include various operations embodied in machine-executable instructions to be executed by a computer system. The computer system may include one or more general-purpose or special-purpose computers (or other electronic devices). The computer system may include hardware components, including specific logical components for performing the operations, or may include a combination of hardware, software, and / or firmware.

[0256] It should be recognized that the systems described herein include descriptions of specific implementations. These implementations may be combined into a single system, partially integrated into other systems, divided into multiple systems, or otherwise partitioned or combined. Furthermore, it is conceivable to use parameters, attributes, aspects, etc., of one implementation in another implementation. For clarity, these parameters, attributes, aspects, etc., are described only in one or more implementations, and it should be recognized that unless specifically stated herein, these parameters, attributes, aspects, etc., may be combined with or substituted for parameters, attributes, aspects, etc., of another implementation.

[0257] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0258] Although the foregoing has been described in considerable detail for clarity, it will be apparent that certain changes and modifications can be made without departing from the principles of the invention. It should be noted that many alternative ways exist to implement both the processes and apparatus described herein. Therefore, embodiments of the invention should be considered illustrative rather than restrictive, and this specification is not limited to the details given herein, but can be modified within the scope of the appended claims and their equivalents.

Claims

1. A method for determining the timing of HARQ-ACK processing for the Physical Downlink Shared Channel (PDSCH), comprising: It is determined that the user equipment (UE) is configured for single downlink control information multiple transmission and reception point (PDSCH) operation, i.e., single DCI multiple TRP PDSCH operation. Determine the first PDSCH and the second PDSCH within the time slot, wherein the first PDSCH and the second PDSCH are used in the single DCI multiple TRP PDSCH operation; and The minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is determined using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

2. The method according to claim 1, wherein the single DCI multiple TRP PDSCH operation is a TDMSchemeA operation.

3. The method of claim 1, wherein the first PDSCH and the second PDSCH have the same duration.

4. The method according to claim 3, wherein the first PDSCH and the second PDSCH have the same frequency resource allocation.

5. The method of claim 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH uses only the one or more symbols of the first PDSCH.

6. The method of claim 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH uses one or more symbols of both the first PDSCH and the second PDSCH, and one or more blank symbols located between the first PDSCH and the second PDSCH.

7. The method of claim 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH uses one or more symbols of both the first PDSCH and the second PDSCH, and does not use any blank symbols located between the first PDSCH and the second PDSCH.

8. The method of claim 1, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is determining the overall HARQ-ACK processing timing, and further comprises: Determine the first minimum HARQ-ACK processing timing k1_1 for the first PDSCH; Determine the second minimum HARQ-ACK processing timing k1_2 for the second PDSCH; as well as The overall HARQ-ACK processing timing is determined using the first minimum HARQ-ACK processing timing and the second minimum HARQ-ACK processing timing. K 1.

9. The method of claim 8, wherein the overall HARQ-ACK processing timing K 1 equals max(k1_1 - Offset, 0) + k1_2 + C, where the Offset value is the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH, and the C value is a constant.

10. The method of claim 8, wherein the overall HARQ-ACK processing timing K 1 equals max(k1_1,k1_2) + C, where C is a constant.

11. The method of claim 8, wherein the overall HARQ-ACK processing timing K 1 equals k1_1 + k1_2 + C, where C is a constant.

12. A non-transitory computer-readable storage medium, the computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to: It is determined that the user equipment (UE) is configured for single downlink control information multiple transmission and reception point (PDSCH) operation, i.e., single DCI multiple TRP PDSCH operation. Determine the first PDSCH and the second PDSCH within the time slot, wherein the first PDSCH and the second PDSCH are used in the single DCI multiple TRP PDSCH operation; and The minimum hybrid automatic repeat request acknowledgment (HARQ-ACK) processing timing for the first PDSCH and the second PDSCH is determined using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

13. The non-transitory computer-readable storage medium of claim 12, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is to determine the overall HARQ-ACK processing timing, and the instruction, when executed by the processor, also causes the processor to: Determine the first minimum HARQ-ACK processing timing k1_1 for the first PDSCH; Determine the second minimum HARQ-ACK processing timing k1_2 of the second PDSCH; and The overall HARQ-ACK processing timing is determined using the first minimum HARQ-ACK processing timing and the second minimum HARQ-ACK processing timing. K 1.

14. The non-transitory computer-readable storage medium of claim 13, wherein the overall HARQ-ACK processing timing... K 1 equals max(k1_1 - Offset, 0) + k1_2 + C, where the Offset value is the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH, and the C value is a constant.

15. The non-transitory computer-readable storage medium of claim 13, wherein the overall HARQ-ACK processing timing... K 1 equals max(k1_1, k1_2) + C, where C is a constant.

16. The non-transitory computer-readable storage medium of claim 13, wherein the overall HARQ-ACK processing timing... K 1 equals k1_1 + k1_2 + C, where C is a constant.

17. A computing device for determining the timing of HARQ-ACK processing for the Physical Downlink Shared Channel (PDSCH), the computing device comprising: processor; and The memory stores instructions that, when executed by the processor, configure the device to: It is determined that the user equipment (UE) is configured for single downlink control information multiple transmission and reception point (PDSCH) operation, i.e., single DCI multiple TRP PDSCH operation. Determine the first PDSCH and the second PDSCH within the time slot, wherein the first PDSCH and the second PDSCH are used in the single DCI multiple TRP PDSCH operation; and The minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is determined using one or more symbols of the first PDSCH or one or more symbols of both the first PDSCH and the second PDSCH.

18. The computing device of claim 17, wherein the determination of the minimum HARQ-ACK processing timing for the first PDSCH and the second PDSCH is to determine the overall HARQ-ACK processing timing, and wherein the instruction, when executed by the processor, also configures the device to: Determine the first minimum HARQ-ACK processing timing k1_1 for the first PDSCH; Determine the second minimum HARQ-ACK processing timing k1_2 of the second PDSCH; and The overall HARQ-ACK processing timing is determined using the first minimum HARQ-ACK processing timing and the second minimum HARQ-ACK processing timing. K 1.

19. The computing device of claim 18, wherein the overall HARQ-ACK processing timing K 1 equals max(k1_1 - Offset, 0) + k1_2 + C, where the Offset value is the offset between the last symbol of the first PDSCH and the first symbol of the second PDSCH, and the C value is a constant.

20. The computing device of claim 18, wherein the overall HARQ-ACK processing timing K 1 equals max(k1_1, k1_2) + C, where C is a constant.

21. The computing device of claim 18, wherein the overall HARQ-ACK processing timing K 1 equals k1_1 + k1_2 + C, where C is a constant.

22. An apparatus for determining the timing of HARQ-ACK processing for the Physical Downlink Shared Channel (PDSCH), comprising: A means for performing the operations included in the method according to any one of claims 1 to 11.

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