A pulse signal width detection circuit and chip

Abstract

This invention discloses a pulse signal width detection circuit and chip. The pulse signal width detection circuit includes an integer width capture unit, a precision width capture unit, and an arithmetic unit. The input terminal of the pulse signal to be measured and the input terminal of the clock signal are connected to the integer width capture unit and the precision width capture unit, respectively. The output terminals of the integer width capture unit and the precision width capture unit are connected to the arithmetic unit. This pulse signal width detection circuit achieves rapid capture and high-precision width detection of the pulse signal to be measured by using a delayed clock signal to form multiple sampling logic modules and employing logic circuits for edge extraction.

Description

Technical Field

[0001] This invention relates to a pulse signal width detection circuit, and also to an integrated circuit chip including the pulse signal width detection circuit, belonging to the field of integrated circuit technology. Background Technology

[0002] In integrated circuit design, many applications require the acquisition of pulse width when processing digital signals, such as motor pulse decoding circuits, pulse acquisition and display circuits, pulse modulation and demodulation circuits, etc. In some industries such as nuclear technology and radar communication, the requirements for the speed of pulse signal acquisition and the accuracy of pulse width detection are becoming increasingly higher. The speed and accuracy of existing voltage pulse signal acquisition and width detection circuits are difficult to meet the high requirements.

[0003] Chinese patent application No. 202110113827.3 discloses a pulse width detection circuit. This pulse width detection circuit includes an edge-conversion circuit, a capacitor charge adjustment circuit, a hysteresis comparator, and a power supply. The edge-conversion circuit controls the charging and discharging of the capacitor in the capacitor charge adjustment circuit based on the pulse width of the digital signal. The hysteresis comparator processes the triangular wave generated in the capacitor, and finally, the output waveform of the hysteresis comparator is used to determine the pulse width of the digital signal. All functional units of this pulse width detection circuit are analog circuits. Due to the inherent characteristics of analog circuits, the pulse width detection circuit is less affected by process precision, temperature, and power supply voltage, thus improving the accuracy of pulse width detection. Summary of the Invention

[0004] The primary technical problem to be solved by this invention is to provide a pulse signal width detection circuit.

[0005] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the pulse signal width detection circuit.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] According to a first aspect of the present invention, a pulse signal width detection circuit is provided, comprising an integer width capture unit, a precision width capture unit, and a calculation unit; wherein,

[0008] The input terminal of the pulse signal to be measured and the input terminal of the clock signal are respectively connected to the integer width capture unit and the precision width capture unit, and the output terminals of the integer width capture unit and the precision width capture unit are respectively connected to the arithmetic unit;

[0009] The integer width capture unit is used to detect the integer width of the pulse signal under test relative to the period of the clock signal, based on the clock signal.

[0010] The precision width capture unit is used to detect the precision width of the pulse signal under test that is less than the period of the clock signal, based on the delayed clock signal.

[0011] The arithmetic unit is used to calculate the width of the pulse signal to be measured based on the detection results of the integer width capture unit and the precision width capture unit.

[0012] Preferably, the integer width capture unit comprises a first register RS1, a second register RS2, and a first counter Count; wherein the input terminal of the pulse signal to be measured is connected to the input terminal of the first register RS1; the input terminal of the clock signal is connected to the clock input terminals of the first register RS1 and the second register RS2 on one hand, and to the second input terminal of the first counter Count on the other hand; the output terminal of the first register RS1 is connected to the input terminal of the second register RS2, and the output terminal of the second register RS2 is connected to the first input terminal of the first counter Count; the output terminal of the first counter Count is connected to the arithmetic unit.

[0013] Preferably, the precision width capture unit comprises an edge sampling subunit and an edge extraction subunit; wherein the input terminal of the pulse signal to be measured and the input terminal of the delayed clock signal are connected to the edge sampling subunit, the output terminal of the edge sampling subunit is connected to the edge extraction subunit, and the output terminal of the edge extraction subunit is connected to the arithmetic unit;

[0014] The edge sampling subunit uses the delayed clock signal to collect and process the rising and falling edges of the pulse signal under test;

[0015] The edge extraction subunit is used to extract the order of the rising and falling edges of the pulse signal under test in the delayed clock signal.

[0016] Preferably, the edge sampling subunit is composed of multiple sampling logic modules, the number of which is the same as the number of delay clocks, and all sampling logic modules have the same structure; wherein...

[0017] The input terminals of the pulse signals to be measured are respectively connected to the first input terminals of each of the sampling logic modules; the input terminals of the delayed clock signals are respectively connected to the second input terminals of the sampling logic modules; the first output terminals and the second output terminals of each of the sampling logic modules are respectively connected to the edge extraction subunit.

[0018] Preferably, the sampling logic module comprises a tenth register RS ​​10, an eleventh register RS ​​11, a twelfth register RS ​​12, a thirteenth register RS ​​13, a first inverter INV11, a second inverter INV12, a first AND gate AND11, and a second AND gate AND12; wherein,

[0019] The clock signal input is connected to the clock terminals of the tenth register RS10, the eleventh register RS11, the twelfth register RS12, and the thirteenth register RS13, respectively. The input terminal of the pulse signal to be measured is connected to the input terminal of the tenth register RS10. The output terminal of the tenth register RS10 is connected to the input terminal of the eleventh register RS11. The output terminal of the eleventh register RS11 is connected to the input terminal of the twelfth register RS12. The output terminal of the twelfth register RS12 is connected to the input terminal of the thirteenth register RS13, the input terminal of the first inverter INV11, and the first input terminal of the second AND gate AND12, respectively. The output terminal of the thirteenth register RS13 is connected to the second input terminal of the first AND gate AND11 and the input terminal of the second inverter INV12, respectively. The output terminal of the first inverter INV11 is connected to the first input terminal of the first AND gate AND11, and the output terminal of the second inverter INV12 is connected to the second AND gate AND12. The second input terminal of 12 is connected; the output terminal of the first AND gate AND11 is connected to the first output terminal of the sampling logic module, and the output terminal of the second AND gate AND12 is connected to the second output terminal of the sampling logic module.

[0020] Preferably, the edge extraction subunit includes a rising edge extraction module and a falling edge extraction module, both with identical circuit structures; wherein, the rising edge extraction module includes a first-stage judgment submodule, (i-2) intermediate-stage judgment submodules, a final-stage judgment submodule, and a first data selector, where i is the number of delay clocks; wherein,

[0021] The output terminals of the first level judgment submodule, each of the intermediate level judgment submodules and the final level judgment submodule are respectively connected to the control terminal of the first data selector. The i input terminals of the first data selector are respectively set to level 1, level 2, level 3... level i. The output terminal of the first data selector is connected to the output terminal of the rising edge extraction module.

[0022] Preferably, the first stage judgment submodule consists of the fifty-first register RS51, the eleventh AND gate AND51, and (i-1) inverters; wherein...

[0023] The input terminal of the final stage delayed clock signal is connected to the clock terminal of the fifty-first register RS51; the output terminal of the first rising edge signal out_p1 of the edge sampling subunit is connected to the first input terminal of the eleventh AND gate AND51; the output terminals of the second rising edge signal out_p2, the third rising edge signal out_p3, ... the i-th rising edge signal out_pi of the edge sampling subunit are respectively connected to the second input terminal, the third input terminal, ... the i-th input terminal of the eleventh AND gate AND51 through inverters; the output terminal of the eleventh AND gate AND51 is connected to the first control terminal of the first data selector.

[0024] Preferably, the circuit structure of each intermediate stage judgment submodule is the same, and the intermediate stage judgment submodule is composed of the fifty-second register RS52, the fourteenth inverter INV52, and the twelfth AND gate AND52; wherein,

[0025] The input terminal of the final stage delayed clock signal is connected to the clock terminal of the 52nd register RS52; the rising edge signal output terminal corresponding to the previous stage delayed clock signal of the edge sampling subunit is connected to the first input terminal of the 12th AND gate AND52 through the 14th inverter INV52; the rising edge signal output terminal corresponding to the current stage delayed clock of the edge sampling subunit is connected to the second input terminal of the 12th AND gate AND52; the output terminal of the 12th AND gate AND52 is connected to the control terminal of the first data selector.

[0026] Preferably, the final-stage series judgment submodule consists of i registers and a fourteenth AND gate (AND54); wherein...

[0027] The input terminals of the final stage delayed clock signals are respectively connected to the clock terminals of i registers; the i rising edge signal output terminals of the edge sampling subunit are respectively connected to the input terminals of i registers, the output terminals of i registers are respectively connected to the input terminals of the fourteenth AND gate AND54, and the output terminal of the fourteenth AND gate AND54 is connected to the i-th control terminal of the first data selector.

[0028] Preferably, when the clock signals of the integer width capture unit and the edge extraction subunit are the final stage delayed clock signal, the width Ts of the pulse signal under test satisfies the following formula:

[0029] Ts=m*T+[(i-p)+(n-i)]*Δt

[0030] Δt=T / i

[0031] Where T is the period of the delayed clock; Δt is the delay time between two adjacent delayed clock signals; m is the integer width of the pulse signal to be measured, i.e., the count value of the counter in the integer width capture unit; i is the number of delayed clocks; p is the number of stages output by the rising edge extraction module, 0 < p ≤ i; n is the number of stages output by the falling edge extraction module, 0 < n ≤ i.

[0032] Preferably, as the number of delayed clock signals increases, the accuracy of the pulse signal width detection circuit improves accordingly.

[0033] According to a second aspect of the present invention, an integrated circuit chip is provided, including the above-described pulse signal width detection circuit.

[0034] Compared with existing technologies, the pulse signal width detection circuit provided by this invention achieves rapid acquisition and high-precision width detection of the pulse signal under test by using a delayed clock signal to form a set of sampling logic modules and using logic circuits for edge extraction. The pulse signal width detection circuit provided by this invention has the advantages of ingenious and reasonable structural design, low design cost, ease of implementation, and high detection accuracy. Attached Figure Description

[0035] Figure 1 The circuit diagram of the pulse signal width detection circuit provided by the present invention;

[0036] Figure 2 This is a circuit schematic diagram of the integer width capture unit in an embodiment of the present invention;

[0037] Figure 3 This is a timing diagram of the integer width capture unit in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the precision width capture unit in an embodiment of the present invention;

[0039] Figure 5 This is a circuit schematic diagram of the edge sampling subunit in an embodiment of the present invention;

[0040] Figure 6 This is a timing comparison diagram of the edge sampling subunit in an embodiment of the present invention;

[0041] Figure 7 This is a circuit schematic diagram of the rising edge extraction module in an embodiment of the present invention;

[0042] Figure 8 This is a timing diagram of the rising edge extraction module in an embodiment of the present invention;

[0043] Figure 9This is a circuit schematic diagram of the falling edge extraction module in an embodiment of the present invention;

[0044] Figure 10 This is a timing comparison diagram of the falling edge extraction module in an embodiment of the present invention. Detailed Implementation

[0045] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0046] like Figure 1 As shown in the figure, an embodiment of the present invention provides a pulse signal width detection circuit, including an integer width capture unit, a precision width capture unit, and an arithmetic unit. The input terminal of the pulse signal to be measured and the input terminal of the clock signal are respectively connected to the integer width capture unit and the precision width capture unit, and the output terminals of the integer width capture unit and the precision width capture unit are respectively connected to the arithmetic unit. The integer width capture unit is used to detect the integer width of the pulse signal to be measured, i.e., a multiple of the clock signal period, based on the clock signal. The precision width capture unit consists of an edge sampling subunit and an edge extraction subunit, used to detect the precision width of the pulse signal to be measured, i.e., the width portion less than the clock signal period, based on the delayed clock signal. The arithmetic unit is used to calculate the width of the pulse signal to be measured based on the detection results of the integer width capture unit and the precision width capture unit.

[0047] In one embodiment of the present invention, such as Figure 2 As shown, the integer width capture unit consists of a first register RS1, a second register RS2, and a first counter Count. The input terminal of the pulse signal to be measured is connected to the input terminal D of the first register RS1; the input terminal of the clock signal is connected to the clock input terminals of both the first register RS1 and the second register RS2, and also to the second input terminal of the first counter Count; the output terminal Q of the first register RS1 is connected to the input terminal D of the second register RS2, and the output terminal Q of the second register RS2 is connected to the first input terminal of the first counter Count; the output terminal of the first counter Count is connected to the arithmetic unit.

[0048] The timing comparison of the integer width capture unit is as follows: Figure 3As shown, when the clock signal uses the final stage delayed clock signal in a delayed clock signal, taking a four-stage clock signal as an example, the first stage is the original clock, and the final stage clock is delayed clock 3. When the pulse signal under test is high, at the rising edge of the first clock pulse, the first register RS1 outputs a high level; at the rising edge of the second clock pulse, the second register RS2 outputs a high level; at the rising edge of the third clock pulse, the counter starts counting; until the pulse signal under test becomes low, the outputs of the first register RS1 and the second register RS2 successively become low, and the counter stops counting. At this time, the counter value is a multiple of the clock period contained in the width of the pulse signal under test, which is the integer width of the pulse signal under test. Figure 3 The integer width of the pulse signal to be tested shown is 5 clock cycles.

[0049] In one embodiment of the present invention, such as Figure 4 As shown, the precision width acquisition unit consists of an edge sampling subunit and an edge extraction subunit. The input terminals of the pulse signal under test and the delayed clock signal are respectively connected to the corresponding input terminals of the edge sampling subunit, and a set of output terminals of the edge sampling subunit are respectively connected to the corresponding input terminals of the edge extraction subunit; the output terminal of the edge extraction subunit is connected to the arithmetic unit.

[0050] The edge sampling subunit uses a delayed clock signal to acquire and process the rising and falling edges of the pulse signal under test. For example... Figure 5 As shown, the edge sampling subunit consists of multiple sampling logic modules, the number of which is the same as the number of delayed clock signals. The input terminal of the pulse signal to be measured is connected to the first input terminal of each sampling logic module; the input terminal of the delayed clock signal is connected to the second input terminal of each sampling logic module; and the first and second output terminals of each sampling logic module are connected to the input terminals of the edge extraction subunit.

[0051] Figure 5 The edge sampling subunit shown consists of four sampling logic modules, each with the same circuit structure. The circuit structure of the first sampling logic module will be described in detail below as an example.

[0052] The first sampling logic module consists of the tenth register RS ​​10, the eleventh register RS ​​11, the twelfth register RS12, the thirteenth register RS ​​13, as well as the first inverter INV11, the second inverter INV12, the first AND gate AND11, and the second AND gate AND12. The original clock signal input is connected to the clock terminals of registers RS10 (10th), RS11 (11th), RS12 (12th), and RS13 (13th). The input of the pulse signal to be measured is connected to the input of register RS10 (10th). The output of register RS10 is connected to the input of register RS11 (11th). The output of register RS11 is connected to the input of register RS12 (12th). The output of register RS12 is connected to the input of register RS13 (13th), the input of the first inverter INV11, and the first input of the second AND gate AND12. The output of register RS13 is connected to the second input of the first AND gate AND11 and the input of the second inverter INV12. The output of the first inverter INV11 is connected to the first input of the first AND gate AND11, and the output of the second inverter INV12 is connected to the second input of the second AND gate AND12. The output of 11 is connected to the first output of the first sampling logic module, and the output of the second AND gate 12 is connected to the second output of the first sampling logic module.

[0053] In the first sampling logic module, the tenth register RS ​​10 is the sampling register, the eleventh register RS ​​11 and the twelfth register RS ​​12 are synchronization registers, and the thirteenth register RS ​​13, together with the first inverter INV11, the second inverter INV12, the first AND gate AND 11 and the second AND gate AND 12, form the edge-fetching logic.

[0054] Timing comparison of edge sampling subunits as follows Figure 6 As shown, after the pulse signal under test is sampled, synchronized and edge-picked by the first sampling logic module controlled by the original clock signal, a first falling edge signal out_n1 related to the falling edge of the pulse signal under test is output at the first output terminal of the first sampling logic module, and a first rising edge signal out_p1 related to the rising edge of the pulse signal under test is output at the second output terminal.

[0055] After the pulse signal under test is sampled, synchronized and edge-picked by the second sampling logic module controlled by the delay clock 1, a second falling edge signal out_n2 related to the falling edge of the pulse signal under test is output at the first output terminal of the second sampling logic module, and a second rising edge signal out_p2 related to the rising edge of the pulse signal under test is output at the second output terminal.

[0056] Similarly, after the pulse signal under test is sampled, synchronized, and edge-captured by the final-stage sampling logic module controlled by the final-stage delayed clock, a falling edge signal out_ni related to the falling edge of the pulse signal under test is output at the first output terminal of the final-stage sampling logic module, and a rising edge signal out_pi related to the rising edge of the pulse signal under test is output at the second output terminal. Here, i is the delayed clock signal or the number of a set of sampling logic modules. Figure 5 and Figure 6 The number of sampling logic modules shown is 4. Therefore, the output signals of the final sampling logic module are the fourth falling edge signal out_n4 and the fourth rising edge signal out_p4, respectively.

[0057] The edge extraction subunit is used to extract the number of stages in the delayed clock signal where the rising and falling edges of the pulse signal under test are located. It consists of a rising edge extraction module and a falling edge extraction module, both with identical circuit structures. The rising edge extraction module includes a first stage judgment submodule, (i-2) intermediate stage judgment submodules, a final stage judgment submodule, and a first data selector, where i is the number of delayed clock signals. The outputs of the first stage judgment submodule, each intermediate stage judgment submodule, and the final stage judgment submodule are connected to the control terminal of the first data selector. The i inputs of the first data selector are set to stage 1, stage 2, stage 3…stage i, respectively. The output of the first data selector is connected to the output of the rising edge extraction module.

[0058] The circuit structure of each intermediate stage judgment submodule is the same. The input signals used by each intermediate stage judgment submodule are the rising edge signal corresponding to the previous stage delayed clock signal output by the edge sampling subunit and the rising edge signal corresponding to the current stage delayed clock.

[0059] The circuit structure of the rising edge extraction module is as follows: Figure 7 As shown below, taking the edge sampling subunit consisting of 4 sampling logic modules as an example, the circuit structure of the rising edge extraction module will be described in detail.

[0060] The rising edge extraction module comprises registers RS51 (51), RS52 (52), RS53 (53), RS54 (54), RS55 (55), RS56 (56), and RS57 (57), as well as inverters INV511 (11), INV512 (12), INV513 (13), INV52 (14), and INV53 (15), and AND gates AND51 (11), AND52 (12), AND53 (13), AND54 (14), and a first data selector MUX51. Register RS51, inverters INV511 (11), INV512 (12), INV513 (13), and AND gate MUX51 constitute the first-level judgment submodule. Figure 7 (Part 501); Register 52 RS52, Inverter 14 INV52, and AND gate 12 AND52 constitute the second-level decision unit ( Figure 7 (Part 502); Register 53 RS53, Inverter 15 INV53, and AND gate 13 AND53 constitute the third-level decision unit ( Figure 7 (Part 503); Register 54 RS54, Register 55 RS55, Register 56 RS56, Register 57 RS57 and AND gate 14 AND54 constitute the fourth-level decision unit ( Figure 7 (Part 504), in this embodiment, the fourth level is the last level, i.e., the final level.

[0061] In the rising edge extraction module, the input of delayed clock 3 (i.e., the final stage delayed clock signal) is connected to the clock terminals of registers RS51 (51), RS52 (52), RS53 (53), RS54 (54), RS55 (55), RS56 (56), and RS57 (57).

[0062] The first rising edge signal out_p1 output of the edge sampling subunit is connected to the first input of the eleventh AND gate AND51 on one hand, and to the input of the fifty-fourth register RS54 on the other hand. Simultaneously, it is connected to the first input of the twelfth AND gate AND52 through the fourteenth inverter INV52. The second rising edge signal out_p2 output of the edge sampling subunit is connected to the second input of the eleventh AND gate AND51 through the eleventh inverter INV511, and to the first input of the thirteenth AND gate AND53 through the fifteenth inverter INV53. Furthermore, it is connected to the second input of the twelfth AND gate AND52. The input terminal is connected to the input terminal of register RS55 (55); the output terminal of the third rising edge signal out_p3 of the edge sampling subunit is connected to the third input of the eleventh AND gate AND51 through the twelfth inverter INV512, and to the second input terminal of the thirteenth AND gate AND53, and is also connected to the input terminal of register RS56 (56); the output terminal of the fourth rising edge signal out_p4 of the edge sampling subunit is connected to the fourth input of the eleventh AND gate AND51 through the thirteenth inverter INV513, and to the input terminal of register RS57 (57).

[0063] The output of the eleventh AND gate AND51 is connected to the input of the fifty-first register RS51, and the output of the fifty-first register RS51 is connected to the first control terminal of the first data selector MUX51; the output of the twelfth AND gate AND52 is connected to the input of the fifty-second register RS52, and the output of the fifty-second register RS52 is connected to the second control terminal of the first data selector MUX51; the output of the thirteenth AND gate AND53 is connected to the input of the fifty-third register RS53, and the output of the fifty-third register RS53 is connected to the third control terminal of the first data selector MUX51; the outputs of the fifty-fourth register RS54, the fifty-fifth register RS55, the fifty-sixth register RS56, and the fifty-seventh register RS57 are respectively connected to the input of the fourteenth AND gate AND54, and the output of the fourteenth AND gate AND54 is connected to the fourth control terminal of the first data selector MUX51;

[0064] The first input of the first data selector MUX51 is set to level 1, the second input is set to level 2, the third input is set to level 3, and the fourth input is set to level 4. The output of the first data selector MUX51 is connected to the arithmetic unit.

[0065] In the first-stage judgment submodule, when the output signal after passing through the eleventh AND gate AND51 and the fifty-first register RS51 is high, the first data selector MUX51 is controlled to output stage 1. At this time, the first rising edge signal out_p1 is high, and the second rising edge signal out_p2, the third rising edge signal out_p3, and the fourth rising edge signal out_p4 are all low, indicating that the rising edge of the pulse signal under test is located at the rising edge of the first-stage delayed clock (i.e., the original clock).

[0066] In the second-stage judgment unit, when the output signal after the inverted signal of the first rising edge signal out_p1 and the second rising edge signal out_p2 through the twelfth AND gate AND52 and the fifty-second register RS52 is high, the first data selector MUX51 is controlled to output stage 2. At this time, the first rising edge signal out_p1 is low and the second rising edge signal out_p2 is high, indicating that the rising edge of the pulse signal under test is located at the rising edge of the second-stage delayed clock (i.e., delayed clock 1).

[0067] In the third-level judgment unit, when the output signal after the inverted signal of the second rising edge signal out_p2 and the third rising edge signal out_p3 through the thirteenth AND gate AND53 and the fifty-third register RS53 is high, the first data selector MUX51 is controlled to output level 3. At this time, the second rising edge signal out_p2 is low and the third rising edge signal out_p3 is high, indicating that the rising edge of the pulse signal under test is located at the rising edge of the third-level delayed clock (i.e., delayed clock 2).

[0068] In the fourth-stage judgment unit, when the first rising edge signal out_p1 passes through the signal in register 54 RS54, the second rising edge signal out_p2 passes through the signal in register 55 RS55, the third rising edge signal out_p3 passes through the signal in register 56 RS56, and the fourth rising edge signal out_p4 passes through register 57 RS57, and the output signal after passing through the fourteenth AND gate AND54 is high, the first data selector MUX51 is controlled to output stage 4. At this time, it indicates that the rising edge of the pulse signal under test is located at the rising edge of the fourth-stage delayed clock (i.e., delayed clock 3). Since when the rising edge of the pulse signal under test is located at the rising edge of the last stage delayed clock signal, the rising edge of the pulse signal under test will be acquired by all the preceding delayed clock signals. Therefore, the first rising edge signal out_p1, the second rising edge signal out_p2, the third rising edge signal out_p3, and the fourth rising edge signal out_p4 are all high.

[0069] Timing comparison of the rising edge extraction module is as follows: Figure 8 As shown in the figure, the rising edge signal generated by the pulse signal under test generates a high-level signal in the third stage judgment unit. Therefore, the first data selector MUX51 outputs stage 3.

[0070] The circuit structure of the falling edge extraction module is as follows: Figure 9 As shown, its circuit structure is exactly the same as that of the rising edge extraction module. The difference is that the input signal is the first falling edge signal out_n1, the second falling edge signal out_n2, the third falling edge signal out_n3, and the fourth falling edge signal out_n4 output by the edge sampling subunit.

[0071] Timing comparison of the falling edge extraction module is as follows: Figure 10 As shown in the figure, the input signal generated by the pulse signal under test is converted into a high-level signal in the second-stage judgment unit. Therefore, the second data selector MUX61 outputs stage number 2, indicating that the falling edge of the pulse signal under test is located at the rising edge of the second-stage delayed clock (i.e., delayed clock 1). The other aspects of the falling edge extraction module's circuit structure and working principle are the same as those of the rising edge extraction module, so they will not be described again here.

[0072] The arithmetic unit calculates the width of the pulse signal under test based on the detection results of the integer width capture unit and the precision width capture unit. When the clock signals of the integer width capture unit and the edge extraction subunit use the last stage (final stage) delayed clock signal, the width Ts of the pulse signal under test is calculated as follows:

[0073] Ts=m*T+[(i-p)+(n-i)]*Δt (1)

[0074] Δt=T / i (2)

[0075] Where T is the period of the delayed clock signal; Δt is the delay time between two adjacent delayed clock signals; m is the integer width of the pulse signal to be measured, i.e., the count value of the counter in the integer width capture unit; i is the number of delayed clock signals; p is the number of stages output by the rising edge extraction module, 0 < p ≤ i; n is the number of stages output by the falling edge extraction module, 0 < n ≤ i.

[0076] According to Formulas 1 and 2, the width Ts of the pulse signal to be measured in the embodiment is calculated as follows:

[0077] Ts=5T+[(4-3)+(2-4)]*(T / 4)=4.75T

[0078] The technical solution of the present invention has been described in detail above through specific embodiments. It should be noted that in the embodiments, both the integer width capture unit and the edge extraction subunit use the last stage delayed clock signal, and the detection result is used to calculate the width of the pulse signal to be measured using formulas 1 and 2. In other embodiments of the present invention, when the integer width capture unit and the edge extraction subunit use other stages of delayed clock signals, since the delay time between two adjacent delayed clock signals is the average of their periods, i.e., Δt = T / i as shown in formula 2, this stage of delayed clock signal can be used as the last stage (final stage). The delayed clock signals following this stage can be used as the original clock signal, the first stage delayed clock signal, the second stage delayed clock signal, etc., in sequence. After adjustment, the detection result still satisfies the width calculation of formulas 1 and 2.

[0079] On the other hand, in the pulse signal width detection circuit provided by the present invention, when the number of delayed clock signals increases, that is, when the number of sampling logic modules in the edge sampling subunit increases, the accuracy of the pulse signal width detection circuit is improved accordingly.

[0080] This invention also provides an integrated circuit chip, which includes the aforementioned pulse signal width detection circuit for detecting the width of pulse signals for an application system within the integrated circuit. The specific structure of the pulse signal width detection circuit in this integrated circuit chip will not be described in detail here.

[0081] In summary, compared with existing technologies, the pulse signal width detection circuit provided by this invention achieves rapid acquisition and high-precision width detection of the pulse signal under test by using a delayed clock signal to form a set of sampling logic modules and employing logic circuits for edge extraction. The pulse signal width detection circuit provided by this invention has the advantages of ingenious and reasonable structural design, low design cost, ease of implementation, and high detection accuracy.

[0082] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0083] The pulse signal width detection circuit and chip provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A pulse signal width detection circuit, characterized by It includes an integer width capture unit, a precision width capture unit, and an arithmetic unit; among which, The input terminal of the pulse signal to be measured and the input terminal of the clock signal are respectively connected to the integer width capture unit and the precision width capture unit, and the output terminals of the integer width capture unit and the precision width capture unit are respectively connected to the arithmetic unit; The integer width capture unit is used to detect the integer width of the pulse signal under test relative to the clock signal period based on the clock signal; The precision width capture unit includes an edge sampling subunit and an edge extraction subunit. The edge sampling subunit is composed of multiple identical sampling logic modules, the number of which is the same as the number of delayed clock signals. Each sampling logic module consists of a tenth register (RS10), an eleventh register (RS11), a twelfth register (RS12), a thirteenth register (RS13), a first inverter (INV11), a second inverter (INV12), a first AND gate (AND11), and a second AND gate (AND12). The input terminals of the clock signals are connected to the clock terminals of the tenth register (RS10), eleventh register (RS11), twelfth register (RS12), and thirteenth register (RS13), respectively. The input terminal of the pulse signal to be measured is connected to the input terminal of the tenth register (RS10), and the output terminal of the tenth register (RS10) is connected to the eleventh register (RS13). The input of (RS11) is connected, the output of the eleventh register (RS11) is connected to the input of the twelfth register (RS12), the output of the twelfth register (RS12) is connected to the input of the thirteenth register (RS13), the input of the first inverter (INV11), and the first input of the second AND gate (AND12), respectively. The output of the thirteenth register (RS13) is connected to the second input of the first AND gate (AND11) and the input of the second inverter (INV12), respectively. The output of the first inverter (INV11) is connected to the first input of the first AND gate (AND11), and the output of the second inverter (INV12) is connected to the second input of the second AND gate (AND12); the output of the first AND gate (AND11) is connected to the first output of the sampling logic module, and the output of the second AND gate (AND12) is connected to the second output of the sampling logic module. The input terminals of the pulse signal under test are respectively connected to the first input terminals of each of the sampling logic modules; the input terminals of the delayed clock signals are respectively connected to the second input terminals of the sampling logic modules; each of the sampling logic modules is used to sample the pulse signal under test under the control of its corresponding delayed clock signal, and output a first output signal and a second output signal; wherein, the first output signal is a signal output by the sampling logic module related to the falling edge of the pulse signal under test, and the second output signal is a signal output by the sampling logic module related to the rising edge of the pulse signal under test; The edge extraction subunit is connected to the output terminal of the edge sampling subunit and is used to receive the first output signal and the second output signal output by each sampling logic module. The edge extraction subunit includes a level judgment circuit and a data selector. The level judgment circuit is used to determine the level of the edge of the pulse signal under test in the delayed clock signal sequence according to the first output signal or the second output signal, and output the level through the data selector. The arithmetic unit is used to calculate the width of the pulse signal to be measured based on the detection results of the integer width capture unit and the precision width capture unit.

2. The pulse signal width detection circuit as described in claim 1, characterized in that: The integer width capture unit consists of a first register (RS1), a second register (RS2), and a first counter (Count). The input terminal of the pulse signal to be measured is connected to the input terminal of the first register (RS1). The input terminal of the clock signal is connected to the clock input terminals of the first register (RS1) and the second register (RS2) on one hand, and to the second input terminal of the first counter (Count) on the other hand. The output terminal of the first register (RS1) is connected to the input terminal of the second register (RS2), and the output terminal of the second register (RS2) is connected to the first input terminal of the first counter (Count). The output terminal of the first counter (Count) is connected to the arithmetic unit.

3. The pulse signal width detection circuit as described in claim 1, characterized in that: The edge sampling subunit uses the delayed clock signal to collect and process the rising and falling edges of the pulse signal under test; The edge extraction subunit is used to extract the order of the rising and falling edges of the pulse signal under test in the delayed clock signal.

4. The pulse signal width detection circuit as described in claim 1, characterized in that: The edge extraction subunit includes a rising edge extraction module and a falling edge extraction module, both with identical circuit structures. The rising edge extraction module includes a first stage judgment submodule, (i-2) intermediate stage judgment submodules, a final stage judgment submodule, and a first data selector, where i is the number of delay clocks. The outputs of the first stage judgment submodule, each of the intermediate stage judgment submodules, and the final stage judgment submodule are connected to the control terminal of the first data selector. The i inputs of the first data selector are set to stage 1, stage 2, stage 3, ..., stage i, respectively. The output of the first data selector is connected to the output of the rising edge extraction module.

5. The pulse signal width detection circuit as described in claim 4, characterized in that: The first stage judgment submodule consists of a fifty-first register (RS51), an eleventh AND gate (AND51), and (i-1) inverters; wherein, the input terminal of the final stage delayed clock signal is connected to the clock terminal of the fifty-first register (RS51); the first rising edge signal (out_p1) output terminal of the edge sampling subunit is connected to the first input terminal of the eleventh AND gate (AND51); the second rising edge signal (out_p2), the third rising edge signal (out_p3), ... the i-th rising edge signal (out_pi) output terminal of the edge sampling subunit are respectively connected to the second input terminal, the third input terminal, ... the i-th input terminal of the eleventh AND gate (AND51) through inverters; the output terminal of the eleventh AND gate (AND51) is connected to the first control terminal of the first data selector.

6. The pulse signal width detection circuit as described in claim 4, characterized in that: Each intermediate stage judgment submodule has the same circuit structure. The intermediate stage judgment submodule consists of a 52nd register (RS52), a 14th inverter (INV52), and a 12th AND gate (AND52). The input terminal of the final stage delayed clock signal is connected to the clock terminal of the 52nd register (RS52). The rising edge signal output terminal corresponding to the previous stage delayed clock signal of the edge sampling subunit is connected to the first input terminal of the 12th AND gate (AND52) through the 14th inverter (INV52). The rising edge signal output terminal corresponding to the current stage delayed clock of the edge sampling subunit is connected to the second input terminal of the 12th AND gate (AND52). The output terminal of the 12th AND gate (AND52) is connected to the control terminal of the first data selector.

7. The pulse signal width detection circuit as described in claim 4, characterized in that: The final stage series judgment submodule consists of i registers and a fourteenth AND gate (AND54); wherein, the input terminal of the final stage delayed clock signal is connected to the clock terminal of i registers respectively; the i rising edge signal output terminals of the edge sampling subunit are respectively connected to the input terminals of i registers respectively, the output terminals of i registers are respectively connected to the input terminals of the fourteenth AND gate (AND54) respectively, and the output terminal of the fourteenth AND gate (AND54) is connected to the i-th control terminal of the first data selector.

8. The pulse signal width detection circuit according to any one of claims 1 to 7, characterized in that: When the clock signals of the integer width capture unit and the edge extraction subunit are final stage delayed clock signals, the width Ts of the pulse signal under test satisfies the following formula: Δt=T / i Where T is the period of the delayed clock; Δt is the delay time between two adjacent delayed clock signals; m is the integer width of the pulse signal to be measured, i.e., the count value of the counter in the integer width capture unit; i is the number of delayed clocks; p is the number of stages output by the rising edge extraction module, 0 < p ≤ i; n is the number of stages output by the falling edge extraction module, 0 < n ≤ i.

9. The pulse signal width detection circuit according to any one of claims 1 to 7, characterized in that: As the number of delayed clock signals increases, the accuracy of the pulse signal width detection circuit improves accordingly.

10. An integrated circuit chip, characterized by Includes the pulse signal width detection circuit according to any one of claims 1 to 7.

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