Test method and system

Abstract

The present disclosure relates to test methods and systems. A test method for testing a chip on a circuit under test, wherein the circuit under test further comprises a direct current (DC) power converter. The test method comprises: generating a test pulse signal; filtering the test pulse signal to generate a first test DC voltage to the DC power converter, wherein the DC power converter converts the first test DC voltage to a second test DC voltage and transmits the second test DC voltage to the chip; and capturing an output signal of the chip to determine a performance of the chip, wherein the chip generates the output signal according to the second test DC voltage.

Description

Technical Field

[0001] This invention relates to a testing method and a testing system, and more particularly to a testing method and a testing system for testing chips on a circuit. Background Technology

[0002] When chips in integrated circuits need to be tested to verify their performance, the chip's supply voltage is adjusted within the rated operating voltage range to check if the chip operates correctly. Regardless of the voltage value selected within the rated operating voltage range for testing, operators need to manually adjust the chip's supply voltage, which consumes a significant amount of manpower and time. Therefore, how to increase the efficiency of chip testing in integrated circuits has become an important issue in this field. Summary of the Invention

[0003] This invention discloses a testing method for testing a chip on a circuit under test (DUT), wherein the DUT further includes a DC-DC converter. The testing method includes: generating a test pulse signal; filtering the test pulse signal to generate a first test DC voltage for the DC-DC converter, wherein the DC-DC converter converts the first test DC voltage into a second test DC voltage and transmits it to the chip; and capturing the chip's output signal to determine the chip's performance, wherein the chip generates the output signal based on the second test DC voltage.

[0004] This invention discloses a testing system for testing chips on a circuit under test (DUT), wherein the DUT further includes a DC-DC converter. The testing system includes a processor, a filtering circuit, and a control interface. The processor generates test pulse signals. The filtering circuit filters the test pulse signals to generate a first test DC voltage for the DC-DC converter, wherein the DC-DC converter generates a second test DC voltage for the chip based on the first test DC voltage. The control interface captures the chip's output signals to determine the chip's performance, wherein the chip generates an output signal based on the second test DC voltage.

[0005] Compared to conventional techniques, the testing method and system of this invention generate a DC voltage with accurate voltage levels through a processor and a filtering circuit, and then provide the DC voltage to the chip. This not only increases the accuracy of the test but also improves the efficiency of the test. Attached Figure Description

[0006] The various aspects of the invention can be best understood by reading the following embodiments and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0007] Figure 1This is a schematic diagram of the testing system in some embodiments of the present invention.

[0008] Figure 2 This is a schematic diagram illustrating the correspondence in some embodiments of the present invention.

[0009] Figure 3 This is a schematic diagram of a filter circuit in some embodiments of the present invention.

[0010] Figure 4 The following is a flowchart of a testing method in some embodiments of the present invention. Detailed Implementation

[0011] Figure 1 This is a schematic diagram of a test system 10 according to some embodiments of the present invention. The test system 10 is used to test the performance of a chip SOC on a circuit under test (DUT). The test system 10 is used to provide different DC voltages to the DUT and capture the output signal VO of the DUT to determine the performance of the chip SOC.

[0012] Test system 10 generates DC voltages V1, V2, and V3 to the circuit under test (DUT). The DUT converts DC voltages V1-V3 into DC voltages V4, V5, and V6 via DC power converters DD1, DD2, and DD3, respectively. The SOC chip operates based on DC voltages V4-V6 to generate output signal VO. For simplicity, the DC voltages will be referred to simply as voltages in this document.

[0013] A System-on-a-Chip (SoC) contains different power domains, each requiring a different voltage. DC-DC converters DD1 through DD3 supply power to these different power domains within the SoC. In some embodiments, the core voltage, central processing unit (CPU), and memory on the SoC belong to different power domains. DC-DC converter DD1 is the core voltage converter, DD2 is the CPU converter, and DD3 is the dual-channel dynamic random access memory converter.

[0014] The test system 10 includes a processor PSR, filter circuits RC1, RC2, and RC3, a control interface UI, and a power transistor M.

[0015] The processor PSR generates control signals SC to power transistor M, and generates pulse signals P1, P2 and P3 respectively and transmits them to filter circuits RC1, RC2 and RC3.

[0016] The power transistor M provides a reference voltage VDD to the circuit under test (DUT) according to the control signal SC. Specifically, the power transistor M is used to provide the reference voltage VDD to the DC-DC power converters DD1 to DD3 for their operation.

[0017] Filter circuit RC1 filters pulse signal P1 to generate voltage V1, which is then transmitted to DC power converter DD1. The duty cycle of pulse signal P1 is related to the voltage level of voltage V1 generated by filter circuit RC1. In some embodiments, a lower duty cycle of pulse signal P1 results in a higher voltage level of voltage V1. Voltage V1 and voltage V4 can be the same or different. The operation of filter circuits RC2 and RC3, DC power converters DD2 and DD3 is similar to that of filter circuit RC1 and DC power converter DD1, and will not be described further.

[0018] Taking the DC-DC power converter DD1 as an example, generally speaking, there is a roughly fixed ratio between voltage V1 and voltage V4. However, due to some process factors or other external conditions, the ratio between voltage V1 and voltage V4 deviates from its original fixed value. When this deviation occurs, the voltage V4 received by the chip SOC deviates from the predetermined voltage level. Different voltage levels may result in different performance of the chip SOC, thus making the test results inaccurate.

[0019] To avoid the aforementioned offset, the processor PSR generates pulse signals P1 and P11 at different times and sends them to the filter circuit RC1. The filter circuit RC1 filters pulse signals P1 and P11 into voltages V1 and V11, respectively. Then, the DC-DC power converter DD1 converts voltages V1 and V11 into voltages V4 and V41, respectively. Pulse signals P1 and P11 have different duty cycles. The processor PSR also captures voltages V4 and V41 and establishes a correspondence FC based on pulse signals P1 and P11, and voltages V4 and V41. Please also refer to... Figure 2 The correspondence FC represents a function between the duty cycle of the pulse signal generated by the processor PSR and the voltage level of the voltage obtained by the pulse signal after passing through the DC-DC power converter DD1. According to this correspondence FC, the processor PSR can control the duty cycle of the pulse signal P1 to obtain a voltage V4 with the expected voltage level.

[0020] In some embodiments, the processor PSR performs interpolation using the difference between the duty cycles of pulse signal P1 and pulse signal P11, and the difference between voltage V4 and voltage V41, and obtains the corresponding relationship FC based on the interpolation result. However, the present invention is not limited to interpolation calculation, and various fitting methods are within the scope of the present invention.

[0021] In some embodiments, the duty cycle of pulse signal P1 is 10%, and the duty cycle of pulse signal P11 is 20%.

[0022] Once the processor PSR obtains the corresponding FC, the voltage received by the chip SOC can be accurately controlled. In some embodiments, the operation of obtaining the corresponding FC is a calibration phase, and the test system 10 can enter the testing phase after obtaining the corresponding FC.

[0023] During the testing phase, the processor PSR generates a test pulse signal PT1 according to the corresponding relationship FC and sends it to the filter circuit RC1. The filter circuit RC1 filters the test pulse signal PT1 to generate a test voltage VT1, which is then sent to the DC-DC converter DD1. The DC-DC converter DD1 then converts the test voltage VT1 into a test voltage VT4. The chip SOC receives the test voltage VT4 and operates according to the test voltage VT4 to generate an output signal VO. In some embodiments, the test voltage VT4 is equal to the upper voltage operating limit Vth1 of the chip SOC (e.g., ...). Figure 2 The upper operating voltage limit Vth1 is shown. In other embodiments, the test voltage VT4 is equal to the lower operating voltage limit Vth2 of the chip SOC (e.g., ...). Figure 2 The lower limit of voltage operation (Vth2) is shown.

[0024] The operation of filter circuits RC2 and RC3, DC voltage converters DD2 and DD3 during the testing phase is similar to that of filter circuits RC1 and DC voltage converters DD1, and will not be described again.

[0025] In some embodiments, the chip SOC needs to be reset when it receives a voltage change. In some embodiments, the processor PSR is used to generate a reset signal SR to the chip SOC to reset the control chip SOC. In other embodiments, the test system 10 resets the chip SOC through a control interface UI.

[0026] In some embodiments, the control interface (UI) includes a computer (PC) with a USB interface. The PC is connected to the processor PSR via a USB / RS232 adapter CTR1. In some embodiments, the test pulse signal PT1 generated by the processor PSR can be controlled by the PC via the USB / RS232 adapter CTR1. The PC is further connected to the chip SOC via a USB / RS232 adapter CTR2. In some embodiments, the reset signal SR is directly generated by the PC and transmitted to the chip SOC via the USB / RS232 adapter CTR2.

[0027] In some embodiments, the SOC chip is a display system chip, and the output signal SO generated by the SOC chip is an HDMI format signal. A computer PC is connected to the SOC chip via a USB / RS232 adapter CTR3 and an RS232 / HDMI adapter CTR4, and is used to receive the HDMI format output signal SO, thereby determining the performance of the SOC chip during the testing phase.

[0028] Please refer to Figure 3 A schematic diagram of an embodiment of the filter circuit RC1 is shown. The filter circuit RC1 includes resistors R1, R2, R3, and R4, and capacitor C. The first terminal of resistor R1 is coupled to... Figure 1 The processor PSR in the system is used to receive pulse signals P1, P11, and test pulse signal PT1. The second terminal of resistor R1 is coupled to the first terminals of resistors R2 and R3. The second terminal of resistor R2 is grounded. The second terminal of resistor R3 is coupled to the first terminal of resistor R4 and capacitor C. The second terminal of capacitor C is grounded. The second terminal of resistor R4 is coupled to... Figure 1 The DC-DC voltage converter DD1 in the middle is used to output voltages V1, V11 and VT1.

[0029] In some embodiments, the resistance values ​​of resistors R2, R3, and R4 are 100K, 15.8K, and 100K ohms, respectively, and the capacitance value of capacitor C is 22n Farads. In some embodiments, resistor R1 can be short-circuited, that is, the resistance value of resistor R1 is 0.

[0030] In some embodiments, DC-DC converters DD2 and DD3 have a similar structure to DC-DC converter DD1, except that the resistance and / or capacitance values ​​are different. For example, DC-DC converter DD3 (applied to DDR) also includes resistors R1, R2, R3, R4 and capacitor C, and the resistance values ​​of resistors R1, R2, R3 and R4 are 0, 100K, 15.8K and 1000K respectively, and the capacitance value of capacitor C is 22nFaradays.

[0031] Please refer to Figure 4 The flowchart for test method 40. Test method 40 is used to test, for example... Figure 1 The circuit under test (DUT) is used in the test system. In some embodiments, the test system 10 is used to perform test method 40 to test the DUT. Test method 40 includes steps S41, S42, S43, S44, S45, S46, and S47. For ease of understanding, test method 40 follows... Figures 1-3 The reference numerals are used for explanation.

[0032] In step S41, pulse signals P1 and P11 (i.e., the first pulse signal and the second pulse signal) are generated, wherein pulse signals P1 and P11 have different duty cycles (i.e., the first duty cycle and the second duty cycle). In step S42, pulse signals P1 and P11 are filtered respectively to generate voltages V1 and V11 (i.e., the first DC voltage and the second DC voltage) to DC power converter DD1. In step S43, voltages V4 and V41 (i.e., the third DC voltage and the fourth DC voltage) are extracted, wherein DC power converter DD1 generates voltages V4 and V41 based on voltages V1 and V11 respectively. In step S44, the correspondence FC is obtained based on the duty cycles of pulse signals P1 and P11, and voltages V4 and V41. In step S45, a test pulse signal PT1 is generated. In step S46, the test pulse signal PT1 is filtered to generate a test voltage VT1 (i.e., the first test DC voltage) to the DC-DC power converter DD1, wherein the DC-DC power converter DD1 converts the test voltage VT1 into a test voltage VT4 (i.e., the second test DC voltage) to the chip SOC. In step S47, the output signal SO of the chip SOC is captured to determine the performance of the chip SOC, wherein the chip SOC generates the output signal SO based on the test voltage VT4.

[0033] Test method 40 is not limited to Figure 4 As shown. In other embodiments, test method 40 further includes, as shown in Figures 1-3 At least one of the operations included in the embodiments.

[0034] In this invention, any chip capable of outputting an adjustable duty cycle pulse signal can be used as the PSR (Processor Signal Relay). Testers can change the duty cycle of the pulse signal output by the PSR through any feasible control interface (UI) to alter the DC voltage output to the chip's SOC (System-on-a-Chip). This operation improves testing efficiency. Furthermore, by appropriately programming the control interface (UI), the generation of DC voltages of varying magnitudes can be automated.

[0035] The foregoing description briefly outlines the features of certain embodiments of the present invention, enabling those skilled in the art to more fully understand the various forms of the invention. Those skilled in the art will readily recognize that the present invention can serve as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of the present invention, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

[0036] [Symbol Explanation]

[0037] 10: Testing System

[0038] 40: Testing Methods

[0039] C: Capacitor

[0040] CTR1: Adapter

[0041] CTR2: Adapter

[0042] CTR3: Adapter

[0043] CTR4: Adapter

[0044] DD1: DC power converter

[0045] DD2: DC power converter

[0046] DD3: DC power converter

[0047] DUT: Circuit Under Test

[0048] FC: Correspondence

[0049] M: Power transistor

[0050] P1: Pulse signal

[0051] P2: Pulse signal

[0052] P3: Pulse signal

[0053] P11: Pulse signal

[0054] PC: Computer

[0055] PSR: Processor

[0056] PT1: Test Pulse Signal

[0057] R1: Resistor

[0058] R2: Resistor

[0059] R3: Resistor

[0060] R4: Resistor

[0061] RC1: Filter circuit

[0062] RC2: Filter circuit

[0063] RC3: Filter circuit

[0064] S41: Steps

[0065] S42: Steps

[0066] S43: Steps

[0067] S44: Steps

[0068] S45: Steps

[0069] S46: Steps

[0070] S47: Steps

[0071] SC: Control Signal

[0072] SO: Output signal

[0073] SOC: Chip

[0074] SR: Reset Signal

[0075] UI: Control Interface

[0076] V1: Voltage

[0077] V2: Voltage

[0078] V3: Voltage

[0079] V4: Voltage

[0080] V5: Voltage

[0081] V6: Voltage

[0082] V11: Voltage

[0083] VDD: Reference voltage

[0084] VT1: Test voltage

[0085] VT4: Test voltage

[0086] Vth1: Upper limit of voltage operation

[0087] Vth2: Lower limit of voltage operation

Claims

1. A test method for testing a chip on a circuit under test (DUT) using a test system, wherein the DUT further includes a DC power converter, the test method comprising: In the calibration phase of this test method, a correspondence is obtained for the DC power converter; In a test phase following the calibration phase, a test pulse signal is generated by a processor of the test system, wherein the test pulse signal is generated according to the correspondence. The test pulse signal is filtered to generate a first test DC voltage to the DC-DC converter, wherein the DC-DC converter receives the first test DC voltage, converts the first test DC voltage into a second test DC voltage, and transmits the second test DC voltage to the chip; and An output signal of the chip is captured to determine the chip's performance, wherein the chip generates the output signal based on the second test DC voltage.

2. The test method according to claim 1, further comprising: A first pulse signal and a second pulse signal are generated, wherein the first pulse signal and the second pulse signal have a first duty cycle and a second duty cycle, respectively; The first pulse signal and the second pulse signal are filtered respectively to generate a first DC voltage and a second DC voltage to the DC power converter; The DC-DC converter acquires a third DC voltage and a fourth DC voltage, wherein the DC-DC power converter generates the third DC voltage and the fourth DC voltage based on the first DC voltage and the second DC voltage, respectively; and The correspondence is obtained based on the first duty cycle, the second duty cycle, the third DC voltage, and the fourth DC voltage.

3. The test method according to claim 2, wherein the correspondence is a function of the first duty cycle and the third DC voltage.

4. The test method according to claim 2, wherein the step of obtaining the correspondence based on the first duty cycle, the second duty cycle, the third DC voltage, and the fourth DC voltage includes: Interpolate the difference between the first duty cycle and the second duty cycle, and the difference between the third DC voltage and the fourth DC voltage; and The correspondence is obtained based on the result of the interpolation.

5. A test system for testing a chip on a circuit under test, wherein the circuit under test further includes a DC power converter, the test system comprising: A processor is configured to obtain a correspondence between the DC power converter during a calibration phase and, during a test phase following the calibration phase, generate a test pulse signal based on the correspondence. A filtering circuit is used to filter the test pulse signal to generate a first test DC voltage to the DC power converter, wherein the DC power converter receives the first test DC voltage, generates a second test DC voltage based on the first test DC voltage, and transmits the second test DC voltage to the chip; and A control interface is provided for acquiring an output signal of the chip to determine the chip's performance, wherein the chip generates the output signal based on the second test DC voltage.

6. The testing system according to claim 5, wherein The processor is further used to generate a first pulse signal and a second pulse signal, wherein the first pulse signal and the second pulse signal have a first duty cycle and a second duty cycle, respectively. The filtering circuit is further used to filter the first pulse signal and the second pulse signal respectively to generate a first DC voltage and a second DC voltage to the DC power converter, and The processor is further used to acquire a third DC voltage and a fourth DC voltage, and to obtain the correspondence based on the first duty cycle, the second duty cycle, the third DC voltage and the fourth DC voltage, wherein the DC power converter generates the third DC voltage and the fourth DC voltage based on the first DC voltage and the second DC voltage respectively.

7. The testing system according to claim 5, further comprising: A power transistor is used to provide a reference voltage to the circuit under test.

8. The test system according to claim 5, wherein the filter circuit comprises: First resistor; A second resistor; A third resistor, wherein a first terminal of the first resistor is grounded, a second terminal of the first resistor is coupled to a first terminal of the second resistor, and a second terminal of the second resistor is coupled to a first terminal of the third resistor, wherein the second terminal of the first resistor and the first terminal of the second resistor are used to receive the test pulse signal; and A capacitor, wherein a first terminal of the capacitor is coupled to a second terminal of a second resistor and a first terminal of a third resistor, and a second terminal of the capacitor is grounded. The second terminal of the third resistor is used to output the first test DC voltage.

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