Multi-band large dynamic pulse detection device and method

Abstract

A multi-band large dynamic pulse detection method and device, two parallel hardware channels are adopted, three power channels are realized by control switching, and signals of high, medium and low power are processed respectively; at the same time, no mixing circuit is adopted, but each band is directly detected; after sampling, the peak power of the measured signal is calibrated based on the sampling value of the standard signal source. The device and method have simple circuit structure and convenient calibration, and can be used for pulse signal detection in multi-band, large instantaneous bandwidth, narrow pulse width, large pulse repetition period, large power dynamic and other scenes.

Description

Technical Field

[0001] This invention relates to the field of signal detection technology, and in particular to a multi-band large dynamic pulse detection device and method. Background Technology

[0002] With the development of radar technology, the requirements for peak power detection of pulse signals are becoming increasingly stringent. Currently available detectors mainly perform power detection for continuous waves, or some have pulse detection capabilities, but their dynamic range is relatively limited. Summary of the Invention

[0003] This disclosure provides a method for detecting the peak power of multi-band, large dynamic range pulse signals. It can detect the power of radar pulse signals in scenarios with a large dynamic range, covering the S, C, and X bands in frequency range and the power range from -70dBm to +40dBm. The circuit structure is simple and calibration is convenient.

[0004] The multi-band large dynamic range pulse detection device disclosed herein includes: a coupling module, a high-power hardware channel, a medium- and low-power hardware channel, and a main control module, wherein:

[0005] The coupling module is used to split the pulse signal under test into two paths, which are respectively fed into the high-power hardware channel and the medium-low power hardware channel;

[0006] The high-power hardware channel and the medium-low power hardware channel are two independent parallel channels, each containing its own detection module and ADC acquisition module. Specifically, the high-power hardware channel is used to appropriately attenuate the high-power signal before it enters the detection module for detection and ADC acquisition processing; the medium-low power hardware channel is used to amplify and appropriately attenuate the medium-low power signal before it enters the detection module for detection and ADC acquisition processing.

[0007] The main control module is used to control the signal attenuation of the high-power hardware channel and the medium- and low-power hardware channel, and to perform pulse peak power calibration on the data obtained by each channel after acquisition and processing by the ADC.

[0008] Furthermore, the high-power hardware channel includes a programmable attenuation module, an equalization module, a detection module, and an ADC acquisition module connected in series.

[0009] The low-to-medium power hardware channel includes a series-connected limiting module, amplification module, programmable attenuation module, equalization module, as well as a detection module and an ADC acquisition module.

[0010] The attenuation amplitude of each channel attenuation module is controlled by the main control module.

[0011] Furthermore, the low-to-medium power hardware channel includes a series-connected four-stage amplification module, a two-stage programmable attenuation module, and a four-stage equalization module.

[0012] Furthermore, the coupling module has an attenuation of 20dB, the high-power hardware channel has a gain of -20dB, the medium- and low-power hardware channel has a gain of 0dB or 35dB, and the detection modules of both channels have an effective detection range of -45dBm to +5dBm, with an optimal detection range of -40dBm to 0dBm.

[0013] Furthermore, the operating frequency bands of each module cover the S, C, and X bands.

[0014] The large dynamic pulse detection method using the above-mentioned detection device includes the following steps:

[0015] S1 splits the pulse signal under test into two paths, which are then fed into the high-power hardware channel and the medium-low-power hardware channel, respectively.

[0016] S2, in the high-power hardware channel, the incoming high-power signal is appropriately attenuated before entering the detection circuit for detection and ADC acquisition processing.

[0017] In the low-to-medium power hardware channel, the incoming low-to-medium power signal is amplified and appropriately attenuated before entering the detection circuit for detection and ADC acquisition processing.

[0018] This also includes real-time control of the signal attenuation amplitude of high-power hardware channels and medium- and low-power hardware channels;

[0019] S3 performs pulse peak power calibration on the data obtained from the two channels after ADC acquisition and processing.

[0020] Furthermore, in step S2:

[0021] In the low-to-medium power hardware channel, the incoming signal is first processed with the first attenuation amplitude. After sampling for a certain period of time, the signal is switched to the second attenuation amplitude for processing and sampling.

[0022] This enables alternating detection processing of medium-power and low-power signals.

[0023] Furthermore, in step S2, the sampling rate of both the high-power hardware channel and the medium-low power hardware channel ADC is 100MSPS, and the continuous sampling time period for the high-power signal, medium-power signal and low-power signal is 120ms respectively.

[0024] Furthermore, the method in step S3 includes:

[0025] Connect a metered standard pulse signal source, set a certain frequency, set the power to -70dBm, and record the peak sampling value at this time as P0. Gradually increase the power in 2dB increments, and record the peak sampling value P each time the power is changed.

[0026] The obtained peak sample values ​​P0, P1, P2... are used as standard peak sample values;

[0027] The peak sample value M of the measured signal must be located between two adjacent standard peak sample values. Assuming that the power between 2dB is linearly variable, linear interpolation can be performed to deduce the peak power of the measured pulse signal.

[0028] Furthermore, the method in step S3 also includes the step of: taking multiple measurements and taking the median value of each measurement as the final power reading.

[0029] This disclosure employs two parallel hardware channels, which are switched by a main control unit to achieve three power channels, respectively conditioning signals of high, medium, and low power. At the same time, instead of using a mixer circuit, it directly detects each band. After detection and sampling, the peak power of the measured signal is calibrated using the sampling value of a standard signal source.

[0030] Compared with the prior art, the beneficial effects of this disclosure are: (1) by constructing three power channels for segmented conditioning, detection of large dynamic and pulse signals is realized; (2) no mixing is required for the entire frequency band, and the signal directly enters the detection circuit, which greatly simplifies the circuit; (3) dependence on imported components is avoided; (4) high detection accuracy is achieved; (5) it can be used to detect the peak power of pulse signals in scenarios such as multi-band, large instantaneous bandwidth, narrow pulse width, large pulse repetition period, and high power dynamic. Attached Figure Description

[0031] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments of this disclosure taken in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0032] Figure 1 This is a schematic diagram of the overall structure of an exemplary embodiment of the pulse signal detection device according to the present disclosure;

[0033] Figure 2 This is a schematic diagram of a specific structure for an exemplary embodiment. Detailed Implementation

[0034] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0035] This disclosure provides a detection method and apparatus for multi-band, high-dynamic-range pulse signals. It achieves segmented processing of signals with different power levels (high, medium, and low) through two independent hardware channels; then, the main control module performs peak power calibration on the sampling results.

[0036] An exemplary overall structure is shown in the appendix. Figure 1 As shown, it includes: a coupler, a high-power channel, a medium- and low-power channel, and a main control unit.

[0037] The measured pulse signal is split into two hardware channels by a coupler. One high-power hardware channel attenuates the high-power signal appropriately, conditioning its amplitude to a certain range before it enters the detection circuit for further processing. The other medium-to-low-power hardware channel includes a multi-stage amplifier, a programmable attenuator, and an equalizer (which balances power across different frequency bands). When the attenuation value of the programmable attenuator is set high, the overall gain of this hardware channel is low, which is beneficial for medium-power signals; in this case, it is the medium-power channel. When the attenuation value of the programmable attenuator is set low, the overall gain of this hardware channel is high, which is beneficial for low-power signals; in this case, it is the low-power channel. In other words, the two hardware channels implement three power levels (high, medium, and low), ensuring that the power of the measured signal within the range of -70dBm to +40dBm can be conditioned by the corresponding channel. Finally, the signal is converted into voltage by the detection circuit, then converted into a digital signal by the ADC before being sent to the main control unit for processing. After screening, calibration, and calculation by the main control unit, the final power reading is sent to the host computer for display.

[0038] The detection device disclosed herein ensures that for a measured pulse signal of unknown power, there is always one channel matched to it, so that after passing through this channel, the power is conditioned to the optimal detection range of the detector. However, after passing through the other two channels, the power cannot enter the optimal detection range of the detector. This achieves coverage of a large dynamic range of pulse power.

[0039] A more specific exemplary embodiment of the structure and signal flow is shown in the appendix. Figure 2 As shown.

[0040] The pulse signal under test first passes through a high-pass filter to remove interference signals below 2 GHz, while signals in the S, C, and X bands can reach the coupler input smoothly. The coupler has two output ports: a coupled output with a coupling degree of 20 dB and a through output with an insertion loss of less than 1 dB.

[0041] After the pulse signal is output from the coupling output terminal, signal S1 enters the high-power channel. Signal S1 at the coupling output terminal has an attenuation of approximately 20dB relative to the measured signal. The main control unit sets the programmable attenuator A to an appropriate attenuation value (approximately 20dB) via control line Q1, ensuring that the total gain of signal S2 after attenuator A relative to the measured signal at the device input is around -40dB. After passing through equalizer B, the gain of each band of signal S2 is relatively flat before reaching detector C. Detector C has an effective detection range of -45dBm to +5dBm, and an optimal detection range of -40dBm to 0dBm. If the power of the measured signal is within the range of 0dBm to +40dBm, then when it reaches the detector through the high-power channel, the power of signal S3 will be exactly within the detector's optimal detection range. Signal S3 is converted into a pulse envelope signal S4 by the detector, and S4 is sent to the ADC for analog-to-digital conversion. The ADC continuously acquires data for 120ms, and the acquired digital signal S5 is sent to the main control unit FPGA for processing. In this embodiment, the main control unit is an FPGA, and the pulse peak power calibration calculation is performed by a connected host computer.

[0042] The coupler's through-terminal signal S6 is connected to a low-to-medium power hardware channel. In this channel, signal S6 first passes through a limiter to prevent excessive power in signal S7 from burning out the subsequent amplifier E. Signal S7 then passes through four stages of amplifiers (E, H, K, M), two stages of programmable attenuators (F and I), and four stages of equalizers (G, J, L, N). The main control unit uses control signals Q2 and Q3 to set the two stages of programmable attenuators F and I in this channel to a relatively large attenuation value, ensuring the total gain of the channel is around 0dB. If the power of the measured signal is in the range of -40dBm to 0dBm, then when it reaches the detector through this channel, the power of signal S9 will be exactly within the optimal detection range of detector O. In this case, the hardware channel is a medium-power channel. Signal S9 is converted into a pulse envelope signal S10, which is then sent to an ADC for analog-to-digital conversion. The acquired digital signal S11 is then sent to the main control unit's FPGA for processing.

[0043] After the ADC continuously acquires data for 120ms in the medium-power channel, the main control unit immediately changes the attenuation value to a small attenuation value through control signals Q2 and Q3, making the total gain of the channel around 35dB. At this time, for the measured signal with a power range of -75dBm to -35dBm, when it reaches the detector through this channel, signal S9 is exactly within the optimal detection range of detector O. Therefore, the hardware channel at this time is a low-power channel. Signal S9 will be converted into a pulse envelope voltage signal S10, which is then sent to the ADC for analog-to-digital conversion. The ADC continuously acquires data in the low-power channel for 120ms, and the acquired digital signal S11 is sent to the main control unit FPGA for processing.

[0044] The pulse signal to be tested in this disclosure has a maximum pulse repetition period of 100ms and a minimum pulse width of 0.5µs. Therefore, the acquisition time for each channel is set to 120ms to ensure that the ADC can capture at least one pulse peak for pulse signals with a repetition period of less than or equal to 100ms during this period. The ADC sampling rate is set to 100MSPS, so that even for extremely narrow pulses with a pulse width as narrow as 0.5µs, the peak can be acquired 50 times, which is convenient for FPGA algorithm processing. To cover a large dynamic range of 110dBc, acquisition is performed for 120ms for each of the high, medium, and low channels. A total of 360ms is required to complete one round of acquisition.

[0045] In the main control unit FPGA, a maximum value is taken every 200,000 sampling points (i.e., every 2ms) and reported to the host computer. Each channel reports 60 maximum value points every 120ms. The three channels (high, medium, and low power) will report 180 maximum value points: the first 60 points are the maximum values ​​of the high-power channel, the middle 60 points are the maximum values ​​of the medium-power channel, and the last 60 points are the maximum values ​​of the low-power channel. For a measured pulse signal of unknown power, there must be a matching channel such that its power is conditioned to the detector's optimal detection range after passing through that channel. The maximum value of the 60 maximum value points obtained from that channel is the peak sampling value M of the measured pulse, which contains the peak power information of the measured pulse signal. After passing through the other two channels, the power cannot enter the detector's optimal detection range, and the 120 points from these two channels are discarded.

[0046] Preferably, pulse power calibration can be performed using the following method: Connect a pre-calibrated standard pulse signal source to the device, set a certain frequency, set the power to -70dBm, and record the peak sample value P0 at this point. Gradually increase the power in 2dB increments, recording the peak sample value P each time the power is changed. The obtained peak sample values ​​P0, P1, P2, etc., are called standard peak sample values. The peak sample value M of the measured signal must lie between two adjacent standard peak sample values. Assuming that the power changes linearly within 2dB, linear interpolation can be performed to deduce the peak power of the measured pulse signal.

[0047] To achieve more accurate measurements, multiple measurements can be performed, and the median value can be taken as the final reading. For example, if five measurements are taken, the median value of the five measurements can be taken as the final power reading. The total time for five measurements is approximately 1.08 seconds.

[0048] In this embodiment, the main control unit controls and switches between two hardware channels, thus realizing three power channels. After obtaining the detection data of each channel, calibration is performed using calibration values ​​for high, medium, and low voltage bands. This method features a simple circuit structure, convenient calibration, and can achieve power detection of radar pulse signals in a wide dynamic range scenario, covering the S, C, and X bands in frequency range and -70dBm to +40dBm in power range.

[0049] The above technical solutions are merely exemplary embodiments of the present invention. For those skilled in the art, based on the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or modifications, and not limited to the methods described in the specific embodiments of the present invention. Therefore, the methods described above are merely preferred and not restrictive.

Claims

1. A multi-band large dynamic pulse detection device, characterized in that, include: The system includes a coupling module, a high-power hardware channel, a medium- and low-power hardware channel, and a main control module, among which: The coupling module is used to split the pulse signal under test into two paths, which are respectively fed into the high-power hardware channel and the medium-low power hardware channel; The high-power hardware channel and the medium-low power hardware channel are two independent parallel channels, each containing its own detection module and ADC acquisition module. Specifically, the high-power hardware channel is used to appropriately attenuate the high-power signal before it enters the detection module for detection and ADC acquisition processing; the medium-low power hardware channel is used to amplify and appropriately attenuate the medium-low power signal before it enters the detection module for detection and ADC acquisition processing. The main control module is used to control the signal attenuation of the high-power hardware channel and the medium- and low-power hardware channel, and to perform pulse peak power calibration on the data obtained by each channel after acquisition and processing by the ADC. Each module operates in the S, C, and X bands; The high-power hardware channel includes a programmable attenuation module, an equalization module, a detection module, and an ADC acquisition module connected in series. The low-to-medium power hardware channel includes a series-connected limiting module, amplification module, programmable attenuation module, equalization module, as well as a detection module and an ADC acquisition module. The attenuation amplitude of each channel attenuation module is controlled by the main control module; The low-to-medium power hardware channel includes a series-connected four-stage amplification module, a two-stage programmable attenuation module, and a four-stage equalization module.

2. The detector according to claim 1, characterized in that, The coupling module has an attenuation of 20dB, the high-power hardware channel has a gain of -20dB, and the medium-low power hardware channel has a gain of 0dB or 35dB. The effective detection range of the detection modules for both channels is -45dBm to +5dBm.

3. A method for large dynamic pulse detection using the detection device described in claim 1 or 2, characterized in that, Includes the following steps: S1 splits the pulse signal under test into two paths, which are then fed into the high-power hardware channel and the medium-low-power hardware channel, respectively. S2, in the high-power hardware channel, the incoming high-power signal is appropriately attenuated before entering the detection circuit for detection and ADC acquisition processing. In the low-to-medium power hardware channel, the incoming low-to-medium power signal is amplified and appropriately attenuated before entering the detection circuit for detection and ADC acquisition processing. This also includes real-time control of the signal attenuation amplitude of high-power hardware channels and medium-low power hardware channels; S3, calibrate the pulse peak power of the data obtained from the two channels after ADC acquisition and processing; In step S2: In the low-to-medium power hardware channel, the incoming signal is first processed with the first attenuation amplitude. After sampling for a certain period of time, the signal is switched to the second attenuation amplitude for processing and sampling. This enables alternating detection processing of medium-power and low-power signals.

4. The method according to claim 3, characterized in that, In step S2, the sampling rate of the high-power hardware channel and the medium-low power hardware channel ADC is 100MSPS, and the continuous sampling time period for the high-power signal, medium-power signal and low-power signal is 120ms.

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