Systems and methods for reducing prediction errors in resist models

Abstract

This paper describes a method for calibrating a resist model. The method includes the following steps: generating a modeled resist profile of the resist structure based on a simulated spatial image of the resist structure and parameters of the resist model; and predicting a measurement profile of the resist structure based on the modeled resist profile, using information about the actual resist structure obtained from a measurement device. The method further includes adjusting the parameters of the resist model based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained from the measurement device.

Description

[0001] This application is a divisional application of the international application PCT / EP2018 / 086415, which entered the Chinese national phase on June 19, 2020, with application number 201880082618.3.

[0002] Cross-reference to related applications

[0003] This application claims priority to US Application 62 / 609,776, filed December 22, 2017, and US Application 62 / 769,283, filed November 19, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0004] This paper describes systems and methods for improving the prediction of resist profiles constructed from resist models. Specifically, this paper provides techniques for reducing the prediction errors of resist models. Background Technology

[0005] Photolithography equipment can be used, for example, to manufacture integrated circuits (ICs) or other devices. In this case, a patterning apparatus (e.g., a mask) can contain or provide a single-layer pattern (“design layout”) corresponding to the device, and this pattern can be transferred to a target portion (e.g., comprising one or more dies) on a substrate (e.g., a silicon wafer) that has already been coated with a layer of radiation-sensitive material (“resist”) (using methods such as irradiating the target portion via a pattern on the patterning apparatus). Typically, a single substrate contains multiple adjacent target portions, and the pattern is transferred sequentially to these adjacent target portions by the photolithography apparatus, one target portion at a time. In one type of photolithography apparatus, the pattern on the entire patterning apparatus is transferred to one target portion at a time; this type of apparatus is often referred to as a stepper. In an alternative apparatus, often referred to as a step-scan apparatus, a projection beam scans across the patterning apparatus in a given reference direction (“scanning” direction) while the substrate is moved synchronously parallel to or antiparallel to that reference direction. Different portions of the pattern on the patterning apparatus are gradually transferred to a target portion. Typically, since the lithography equipment will have a magnification factor M (usually < 1), the rate at which the substrate is moved, F, will be a factor M times the rate of the projection beam scanning patterning device.

[0006] Before the pattern is transferred from the patterning apparatus to the substrate in the device fabrication process, the substrate can undergo various device fabrication procedures, such as primer coating, resist coating, and soft baking. After pattern transfer, the substrate can undergo other device fabrication procedures, such as post-exposure baking (PEB) with the transferred pattern, development, hard baking, and measurement / inspection. This series of device fabrication procedures forms the basis for the monolayer used to manufacture devices (e.g., ICs). The substrate can then undergo various device fabrication procedures, such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, and metrology (e.g., using scanning electron microscopy (SEM)), all aimed at finishing the monolayer of the device. If several layers are required in the device, the entire process or its variations are repeated for each layer. Ultimately, a device will be present in each target portion of the substrate. If multiple devices are present, they are subsequently separated from each other using techniques such as dicing or sawing, allowing individual devices to be mounted on carriers, connected to pins, etc.

[0007] Therefore, fabricating devices (such as semiconductor devices) typically involves processing a substrate (e.g., a semiconductor wafer) using several fabrication processes to form various features and multiple layers of the device. These layers and features are typically fabricated and processed using processes such as deposition, photolithography, etching, chemical mechanical polishing, and ion implantation. Multiple devices can be fabricated on multiple dies on the substrate, and these devices are then separated into individual devices. This device fabrication process can be considered a patterning process. A patterning process involves patterning steps, such as optical or nanoimprint lithography using photolithography equipment, to provide a pattern on the substrate and typically, but optionally, involves one or more related patterning processing steps, such as resist development performed by a developing equipment, baking the substrate using a baking tool, etching using an etching equipment and the pattern, etc. Additionally, one or more measurement processes are typically involved in the patterning process.

[0008] As semiconductor manufacturing processes have continued to advance, the size of functional components has shrunk over the decades, while the number of functional components, such as transistors, per device has steadily increased, following a trend commonly known as "Moore's Law." In the current state of technology, multiple layers of a device are fabricated using a photolithography projection apparatus. This apparatus uses illumination from a deep ultraviolet irradiation source to project a pattern corresponding to a design layout onto a substrate, thereby producing individual functional components whose size is much smaller than 100 nm (i.e., less than half the wavelength of radiation from the irradiation source (e.g., a 193 nm irradiation source)). This process, which produces features with print sizes smaller than the classical resolution limit of the photolithography projection apparatus, is often referred to as low-k1 lithography according to the resolution formula CD = k1 × λ / NA, where λ is the wavelength of the radiation used (currently 248 nm or 193 nm in most cases), NA is the numerical aperture of the projection optics in the photolithography projection apparatus, CD is the "critical size" (typically the smallest feature size that can be printed), and k1 is an empirical resolution factor. Typically, the smaller k1 is, the more difficult it becomes to reproduce patterns on a substrate that resemble the shape and size planned by the circuit designer to achieve specific electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps are applied to the photolithography projection equipment and / or the pattern corresponding to the design layout. These steps include, for example, but not limited to, optimization of NA and / or optical coherence settings, customized illumination schemes, use of phase-shifting patterning devices, optical proximity correction (OPC) in the pattern corresponding to the design layout (such as deviations in pattern features, addition of auxiliary features, application of wiring to pattern features, etc.), or other methods generally defined as "resolution enhancement techniques" (RET).

[0009] In photolithography applications, resist models (e.g., tachyon resist models) are often used to predict the resist profile of a contour to be measured by a SEM device. Resist models are introduced to correct for resist bias relative to resist profiles predicted from a single spatial image. Specifically, a spatial image at a suitable height within the resist thickness, or the average intensity of a spatial image over the resist thickness, is used for prediction purposes. Such resist models cannot accurately predict the effects of focus-dependent features, such as 1D line spatial patterns in negative tone development (NTD) resists with sub-resolution auxiliary features (SRAF) close to the primary feature.

[0010] The inability of current resist models to accurately predict the effects of focus-dependent features can be attributed to feature-dependent biases in the metrological measurements of the resist profile (e.g., CDSEM measurements). As the expected feature size continues to decrease, the relative contribution of this bias introduced by the metrological device will continue to increase, thus introducing further modeling errors. Therefore, there is a need to develop systems and methods to reduce predictive errors in resist models. Summary of the Invention

[0011] In order to understand how the patterning process works, computational lithography can be used to simulate how one or more aspects of the patterning process “work.” Thus, appropriate computational lithography software can predict one or more characteristics of the formation of a pattern on a substrate, such as the predicted CD of the pattern, the predicted profile, etc., and may do so at different stages of pattern formation.

[0012] One aspect of computational lithography is the prediction of patterns in resist layers. However, existing techniques for predicting pattern formation in resist layers have been found to be inadequate and / or slow in assessing potential patterns within the resist layer. Therefore, for example, it is desirable to provide a technique for accurately and / or rapidly predicting the expected (often very complex) shape of resist patterns. Consequently, for example, methods and systems are provided for improving resist modeling prediction of resist layers. Specifically, this paper describes a method for reducing resist modeling errors by correcting artifacts induced by a metrological device (e.g., a SEM apparatus) for focus-dependent features using information such as SEM measurements from the resist profile.

[0013] An embodiment of the present invention provides a method for calibrating a resist model. The method includes the following steps: generating a modeled resist profile of the resist structure based on a simulated spatial image of the resist structure and parameters of the resist model; predicting a measurement profile of the resist structure using the modeled resist profile based on information about the actual resist structure obtained by a measurement device; and adjusting the parameters of the resist model based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measurement device.

[0014] The information about the actual resist structure obtained by the measuring device corresponds to the width of a portion of the waveform generated by the measuring device.

[0015] A portion of the waveform corresponds to the edge of the actual resist structure imaged by the measuring device.

[0016] The predicted measurement profile of the resist structure is generated from the modeled resist profile based on parameters associated with the measurement device.

[0017] The method further includes the step of updating the parameters of the measuring device based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measuring device.

[0018] The measuring device is a scanning electron microscope.

[0019] The method further includes the following steps: optimizing the parameters of the mask layout and the parameters of the light source based on the adjusted resist parameters of the resist model.

[0020] The method further includes the following steps: predicting the measurement profile of another resist structure based on the adjusted parameters of the resist model; obtaining the actual measurement profile of the other resist structure by the measurement device; and calculating the error based on the comparison between the predicted measurement profile of the other resist structure and the actual measurement profile of the other resist structure.

[0021] One embodiment provides an apparatus for calibrating a resist model. The apparatus includes a processor configured to: generate a modeled resist profile of the resist structure based on a simulated spatial image of the resist structure and parameters of the resist model; predict a measured profile of the resist structure using the modeled resist profile based on information about the actual resist structure obtained by a measurement device; and adjust the parameters of the resist model based on a comparison between the predicted measured profile and the actual measured profile of the actual resist structure obtained by the measurement device.

[0022] The information about the actual resist structure obtained by the measuring device corresponds to the width of a portion of the waveform generated by the measuring device.

[0023] A portion of the waveform corresponds to the edge of the actual resist structure imaged by the measuring device.

[0024] The width of a portion of the waveform is measured at a predetermined threshold intensity level.

[0025] The predicted measurement profile of the resist structure is generated from the modeled resist profile based on parameters associated with the measurement device.

[0026] The processor included in the device is further configured to update the parameters of the measurement device based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measurement device.

[0027] The measuring device is a scanning electron microscope.

[0028] The processor included in the device is further configured to optimize the parameters of the mask layout and the parameters of the light source based on the adjusted resist parameters of the resist model.

[0029] The processor included in the device is further configured to: predict the measurement profile of another resist structure based on adjusted parameters of the resist model; obtain the actual measurement profile of the other resist structure by the measurement device; and calculate the error based on a comparison between the predicted measurement profile of the other resist structure and the actual measurement profile of the other resist structure.

[0030] One embodiment provides a method comprising the steps of: generating a modeled resist profile of the resist structure based at least on a simulated spatial image of the resist structure; predicting a measurement value of a portion of a waveform corresponding to an edge of an actual resist structure imaged by a measurement device based on the modeled resist profile, the simulated spatial image, and at least one resist sidewall parameter from a set of resist sidewall parameters associated with the resist structure; and adjusting the at least one resist sidewall parameter based on a comparison between the predicted measurement value of the portion of the waveform and an actual measurement value corresponding to a portion of the waveform of the edge of the actual resist structure imaged by the measurement device.

[0031] The predicted measurement of a portion of the waveform is the width of a portion of the waveform generated by the measuring device, which is measured at a predetermined threshold intensity level.

[0032] The predicted measurement value of a portion of the waveform generated by the measuring device is based on at least two of the set of resist sidewall parameters.

[0033] The set of resist sidewall parameters includes three resist sidewall parameters, and the predicted measurement value of a portion of the waveform generated by the measuring device is based on each of the resist sidewall parameters in the set of resist sidewall parameters.

[0034] The vertical intensity range parameter is calculated as the difference between a first intensity of a first spatial image and a second intensity of a second spatial image, the first spatial image corresponding to a first position within the resist layer, and the second spatial image corresponding to a second position within the resist layer.

[0035] The first position is in the top third portion of the resist layer, and the second position is in the bottom third portion of the resist layer.

[0036] The first position is located 15 nanometers below the top surface of the resist layer, and the second position is located 75 nanometers below the top surface of the resist layer.

[0037] The method further includes the following steps: optimizing the parameters of the mask layout and the parameters of the light source based on the adjusted resist sidewall parameters.

[0038] The method further includes the steps of: predicting another measurement value corresponding to a portion of another waveform of the edge of another actual resist structure imaged by the measurement device based on a modeled resist profile of another resist structure, a simulated spatial image of another resist structure, and at least one adjusted resist sidewall parameter from the set of resist sidewall parameters; and determining the etching quality of the edge of the other actual resist structure based on the predicted measurement value of the portion of the other waveform.

[0039] In one embodiment, a non-transitory computer program product is provided, comprising machine-readable instructions for causing a processor to perform the methods described herein. In another embodiment, a system is provided, comprising: a hardware processor; and a non-transitory computer program product as described herein. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments, and explain these embodiments together with this specification. Embodiments of the invention will now be described by way of example only with reference to the accompanying illustrative drawings. In the drawings, corresponding reference numerals indicate corresponding portions, and wherein:

[0041] Figure 1 It is a block diagram of the various subsystems of the photolithography system.

[0042] Figure 2 It is a block diagram of a simulation model of computational lithography technology.

[0043] Figure 3A , Figure 3B , Figure 3C and Figure 3D An exemplary deformation of the resist layer on the substrate is schematically shown.

[0044] Figure 4A , Figure 4B , Figure 4C and Figure 4D An exemplary additional deformation caused by the development of the resist layer is schematically shown.

[0045] Figure 5A An exemplary SEM image is depicted.

[0046] Figure 5B An exemplary SEM waveform corresponding to a portion of a SEM image is depicted.

[0047] Figure 6A An exemplary graph illustrating the effect of vertical intensity range on the shape of the etchant layer is provided.

[0048] Figure 6BAn exemplary graph illustrating the effect of the logarithmic slope of an image on the shape of the etchant layer is provided.

[0049] Figure 7A and Figure 7B A schematic diagram illustrating the effect of vertical strength range on the shape of the etchant according to an embodiment is shown.

[0050] Figure 8A and Figure 8B A schematic diagram illustrating the effect of the logarithmic slope on the shape of the etchant according to an embodiment is shown.

[0051] Figure 9 An exemplary flowchart illustrating the steps performed when calibrating a resist model according to an embodiment of the present invention is shown.

[0052] Figure 10 An exemplary flowchart illustrating the steps performed to verify a calibrated resist model according to an embodiment of the present invention is depicted.

[0053] Figure 11 An exemplary flowchart illustrating the steps performed during source mask optimization according to an embodiment of the present invention is shown.

[0054] Figure 12 An exemplary flowchart illustrating the steps performed when calibrating resist sidewall parameters to predict the width of the white stripe according to an embodiment of the present invention is shown.

[0055] Figure 13 An exemplary flowchart illustrating the execution of an unusual feature detection method for a resist layer is depicted.

[0056] Figure 14 This is a block diagram of an exemplary computer system.

[0057] Figure 15 This is a schematic diagram of a photolithography projection device.

[0058] Figure 16 This is a schematic diagram of another photolithography projection device.

[0059] Figure 17 yes Figure 16 A more detailed view of the device.

[0060] Figure 18 yes Figure 16 and Figure 17 A more detailed view of the device's source collector module. Detailed Implementation

[0061] As background to the embodiment and turning to Figure 1This describes an exemplary photolithography projection apparatus 10A. The main components are: a radiation source 12A, which may be a deep ultraviolet excimer laser source or other types of light sources including extreme ultraviolet (EUV) sources; irradiation optics defining partial coherence (denoted as σ) and potentially including optics 14A, 16Aa, and 16Ab for shaping the radiation from source 12A; a support configured to hold a patterning device 18A; and a projection optics 16Ac that projects an image of the pattern from the patterning device onto a substrate plane 22A. An adjustable filter or aperture 20A at the pupil plane of the projection optics can define the range of beam angles irradiating the substrate plane 22A, wherein the maximum possible angle defines the numerical aperture NA of the projection optics as sin(Θ). max In this embodiment, the photolithography projection device itself does not need to have a radiation source 12A.

[0062] Therefore, in a photolithography projection apparatus, optics 16Ac guide a spatial image (typically a scaled-down version) of a patterned device onto a substrate. The spatial image (AI) is the distribution of radiation intensity at a specific level on the substrate. A resist layer on the substrate is exposed, and the spatial image is transferred to the resist layer as a latent image, known as a "resist image" (RI). The resist image (RI) can be defined as the spatial distribution of the solubility of the resist within the resist layer.

[0063] Currently, there is a frequent need to be able to computationally determine how a patterning process will produce a desired pattern on a substrate. Therefore, simulations can be provided to model one or more parts of the process. For example, there is a need to simulate the photolithography process of transferring a patterning apparatus pattern onto a resist layer of a substrate after developing the resist, and the resulting pattern in that resist layer.

[0064] Figure 2 An exemplary flowchart for simulating lithography in a lithographic projection apparatus is illustrated. Illumination model 31 represents the optical characteristics of illumination (including radiation intensity distribution and / or phase distribution). Projection optics model 32 represents the optical characteristics of projection optics (including changes in radiation intensity distribution, polarization, and / or phase distribution caused by projection optics). Design layout model 35 represents the optical characteristics of a design layout (including changes in radiation intensity distribution and / or phase distribution caused by a given design layout), which is a representation of the configuration of features on or formed by a patterning apparatus. Spatial image 36 can be simulated using illumination model 31, projection optics model 32, and design layout model 35. Resist image 38 can be simulated from spatial image 36 using resist model 37. The simulation of lithography can, for example, predict the contours and / or CDs in the resist image.

[0065] More specifically, it should be noted that the illumination model 31 can represent the optical characteristics of the illumination, including but not limited to, NA-sigma (σ) settings and any particular illumination shape (e.g., off-axis illumination, such as ring, quadrupole, dipole, etc.). The projection optics model 32 can represent the optical characteristics of the projection optics, including, for example, aberrations, distortion, refractive index, solid size or dimensions, etc. As described in, for example, U.S. Patent No. 7,587,704, which is incorporated herein by reference in its entirety, the design layout model 35 can also represent one or more physical properties of the solid patterning apparatus. The optical properties associated with the lithographic projection apparatus (e.g., the properties of the illumination, patterning apparatus and projection optics) define the spatial image. Since the patterning apparatus used in the lithographic projection apparatus can be varied, it is necessary to separate the optical properties of the patterning apparatus from the optical properties of the rest of the lithographic projection apparatus, which includes at least the illumination and projection optics, and thus the design layout model 35 is provided.

[0066] A resist model 37 can be used to calculate a resist image based on a spatial image, an example of which can be found in U.S. Patent No. 8,200,468, which is incorporated herein by reference in its entirety. While resist models are generally primarily related to the properties of the resist layer (e.g., the effects of chemical processes occurring during exposure, post-exposure baking, and / or development), they will tend to also contain SEM artifacts because they are typically calibrated based on SEM measurements.

[0067] The goal of the simulation is to accurately predict, for example, edge placement, spatial image intensity slope, and / or CD, which can then be compared to the expected design. The expected design is typically defined as a pre-designed layout that can be provided in a standardized digital file format such as GDSII, OASIS, or other file formats.

[0068] Based on the design layout, one or more portions referred to as "segments" can be identified. In embodiments, a set of segments is extracted that represent complex patterns in the design layout (though typically around 50 to 1000 segments, but any number of segments can be used). Those skilled in the art will understand that these patterns or segments represent small parts of the design (i.e., circuits, cells, etc.), and that these segments represent small parts that require specific attention and / or verification. In other words, these segments can be multiple parts of the design layout, or they can resemble or have critical characteristics that are identified through experience (including segments provided by the customer), through trial and error, or through performing full-wafer simulation. Segments often contain one or more test patterns or gauge patterns. An initial large set of segments can be provided a priori by the customer based on known critical feature regions in the design layout that require specific image optimization. Alternatively, in another embodiment, an initial large set of segments can be extracted from the entire design layout by using some automated (such as machine vision) or manual algorithm to identify critical feature regions.

[0069] In some examples, simulation and modeling can be used to configure one or more features of a patterned device pattern (e.g., performing optical proximity correction), one or more features of illumination (e.g., altering one or more properties of the spatial / angular intensity distribution of illumination, such as changing shape), and / or one or more features of a projection optics (e.g., numerical aperture, etc.). Such configurations are often referred to as mask optimization, source optimization, and projection optimization, respectively. These optimizations can be performed independently or combined in different ways. One such example is source-mask optimization (SMO), which involves configuring one or more features of a patterned device pattern and one or more features of illumination. The optimization technique can focus on one or more segments within a fragment. Optimization can be achieved using simulations described herein to produce values ​​for various parameters.

[0070] In the optimization process of a system, the quality factor of the system can be represented as a cost function. The optimization process boils down to finding a set of system parameters (design variables) that minimize the cost function. The cost function can have any suitable form depending on the optimization objective. For example, the cost function can be the weighted root mean square (RMS) of the deviations of certain characteristics of the system (evaluation points) from the expected values ​​(e.g., ideal values) of these characteristics; the cost function can also be the maximum value of these deviations (i.e., the worst deviation). The term "evaluation point" in this invention should be interpreted broadly to include any characteristic of the system. Due to the practicality of system implementation, the design variables of the system can be limited to a finite range and / or can be interdependent. In the case of photolithography projection equipment, constraints are often associated with the physical properties and characteristics of the hardware (such as tunability range and / or manufacturability design rules for patterning devices), and evaluation points can include physical points on the resist image on the substrate as well as non-physical characteristics such as dose and focus.

[0071] As mentioned above, layers on a substrate can have patterns transferred to that layer. These layers are typically referred to as resist layers and can have various chemical compositions. In this embodiment, the resist layer is a radiation-sensitive material layer. Resist layers typically have a small but finite thickness, comparable in size to the pattern imaged onto the resist. The resist layer can undergo various treatments in the photolithography process. For example, the resist can be exposed to radiation such as EUV or DUV, which induces a chemical reaction in the resist. The resist can undergo post-exposure baking (PEB), development (e.g., positive-tone development or negative-tone development), and / or hard baking. Each of these treatments can cause the resist to deform in one, two, or three dimensions, and the deformation can be location-dependent (e.g., three-dimensional location-dependent). The deformation of the resist can affect downstream processes such as material deposition and etching. In photolithography processes using negative-tone development, the effect of resist deformation on the maximum loss and critical size of the resist top can be particularly significant. Therefore, a resist model 37 capable of predicting resist deformation is beneficial for more accurate lithography and higher yield. The resist model 37 can also predict the reaction of the resist layer to various other physical and chemical treatments in the lithography process. An exemplary resist model according to one aspect of the invention will be described later.

[0072] Figure 3A , Figure 3B , Figure 3C and Figure 3DAn exemplary deformation of the resist layer 310 on substrate 320 is schematically illustrated. A pattern is formed in the resist layer 310, for example, by exposing it to radiation 330 via a patterning device 340. The resist layer 310 may undergo a post-exposure treatment such as PEB and be deformed into a deformed resist layer 350. In this example, the deformation of the resist layer 310 results in a smaller thickness in the portion of the deformed resist layer 350 exposed to radiation compared to the rest of the deformed resist layer 350. A portion 355 of the deformed resist layer 350 receives a sufficiently high dose during exposure to remain on substrate 320 after negative tone development, and the remaining portion of the deformed resist layer 350 (e.g., portion 356) dissolves after negative tone development. Alternatively, a portion 355 of the deformable resist layer 350 receives a sufficiently high dose during exposure to dissolve after positive tone development, and the remainder of the deformable resist layer 350 remains on the substrate 320 after positive tone development. Whether portion 355 is retained or dissolved depends on the chemical composition of the resist and the developer.

[0073] During development, the developer-soluble portions of the resist layer are removed. The removal of these portions can cause deformation of the remaining portions of the resist layer, in addition to the deformation of the resist layer 350 as described with reference to FIG3, or deformation that replaces the deformation. Figure 4A , Figure 4B , Figure 4C and Figure 4D This exemplary additional deformation is illustrated schematically. Figure 4A The exposed resist layer 350 shown in Figure 3 (with) Figure 3C (An optional variation shown) has portions 355 and 356, wherein portion 355 receives a sufficiently high dose during exposure and is therefore soluble in the positive tint developer, and portion 356 does not receive a sufficiently high dose and is therefore insoluble in the positive tint developer. Figure 3B The diagram shows portion 355 dissolving during development while portion 356 remains. As part of this development or at a subsequent time, portion 356 may transform into portion 357. This can occur during the removal of portion 355 and / or at a time after development is complete. The dotted lines represent the outline of portion 356. In the example, portion 356 shrinks and becomes portion 357. Figure 4C The exposed resist layer 350 shown in Figure 3 (with) Figure 3C (An optional variation shown in the figure), wherein portion 355 receives a sufficiently high dose during exposure and is therefore insoluble in the negative tint developer, while portion 356 does not receive a sufficiently high dose and is therefore soluble in the negative tint developer. Figure 4DThe diagram shows portion 355 remaining and portion 356 dissolving during development. As part of this development or for a subsequent period, portion 355 can deform into portion 354. This can occur during the removal of portion 356 and / or for a period after development is complete. Dotted lines represent the outline of portion 355. In the example, portion 355 shrinks and becomes portion 354.

[0074] An embodiment of the present invention provides a method for reducing resist modeling errors when predicting the contour of a resist layer. This method accurately predicts the resist contour by correcting for artifacts induced by SEM (i.e., measurement devices), particularly for focus-dependent features. Specifically, the method utilizes information from the SEM waveform to correct for SEM-induced artifacts. In one embodiment, the information from the SEM waveform corresponds to the width of the white band in the SEM waveform that corresponds to the resist contour. (Refer to...) Figure 5A and Figure 5B Describe the details about the SEM waveform.

[0075] The motivation for correcting SEM-induced artifacts by using the width of the white band in a CDSEM image, as exemplified by one embodiment, is that the width of the white band is a measure of the resist's sidewall shape. The resist's sidewall shape is determined by three parameters: the slope of the spatial image, the vertical intensity range parameter, and the line CD. Furthermore, the width of the white band is related to resist model errors; in one embodiment of the invention, these errors are attributed to shape-induced biases in the CDSEM measurements. It must be understood that biases in CDSEM measurements are not currently modeled in resist models such as tachyon resist models. Therefore, in the following text, the width of the white band is used in the resist model calibration procedure. Furthermore, as described below, the calibrated resist model can be used for validation purposes and source-mask optimization applications.

[0076] Now go to Figure 5A The figure depicts an exemplary SEM image 500. This SEM image includes multiple resist contours (e.g., 1D line features), represented by 510. Each line feature includes a white band 520 on either side of the line feature. It must be understood that, due to artifacts in current scanning electron microscopy, the width and brightness of the white band on the left and right sides of the line feature differ. Therefore, by one embodiment, the measured width of the white band only on one side (e.g., the left or right side) of the feature is used in the calibration process of the resist model.

[0077] As will be clear, not the entire contour needs to be used to perform the methods described herein. For example, the dimensions of the contour can be used. If the contour is a circle, then, for example, the size of the circle can be used as a parameterization of the contour. In one approach, the dimension can be the width in one direction (e.g., x or y). In general, any type of parameterization of the contour can be used in place of the contour itself.

[0078] As an example, a slender feature can be fitted to an ellipse, and the parameterization can be either the major or minor axis. In a typical pattern, the feature is printed along the x or y direction, such that the major and minor axes of the ellipse fitted to that feature will also be in the x or y direction.

[0079] More generally, a profile can be fitted to a predefined shape (circle, ellipse, straight line, line with a dome), and parameters are determined based on, for example, the axis of the ellipse, the width (CD) of the line, and the distance between one feature and other features (tip to tip).

[0080] Figure 5B An exemplary SEM waveform 550 corresponding to a region of a SEM image is depicted. Specifically, Figure 5B The SEM waveform 550 in the image corresponds to, for example: Figure 5A The white stripe area 520 depicted in the image. (See reference...) Figure 5B The width of the white stripe in the SEM waveform is 570 relative to a predetermined threshold intensity level of 560.

[0081] In the embodiments, the threshold is based on, for example... Figure 5B The minimum and maximum values ​​of the filtered SEM signal are shown. Typically, while the threshold can be set to approximately 60% of the difference between the minimum and maximum values, other percentages can be used in principle.

[0082] In this embodiment, since the SEM artifacts or other sources do not represent the features of interest or local extrema, the minimum and maximum values ​​are measured locally near the white band of interest, rather than measuring the minimum and maximum values ​​of the entire image.

[0083] Typical resist models (e.g., tachyon resist models) involve averaging the spatial image over the resist thickness or selecting a spatial image at a suitable height within the resist layer. This approach leads to inaccurate predictions of focus-dependent features, such as 1D line spatial patterns in negative tone development (NTD) resists with sub-resolution auxiliary features (SRAF) close to the primary feature. Therefore, by one embodiment of the invention, a parameter referred to herein as the Vertical Intensity Range (VIR) parameter at the feature edges is used as a measure of the change in spatial image intensity over the resist thickness. Specifically, the VIR parameter is defined as follows:

[0084] VIR(x, y) = AI(x, y, AI) location =15 nm)-AI(x, y, AI location =75 nm) (1)

[0085] Where x and y correspond to the coordinates within the resist layer, and AI location This corresponds to the depth within the resist thickness. Note that the depth can be measured relative to the top surface of the resist layer.

[0086] In one embodiment, the slope of the spatial image and VIR affect the shape of the resist. The slope of the spatial image intensity, which varies with location, measures the steepness of the image during the transition from bright to dark. The normalized slope of the spatial image (referred to herein as the image logarithmic slope (ILS)) is obtained by dividing the slope by the image intensity. Figure 6A An exemplary graph illustrates the effect of a feature shape on the range of vertical intensity for features with a similar image logarithmic slope. Specifically, Figure 6A The profile of the resist layer sidewalls is depicted as changing with VIR. It can be observed that increasing VIR leads to a decrease in the size of the resist layer sidewalls. Similarly, Figure 6B An exemplary graph depicts the effect of the logarithmic slope on the feature shape for a feature image with a similar VIR. Figure 6B The increase in ILS leads to an increase in the sidewalls of the resist layer.

[0087] Go to Figure 7A and Figure 7B The figure depicts a schematic diagram illustrating the effect of the vertical strength range on the feature shape according to an embodiment. Figure 7A The case of a large positive VIR between the top and bottom surfaces of the resist thickness is depicted. Lines 701 and 703 correspond to points with the same spatial image intensity at the bottom and top of the resist layer, respectively. It must be understood that when the VIR has a large positive value (i.e., a large difference in spatial image intensity between the top and bottom layers of the resist), the isointense curve 730 is essentially overhanging. This results in a vertical resist shape 710 formed on the substrate 720.

[0088] On the contrary, Figure 7B The case of a small positive VIR between the top and bottom surfaces of the resist thickness is depicted. Lines 751 and 753 correspond to points with the same spatial image intensity at the bottom and top of the resist layer, respectively. When the VIR between the top and bottom surfaces of the resist thickness is small (i.e., the spatial image intensity difference between the top and bottom layers of the resist is small), the isointense curve 780 is essentially vertical. In this case, the resist 760 formed on the substrate 770 has significant sidewalls.

[0089] Now go to Figure 8A and Figure 8B The image illustrates the effect of the logarithmic slope (ILS) on the shape of the resist according to an embodiment. It must be understood that when the resist absorbs light, the intensity at the top of the resist is always slightly higher than at the bottom.

[0090] Figure 8A The diagram depicts the case where there is a small ILS between the top and bottom surfaces of the resist layer. Curves 801 and 803 correspond to points with the same spatial image intensity at the bottom and top of the resist layer, respectively. It must be understood that when the ILS is small, the horizontal distance between points with the same intensity on the top and bottom layers of the resist is large. Specifically, considering a particular intensity level represented by line 807, one can notice that the horizontal distance between the points on curve 801 (or 803) and those intersecting with line 807 is large. In the case of a small ILS, the iso-intensity curve 805 is essentially overhanging. This results in a vertical resist shape 810 formed on the substrate 820.

[0091] On the contrary, Figure 8B The case of a large ILS between the top and bottom surfaces of the resist layer is depicted. Curves 851 and 853 correspond to points with the same spatial image intensity at the bottom and top of the resist layer, respectively. It must be understood that when the ILS is large, the horizontal distance between points with the same intensity on the top and bottom layers of the resist is small. Specifically, considering a particular intensity level represented by line 857, one can notice that the horizontal distance between the points on curve 851 (or 853) and those intersecting with line 857 is small. In this case with a large ILS, the iso-intensity curve 855 is essentially vertical. In this case, the resist 860 formed on the substrate 870 has significant sidewalls.

[0092] As mentioned earlier, the width of the white band (obtained via SEM image) is a measure of the sidewall shape of the resist. The sidewall shape of the resist is determined by three parameters: the slope of the spatial image, the vertical intensity range parameter of the resist, and the line CD (critical dimension).

[0093] The VIR parameter is calculated as the difference between a first intensity of a first spatial image at a first location within the resist and a second intensity of a second spatial image at a second location within the resist layer. In one embodiment, the first location is 15 nm below the top surface of the resist layer, and the second location is 75 nm below the top surface of the resist layer. However, it must be understood that the above values ​​of 15 nm and 75 nm do not limit the scope of the invention. For example, the first location may be selected from the top third portion of the resist layer, and the second location may be selected from the bottom third portion of the resist layer.

[0094] Additionally, in one embodiment of the invention, the first position may correspond to a position corresponding to a first average intensity of a spatial image calculated in a first portion of the resist layer, and the second position may correspond to a position corresponding to a second average intensity of a spatial image calculated in a second portion of the resist layer. The first portion may be a top portion of the resist layer having a first height, and the second portion may be a bottom portion of the resist layer having a second height, wherein the first height is 20% of the height of the resist layer, and the second height is 20% of the height of the resist layer. Alternatively, the first height may be 30% of the height of the resist layer, and the second height may be 30% of the height of the resist layer.

[0095] Furthermore, in one embodiment, the width of the white band in the SEM image depends on the line CD, the VIR parameter, and the slope of the spatial image. Specifically, in one embodiment, the width of the white band increases with increasing line CD and decreases with increasing slope of the spatial image. Additionally, the width of the white band in the SEM image decreases with increasing VIR value. Therefore, the width of the white band is affected by the same parameters of the separately determined sidewall shape, namely the line CD, the slope of the spatial image, and the VIR parameter. Thus, in one embodiment, the width of the white band in the SEM image is a measure of the sidewall shape of the resist. Therefore, as described below, the width of the white band in the SEM image is used to correct SEM-induced artifacts in resist model prediction of the resist profile.

[0096] Now go to Figure 9 The figure provides an exemplary flowchart illustrating the steps performed when calibrating a resist model according to an embodiment of the present invention.

[0097] The calibration of the resist model (e.g., a tachyon resist model) begins with obtaining a mask (step 910) and irradiating an optical system model (step 920) to generate a simulated spatial image of the resist layer (step 930).

[0098] Additionally, in step 940, initial values ​​for a set of resist parameters for the resist model under consideration are determined. In step 950, a resist profile of the resist structure is generated (i.e., predicted) based on the resist parameters determined in step 940 and the simulated spatial image generated in step 930.

[0099] Additionally, the calibration process obtains information about the actual resist structure, such as that obtained by a measurement device (e.g., a SEM device), in step 955. For example, in one embodiment, a measurement of the width of the white band, such as that obtained by a CDSEM, is obtained in step 955. Based on the measured width of the white band obtained by the CDSEM, the predicted resist profile from step 950, and the initial value of the SEM deviation parameter (characterizing the SEM device) from step 980, the calibration process predicts the SEM profile of the resist structure in step 960. In one embodiment, the deviation associated with the SEM device can be expressed as:

[0100] SEM bias = c0 + cW white band ×W white band (2)

[0101] Among them, c0 and cW white band The parameters are valid SEM parameters. The process then proceeds to step 970, where a query is performed to determine whether the predicted SEM profile from step 960 matches the actual SEM profile measured by CDSEM (step 990). Based on the degree of matching between the predicted and actual SEM profiles, the calibration process provides feedback to steps 940 and 980, respectively. Specifically, the feedback loop corresponds to the parameter calibration steps, where the resist parameters are updated in step 940, and the valid SEM parameters are updated in step 980, respectively.

[0102] In addition, such as Figure 9 The calibration process outlined herein repeats steps 940, 950, 980, 960, and 970 until a stopping criterion is met. In one embodiment, the stopping criterion may correspond to a precise match between the predicted and actual SEM profiles. Alternatively, in one embodiment, the stopping criterion may correspond to a matching error between the predicted and actual SEM profiles within a predetermined or selected threshold level. In this embodiment, calibration can be performed using a preset combination of resist parameters. The model is evaluated at various points on the parameter grid, and the result with the minimum error is selected. In this case, there is no "stopping criterion" itself, but rather a selection from various alternatives.

[0103] Note that, when the stopping criteria are met, the resist parameters of the resist model are calibrated in a manner that makes the resist model substantially independent of the SEM settings. That is, recognizing that perfect calibration may be practically unattainable, ideally, repeating experiments with different SEM voltages should only change the parameters of model 980. Therefore, the embodiments can provide the ability to use multiple SEM measurements under different processing conditions, which can provide additional calibration options for the resist model. In this regard, the resist parameters can further include VIR parameters as discussed above.

[0104] Figure 10 An exemplary flowchart illustrating the steps performed to verify a calibrated resist model according to an embodiment of the present invention is depicted.

[0105] The process of validating the calibrated resist model begins with obtaining a mask (step 1010) and illuminating an optical system (step 1020) to generate a simulated spatial image of another resist structure (step 1030).

[0106] Additionally, in step 1050, the resist profile of another resist structure under consideration is predicted using the calibrated values ​​of the resist parameters of the resist model (step 1040) and the simulated spatial image generated in step 1030.

[0107] Furthermore, in step 1055, the verification process obtains information about the actual resist structure acquired by a measurement device (e.g., a SEM device). For example, as described above, in one embodiment, a measurement of the width of the white stripe, as obtained by a CDSEM, can be obtained in step 1055. Based on the measured width of the white stripe, as obtained by the CDSEM, the predicted resist profile from step 1050, and the calibrated value of the SEM deviation parameter (step 1080), the verification process predicts the SEM profile of the resist structure in step 1060.

[0108] The verification process proceeds further to step 1070, where a query is performed to determine whether the predicted SEM profile from step 1060 matches the actual SEM profile (of the resist structure under consideration) as measured by CDSEM (step 1090). The process further proceeds to step 1095, where the root mean square error between the predicted and actual SEM profiles can be calculated to determine the validity of the calibrated model. It must be understood that a low value of the root mean square error calculated in step 1095 corresponds to an accurately calibrated resist model.

[0109] Figure 11 An exemplary flowchart illustrating the steps performed during source mask optimization (SMO) according to an embodiment of the present invention is shown.

[0110] The SMO optimization process begins by determining the initial parameter values ​​for the mask layout pattern (step 1110) and the optical illumination system parameters (step 1120). In one embodiment, the initial parameters of the optical illumination system include tuning and adjustment parameters such as the outer radius of the circular illumination area, the inner radius of the annular area, and the polar angles corresponding to each pole of the defined inner and outer radii. The mask layout pattern parameters may correspond to the phase shift associated with the mask or binary mask.

[0111] In step 1130, a spatial image is generated based on the mask layout pattern and the initial parameters of the optical illumination system. Furthermore, in step 1150, the optimization process predicts the resist profile based on the generated spatial image (step 1130) and the resist parameters of the resist model (step 1140). It must be understood that this can be achieved through... Figure 9 The calibration process outlined herein is used to initially calibrate the SMO process with the resist model in mind.

[0112] Additionally, the process proceeds to step 1160, where a query is performed to determine whether the predicted resist profile of step 1150 matches, for example, the actual profile designed by the wafer designer (step 1170).

[0113] In one embodiment, based on the degree of matching between the predicted resist profile and the actual profile in step 1150, the SMO process provides feedback to steps 1110 and 1120, respectively. Specifically, the feedback loop corresponds to the parameter calibration steps for the mask layout parameters and the optical illumination system parameters.

[0114] It must be understood that, as Figure 11 The SMO process outlined herein repeats the calibration steps (i.e., updating the parameters of the mask layout and optical illumination system) until a stopping criterion is met. In one embodiment, the stopping criterion may correspond to a precise match between the predicted resist profile and the actual profile, as designed by the wafer designer. Alternatively, in one embodiment, the stopping criterion may correspond to a matching error between the predicted and actual resist profiles within a predetermined threshold level. Furthermore, the SMO process may continue until the parameters of the mask layout and / or the optical illumination system are calibrated, until an optimization objective (e.g., a cost function) associated with the SMO is obtained. It must be understood that, as Figure 11 The SMO process outlined in this paper differs from typical source-mask optimization applications in that... Figure 11 The SMO (Stencil Occlusion Model) attempts to match the desired profile to a predicted resist profile that excludes SEM artifacts. Note that the predicted resist profile excludes SEM-induced artifacts because the resist parameters used to predict the resist profile are calibrated in a manner that incorporates SEM bias. Specifically, this is achieved through methods such as... Figure 9 The calibration process outlined herein is used to calibrate the resist parameters.

[0115] Figure 12 An exemplary flowchart illustrating the steps performed when calibrating resist sidewall parameters to predict the width of a white stripe according to an embodiment of the present invention is shown. By one embodiment, information obtained from SEM waveforms can be used to calibrate a 3D resist model. As described below, the predicted width of the white stripe can be used to indicate resist features with unique sidewall shapes. Therefore, as referenced... Figure 12 The outlined process can be used to indicate the presence of hot spots, which are resist features expected to print poorly, i.e., resist features with unusual print shapes.

[0116] Figure 12 The process begins with obtaining the parameters of the mask (step 1210) and the parameters of the illumination optical system (step 1220) to generate a simulated spatial image of the resist layer (step 1230).

[0117] Additionally, in step 1250, the resist profile of the resist structure is predicted using a set of calibrated resist parameters of the resist model (step 1240) and the spatial image generated in step 1230.

[0118] The process then proceeds to step 1260, where the width of the white stripe is predicted based on the spatial image (step 1230), the predicted resist profile (1250), and initial values ​​of the resist sidewall parameters (step 1280). In one embodiment, the resist sidewall parameters include at least the VIR of the resist layer, the line CD of the resist profile, and the slope of the spatial image.

[0119] Furthermore, through one aspect of the invention, the predicted width of the white stripe can be generated using only one sidewall parameter. Alternatively, through one aspect, the width of the white stripe can be predicted using any two sidewall parameters. Additionally, through one aspect, the width of the white stripe can be predicted using all three sidewall parameters (i.e., the VIR of the resist layer, the CD of the resist profile, and the slope of the spatial image).

[0120] After predicting the width of the white band, Figure 12 The process proceeds to step 1270, where a query is performed to determine whether the predicted width of the white band from step 1260 matches the measured white band obtained from the SEM device. Furthermore, based on the degree of matching between the predicted and measured widths of the white band, the calibration process provides feedback to step 1280. Specifically, the feedback loop corresponds to the parameter calibration step, where at least one resist sidewall parameter is updated in step 1280.

[0121] In addition, such as Figure 12The calibration process outlined herein repeats steps 1260, 1270, and 1280 until a stopping criterion is met. In one embodiment, the stopping criterion may correspond to a precise match between the predicted width and the measured width of the white stripe. Alternatively, in one embodiment, the stopping criterion may correspond to a matching error between the predicted width and the measured width of the white stripe being within a predetermined threshold level. As described below, Figure 12 The calibration process can be used to indicate resist features on a substrate that are expected to be printed in an unacceptable manner on the resist layer.

[0122] Figure 13 An exemplary flowchart illustrating the steps performed to detect unusual features of the resist layer (i.e., resist patterns expected to be printed on the substrate in an unacceptable manner).

[0123] Figure 13 The process begins with obtaining the parameters of the mask (step 1310) and the parameters of the illumination optical system (step 1320) to generate a simulated spatial image of the resist layer (step 1330).

[0124] Additionally, in step 1350, the resist profile of the resist structure is predicted using a set of calibrated resist parameters of the resist model (step 1340) and the spatial image generated in step 1330.

[0125] The process then moves to step 1360, where the width of a white stripe corresponding to a specific resist feature under consideration is predicted based on the spatial image (step 1330), the predicted resist profile (1350), and calibrated values ​​of the resist sidewall parameters (step 1370). In one embodiment, the resist sidewall parameters include the VIR of the resist layer, the CD of the resist profile, and the slope of the spatial image, wherein, by means of... Figure 12 The procedure outlined herein is used to calibrate at least one of the parameters in the resist sidewall parameters.

[0126] Based on the predicted width of the white stripe in step 1360, exotic resist printing features may be flagged in step 1380. Specifically, resist features expected to be poorly printed are flagged based on the predicted width of the white stripe. For example, by one embodiment, a corresponding resist feature may be flagged as unacceptably printed based on a large predicted white stripe width (i.e., a wide white stripe). It must be understood that information corresponding to the predicted width of the white stripe can be used to improve the efficiency of the etching model. The degree to which something is considered too wide will vary depending on the specific pattern being considered. For example, it may depend on the type of resist or typical linewidth of the pattern. In the specific case considered here, a white stripe wider than 18 nm may be considered too wide. Broadly speaking, a given process may include a selected threshold that defines an external constraint on acceptable feature sizes.

[0127] Figure 14 This is a block diagram illustrating one or more aspects of a computer system 100 performing the methods and processes disclosed herein. The computer system 100 includes a bus 102 or other communication mechanism for transmitting information and a processor 104 (or multiple processors 104 and 105) coupled to the bus 102 for processing information. The computer system 100 also includes a main memory 106, such as random access memory (RAM) or other dynamic storage device, coupled to the bus 102 for storing information and instructions to be executed by the processor 104. The main memory 106 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 104. The computer system 100 also includes a read-only memory (ROM) 108 or other static storage device coupled to the bus 102 for storing static information and instructions for the processor 104. A storage device 110 (such as a magnetic disk or optical disk) is provided and coupled to the bus 102 for storing information and instructions.

[0128] Computer system 100 can be connected via bus 102 to a display 112 for displaying information to a computer user, such as a cathode ray tube (CRT), flat panel display, or touch panel display. Input device 114, including alphanumeric keys and other keys, is connected to bus 102 for transmitting information and command selections to processor 104. Another type of user input device is a cursor controller 116, such as a mouse, trackball, or cursor direction keys, for transmitting directional information and command selections to processor 104 and for controlling cursor movement on display 112. Such input devices typically have two degrees of freedom on two axes (a first axis, e.g., x) and a second axis, e.g., y), allowing the device to specify a position in a plane. Touch panel (screen) displays can also be used as input devices.

[0129] According to one embodiment, portions of the process described herein may be executed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. Such instructions may be read into main memory 106 from another computer-readable medium, such as storage device 110. Execution of the instruction sequence contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multiprocessor arrangement may also be employed to execute the instruction sequence contained in main memory 106. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Therefore, the description herein is not limited to any particular combination of hardware circuitry and software.

[0130] As used herein, the term "computer-readable medium" refers to any medium that participates in providing instructions to processor 104 for execution. Such media can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical discs or magnetic disks, such as storage device 110. Volatile media include dynamic memory, such as main memory 106. Transmission media include coaxial cables, copper wires, and optical fibers, including lines containing bus 102. Transmission media can also take the form of acoustic or optical waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, any other magnetic media, CD-ROMs, DVDs, any other optical media, punched cards, paper tape, any other physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cartridges, carrier waves as described below, or any other media that can be read by a computer.

[0131] Various forms of computer-readable media may involve carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may be initially carried on the disk of a remote computer. The remote computer may load the instructions into its dynamic memory and transmit the instructions via a telephone line using a modem. A modem at the local end of computer system 100 may receive data over the telephone line and use an infrared transmitter to convert the data into an infrared signal. An infrared detector coupled to bus 102 may receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries the data to main memory 106, from which processor 104 fetches and executes the instructions. The instructions received by main memory 106 may optionally be stored on storage device 110 before or after execution by processor 104.

[0132] Computer system 100 also preferably includes a communication interface 118 coupled to bus 102. Communication interface 118 provides a bidirectional data communication connector to network link 120 connected to local area network 122. For example, communication interface 118 may be an Integrated Services Network (ISDN) card or modem to provide data communication connectivity to a corresponding type of telephone line. As another example, communication interface 118 may be a local area network (LAN) card to provide data communication connectivity to a compatible LAN. Wireless connectivity may also be implemented. In any such implementation, communication interface 118 transmits and receives electrical, electromagnetic, or optical signals carrying digital data streams representing various types of information.

[0133] Network link 120 typically provides data communication to other data devices via one or more networks. For example, network link 120 may provide a connection to host computer 124 or a connection to data equipment operated by Internet Service Provider (ISP) 126 via local area network 122. ISP 126, in turn, provides data communication services via a global packet data communication network (now commonly referred to as "the Internet" 128). Both local area network 122 and Internet 128 use electrical, electromagnetic, or optical signals carrying digital data streams. Signals via various networks and signals on network link 120 and via communication interface 118 are exemplary forms of carrier waves for transmitting information, carrying digital data to and from computer system 100.

[0134] Computer system 100 can send messages and receive data, including program code, via a network, network link 120, and communication interface 118. In an Internet example, server 130 can transmit program code requested by an application via the Internet 128, ISP 126, local area network 122, and communication interface 118. Such a downloaded application can provide processes such as those described herein. The received code can be executed by processor 104 upon receipt and / or stored in storage device 110 or other non-volatile memory for later execution. In this way, computer system 100 can obtain application code in carrier form.

[0135] Figure 15 An exemplary photolithography projection apparatus for use with the methods described herein is schematically depicted. The apparatus includes:

[0136] - An irradiation system IL, which is used to modulate the radiation beam B. In this specific case, the irradiation system also includes a radiation source SO;

[0137] - A first stage (e.g., a mask stage) MT, which is equipped with a patterning device holder for holding a patterning device MA (e.g., a mask), and connected to a first locator for accurately positioning the patterning device relative to the item PS.

[0138] - A second stage (substrate stage) WT, which has a substrate holder for holding a substrate W (e.g., a silicon wafer coated with resist) and is connected to a second positioner for accurately positioning the substrate relative to the project PS.

[0139] - A projection system (“lens”) PS (e.g., a refractive, reflective, or reflective-refractive optical system) for imaging a radiated portion of a patterning device MA onto a target portion C (e.g., comprising one or more dies) of a substrate W.

[0140] As described herein, the device is transmissive (i.e., has a transmissive mask). However, it can also typically be, for example, reflective (with a reflective mask). Alternatively, the device can use another patterning device as an alternative to the use of a classic mask; examples include programmable mirror arrays or LCD matrices.

[0141] A source SO (e.g., a mercury lamp or excimer laser) generates a radiation beam. This beam is fed into the irradiation system (irradiator) IL, either directly or after passing through an adjustment member such as a beam expander Ex. The irradiator IL may include an adjustment member AD for setting the outer radial range and / or inner radial range (typically referred to as σ_outer and σ_inner, respectively) of the intensity distribution in the beam. Additionally, the irradiator IL will typically include various other components, such as a beam accumulator IN and a condenser CO. Thus, the beam B irradiated onto the patterning device MA has the desired uniformity and intensity distribution in its cross-section.

[0142] It should be noted that, regarding Figure 15 Although the source SO can be inside the housing of the photolithography projection device (which is often the case when the source SO is, for example, a mercury lamp), the source SO can also be located away from the photolithography projection device, and the radiation beam generated by the source SO is guided to the device (e.g., by means of a suitable guide mirror); the latter case is often the case when the source SO is an excimer laser (e.g., emitting lasers based on KrF, ArF or F2).

[0143] The beam PB then intercepts the patterned device MA held on the patterning device stage MT. Having passed through the patterned device MA, the beam B is conveyed through the lens PL, which focuses the beam B onto the target portion C of the substrate W. The substrate stage WT can be precisely moved by means of a second positioning member (and an interferometric member IF) to, for example, position different target portions C within the path of the beam PB. Similarly, the first positioning member can be used, for example, to accurately position the patterned device MA relative to the path of the beam B, either after mechanical acquisition of the patterned device MA from the patterning device library or during scanning. Typically, methods not in use will be employed... Figure 15 The long-stroke module (coarse positioning) and short-stroke module (fine positioning) are clearly described in the text to realize the movement of the stage MT and WT. However, in the case of a wafer stepper (as opposed to a stepping scanning tool), the patterning stage MT may only be connected to the short-stroke actuator, or it may be fixed.

[0144] The tools described can be used in two different modes:

[0145] - In step mode, the patterning stage MT remains substantially fixed, and the entire patterning image is projected onto the target portion C in one go (i.e., a single "flash"). Then, the substrate stage WT is shifted in the x and / or y directions, allowing the beam PB to radiate different target portions C;

[0146] In scanning mode, the same principle applies, except that the given target portion C is not exposed in a single "flash." In practice, the patterning stage MT can move at a speed v in a given direction (the so-called "scanning direction," e.g., the y-direction) so that the projection beam B sweeps across the patterning image; simultaneously, the substrate stage WT moves synchronously at a speed V = Mv in the same or opposite direction, where M is the magnification of the lens PL (typically M = 1 / 4 or 1 / 5). This allows for the exposure of a relatively large target portion C without compromising resolution.

[0147] Figure 16 Another exemplary photolithography projection device 1000 that can be used in the methods described herein is schematically depicted.

[0148] The photolithography projection equipment 1000 includes:

[0149] -Source Collector Module SO

[0150] - Irradiation system (irradiator) IL, which is configured to modulate the radiation beam B (e.g., EUV radiation);

[0151] - A support structure (e.g., a mask stage) MT, which is configured to support a patterning device (e.g., a mask or a mask plate) MA and is connected to a first locator PM configured to accurately position the patterning device;

[0152] - A substrate stage (e.g., a wafer stage) WT, configured to hold a substrate (e.g., a wafer coated with resist) W, and connected to a second positioner PW configured to accurately position the substrate; and

[0153] - A projection system (e.g., a reflective projection system) PS, which is configured to project a pattern imparted to a radiation beam B onto a target portion C (e.g., comprising one or more dies) of a substrate W by a patterning device MA.

[0154] As depicted here, device 1000 is reflective (e.g., using a reflective mask). It should be noted that because most materials are absorptive in the EUV wavelength range, the mask can have a multilayer reflector comprising, for example, multiple stacks of molybdenum and silicon. In one example, the multilayer reflector has 40 pairs of molybdenum and silicon layers, each layer being a quarter wavelength thick. Smaller wavelengths can be produced using X-ray lithography. Since most materials are absorptive at both EUV and X-ray wavelengths, the thin pieces of patterned absorbing material on the patterned device morphology (e.g., a TaN absorber on top of the multilayer reflector) define where features will be printed (positive resist) or not printed (negative resist).

[0155] Reference Figure 16 The irradiator IL receives an extreme ultraviolet (EUV) radiation beam from the source collector module SO. Methods for generating EUV radiation include, but are not limited to, converting a material into a plasma state, the material having at least one element possessing one or more emission lines in the EUV range, such as xenon, lithium, or tin. In one such method (often referred to as laser-generated plasma (“LPP”)), plasma can be generated by radiating a fuel (such as material droplets, streams, or clusters having spectral emission elements) using a laser beam. The source collector module SO may include a laser ( Figure 16 As part of an EUV radiation system (not shown), the laser is used to provide a laser beam for exciting the fuel. The resulting plasma emits output radiation (e.g., EUV radiation), which is collected by a radiation collector housed in a source collector module. For example, when a CO2 laser is used to provide a laser beam for fuel excitation, the laser and the source collector module can be separate entities.

[0156] In these cases, the laser is not considered part of the photolithography apparatus, and a beam delivery system, including, for example, suitable guide mirrors and / or beam expanders, delivers the radiation beam from the laser to the source collector module. In other cases, such as when the source is a discharge-generated plasma EUV generator (often referred to as a DPP source), the source can be part of the source collector module.

[0157] An irradiator IL may include adjusters for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer radial range and / or inner radial range (often referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the pupil plane of the irradiator can be adjusted. Additionally, the irradiator IL may include various other components, such as faceted field mirror assemblies and faceted pupil mirror assemblies. The irradiator can be used to adjust the radiation beam to have a desired uniformity and intensity distribution in its cross-section.

[0158] A radiation beam B is incident on a patterning device (e.g., a mask) MA held on a support structure (e.g., a mask stage) MT and patterned by the patterning device. After being reflected from the patterning device (e.g., the mask) MA, the radiation beam B is transmitted through a projection system PS, which focuses the radiation beam B onto a target portion C of the substrate W. The substrate stage WT can be accurately moved by means of a second locator PW and a position sensor PS2 (e.g., an interferometer, a linear encoder, or a capacitive sensor) to position, for example, different target portions C in the path of the radiation beam B. Similarly, a first locator PM and another position sensor PS1 can be used to accurately position the patterning device (e.g., the mask) MA relative to the path of the radiation beam B. The patterning device (e.g., the mask) MA and the substrate W can be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2.

[0159] The described device 1000 can be used in at least one of the following modes:

[0160] 1. In step mode, the support structure (e.g., mask stage) MT and substrate stage WT remain substantially fixed while the entire pattern of the radiation beam is projected onto the target portion C in one (i.e., single static exposure). Then, the substrate stage WT is shifted in the X and / or Y directions, allowing different target portions C to be exposed.

[0161] 2. In scanning mode, while projecting the pattern imparted by the radiation beam onto the target portion C, the support structure (e.g., mask stage) MT and the substrate stage WT are scanned simultaneously (i.e., single dynamic exposure). The velocity and direction of the substrate stage WT relative to the support structure (e.g., mask stage) MT can be determined by the magnification (reduction) and image inversion characteristics of the projection system PS.

[0162] 3. In another mode, the support structure (e.g., mask stage) MT remains substantially fixed to hold the programmable patterning device, while the substrate stage WT moves or scans the pattern imparted by the radiation beam onto the target portion C. In this mode, typically a pulsed radiation source is used, and the programmable patterning device is updated as needed after each movement of the substrate stage WT or between successive radiation pulses during scanning. This mode of operation can be readily applied to maskless lithography utilizing programmable patterning devices, such as programmable mirror arrays of the type mentioned above.

[0163] Figure 17 The apparatus 1000 is shown in more detail, comprising a source collector module SO, an irradiation system IL, and a projection system PS. The source collector module SO is constructed and configured such that a vacuum environment can be maintained within a closed structure 220 of the source collector module SO. An EUV radiation emitting plasma 210 can be formed by a discharge-generated plasma source. EUV radiation can be generated from a gas or vapor (e.g., xenon gas, lithium vapor, or tin vapor), wherein an extremely hot plasma 210 is generated to emit radiation in the EUV range of the electromagnetic spectrum. For example, the extremely hot plasma 210 is generated by a discharge that induces at least partial ionization of the plasma. For efficient radiation generation, xenon, lithium, tin vapor, or any other suitable gas or vapor with a partial pressure of, for example, 10 Pa may be required. In an embodiment, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0164] Radiation emitted by thermal plasma 210 is transmitted from source cavity 211 to collector cavity 212 via an optional gas barrier or contaminant trap 230 (also referred to in some cases as a contaminant barrier or foil trap) positioned in or behind an opening in source cavity 211. Contaminant trap 230 may include a channel structure. Contaminant trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. As is known in the art, the contaminant trap or contaminant barrier 230 further indicated herein includes at least a channel structure.

[0165] Collector cavity 211 may include a radiation collector CO, which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation passing through the collector CO may be reflected by a grating spectral filter 240, which is to be focused along the optical axis indicated by the dotted dashed line "O" into a virtual source point IF. The virtual source point IF is commonly referred to as the intermediate focus, and the source collector module is configured such that the intermediate focus IF is located at or near the opening 221 in the enclosure structure 220. The virtual source point IF is an image of the radiative emission plasma 210.

[0166] Subsequently, the radiation passes through an illumination system IL, which may include a faceted field mirror assembly 22 and a faceted pupil mirror assembly 24, configured to provide a desired angular distribution of the radiation beam 21 at the patterning device MA and a desired uniformity of radiation intensity at the patterning device MA. After the radiation beam 21 is reflected at the patterning device MA held by the support structure MT, a patterned beam 26 is formed, and the patterned beam 26 is imaged by the projection system PS onto the substrate W held by the substrate stage WT via reflective elements 28 and 30.

[0167] The illumination optics unit IL and the projection system PS can typically contain more elements than are shown. Depending on the type of photolithography equipment, a grating spectral filter 240 may optionally be present. Additionally, more mirrors than are shown in the figures, for example, in the projection system PS, there may be more than [number missing]. Figure 17 The reflective element shown has 1 to 6 additional reflective elements.

[0168] like Figure 17 The collector optics CO described herein are depicted as a nested collector with grazing incidence reflectors 253, 254, and 255, and are used only as an example of a collector (or collector mirror). The grazing incidence reflectors 253, 254, and 255 are arranged axially symmetrically about the optical axis O, and this type of collector optics CO is preferably used in combination with a discharge-generating plasma source (often referred to as a DPP source).

[0169] Alternatively, the source collector module SO can be as follows: Figure 18 This is a portion of the LPP radiation system shown. The laser LA is configured to deposit laser energy onto a fuel such as xenon (Xe), tin (Sn), or lithium (Li), thereby generating a highly ionized plasma 210 with an electron temperature of tens of electron volts. High-energy radiation generated during the deexcitation and recombination of these ions is emitted from the plasma, collected by near-normal incident collector optics CO, and focused onto an opening 221 in the enclosure structure 220.

[0170] While specific references may be made to the manufacture of devices such as ICs in this invention, it should be clearly understood that the description herein has many other possible applications. For example, it can be used to manufacture integrated optical systems, guide and detection patterns for magnetic domain memory, liquid crystal display panels, thin-film magnetic heads, etc. Those skilled in the art will understand that, in the context of these alternative applications, any use of the terms “mask,” “wafer,” or “die” herein should be considered interchangeable with the more general terms “mask,” “substrate,” and “target portion,” respectively.

[0171] The embodiments can be further described using the following terms:

[0172] 1. A method for calibrating a resist model, the method comprising:

[0173] The modeled resist profile of the resist structure is generated based on the simulated spatial image of the resist structure and the parameters of the resist model.

[0174] Based on information about the actual resist structure obtained from the measurement device, the measurement profile of the resist structure is predicted using the modeled resist profile; and

[0175] The parameters of the resist model are adjusted based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measurement device.

[0176] 2. The method as described in item 1, wherein the information on the actual resist structure obtained by the measuring device corresponds to the width of a portion of the waveform generated by the measuring device.

[0177] 3. The method as described in item 2, wherein a portion of the waveform corresponds to the edge of the actual resist structure imaged by the measuring device.

[0178] 4. The method of any one of clauses 1 to 3, wherein the width of a portion of the waveform is measured at a predetermined threshold intensity level.

[0179] 5. The method of any one of clauses 1 to 4, wherein the predicted measurement profile of the resist structure is generated from the modeled resist profile based on parameters associated with the measurement device.

[0180] 6. The method as described in any one of clauses 1 to 5, further comprising:

[0181] The parameters of the measuring device are updated based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measuring device.

[0182] 7. The method of any one of clauses 1 to 6, wherein the measuring device is a scanning electron microscope.

[0183] 8. The method described in item 1 further includes:

[0184] The parameters of the mask layout and the light source are optimized based on the adjusted resist parameters of the resist model.

[0185] 9. The method described in item 1 further includes:

[0186] The measurement profile of another resist structure is predicted based on the adjusted parameters of the resist model.

[0187] The actual measurement profile of the other resist structure is obtained by the measuring device; and

[0188] The error is calculated by comparing the predicted measurement profile of another resist structure with the actual measurement profile of the other resist structure.

[0189] 10. An apparatus for calibrating a resist model, the apparatus comprising:

[0190] The processor is configured as

[0191] The modeled resist profile of the resist structure is generated based on the simulated spatial image of the resist structure and the parameters of the resist model.

[0192] Based on information about the actual resist structure obtained from the measurement device, the measurement profile of the resist structure is predicted using the modeled resist profile; and

[0193] The parameters of the resist model are adjusted based on a comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measurement device.

[0194] 11. The apparatus of claim 10, wherein the information on the actual resist structure obtained by the measuring device corresponds to the width of a portion of the waveform generated by the measuring device.

[0195] 12. The apparatus of claim 11, wherein a portion of the waveform corresponds to the edge of the actual resist structure imaged by the measuring device.

[0196] 13. The apparatus of any one of clauses 10 to 12, wherein the width of a portion of the waveform is measured at a predetermined threshold intensity level.

[0197] 14. The apparatus of any one of clauses 10 to 13, wherein the predicted measurement profile of the resist structure is generated from the modeled resist profile based on parameters associated with the measurement apparatus.

[0198] 15. The apparatus of any one of clauses 10 to 14, wherein the processor is further configured to:

[0199] The parameters of the measuring device are updated based on the comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure.

[0200] 16. The apparatus of any one of clauses 10 to 16, wherein the measuring device is a scanning electron microscope.

[0201] 17. The apparatus of claim 10, wherein the processor is further configured to:

[0202] The parameters of the mask layout and the light source are optimized based on the adjusted resist parameters of the resist model.

[0203] 18. The apparatus of claim 10, wherein the processor is further configured to:

[0204] The measurement profile of another resist structure is predicted based on the adjusted parameters of the resist model.

[0205] The actual measurement profile of the other resist structure is obtained by the measuring device; and

[0206] The error is calculated by comparing the predicted measurement profile of another resist structure with the actual measurement profile of the other resist structure.

[0207] 19. A non-transitory computer program product comprising machine-readable instructions for causing a processor to perform the method as described in any one of items 1 to 9.

[0208] 20. A system comprising:

[0209] Hardware processor; and

[0210] Non-transitory computer program products as described in clause 19.

[0211] 21. A method comprising:

[0212] At least based on a simulated spatial image of the resist structure, a modeled resist profile of the resist structure is generated;

[0213] Based on the modeled resist profile, the simulated spatial image, and at least one of a set of resist sidewall parameters associated with the resist structure, a measurement value is predicted corresponding to a portion of the waveform of the edge of the actual resist structure imaged by the measurement device; and

[0214] The at least one resist sidewall parameter is adjusted based on a comparison between a predicted measurement of a portion of the waveform and an actual measurement of a portion of the waveform corresponding to the edge of the actual resist structure imaged by the measuring device.

[0215] 22. The method of claim 21, wherein the predicted measurement of a portion of the waveform is the width of a portion of the waveform generated by the measuring device, the width being measured at a predetermined threshold intensity level.

[0216] 23. The method of claim 21, wherein the predicted measurement of a portion of the waveform generated by the measuring device is based on at least two of the set of resist sidewall parameters.

[0217] 24. The method of claim 21, wherein the set of resist sidewall parameters comprises three resist sidewall parameters, and the predicted measurement of a portion of the waveform generated by the measuring device is based on each of the set of resist sidewall parameters.

[0218] 25. The method as described in items 21 to 24, wherein the set of resist sidewall parameters includes a vertical strength range parameter, a critical distance linewidth parameter, and the slope of the spatial image parameters.

[0219] 26. The method of claim 25, wherein the vertical intensity range parameter is calculated as the difference between a first intensity of a first spatial image and a second intensity of a second spatial image, the first spatial image corresponding to a first position within the resist layer, and the second spatial image corresponding to a second position within the resist layer.

[0220] 27. The method of claim 25, wherein the first position is in the top third portion of the resist layer, and the second position is in the bottom third portion of the resist layer.

[0221] 28. The method of any one of clauses 26 to 27, wherein the first position is located 15 nanometers below the top surface of the resist layer, and the second position is located 75 nanometers below the top surface of the resist layer.

[0222] 29. The method described in clause 21 further includes:

[0223] The parameters of the mask layout and the light source are optimized based on the adjusted resist sidewall parameters.

[0224] 30. The method described in clause 21 further includes:

[0225] Based on a modeled resist profile of another resist structure, a simulated spatial image of another resist structure, and at least one adjusted resist sidewall parameter from the set of resist sidewall parameters, another measurement value is predicted corresponding to a portion of another waveform at the edge of another actual resist structure imaged by the measurement device; and

[0226] The etching quality of the edge of another actual resist structure is determined based on the predicted measurements of a portion of another waveform.

[0227] 31. A non-transitory computer program product comprising machine-readable instructions for causing a processor to perform the method as described in any one of items 21 to 30.

[0228] 32. A system comprising

[0229] Hardware processor; and

[0230] Such as non-transitory computer program products as in clause 31.

[0231] 33. The method of any one of clauses 1 to 9, wherein the predicted measurement profile and the actual measurement profile are parameterized, and the parameterization of these profiles is used in the comparison.

[0232] 34. The apparatus of any one of clauses 10 to 18, wherein the predicted measurement profile and the actual measurement profile are parameterized, and the parameterization of these profiles is used in the comparison.

[0233] It should be noted that the terms "mask," "patterning plate," and "patterning apparatus" are used interchangeably in this invention. Furthermore, those skilled in the art will recognize that, particularly in the context of lithography simulation / optimization, the terms "mask" / "patterning apparatus" and "design layout" are used interchangeably, because in lithography simulation / optimization, a physical patterning apparatus is not necessarily used, but a design layout can be used to represent a physical patterning apparatus.

[0234] In this document, the terms “radiation” and “beam” are used to cover all types of electromagnetic radiation, including ultraviolet radiation (e.g., wavelengths of 365 nm, 248 nm, 193 nm, 157 nm, or 126 nm) and extreme ultraviolet radiation (EUV) (e.g., wavelengths in the range of 5–20 nm).

[0235] As used herein, the terms “optimize” and “optimize” mean adjusting the lithography projection equipment and / or patterning process to give the results and / or processing of the patterning process (such as lithography) more desirable characteristics, such as higher projection accuracy of the design layout on the substrate, a larger processing window, etc. The term “optimize” does not necessarily require the results and / or processing of the lithography to have the most desirable characteristics, such as the highest projection accuracy of the design layout on the substrate, the largest processing window, etc.

[0236] The patterning devices mentioned above include, or can form, design layouts. Design layouts can be generated using computer-aided design (CAD) programs, a process often referred to as electronic design automation (EDA). Most CAD programs follow a predetermined set of design rules to produce functional design layouts / patterned devices. These rules are set by processing and design constraints. For example, design rules define the space tolerances between circuit devices (such as gates, capacitors, etc.) to ensure that the circuit devices or lines do not interact with each other in an undesirable manner. Design rule constraints are often referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the minimum width of a line or via, or the minimum space between two lines or two vias. Therefore, CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design (via patterning devices) on a substrate.

[0237] As used herein, the terms “mask” or “patterning device” can be broadly interpreted as any general patterning device that can be used to impart a patterned cross-section to an incident radiation beam, the patterned cross-section corresponding to a pattern to be generated in a target portion of a substrate; the term “optical valve” may also be used in this context. Examples of such patterning devices, besides classic masks (transmissive or reflective, binary, phase-shifting, hybrid, etc.), include programmable mirror arrays and programmable LCD arrays.

[0238] The concepts disclosed herein can simulate or mathematically model any patterning process and are particularly applicable to imaging techniques capable of producing increasingly shorter wavelengths. Examples of such imaging techniques already in use include extreme ultraviolet (EUV) and DUV lithography, which can generate wavelengths of 193 nm using ArF lasers and / or 157 nm using fluorine lasers. Furthermore, EUV lithography can generate wavelengths in the range of approximately 5 nm to approximately 20 nm by using, for example, synchrotrons or by using high-energy electrons to strike a material (solid or plasma), thereby producing photons within this range.

[0239] While the concepts disclosed herein can be used for patterning processes involving imaging on substrates such as silicon wafers, it should be understood that the disclosed concepts can be used with any type of lithography imaging system, such as lithography imaging systems used for imaging on substrates other than silicon wafers.

[0240] In the block diagrams, although the illustrated components are depicted as discrete functional blocks, the embodiments are not limited to systems in which the functionality described herein is organized as shown. The functionality provided by each of the plurality of components may be provided by software or hardware modules organized in a manner different from that depicted herein, such as being mixed, combined, copied, disassembled, distributed (e.g., within a data center or by region), or otherwise organized differently. The functionality described herein may be provided by one or more processors of one or more computers executing program code stored on a tangible, non-transitory machine-readable medium. In some cases, a third-party content delivery network may have control over some or all of the information transmitted via the network; in such cases, information (e.g., content) may be provided by sending instructions to retrieve it from the content delivery network, provided that information is allegedly supplied or otherwise provided.

[0241] Unless otherwise specifically stated, it will be understood from the discussion that in this specification, the use of terms such as “processing,” “calculation,” “operation,” “determine,” or similar terms refers to the actions or processes of a particular device such as a dedicated computer or similar dedicated electronic processing / computing apparatus.

[0242] Readers should understand that this application describes several inventions. Instead of separating these inventions into multiple independent patent applications, they have been grouped into a single document because their related subject matter is economically applicable in practice. However, the dissimilar advantages and aspects of these inventions should not be combined. In some cases, embodiments resolve all the disadvantages mentioned herein, but it should be understood that these inventions are independently useful; and some embodiments resolve only a subset of these problems or provide other unmentioned benefits that would be obvious to those skilled in the art upon review of this document. Due to cost constraints, some inventions disclosed herein may not be claimed at present, but may be claimed in subsequent applications (such as successive applications or by amending the present claims). Similarly, due to space limitations, the abstract and summary section of this document should not be considered an exhaustive list containing all such inventions or all aspects of them.

[0243] It should be understood that this specification and drawings are not intended to limit the invention to the specific forms disclosed, but rather are intended to cover all variations, equivalents and alternatives that fall within the spirit and scope of the invention as defined by the appended claims.

[0244] In view of this specification, variations and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art. Therefore, this specification and the accompanying drawings should be understood as illustrative only and for the purpose of teaching those skilled in the art the general manner of practicing the invention. It should be understood that the forms of the invention shown and described herein should be considered as examples of embodiments. Elements and materials may be substituted for those described and illustrated herein, some parts and procedures may be reversed or omitted, certain features may be utilized independently, and embodiments or features of embodiments may be combined, as will be apparent to those skilled in the art upon obtaining the benefits of this specification. Changes may be made to the elements described herein without departing from the spirit and scope of the invention as set forth in the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of this specification.

[0245] As used herein, the word “may” is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). The word “comprising” and similar words mean including but not limited to. As used herein, the singular forms “a” and “the” include multiple references unless expressly indicated otherwise. Thus, for example, reference to “an element” includes a combination of two or more elements, although other terms and phrases such as “one or more” may be used for one or more elements. Unless otherwise indicated, the term “or” is non-exclusive, i.e., encompasses both “and” and “or”. Terms describing conditional relationships, such as “in response to X and Y,” “Y after X,” “if X, then Y,” “Y when X,” etc., encompass causal relationships, where the premise is a necessary causal condition, the premise is a sufficient causal condition, or the premise is a contributing causal condition to the result; for example, “state X occurs after condition Y is obtained” is common to “X occurs only after Y” and “X occurs after Y and Z.” These conditional relationships are not limited to results obtained immediately by following the premises, as some results may be delayed; and in a conditional statement, the premise is linked to its result, for example, the premise relates to the probability of the result occurring. Unless otherwise specified, a statement that multiple traits or functions are mapped to multiple objects (e.g., one or more processors performing steps A, B, C, and D) covers both cases where all traits or functions are mapped to all objects and cases where a subset of traits or functions is mapped to a subset of traits or functions (e.g., all processors each perform steps A through D, and where processor 1 performs step A, processor 2 performs a portion of steps B and C, and processor 3 performs a portion of step C and step D). Additionally, unless otherwise indicated, a statement that a value or action is “based on” another condition or value covers both cases where the condition or value is a single factor and cases where the condition or value is one of multiple factors. Unless otherwise indicated, a statement that “every” instance of a set has a certain property should not be construed as excluding cases where some other identical or similar parts of a larger set do not have that property; that is, “every” does not necessarily mean “everyone.” References to selection from a range include the endpoints of that range.

[0246] In the above description, any program, description, or block in the flowchart should be understood as representing a module, fragment, or portion of program code, which includes one or more executable instructions for implementing a particular logical function or step in the program, and alternative implementations are included within the scope of exemplary embodiments of the present invention, wherein functionality may depend on the functionality involved and may not be performed in the order shown or discussed, including substantially simultaneously or in reverse order, as will be understood by those skilled in the art.

[0247] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel methods, apparatuses, and systems described herein can be embodied in many other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the methods, apparatuses, and systems described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or variations that fall within the scope and spirit of the invention.

Claims

1. A method for calibrating a resist model, comprising: At least based on a simulated spatial image of the resist structure, a modeled resist profile of the resist structure is generated; Based on the modeled resist profile, the simulated spatial image, and at least one of a set of resist sidewall parameters associated with the resist structure, a measurement value is predicted corresponding to a portion of the waveform of the edge of the actual resist structure imaged by the measurement device. as well as The at least one resist sidewall parameter is adjusted based on a comparison between a predicted measurement of a portion of the waveform and an actual measurement of a portion of the waveform corresponding to the edge of the actual resist structure imaged by the measuring device.

2. The method as described in claim 1, wherein, The predicted measurement of a portion of the waveform is the width of a portion of the waveform generated by the measuring device, which is measured at a predetermined threshold intensity level.

3. The method as described in claim 1, wherein, The predicted measurement value of a portion of the waveform generated by the measuring device is based on at least two of the set of resist sidewall parameters.

4. The method of claim 1, wherein, The set of resist sidewall parameters includes three resist sidewall parameters, and the predicted measurement value of a portion of the waveform generated by the measuring device is based on each of the resist sidewall parameters in the set of resist sidewall parameters.

5. The method according to any one of claims 1 to 4, wherein, The set of resist sidewall parameters includes vertical strength range parameters, critical distance linewidth parameters, and the slope of the spatial image parameters.

6. The method of claim 5, wherein, The vertical intensity range parameter is calculated as the difference between a first intensity of a first spatial image and a second intensity of a second spatial image, the first spatial image corresponding to a first position within the resist layer, and the second spatial image corresponding to a second position within the resist layer.

7. The method of claim 6, wherein, The first position is in the top third portion of the resist layer, and the second position is in the bottom third portion of the resist layer.

8. The method according to any one of claims 6 to 7, wherein, The first position is located 15 nanometers below the top surface of the resist layer, and the second position is located 75 nanometers below the top surface of the resist layer.

9. The method of claim 1, further comprising: The parameters of the mask layout and the light source are optimized based on the adjusted resist sidewall parameters.

10. The method of claim 1, further comprising: Based on a modeled resist profile of another resist structure, a simulated spatial image of another resist structure, and at least one adjusted resist sidewall parameter from the set of resist sidewall parameters, another measurement value is predicted corresponding to a portion of another waveform at the edge of another actual resist structure imaged by the measurement device; and The etching quality of the edge of another actual resist structure is determined based on the predicted measurements of a portion of another waveform.

11. A non-transitory computer program product comprising machine-readable instructions for causing a processor to perform the method as described in any one of claims 1 to 10.

12. A system for calibrating a resist model, comprising: Hardware processor; and The non-transitory computer program product as described in claim 11.

13. The method according to any one of claims 1 to 9, wherein, The predicted measurement profile and the actual measurement profile are parameterized, and the parameterization of these profiles is used in the comparison.

14. An apparatus for calibrating a resist model, the apparatus comprising: The processor is configured as The modeled resist profile of the resist structure is generated based on the simulated spatial image of the resist structure and the parameters of the resist model. Based on the information of the actual measured profile of the actual resist structure obtained by the measuring device, the measured profile of the resist structure is predicted by the modeled resist profile. as well as The parameters of the resist model are adjusted based on the comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure obtained by the measurement device. Specifically, the predicted measurement profile and the actual measurement profile are parameterized, and the parameterization of these profiles is used in the comparison.

15. The apparatus according to claim 14, wherein, The actual measured profile information of the actual resist structure obtained by the measuring device corresponds to the width of a portion of the waveform generated by the measuring device.

16. The apparatus according to claim 15, wherein, A portion of the waveform corresponds to the edge of the actual resist structure imaged by the measuring device.

17. The apparatus according to claim 15, wherein, The width of a portion of the waveform is measured at a predetermined threshold intensity level.

18. The apparatus according to any one of claims 14 to 16, wherein, The predicted measurement profile of the resist structure is generated from the modeled resist profile based on parameters associated with the measurement device.

19. The apparatus according to any one of claims 14 to 16, wherein, The processor is further configured to: The parameters of the measuring device are updated based on the comparison between the predicted measurement profile and the actual measurement profile of the actual resist structure.

20. The apparatus according to any one of claims 14 to 16, wherein, The measuring device is a scanning electron microscope.

21. The apparatus according to claim 14, wherein, The processor is further configured to: The parameters of the mask layout and the light source are optimized based on the adjusted resist parameters of the resist model.

22. The apparatus according to claim 14, wherein, The processor is further configured to: The measurement profile of another resist structure is predicted based on the adjusted parameters of the resist model. The actual measurement profile of the other resist structure is obtained by the measuring device; as well as The error is calculated by comparing the predicted measurement profile of another resist structure with the actual measurement profile of the other resist structure.

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