A low voltage fully integrated low dropout linear regulator

Abstract

The application discloses a low-voltage fully integrated low-dropout linear voltage regulator, which comprises an error amplifier and an auxiliary operational amplifier A1; the auxiliary operational amplifier A1 comprises a PMOS tube P4, a PMOS tube P5, a current source IB2 and a current source IB3; the gate of the PMOS tube P4 is connected with the gate of the PMOS tube P5; and the gates of the PMOS tube P4 and the PMOS tube P5 are connected with the drain of the PMOS tube P4. The drain of the PMOS tube P4 is connected with the output end of the current source IB2, and the output end of the current source IB2 is grounded; under the action of the auxiliary operational amplifier A1, the PMOS tube P2 can maintain a high enough output impedance even when the drain-source voltage drop is very low due to full load, so that excellent voltage stabilizing performance can be obtained at a low voltage.

Description

Technical Field

[0001] This invention relates to the field of voltage regulators, and more specifically, to a low-voltage fully integrated low-dropout linear voltage regulator. Background Technology

[0002] A low-dropout (LDO) linear regulator, commonly abbreviated as LDO, is a circuit module that provides a clean and stable voltage source. Fully integrated, on the other hand, requires all its components to be implemented on-chip to power the system-on-a-chip (SoC).

[0003] Traditional LDO circuit architectures typically use large external capacitors in the μF range at the output to achieve fast transient response under sudden load changes. However, in SoC systems, for ease of on-chip integration, the output capacitors of LDOs are usually built-in. The capacitance values ​​that can be implemented on-chip are generally small, typically in the pF range; moreover, chip area is also a significant design constraint, and sometimes no additional output capacitors are added. This leads to a deterioration in the load transient response of the LDO. To improve load transient response performance, suppress output overshoot voltage, and select appropriate frequency compensation schemes to stabilize the loop, LDO circuits often require additional complex circuitry to control the charging and discharging of the output power transistor's gate. These additional circuits often mean more current branches, inevitably increasing the LDO's quiescent current.

[0004] Low quiescent current is a fundamental requirement for linear regulators (LDOs), referring to the current consumed by the LDO itself when the external load current is zero. This includes the operating current of circuits such as the reference voltage source, error amplifier, and output voltage divider resistors. Quiescent current is determined by the topology, input voltage, and temperature.

[0005] To extend the operating time of battery-powered systems, SOC systems generally require low power consumption in standby mode. This invention consumes only 4.6μA of static current, meeting the low power consumption requirements of SOC systems.

[0006] Currently, the core voltage of a System-on-a-Chip (SoC) using advanced processes is only 0.9V, while the input voltage of an LDO (Low Voltage Regulator) is typically only 1.1V to ensure sufficiently high power efficiency. Furthermore, to ensure the stability and fast response of fully integrated LDOs, intrinsic NMOS transistors with threshold voltages close to 0V are generally used for power transmission. Even so, this still presents significant challenges to the design of the error amplifier under full load current. Due to the limited supply voltage, a differential amplifier with a current mirror as an active load (i.e., a five-MOSFET amplifier) ​​is almost always the necessary structural choice for the error amplifier in low-supply-voltage fully integrated LDOs. Because the output impedance of MOSFETs is severely degraded under advanced CMOS processes, their intrinsic gain is only about 20dB, and it will be even lower when the drain-source voltage drop drops to 200mV. Under full load, the output voltage margin of the error amplifier is further compressed, and its output PMOS transistor is likely to approach the linear region, further reducing the gain it can provide. Summary of the Invention

[0007] To address at least one of the aforementioned technical problems, this invention proposes a low-voltage fully integrated low-dropout linear regulator.

[0008] Linear regulators, commonly known as voltage sources, have a certain load current supply capability. They provide a stable output voltage when the load current does not exceed their design range, and voltage fluctuations caused by load changes quickly decay to within acceptable limits. Since their value lies in providing power to the load, their own current consumption must be sufficiently low to improve energy efficiency.

[0009] The first aspect of this invention provides a low-voltage fully integrated low-dropout linear regulator, comprising: an error amplifier based on an auxiliary operational amplifier A1, a power transmission transistor, and a voltage divider network; characterized in that,

[0010] The error amplifier includes multiple P-type MOS transistors and multiple N-type MOS transistors. The multiple P-type MOS transistors are designated as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, and PMOS transistor P5, respectively; the multiple N-type MOS transistors are designated as NMOS transistor N1, NMOS transistor N2, and NMOS transistor N3, respectively.

[0011] The non-inverting input terminal of the auxiliary operational amplifier A1 is connected to the drain of the PMOS transistor P2, the inverting input terminal of the auxiliary operational amplifier A1 is connected to the drain of the PMOS transistor P1, and the output terminal of the auxiliary operational amplifier A1 is connected to the gate of the PMOS transistor P3.

[0012] The source of PMOS transistor P1 is connected to the source of PMOS transistor P2, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2, the drain of PMOS transistor P1 is connected to the source of PMOS transistor P3, the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N1, the source of NMOS transistor N1 is connected to the source of NMOS transistor N2, the drain of NMOS transistor N2 is connected to the source of NMOS transistor N3, and the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P2.

[0013] The power transmission transistor is denoted as MOS transistor MP. The drain of MOS transistor MP is connected to the source of PMOS transistor P2, and the gate of MOS transistor MP is connected to the drain of PMOS transistor P2.

[0014] The voltage divider network includes resistors Rf1 and Rf2. The source of the MOS transistor MP is connected to one end of resistor Rf1, the other end of resistor Rf1 is connected to one end of resistor Rf2, and the other end of resistor Rf2 is connected to the output terminal of current source IB1 and grounded.

[0015] Based on the virtual short characteristic of the auxiliary operational amplifier A1, the auxiliary operational amplifier A1 clamps the drain voltage of PMOS transistors P1 and P2, making the potentials at the two points equal, thus achieving the equality of the source and drain voltages of PMOS transistors P1 and P2.

[0016] In a preferred embodiment of the present invention, the source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to the input voltage V. in .

[0017] In a preferred embodiment of the present invention, a current source IB1 is further included, wherein the gate of the NMOS transistor N1 is connected to a reference voltage V. ref The source of NMOS transistor N1 is connected to the source of NMOS transistor N1, and together they are connected to the output terminal of current source IB1.

[0018] In a preferred embodiment of the present invention, the auxiliary operational amplifier A1 includes PMOS transistors P4 and P5, current source IB2 and current source IB3. The gate of PMOS transistor P4 is connected to the gate of PMOS transistor P5, the gates of PMOS transistors P4 and P5 are connected together to the drain of PMOS transistor P4, and the drain of PMOS transistor P4 is connected to the output terminal of current source IB2.

[0019] In a preferred embodiment of the present invention, the source of PMOS transistor P5 is connected to the drain of PMOS transistor P2, the drain of PMOS transistor P5 is connected to the output terminal of current source IB3, the gate of PMOS transistor P3 is connected to the drain of PMOS transistor P5, and the source of PMOS transistor P5 is connected to the drain of PMOS transistor P2.

[0020] In a preferred embodiment of the present invention, the source of the MOS transistor MP is connected to the voltage output V. out .

[0021] The technical solution of the present invention has the following advantages compared with the prior art:

[0022] 1. By utilizing the virtual short characteristic of the operational amplifier, A1 clamps the drain voltages of P1 and P2, making the potentials at the two points equal and ensuring that the currents of P1 and P2 are equal. Since the changes in the drain voltages of P1 and P2 are insufficient to force P3 into the linear region, the change in the drain voltage of P3 is very small. Therefore, the current flowing through P3 and P1 remains essentially constant. Due to the current mirror relationship between P1 and P2, as long as the drain voltage of P2 meets the above constraints, the current flowing through P2 is also essentially constant, resulting in a higher output impedance. Therefore, the error amplifier in this invention can maintain a sufficiently high voltage gain even at a 1.1V power supply voltage, which means better load regulation capability.

[0023] 2. The power transfer transistor (MP) uses a native-NMOS. This type of NMOS transistor has a threshold voltage close to 0, which effectively reduces the voltage drop across the power transfer transistor. Traditional enhancement-type NMOS transistors have a larger threshold voltage, resulting in a large voltage drop across the power transfer transistor and low LDO efficiency. If used in conjunction with a charge pump or DC-DC converter, it will introduce large ripple. Using a native-NMOS as the power transfer transistor achieves a lower voltage drop while simplifying the circuit structure and eliminating the need for an additional power supply to the error amplifier; at the same time, the power consumption of the error amplifier is also reduced.

[0024] 3. This invention consumes only 4.6μA of static current, meeting the low power consumption requirements of SOC systems.

[0025] 4. This invention does not require additional compensation capacitors and Qualcomm network capacitors, and will not increase costs due to the large area occupied by on-chip capacitors. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is the overall circuit diagram of the LDO without external capacitors in this embodiment of the invention;

[0028] Figure 2 This is a specific implementation of the auxiliary operational amplifier A1 in this embodiment of the invention;

[0029] Figure 3 This is the undershoot response of the output voltage when the load current switches from 100μA to 10mA within 1ns in an embodiment of the present invention;

[0030] Figure 4 This is the overshoot response of the output voltage when the load current switches from 10mA to 100μA within 1ns in an embodiment of the present invention;

[0031] Figure 5 This is a linear adjustment rate curve diagram of an embodiment of the present invention;

[0032] Figure 6 This is a load regulation rate curve diagram according to an embodiment of the present invention.

[0033] Figure 7 This is a power suppression curve diagram of an embodiment of the present invention. Detailed Implementation

[0034] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0036] Example 1

[0037] See Figure 1-7 As shown, this invention proposes a low-voltage fully integrated low-dropout linear regulator, comprising: an error amplifier based on an auxiliary operational amplifier A1, a power transmission transistor, and a voltage divider network;

[0038] The error amplifier includes multiple P-type MOS transistors and multiple N-type MOS transistors. The multiple P-type MOS transistors are designated as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, and PMOS transistor P5, respectively; the multiple N-type MOS transistors are designated as NMOS transistor N1, NMOS transistor N2, and NMOS transistor N3, respectively.

[0039] The non-inverting input of auxiliary operational amplifier A1 is connected to the drain of PMOS transistor P2, the inverting input of auxiliary operational amplifier A1 is connected to the drain of PMOS transistor P1, and the output of auxiliary operational amplifier A1 is connected to the gate of PMOS transistor P3.

[0040] The source of PMOS transistor P1 is connected to the source of PMOS transistor P2, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2, the drain of PMOS transistor P1 is connected to the source of PMOS transistor P3, the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N1, the source of NMOS transistor N1 is connected to the source of NMOS transistor N2, the drain of NMOS transistor N2 is connected to the source of NMOS transistor N3, and the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P2.

[0041] The power transmission transistor is denoted as MOS transistor MP. The drain of MOS transistor MP is connected to the source of PMOS transistor P2, and the gate of MOS transistor MP is connected to the drain of PMOS transistor P2.

[0042] The voltage divider network includes resistors Rf1 and Rf2. The source of MOSFET MP is connected to one end of resistor Rf1, and the other end of resistor Rf1 is connected to one end of resistor Rf2. The other end of resistor Rf2 is connected to the output of current source IB1 and grounded.

[0043] Based on the virtual short characteristic of the auxiliary operational amplifier A1, the auxiliary operational amplifier A1 clamps the drain voltage of PMOS transistors P1 and P2, making the potentials at the two points equal, thus achieving the equality of the source and drain voltages of PMOS transistors P1 and P2.

[0044] This application utilizes the virtual short characteristic of the operational amplifier (op-amp) to clamp the drain voltages of P1 and P2 using A1, ensuring that the potentials at the two points are equal and thus guaranteeing equal currents in P1 and P2. When the changes in the drain voltages of P1 and P2 are insufficient to force P3 into the linear region, the change in the drain voltage of P3 is very small. Therefore, the current flowing through P3 and P1 remains essentially constant. Due to the current mirror relationship between P1 and P2, as long as the drain voltage of P2 meets the above constraints, the current flowing through P2 is also essentially constant, resulting in a higher output impedance. Therefore, the error amplifier in this invention can maintain a sufficiently high voltage gain even at a 1.1V power supply voltage, which translates to better load regulation capability.

[0045] Specifically, transistors P1, P2, P3, P4, P5, N1, N2, N3 and current sources IB1, IB2, IB3 constitute the error amplifier of this invention. P4, P5, IB2, IB3 constitute the auxiliary operational amplifier A1. Based on the virtual short characteristic of the operational amplifier, A1 clamps the drain voltages of P1 and P2, making the potentials at the two points equal. When a small signal v is applied to the output of the error amplifier... x Approximately the same small change will also appear at the drain of transistor P1, and at the same time, there will be an even smaller small voltage change (V) at the gates of transistors P1 and P2. g This is because the gate voltage has a much stronger control over the channel current compared to the drain voltage. According to the law of current conservation, the following equation can be obtained:

[0046] v x / r dsP1 +g mP1 v g +v g / r dsN1 =0 (1)

[0047]

[0048] Also affected by v g The small-signal voltage V at the output terminal (i.e., its drain terminal) of the P2 transistor is affected. x The response current under these conditions can be expressed as:

[0049] i x =v x / r dsP2 +v x / (g mN3 r dsN3 r dsN2 )+g mP2 v g (3)

[0050] Therefore, from equations (2) and (3), the output impedance of the error amplifier of the present invention can be obtained as:

[0051]

[0052] r dsP1 r dsP2 r dsN1 r dsN2 r dsN3 These represent the output impedances of transistors P1, P2, N1, N2, and N3, respectively. mP1 g mp2 g mN3 These represent the transconductance of transistors P1, P2, and N3, respectively.

[0053] As can be seen, the error amplifier of the present invention achieves a significant increase in output impedance without the need for stacked MOS transistors, thereby enabling higher gain.

[0054] More importantly, the P2 transistor in this invention does not rely on full saturation to maintain high output impedance like a traditional MOSFET; in other words, the P2 transistor in this invention does not require its gate to have a much stronger control over the channel current than its drain. In short, as long as there is a good match between P1 and P2 (r... dsP1 =r dsP2 And g mP1 =g mp2 Furthermore, the auxiliary amplifier A1 can function normally, and even if the P2 transistor is squeezed into the linear region, it can still maintain a considerable output impedance.

[0055] The source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to the input voltage V. in .

[0056] The gate connection reference voltage V of NMOS transistor N1 ref The source of NMOS transistor N1 is connected to the source of NMOS transistor N1, and together they are connected to the output terminal of current source IB1, which is grounded.

[0057] Furthermore, the drain of the MOS transistor MP is connected to the source of the PMOS transistor P2, and the gate of the MOS transistor MP is connected to the drain of the PMOS transistor P2.

[0058] Furthermore, the voltage divider network includes resistors Rf1 and Rf2. The source of MOSFET MP is connected to one end of resistor Rf1, and the other end of resistor Rf1 is connected to one end of resistor Rf2. The other end of resistor Rf2 is connected to the output terminal of current source IB1 and grounded. The source of MOSFET MP is connected to the voltage output V. out .

[0059] Furthermore, in this invention, P1 and P2 do not rely on long channel length to maintain output impedance. On the contrary, smaller P1 and P2 tubes are beneficial to increasing the bandwidth of the loop where the auxiliary amplifier A1 is located, which better ensures the normal operation of A1. Of course, the negative impact of size reduction on mismatch must also be taken into account.

[0060] This invention effectively solves the problem of insufficient gain in traditional five-transistor operational amplifiers at lower power supply voltages, thus achieving higher adjustment accuracy, load regulation, and other performance characteristics.

[0061] By utilizing the virtual short characteristic of the op-amp, A1 clamps the drain voltages of P1 and P2, making the potentials at the two points equal. This reduces the impact of changes in the drain voltage of P3 on the source voltage of P3, resulting in a more constant current through P3 and a higher output impedance.

[0062] The power transfer transistor (MP) uses a native-NMOS. A native MOS is a transistor with a threshold voltage close to zero, essentially a power dissipator. When used in an LDO source follower, it effectively reduces drop-voltage. The near-zero threshold voltage of this type of NMOS transistor significantly reduces the voltage drop across the power transfer transistor. Traditional enhancement-mode NMOS transistors have a larger threshold voltage, resulting in a large voltage drop across the power transfer transistor and low LDO efficiency. When used with a charge pump or DC-DC converter, they can introduce significant ripple. Using a native-NMOS as the power transfer transistor achieves a lower voltage drop while simplifying the circuit structure and eliminating the need for an external supply voltage.

[0063] This invention consumes only 4.6μA of static current, meeting the low power consumption requirements of SOC systems. This invention does not require additional compensation capacitors and high-pass network capacitors, and will not increase costs due to the large area occupied by on-chip capacitors.

[0064] In the diagram, the linear regulation rate refers to the effect of changes in the input voltage of the regulator on changes in the output voltage. It is generally measured by the effect of DC changes, and the smaller the rate, the better the performance. Its unit is usually mV / V.

[0065] Furthermore, Figure 5 The present invention was compared with the traditional scheme of using a basic five-transistor OTA error amplifier under no-load and 4mA load conditions. When the input voltage is 1.1V and the output voltage is 0.9V, the linear regulation of the traditional scheme under no-load and 4mA load is 3.1mV / V and 4.1mV / V, respectively, while that of the present invention is only 0.48mV / V and 0.6mV / V, respectively.

[0066] Load regulation: its unit is mV / A. It is the effect of changes in the load current of the voltage regulator on changes in the output voltage, and is generally measured by the effect of DC changes (changes in steady-state value).

[0067] Furthermore, such as Figure 6 As shown, a comparison was made with the traditional scheme using a basic five-transistor OTA error amplifier under no-load and 4mA load conditions. With an input voltage of 1.1V and an output voltage of 0.9V, the load regulation of the traditional scheme was 153.8mV / A, while that of this invention was only 3mV / A.

[0068] Settlement time: The time required for the output voltage of the regulator to recover to near its steady-state value when the load changes.

[0069] Load current range: The regulator must output voltage normally and remain stable when the load current is 0. When the load current exceeds the maximum value, the regulator can no longer maintain the set output voltage, which is generally manifested as a drop in output voltage (because the error amplifier enters the saturation region at this time, and the regulation capability decreases). The area between 0 and this maximum load current is the load current range.

[0070] like Figure 7 As shown, a comparison was made with the traditional scheme using a basic five-transistor OTA error amplifier under no-load and 4mA load conditions. It can be seen that power supply rejection in both the low-frequency and high-frequency ranges is improved, and these improvements in voltage regulation performance are due to the increase in the gain of the error amplifier.

[0071] The total quiescent power dissipation of an LDO is calculated by multiplying the quiescent current by the input voltage. The quiescent current includes the quiescent power dissipation of the reference circuit, feedback resistor network, error amplifier bias current, and other auxiliary circuit modules. A lower total quiescent power dissipation results in higher efficiency. However, increasing the quiescent current can achieve a good slew rate, shift the dominant pole to a higher frequency, and ensure stability under very light loads.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to the above embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0074] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-voltage fully integrated low-dropout linear regulator, comprising: An error amplifier, power transmission transistor, and voltage divider network based on auxiliary operational amplifier A1 are characterized by: The error amplifier includes multiple P-type MOS transistors and multiple N-type MOS transistors. The multiple P-type MOS transistors are designated as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, and PMOS transistor P5, respectively; the multiple N-type MOS transistors are designated as NMOS transistor N1, NMOS transistor N2, and NMOS transistor N3, respectively. The non-inverting input terminal of the auxiliary operational amplifier A1 is connected to the drain of the PMOS transistor P2, the inverting input terminal of the auxiliary operational amplifier A1 is connected to the drain of the PMOS transistor P1, and the output terminal of the auxiliary operational amplifier A1 is connected to the gate of the PMOS transistor P3. The source of PMOS transistor P1 is connected to the source of PMOS transistor P2, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2, the drain of PMOS transistor P1 is connected to the source of PMOS transistor P3, the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N1, the source of NMOS transistor N1 is connected to the source of NMOS transistor N2, the drain of NMOS transistor N2 is connected to the source of NMOS transistor N3, and the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P2. The power transmission transistor is denoted as MOS transistor MP. The drain of MOS transistor MP is connected to the source of PMOS transistor P2, and the gate of MOS transistor MP is connected to the drain of PMOS transistor P2. The voltage divider network includes resistors Rf1 and Rf2. The source of the MOS transistor MP is connected to one end of resistor Rf1, the other end of resistor Rf1 is connected to one end of resistor Rf2, and the other end of resistor Rf2 is connected to the output terminal of current source IB1 and grounded. Based on the virtual short characteristic of the auxiliary operational amplifier A1, the auxiliary operational amplifier A1 clamps the drain voltage of PMOS transistors P1 and P2, making the potentials at the two points equal, thus achieving the equality of the source and drain voltages of PMOS transistors P1 and P2.

2. The low-voltage fully integrated low-dropout linear regulator according to claim 1, characterized in that, The source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to the input voltage V. in .

3. A low-voltage fully integrated low-dropout linear regulator according to claim 2, characterized in that, It also includes a current source IB1, and the gate of the NMOS transistor N1 is connected to the reference voltage V. ref The source of NMOS transistor N1 is connected to the source of NMOS transistor N2, and together they are connected to the input terminal of current source IB1.

4. A low-voltage fully integrated low-dropout linear regulator according to claim 1, characterized in that, The auxiliary operational amplifier A1 includes PMOS transistors P4 and P5, current source IB2 and current source IB3. The gate of PMOS transistor P4 is connected to the gate of PMOS transistor P5. The gates of PMOS transistors P4 and P5 are connected together to the drain of PMOS transistor P4. The drain of PMOS transistor P4 is connected to the input terminal of current source IB2.

5. A low-voltage fully integrated low-dropout linear regulator according to claim 1, characterized in that, The source of PMOS transistor P5 is connected to the drain of PMOS transistor P2, the drain of PMOS transistor P5 is connected to the input terminal of current source IB3, and the gate of PMOS transistor P3 is connected to the drain of PMOS transistor P5.

6. A low-voltage fully integrated low-dropout linear regulator according to claim 1, characterized in that, The source of the MOSFET MP is connected to the voltage output V. out .

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