A multi-backplane interconnect system

Abstract

The embodiment of the application provides a multi-backboard cascade system, which comprises a server mainboard, a plurality of hard disk backboards, a two-wire serial I2C connector and a cascade processing module. The server mainboard comprises a first coaxial connector, a first cascade backboard comprises a second coaxial connector, the first coaxial connector is connected with the second coaxial connector, the first coaxial connector is connected with the input end of the cascade processing module, the second coaxial connector is connected with the output end of the cascade processing module, the I2C connector is connected with the server mainboard, the I2C is used for converting a work signal into a board card input address when the work signal is received, the server mainboard is used for sending the board card input address to the cascade processing module through the first coaxial connector, the cascade processing module is used for receiving the board card input address and converting the board card input address into a board card output address, and the first cascade backboard and N cascade backboards are used for receiving the board card output address.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to a multi-backplane cascading system. Background Technology

[0002] A backplane is a circuit board or frame that supports other circuit boards, components, and interconnections between components, and provides power and data signals to the supported components (such as the motherboard). A hard drive backplane is a circuit board used to connect more hard drives to a computer. It can be used to build a personal storage system. The hard drive backplane is directly connected to the motherboard or various adapter cards via cables. To adapt to different application scenarios, servers often have multiple backplanes configured on the motherboard to connect various hard drives.

[0003] In existing technologies, one approach is to connect different hard drive backplanes to different I2C (Inter-Integrated Circuit, two-wire serial) connectors on the motherboard, and another approach is to connect different hard drive backplanes to one I2C bus on the motherboard. However, when the number of backplanes that the motherboard needs to connect is large, the number of power cables, high-speed cables and other cables between the motherboard and the backplanes increases significantly, which limits the placement of the hard drive backplanes. Furthermore, the I2C connectors on the motherboard are overloaded, resulting in a smaller number of backplanes that the motherboard can connect to. Summary of the Invention

[0004] This invention provides a multi-backplane cascading system to solve or partially solve the problems in the prior art where the placement of hard drive backplanes is limited, the I2C load is too high, and the number of backplanes connected to the motherboard is too small when the motherboard is connected to too many backplanes.

[0005] This invention discloses a multi-backplane cascading system, which includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascading processing module.

[0006] The hard drive backplane includes a first-level cascaded backplane and N cascaded backplanes connected to the first-level cascaded backplane, where N is an integer greater than 1.

[0007] The server motherboard includes a first coaxial connector, and the first-level cascaded backplane includes a second coaxial connector, wherein the first coaxial connector is connected to the second coaxial connector.

[0008] The first coaxial connector is connected to the input terminal of the cascaded processing module, and the second coaxial connector is connected to the output terminal of the cascaded processing module.

[0009] The I2C connector is connected to the server motherboard, and the I2C is used to convert the working signal into a board input address when a working signal is received.

[0010] The server motherboard is used to send the board input address to the cascaded processing module through the first coaxial connector;

[0011] The cascaded processing module is used to receive the board input address and convert the board input address into the board output address.

[0012] The first-level cascaded backplane and the N cascaded backplanes are used to receive the output address of the board.

[0013] Optionally, the system further includes a grounding terminal and a power supply terminal;

[0014] The cascaded processing module includes a transistor connected between the grounding terminal and the power supply terminal;

[0015] And a resistor connected to the transistor and the power supply terminal, the resistor including a first resistor and a second resistor;

[0016] The first resistor is connected to the collector of the transistor, and the second resistor is connected to the first resistor.

[0017] Optionally, the board input address includes a first input signal and a second input signal;

[0018] The board output address includes a first output signal and a second output signal;

[0019] The first coaxial connector includes a first output connection line connected to the first input signal and a second output connection line connected to the second input signal;

[0020] The second coaxial connector includes a first input connection line connected to the first output signal and a second input connection line connected to the second output signal.

[0021] Optionally, the N cascaded backplanes are four-level cascaded backplanes, and the cascaded processing module includes NOT gates and OR gates;

[0022] The input terminal of the NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line;

[0023] The first input terminal of the OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line.

[0024] Optionally, the NOT gate circuit is used to receive the first input signal and output the first output signal to the first input connection line according to the first input signal;

[0025] The OR gate circuit is used to receive the first input signal and the second input signal, and output the second output signal to the second input connection line according to the first input signal and the second input signal.

[0026] Optionally, the N cascaded backplanes are five-level cascaded backplanes; the board input address further includes a third input signal, and the board output address further includes a third output signal; the OR gate circuit includes a first OR gate circuit and a second OR gate circuit;

[0027] The first coaxial connector also includes a third output connection line connected to the third input signal;

[0028] The second coaxial connector also includes a third input connection line connected to the third output signal;

[0029] The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line;

[0030] The first input terminal of the second OR gate circuit is connected to the second output connection line, the second input terminal is connected to the third output connection line, and the output terminal is connected to the third input connection line.

[0031] Optionally, the first OR gate circuit is used to receive the first input signal and the second input signal, and output the second output signal to the second input connection line according to the first input signal and the second input signal;

[0032] The second OR gate circuit is used to receive the second input signal and the third input signal, and output the third output signal to the third input connection line according to the second input signal and the third input signal.

[0033] Optionally, the N cascaded backplanes are six-level cascaded backplanes; the cascaded processing module further includes AND gate circuits;

[0034] The first input terminal of the AND gate is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the second OR gate.

[0035] The second input terminal of the second OR gate circuit is connected to the third output connection line, and the output terminal is connected to the third input connection line.

[0036] Optionally, the AND gate circuit is used to receive the first input signal and the second input signal, generate an initial output signal based on the first input signal and the second input signal, and output the initial output signal to the input terminal of the second OR gate circuit;

[0037] The second OR gate circuit is used to receive the initial output signal and the third input signal, and output the third output signal to the third input connection line according to the initial output signal and the third input signal.

[0038] Optionally, the N cascaded backplanes are seven-level cascaded backplanes; the NOT gate circuit includes a first NOT gate circuit and a second NOT gate circuit, the OR gate circuit includes a first OR gate circuit and a second OR gate circuit, and the AND gate circuit includes a first AND gate circuit and a second AND gate circuit.

[0039] The input terminal of the first NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line;

[0040] The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the first AND gate circuit.

[0041] The input terminal of the second NOT gate is connected to the third output connection line, and the output terminal is connected to the second input terminal of the first AND gate.

[0042] The first input terminal of the first AND gate is connected to the output terminal of the first OR gate, the second input terminal is connected to the output terminal of the second NOT gate, and the output terminal is connected to the second input connection line.

[0043] The first input terminal of the second AND gate is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the second OR gate.

[0044] The second input terminal of the second OR gate circuit is connected to the third output connection line, and the output terminal is connected to the third input connection line.

[0045] Optionally, the first NOT gate is used to receive the first input signal and output the first output signal to the first input connection line according to the first input signal;

[0046] The first OR gate circuit is used to receive the first input signal and the second input signal, generate a first initial output signal based on the first input signal and the second input signal, and output the first initial output signal to the first input terminal of the first AND gate circuit;

[0047] The second NOT gate circuit is used to receive the third input signal, generate a second initial output signal based on the third input signal, and output the second initial output signal to the second input terminal of the first AND gate circuit;

[0048] The first AND gate circuit is used to receive the first initial output signal and the second initial output signal, and output the second output signal to the second input connection line according to the first initial output signal and the second initial output signal;

[0049] The second AND gate is used for the first input signal and the second input signal, generates a third initial output signal based on the first input signal and the second input signal, and outputs the third initial output signal to the first input terminal of the second OR gate.

[0050] The second OR gate circuit is used to receive the third initial output signal and the third input signal, and output the third output signal to the third input connection line according to the third initial output signal and the third input signal.

[0051] The embodiments of the present invention have the following advantages:

[0052] In this embodiment of the invention, the multi-backplane cascade system includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. The hard disk backplanes include a primary cascade backplane and N cascade backplanes connected to the primary cascade backplane, where N is an integer greater than 1. The server motherboard includes a first coaxial connector, and the primary cascade backplanes include second coaxial connectors. The first and second coaxial connectors are connected. The first coaxial connector is connected to the input terminal of the cascade processing module, and the second coaxial connector is connected to the output terminal of the cascade processing module. The I2C connector is connected to the server motherboard. The I2C connector is used to convert a received working signal into a board input address. The server motherboard is used for communication... The motherboard sends the board input address to the cascade processing module via the first coaxial connector. The cascade processing module receives the board input address and converts it into a board output address. One cascaded backplane and N cascaded backplanes receive the board output addresses, thus enabling the motherboard to transmit data with the hard drive backplanes via the I2C connector. By sending the board input address to the cascade processing module, the motherboard controls the cascade processing module to process the board input address and obtain the corresponding board output address. This allows multiple hard drive backplanes with compatible board output addresses to share one I2C connector on the motherboard, increasing the number of cascaded hard drive backplanes on the motherboard and enabling real-time monitoring of the working status of different devices corresponding to each cascaded hard drive backplane. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the communication connection of the multi-backplane cascaded system provided in the embodiments of the present invention;

[0054] Figure 2 This is a schematic diagram of the multi-backplane cascaded circuit provided in an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the cascading processing module of the four-level cascading backplane provided in this embodiment of the invention;

[0056] Figure 4 This is a schematic diagram of the cascading processing module of the five-level cascading backplane provided in this embodiment of the invention;

[0057] Figure 5 This is a schematic diagram of the cascading processing module of the six-level cascading backplane provided in this embodiment of the invention;

[0058] Figure 6 This is a schematic diagram of the cascading processing module of the seven-level cascading backplane provided in this embodiment of the invention. Detailed Implementation

[0059] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] Reference Figure 1 The diagram illustrates a communication connection schematic of a multi-backplane cascaded system provided in an embodiment of the present invention. The multi-backplane cascaded system specifically includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. I2C connectors are configured in both the server motherboard and each hard disk backplane, and a cascade processing module is connected between the server motherboard and the hard disks.

[0061] Specifically, the hard drive backplane includes a first-level cascaded backplane and N cascaded backplanes connected to the first-level cascaded backplane, where N is an integer greater than 1, such as 4, 5, 6, 7, etc. Correspondingly, the number of hard drive backplanes connected to the server motherboard is 4, 5, 6, or 7.

[0062] The server motherboard includes a first coaxial connector, and the first-level cascaded backplane includes a second coaxial connector. The first coaxial connector is connected to the second coaxial connector. The first coaxial connector is connected to the input terminal of the cascaded processing module, and the second coaxial connector is connected to the output terminal of the cascaded processing module. Through the first and second coaxial connectors, an effective communication link can be formed between the server motherboard, the cascaded processing module, and the hard drive backplane. For example, the coaxial connector can be an SMB (Sub-Miniature version B, radio frequency connector). The SMB coaxial connector is a small push-lock radio frequency coaxial connector, which has the characteristics of small size, light weight, easy use, and excellent electrical performance. It is suitable for connecting coaxial cables in the high-frequency circuits of wireless equipment and electronic instruments.

[0063] The I2C connector connects to the server motherboard. I2C is used to convert received working signals into board input addresses. The I2C connector is equipped with an I2C bus, which requires only two wires: one data line and one clock line. The bus interface is integrated inside the chip, eliminating the need for special interface circuitry. Therefore, the I2C bus simplifies hardware PCB routing. Furthermore, the I2C bus is a true multi-master bus; if two or more masters initialize data transmission simultaneously, collision detection and arbitration prevent data corruption. Each device connected to the bus has a unique address, and any device can act as both a master and a slave, but only one master is allowed at a time. The I2C bus also allows for online monitoring via external connections, facilitating system fault diagnosis and debugging. Faults can be addressed immediately, and the software is more standardized and modular, shortening development time.

[0064] The server motherboard sends the board input address to the cascade processing module via the first coaxial connector. The cascade processing module receives the board input address and converts it into a board output address. One cascaded backplane and N cascaded backplanes receive the board output addresses. Thus, the server motherboard can monitor the working status and device status information of the devices associated with each hard drive backplane in real time through the board input address and board output address.

[0065] In an embodiment of the present invention, reference is made to Figure 2 A schematic diagram of a multi-backplane cascaded circuit is shown. The multi-backplane cascaded system also includes a ground terminal and a power supply terminal (P3V3). The cascaded processing module includes a transistor connected between the ground terminal and the power supply terminal, and resistors connected to the transistor and the power supply terminal. The resistors include a first resistor and a second resistor. The first resistor is connected to the collector of the transistor, and the second resistor is connected to the first resistor.

[0066] Specifically, the transistor can be an NPN transistor. An NPN transistor can amplify the input signal sent by the motherboard. An NPN transistor includes a base, a collector, and an emitter. The signal is input through the base, the collector is connected to the first resistor and outputs the signal, and the emitter is grounded.

[0067] In an embodiment of the present invention, the board input address includes a first input signal and a second input signal, the board output address includes a first output signal and a second output signal, the first coaxial connector includes a first output connection line connected to the first input signal and a second output connection line connected to the second input signal, and the second coaxial connector includes a first input connection line connected to the first output signal and a second input connection line connected to the second output signal.

[0068] Specifically, the first input signal corresponds to ADDR0_IN, and the second input signal corresponds to ADDR1_IN. Therefore, the board input address is ADDR0_IN||ADDR1_IN. If ADDR1_IN is 1 and ADDR0_IN is 0, the board input address is 10. The first output signal corresponds to ADDR0_OUT, and the second output signal corresponds to ADDR1_OUT. Therefore, the board output address is ADDR0_OUT||ADDR1_OUT. If ADDR1_OUT is 0 and ADDR0_OUT is 0, the board output address is 00.

[0069] In an embodiment of the present invention, reference is made to Figure 3 A schematic diagram of a cascaded processing module for a four-level cascaded backplane is shown. N cascaded backplanes constitute a four-level cascaded backplane. The cascaded processing module includes NOT gates and OR gates. The input terminal of the NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line. The first input terminal of the OR gate is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line.

[0070] In a specific implementation, the NOT gate is used to receive the first input signal and output the first output signal to the first input connection line according to the first input signal; the OR gate is used to receive the first input signal and the second input signal and output the second output signal to the second input connection line according to the first input signal and the second input signal.

[0071] Specifically, the board output address (ADDR1_OUT = ADDR0_IN || ADDR1_IN, !ADDR0_IN) consists of the second output signal from an OR gate and the first output signal from a NOT gate. If the server motherboard is cascaded with four hard drive backplanes (N = 4), then the board output address ① of the first-level backplane is 00. The logical processing of the board output addresses of other backplanes connected to the first-level backplane is as follows: if the board output address of the first-level backplane is "00", then ADDR0_IN is "0", which is processed by the NOT gate... After the path is inverted, the output is "1" (first output signal), and ADDR0_IN and ADDR1_IN are both "0". After passing through the OR gate, the output is "0" (second output signal). Therefore, the board output address ② of the second-level backplane is "01". Correspondingly, the board output address ③ of the third-level backplane is "10", and the board output address ④ of the fourth-level backplane is "11". If the fourth-level backplane continues to connect to the next backplane, the board output address ⑤ of the fifth-level backplane will be "10", which conflicts with the board output address ③. The current system can achieve four-level cascading.

[0072] In an embodiment of the present invention, reference is made to Figure 4 A schematic diagram of a cascaded processing module for a five-level cascaded backplane is shown. N cascaded backplanes constitute a five-level cascaded backplane. The board input address also includes a third input signal, and the board output address also includes a third output signal. The OR gate circuit includes a first OR gate circuit and a second OR gate circuit. The first coaxial connector also includes a third output connection line connected to the third input signal, and the second coaxial connector also includes a third input connection line connected to the third output signal. The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line. The first input terminal of the second OR gate circuit is connected to the second output connection line, the second input terminal is connected to the third output connection line, and the output terminal is connected to the third input connection line.

[0073] In a specific implementation, the first OR gate circuit is used to receive the first input signal and the second input signal, and outputs the second output signal to the second input connection line according to the first input signal and the second input signal. The second OR gate circuit is used to receive the second input signal and the third input signal, and outputs the third output signal to the third input connection line according to the second input signal and the third input signal. The third input signal corresponds to ADDR2_IN, and the third output signal corresponds to ADDR2_OUT.

[0074] Specifically, the board output address (ADDR2_OUT = ADDR2_IN || ADDR1_IN, ADDR1_OUT = ADDR1_IN || ADDR0_IN, !ADDR0_OUT) consists of the third output signal from the second OR gate, the second output signal from the first OR gate, and the first output signal from the NOT gate. If the server motherboard is cascaded with five hard drive backplanes (N = 5), then the board output address ① of the first-level backplane is 000. The logical processing of the board output addresses of the other backplanes connected to the first-level backplane is as follows: If the board output address of the first-level backplane is "000", then ADDR0_IN is "0", which is inverted by the NOT gate and outputs "1". ADDR0_IN and ADDR1_IN are both "0", which are inverted by the first OR gate and output "0". ADDR2_IN and ADDR1_IN are both "0", which are inverted by the second OR gate and output "1". After the gate circuit, the output is "0", therefore, the output address ② of the second-level backplane is "001"; since the output address ② of the second-level backplane is "001", ADDR0_IN is "1", which, after being inverted by the NOT gate circuit, outputs "0" (first output signal). ADDR0_IN is "1" and ADDR1_IN is "0", which, after being passed through the first OR gate circuit, outputs "1" (second output signal). ADDR2_IN and ADDR1_IN are both "0" (third output signal), which, after being passed through the second OR gate circuit, outputs "0". Therefore, the output address ③ of the third-level backplane is "010", and correspondingly, the output address ④ of the fourth-level backplane is "111", and the output address ⑤ of the fifth-level backplane is "110". If the fifth-level backplane continues to connect to the next backplane, the output address ⑥ of the sixth-level backplane is "111", which conflicts with the output address ④. The current system can achieve five-level cascading.

[0075] In an embodiment of the present invention, reference is made to Figure 5 A schematic diagram of a cascaded processing module for a six-level cascaded backplane is shown. N cascaded backplanes constitute a six-level cascaded backplane. The cascaded processing module also includes an AND gate circuit. The first input terminal of the AND gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of a second OR gate circuit. The second input terminal of the second OR gate circuit is connected to the third output connection line, and the output terminal is connected to the third input connection line.

[0076] In a specific implementation, the AND gate is used to receive the first input signal and the second input signal, generate an initial output signal based on the first input signal and the second input signal, and output the initial output signal to the input terminal of the second OR gate. The second OR gate is used to receive the initial output signal and the third input signal, and output the third output signal to the third input connection line based on the initial output signal and the third input signal.

[0077] Specifically, the board output address (ADDR2_OUT = ADDR2_IN || (ADDR1_IN && ADDR0_IN), ADDR1_OUT = ADDR1_IN || ADDR0_IN, !ADDR0_OUT) consists of the third output signal from the AND gate and the second OR gate, the second output signal from the first OR gate, and the first output signal from the NOT gate. If the server motherboard is cascaded with six hard drive backplanes (N = 6), then the board output address ① of the first-level backplane is 000, and the other backplanes connected to the first-level backplane... The logical processing of the board's output address is as follows: If the first-level backplane's output address is "000", then ADDR0_IN is "0". After being inverted by a NOT gate, it outputs "1" (first output signal). If both ADDR0_IN and ADDR1_IN are "0", they output "0" (second output signal) after passing through a first OR gate. If both ADDR0_IN and ADDR1_IN are "0", they output "0" after passing through an AND gate, and ADDR2_I is "0". The "0" output by the AND gate and the "0" output by ADDR2_I are then processed by the first OR gate... After the OR gate, the output is "0" (third output signal). Therefore, the second-level backplane's output address ② is "001". Since the second-level backplane's output address ② is "001", ADDR0_IN is "1". After being inverted by the NOT gate, it outputs "0" (first output signal). ADDR0_IN is "1" and ADDR1_IN is "0". After passing through the first OR gate, they output "1" (second output signal). ADDR0_IN is "1" and ADDR1_IN is "0". After passing through the AND gate, it outputs "0", and ADDR2... _I is "0". The "0" output from the AND gate and the "0" output from ADDR2_I are passed through the second OR gate to output "0" (the third output signal). Therefore, the board output address ③ of the third-level backplane is "010". Correspondingly, the board output address ④ of the fourth-level backplane is "011", the board output address ⑤ of the fifth-level backplane is "110", and the board output address ⑥ of the sixth-level backplane is "111". If the sixth-level backplane continues to connect to the next backplane, the board output address ⑦ of the seventh-level backplane will be "110", which conflicts with the board output address ⑤. The current system can achieve six-level cascading.

[0078] In an embodiment of the present invention, reference is made to Figure 6This diagram illustrates a cascaded processing module for a seven-level cascaded backplane. N cascaded backplanes constitute a seven-level cascaded backplane. The NOT gate circuit includes a first NOT gate circuit and a second NOT gate circuit; the OR gate circuit includes a first OR gate circuit and a second OR gate circuit; the AND gate circuit includes a first AND gate circuit and a second AND gate circuit. The input terminal of the first NOT gate circuit is connected to the first output connection line, and the output terminal is connected to the first input connection line. The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the first AND gate circuit. The second NOT gate circuit... The input terminal of the gate circuit is connected to the third output connection line, and the output terminal is connected to the second input terminal of the first AND gate circuit. The first input terminal of the first AND gate circuit is connected to the output terminal of the first OR gate circuit, and the second input terminal is connected to the output terminal of the second NOT gate circuit. The output terminal is connected to the second input connection line. The first input terminal of the second AND gate circuit is connected to the first output connection line, and the second input terminal is connected to the second output connection line. The output terminal is connected to the first input terminal of the second OR gate circuit, and the second input terminal of the second OR gate circuit is connected to the third output connection line. The output terminal is connected to the third input connection line.

[0079] In a specific implementation, a first NOT gate is used to receive a first input signal and output a first output signal to a first input connection line based on the first input signal. A first OR gate is used to receive a first input signal and a second input signal, generate a first initial output signal based on the first input signal and the second input signal, and output the first initial output signal to the first input terminal of a first AND gate. A second NOT gate is used to receive a third input signal, generate a second initial output signal based on the third input signal, and output the second initial output signal to the second input terminal of a first AND gate. A first AND gate is used to receive the first initial output signal and the second initial output signal, and output a second output signal to a second input connection line based on the first initial output signal and the second initial output signal. A second AND gate is used to receive the first input signal and the second input signal, generate a third initial output signal based on the first input signal and the second input signal, and output the third initial output signal to the first input terminal of a second OR gate. A second OR gate is used to receive the third initial output signal and the third input signal, and output a third output signal to a third input connection line based on the third initial output signal and the third input signal.

[0080] Specifically, the board output address (ADDR2_OUT = ADDR2_IN || (ADDR1_IN && ADDR0_IN), ADDR1_OUT = !ADDR2_IN && (ADDR1_IN || ADDR0_IN), !ADDR0_OUT) is composed of the third output signal from the AND gate and the second OR gate, the second output signal from the first OR gate, and the first output signal from the NOT gate. If the server motherboard is cascaded with six hard drive backplanes (N = 7), then the board output address ① of the first-level backplane is 000. The logical processing of the board output addresses of other backplanes connected to the first-level backplane is as follows: First If the backplane card output address is "000", then ADDR0_IN is "0". After being inverted by the first NOT gate, it outputs "1" (first output signal). If both ADDR0_IN and ADDR1_IN are "0", they output "0" after passing through the first OR gate. If ADDR2_I is "0", it outputs "1" after being inverted by the second NOT gate. Then, "0" and "1" are input into the first AND gate, outputting "0" (second output signal). If both ADDR0_IN and ADDR1_IN are "0", they output "0" after passing through the second AND gate, and ADDR2_I is "0". Then, "0" and "0" are input into the second OR gate. The circuit outputs "0" (third output signal), therefore, the second-level backplane's board output address ② is "001"; the second-level backplane's board output address ② is "001", then ADDR0_IN is "1", which, after being inverted by a NOT gate, outputs "0" (first output signal). ADDR0_IN is "1" and ADDR1_IN is "0", which, after being passed through a first OR gate, outputs "1". ADDR2_IN is "0", which, after being inverted by a second NOT gate, outputs "1". Then, "1" and "1" are input into a first AND gate, outputting "1" (second output signal). ADDR0_IN is "1" and ADDR1_IN is "001". The input "0" is passed through the second AND gate circuit and outputs "0", and ADDR2_I is "0". Then, "0" is input to the second OR gate circuit and outputs "0" (the third output signal). Therefore, the board output address ③ of the third-level backplane is "010", and the corresponding board output address ④ of the fourth-level backplane is "011", the board output address ⑤ of the fifth-level backplane is "110", the board output address ⑥ of the sixth-level backplane is "101", and the board output address ⑦ of the seventh-level backplane is "100". If the seventh-level backplane continues to connect to the next backplane, the board output address ⑧ of the eighth-level backplane is "101", which conflicts with the board output address ⑥. The current system can achieve seven-level cascading.

[0081] In this embodiment of the invention, the multi-backplane cascade system includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. The hard disk backplanes include a primary cascade backplane and N cascade backplanes connected to the primary cascade backplane, where N is an integer greater than 1. The server motherboard includes a first coaxial connector, and the primary cascade backplanes include second coaxial connectors. The first and second coaxial connectors are connected. The first coaxial connector is connected to the input terminal of the cascade processing module, and the second coaxial connector is connected to the output terminal of the cascade processing module. The I2C connector is connected to the server motherboard. The I2C connector is used to convert a received working signal into a board input address. The server motherboard is used for communication... The motherboard sends the board input address to the cascade processing module via the first coaxial connector. The cascade processing module receives the board input address and converts it into a board output address. One cascaded backplane and N cascaded backplanes receive the board output addresses, thus enabling the motherboard to transmit data with the hard drive backplanes via the I2C connector. By sending the board input address to the cascade processing module, the motherboard controls the cascade processing module to process the board input address and obtain the corresponding board output address. This allows multiple hard drive backplanes with compatible board output addresses to share one I2C connector on the motherboard, increasing the number of cascaded hard drive backplanes on the motherboard and enabling real-time monitoring of the working status of different devices corresponding to each cascaded hard drive backplane.

[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0083] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0084] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0085] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0087] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0088] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0089] The above provides a detailed description of a multi-backplane cascade system provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A multi-backplane cascade system, characterized in that, The multi-backplane cascade system includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. The hard drive backplane includes a primary cascaded backplane and three cascaded backplanes connected to the primary cascaded backplane. The server motherboard includes a first coaxial connector, and the first-level cascaded backplane includes a second coaxial connector, wherein the first coaxial connector is connected to the second coaxial connector. The first coaxial connector is connected to the input terminal of the cascaded processing module, and the second coaxial connector is connected to the output terminal of the cascaded processing module. The I2C connector is connected to the server motherboard, and the I2C connector is used to convert the working signal into a board input address when it receives a working signal; The server motherboard is used to send the board input address to the cascaded processing module through the first coaxial connector; The cascaded processing module is used to receive the board input address and convert the board input address into the board output address. The first-level cascaded backplane and the three cascaded backplanes are used to receive the output address of the board; The board input address includes a first input signal and a second input signal; The board output address includes a first output signal and a second output signal; The first coaxial connector includes a first output connection line connected to the first input signal and a second output connection line connected to the second input signal; The second coaxial connector includes a first input connection line connected to the first output signal and a second input connection line connected to the second output signal; The cascaded processing module includes NOT gate circuits and OR gate circuits; The input terminal of the NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line; The first input terminal of the OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line.

2. A multi-backplane cascade system, characterized in that, The multi-backplane cascade system includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. The hard drive backplane includes a primary cascaded backplane and four cascaded backplanes connected to the primary cascaded backplane. The server motherboard includes a first coaxial connector, and the first-level cascaded backplane includes a second coaxial connector, wherein the first coaxial connector is connected to the second coaxial connector. The first coaxial connector is connected to the input terminal of the cascaded processing module, and the second coaxial connector is connected to the output terminal of the cascaded processing module. The I2C connector is connected to the server motherboard, and the I2C connector is used to convert the working signal into a board input address when it receives a working signal; The server motherboard is used to send the board input address to the cascaded processing module through the first coaxial connector; The cascaded processing module is used to receive the board input address and convert the board input address into the board output address. The first-level cascaded backplane and the four cascaded backplanes are used to receive the output address of the board; The board input address includes a first input signal, a second input signal, and a third input signal; The board output address includes a first output signal, a second output signal, and a third output signal; The first coaxial connector includes a first output connection line connected to the first input signal, a second output connection line connected to the second input signal, and a third output connection line connected to the third input signal; The second coaxial connector includes a first input connection line connected to the first output signal, a second input connection line connected to the second output signal, and a third input connection line connected to the third output signal; The cascaded processing module includes NOT gate circuits and OR gate circuits, and the OR gate circuits include a first OR gate circuit and a second OR gate circuit. The input terminal of the NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line; The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line; The first input terminal of the second OR gate circuit is connected to the second output connection line, the second input terminal is connected to the third output connection line, and the output terminal is connected to the third input connection line.

3. A multi-backplane cascade system, characterized in that, The multi-backplane cascade system includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. The hard drive backplane includes a first-level cascaded backplane and five cascaded backplanes connected to the first-level cascaded backplane. The server motherboard includes a first coaxial connector, and the first-level cascaded backplane includes a second coaxial connector, wherein the first coaxial connector is connected to the second coaxial connector. The first coaxial connector is connected to the input terminal of the cascaded processing module, and the second coaxial connector is connected to the output terminal of the cascaded processing module. The I2C connector is connected to the server motherboard, and the I2C connector is used to convert the working signal into a board input address when it receives a working signal; The server motherboard is used to send the board input address to the cascaded processing module through the first coaxial connector; The cascaded processing module is used to receive the board input address and convert the board input address into the board output address. The first-level cascaded backplane and the five cascaded backplanes are used to receive the output address of the board; The board input address includes a first input signal, a second input signal, and a third input signal; The board output address includes a first output signal, a second output signal, and a third output signal; The first coaxial connector includes a first output connection line connected to the first input signal, a second output connection line connected to the second input signal, and a third output connection line connected to the third input signal; The second coaxial connector includes a first input connection line connected to the first output signal, a second input connection line connected to the second output signal, and a third input connection line connected to the third output signal; The cascaded processing module includes NOT gate circuits, OR gate circuits and AND gate circuits, and the OR gate circuits include a first OR gate circuit and a second OR gate circuit. The input terminal of the NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line; The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the second input connection line; The first input terminal of the AND gate is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the second OR gate. The second input terminal of the second OR gate circuit is connected to the third output connection line, and the output terminal is connected to the third input connection line.

4. A multi-backplane cascade system, characterized in that, The multi-backplane cascade system includes a server motherboard, multiple hard disk backplanes, a two-wire serial I2C connector, and a cascade processing module. The hard drive backplane includes a first-level cascaded backplane and six cascaded backplanes connected to the first-level cascaded backplane. The server motherboard includes a first coaxial connector, and the first-level cascaded backplane includes a second coaxial connector, wherein the first coaxial connector is connected to the second coaxial connector. The first coaxial connector is connected to the input terminal of the cascaded processing module, and the second coaxial connector is connected to the output terminal of the cascaded processing module. The I2C connector is connected to the server motherboard, and the I2C connector is used to convert the working signal into a board input address when it receives a working signal; The server motherboard is used to send the board input address to the cascaded processing module through the first coaxial connector; The cascaded processing module is used to receive the board input address and convert the board input address into the board output address. The first-level cascaded backplane and the six cascaded backplanes are used to receive the output address of the board; The board input address includes a first input signal, a second input signal, and a third input signal; The board output address includes a first output signal, a second output signal, and a third output signal; The first coaxial connector includes a first output connection line connected to the first input signal, a second output connection line connected to the second input signal, and a third output connection line connected to the third input signal; The second coaxial connector includes a first input connection line connected to the first output signal, a second input connection line connected to the second output signal, and a third input connection line connected to the third output signal; The cascaded processing module includes NOT gates, OR gates, and AND gates. The NOT gates include a first NOT gate and a second NOT gate. The OR gates include a first OR gate and a second OR gate. The AND gates include a first AND gate and a second AND gate. The input terminal of the first NOT gate is connected to the first output connection line, and the output terminal is connected to the first input connection line; The first input terminal of the first OR gate circuit is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the first AND gate circuit. The input terminal of the second NOT gate is connected to the third output connection line, and the output terminal is connected to the second input terminal of the first AND gate. The first input terminal of the first AND gate is connected to the output terminal of the first OR gate, the second input terminal is connected to the output terminal of the second NOT gate, and the output terminal is connected to the second input connection line. The first input terminal of the second AND gate is connected to the first output connection line, the second input terminal is connected to the second output connection line, and the output terminal is connected to the first input terminal of the second OR gate. The second input terminal of the second OR gate circuit is connected to the third output connection line, and the output terminal is connected to the third input connection line.

5. A multi-backplane cascade system as described in any one of claims 1 to 4, characterized in that, The multi-backplane cascaded system also includes a grounding terminal and a power supply terminal; The cascaded processing module includes a transistor connected between the grounding terminal and the power supply terminal; And a resistor connected to the transistor and the power supply terminal, the resistor including a first resistor and a second resistor; The first resistor is connected to the collector of the transistor, and the second resistor is connected to the first resistor.

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