Data access method, memory storage device and memory controller

Abstract

The application provides a data access method, a memory storage device and a memory controller. The method comprises: erasing, data writing and data read / write test operation on the physical unit, and establishing a state bitmap of the physical unit; dividing a plurality of physical windows in the physical unit according to an interval value and the state bitmap, and constructing a physical window table of the plurality of physical windows; establishing a logical-to-physical mapping table according to the physical window table and the interval value; and realizing data access from a host system to the memory storage device according to the logical-to-physical mapping table. Therefore, the speed of data access from the host system to the memory storage device can be improved.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a data access method, a memory storage device, and a memory controller. Background Technology

[0002] Non-volatile memory modules (such as flash memory modules) offer advantages such as non-volatile data retention, low power consumption, and fast data access. For non-volatile memory modules like NAND flash, their manufacturing process and storage principles inevitably lead to bad blocks during production and use, necessitating methods for bad block management. However, traditional management methods operate on a block-by-block basis; if a block contains bad pages or the number of bad pages exceeds a certain limit, the block is discarded. This block-by-block management method suffers from low flash memory utilization. With the continuous increase in the capacity of each flash memory block, discarding entire blocks results in significant waste; therefore, the development of a page-by-page management method is essential. Summary of the Invention

[0003] The present invention provides a data access method, a memory storage device, and a memory controller, which can improve the speed of data access from the host system to the memory storage device.

[0004] Embodiments of the present invention provide a data access method for a memory storage device, wherein the memory storage device includes a memory module, the memory module includes at least one physical unit, the physical unit includes multiple physical programmable units, and the data access method includes: performing erase, data write, and data write-read test operations on the physical unit; establishing a state bitmap of the physical unit, the state bitmap being used to store management information of the physical unit, the management information including the total number of physical programmable units in the physical unit, the number of physical programmable units in a valid state, and the address values ​​of the valid physical programmable units in the physical unit; dividing the physical unit into multiple physical windows according to an interval value and the state bitmap, and constructing a physical window table of the multiple physical windows; establishing a logical-to-physical mapping table according to the physical window table and the interval value; and implementing data access from the host system to the memory storage device according to the logical-to-physical mapping table.

[0005] Optionally, embodiments of the present invention further provide a memory storage device, comprising: a connection interface for connecting to a host system; a memory module including at least one physical unit; and a memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to perform erase, data write, and data write-read test operations on the physical unit, establish a state bitmap of the physical unit, the state bitmap being used to store management information of the physical unit, the management information including the total number of physical programmable units of the physical unit, the number of physical programmable units in a valid state, and the address value of the valid physical programmable units in the physical unit; the memory controller is further configured to divide the physical unit into multiple physical windows according to an interval value and the state bitmap, and construct a physical window table of the multiple physical windows; the memory controller is further configured to establish a logic-to-physical mapping table according to the physical window table and the interval value; and the memory controller is further configured to implement data access from the host system to the memory storage device according to the logic-to-physical mapping table.

[0006] Optionally, embodiments of the present invention further provide a memory controller for controlling a memory module, wherein the memory module includes at least one physical unit, and the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; and a memory control circuit connected to the host interface and the memory interface; wherein the memory control circuit is used to perform erase, data write, and data write-read test operations on the physical unit, establish a state bitmap of the physical unit, the state bitmap is used to store management information of the physical unit, the management information includes the total number of physical programmable units of the physical unit, the number of physical programmable units in a valid state, and the address value of the valid physical programmable units in the physical unit; the memory control circuit is used to divide the physical unit into multiple physical windows according to an interval value and the state bitmap, and construct a physical window table of the multiple physical windows; the memory control circuit is used to establish a logic-to-physical mapping table according to the physical window table and the interval value; the memory control circuit is used to realize data access from the host system to the memory storage device according to the logic-to-physical mapping table.

[0007] Based on the above, erase, data write, and data read / write test operations are performed on the entity unit to establish a state bitmap for the entity unit. The state bitmap stores the management information of the entity unit, including the total number of entity programmable units, the number of entity programmable units in a valid state, and the address values ​​of valid entity programmable units within the entity unit. Multiple entity windows are divided within the entity unit according to an interval value and the state bitmap, constructing an entity window table for multiple entity windows. A logical-to-entity mapping table is established based on the entity window table and the interval value. Data access from the host system to the memory storage device is implemented using the logical-to-entity mapping table. This significantly improves the speed of accessing large files and large data from the host system to the memory storage device and memory module. Even with a small SRAM capacity in the memory storage device and memory module, access to large files and large data can still be achieved. The embodiments of this application can improve the speed of data access from the host system to the memory module. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a memory storage device according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic block diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0012] Figure 5 This is a flowchart illustrating a data access method according to an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram of a state bitmap according to an embodiment of the present invention;

[0014] Figure 7 This is a schematic diagram of a solid window table according to an embodiment of the present invention;

[0015] Figure 8 This is a flowchart illustrating a data access method according to an embodiment of the present invention;

[0016] Figure 9 This is a schematic diagram illustrating the mapping of logical entity programmable units to corresponding entity programmable units according to an embodiment of the present invention;

[0017] Figure 10This is a schematic diagram illustrating the mapping of a "page-by-page" logical entity programming unit to a corresponding entity programming unit according to an embodiment of the present invention. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a schematic diagram of a memory storage device according to an embodiment of the present invention. Please refer to... Figure 1 The memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example, the host system 11 can be a laptop computer, desktop computer, smartphone, tablet computer, industrial computer, game console, digital camera, or other electronic systems. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express) interface, a Universal Serial Bus (USB) interface, or other types of connection interfaces. Therefore, the host system 11 can store data to and / or read data from the memory storage device 12.

[0020] The memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 can communicate with the host system 11 via the connection interface 121.

[0021] Memory module 122 is used to store data. Memory module 122 may include a rewritable non-volatile memory module. Memory module 122 includes a memory cell array. The memory cells in memory module 122 store data in the form of voltage. For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

[0022] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be used to control memory storage device 12. For example, memory controller 123 can control connection interface 121 and memory module 122 for data access and data management. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices.

[0023] In one embodiment, the memory controller 123 is also referred to as a flash memory controller. In another embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a sequence of instructions from the memory controller 123 and access memory cells according to the sequence of instructions.

[0024] Figure 2 This is a schematic block diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 2 The memory controller 123 includes a memory control circuit 1233, a host interface 1231, and a memory interface 1232.

[0025] The memory control circuit 1233 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 1233 has multiple control instructions, and these control instructions are executed when the memory storage device 12 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory control circuit 1233 is equivalent to the description of the operation of the memory controller 123.

[0026] In this embodiment, the control instructions of the memory control circuit 1233 are operated in firmware form. For example, the memory control circuit 1233 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into this read-only memory. When the memory storage device 12 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0027] In another embodiment, the control instructions of the memory control circuit 1233 may also be stored in program code form in a specific area of ​​the memory module 122 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory control circuit 1233 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, the read-only memory has a boot code, and when the memory controller 123 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the memory module 122 into the random access memory of the memory control circuit 1233. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0028] In another embodiment, the control instructions for the memory control circuit 1233 can also be operated in hardware. For example, the memory control circuit 1233 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are electrically connected to the microcontroller. The memory cell management circuit manages the memory cells or groups thereof of the memory module 122. The memory write circuit issues a sequence of write instructions to the memory module 122 to write data into the memory module 122. The memory read circuit issues a sequence of read instructions to the memory module 122 to read data from the memory module 122. The memory erase circuit issues a sequence of erase instructions to the memory module 122 to erase data from the memory module 122. The data processing circuit processes the data to be written to the memory module 122 and the data to be read from the memory module 122. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the memory module 122 to perform corresponding write, read, and erase operations. In one embodiment, the memory control circuit 1233 may also issue other types of instruction sequences to the memory module 122 to instruct it to perform corresponding operations.

[0029] The host interface 1231 is electrically connected to the memory control circuit 1233 and is used to receive and identify instructions and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 1233 through the host interface 1231. In this embodiment, the host interface 1231 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto; the host interface 1231 may also be compatible with PATA, IEEE 1394, PCI Express, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0030] The memory interface 1232 is electrically connected to the memory control circuit 1233 and is used to access the memory module 122. That is, data to be written to the memory module 122 is converted into a format acceptable to the memory module 122 via the memory interface 1232. Specifically, if the memory control circuit 1233 needs to access the memory module 122, the memory interface 1232 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated, for example, by the memory control circuit 1233 and transmitted to the memory module 122 via the memory interface 1232. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as a read identifier and memory address.

[0031] In this embodiment, the memory controller 123 can perform single-frame encoding on data stored in the same physical programming unit, or multi-frame encoding on data stored in multiple physical programming units. Depending on the encoding algorithm used, the memory controller 123 can encode the data to be protected to generate corresponding error correction codes and / or error checking codes.

[0032] In one embodiment, the memory controller 123 further includes a buffer memory 1235, an error checking and correction circuit 1234, and a power management circuit 1236. The buffer memory 1235 is electrically connected to the memory control circuit 1233 and is used to temporarily store data and instructions from the host system 11 or data from the memory module 122. The power management circuit 1236 is electrically connected to the memory control circuit 1233 and is used to control the power supply of the memory storage device 12. The error checking and correction circuit 1234 is electrically connected to the memory control circuit 1233 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when the memory control circuit 1233 receives a write instruction from the host system 11, the error checking and correction circuit 1234 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write instruction, and the memory control circuit 1233 writes the data corresponding to the write instruction and the corresponding error correcting code and / or error detecting code into the memory module 122. Subsequently, when the memory control circuit 1233 reads data from the memory module 122, it will simultaneously read the error correction code and / or error check code corresponding to the data, and the error checking and correction circuit 1234 will perform error checking and correction operations on the read data based on the error correction code and / or error check code.

[0033] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes a plurality of physical units 301(1) to 301(A). Each physical unit includes a plurality of storage cells for non-volatile storage of data. For example, a physical unit may include one or more physical blocks. Each physical block may include a plurality of physical programming units. A physical programming unit may include one or more physical pages. The plurality of storage cells in a physical programming unit may be programmed simultaneously to store data. Furthermore, all storage cells in a physical block may be erased simultaneously.

[0034] In one embodiment, physical units 301(1) to 301(A) in memory module 122 are allocated to data area 31. Physical units 301(1) to 301(A) in data area 31 store data from host system 11.

[0035] In one embodiment, such as Figure 3As shown, the memory control circuit 1233 can be configured with multiple logic units 302(1) to 302(B) to map physical units in the data area 31. For example, a logic unit can consist of one or more logic addresses. The mapping relationship between logic units and physical units can be recorded in a logic-to-physical mapping table. When an access instruction is received from the host system 11, the memory control circuit 1233 can access data into the physical units in the data area 31 according to the corresponding logic-to-physical mapping table. Specifically, this mapping method is block mapping.

[0036] In one embodiment, such as Figure 4 As shown, the memory control circuit 1233 can configure multiple logical entity programming units 42(0) to 42(D) to map the entity programming units 41(0) to 41(C) in the entity units 301 in the data area 31. For example, a logical entity programming unit can consist of one or more logical entity programming addresses. The mapping relationship between logical entity programming units and entity programming units can be recorded in a logical-to-entity mapping table between logical entity programming units and entity programming units. When an access instruction is received from the host system 11, the memory control circuit 1233 can access data into the entity units in the data area 31 according to the corresponding logical entity programming unit and the logical-to-entity mapping table between entity programming units. Specifically, this mapping method is page mapping.

[0037] Figure 4 This is a schematic diagram of the entity units in the management memory module according to an embodiment of the present invention. It is a schematic diagram of the logic-to-entity mapping of the logical entity programmable units in entity unit 301(1) to the entity programmable units. Wherein, D is the total number of entity programmable units in entity unit 301(1), which includes the value of the valid entity programmable units and the value of the invalid entity programmable units in entity unit 301(1); the value of the valid entity programmable units is ≤ D; it is a positive integer. E is a positive integer, which is less than or equal to D; the value of E indicates that it is the value of the valid entity programmable units in entity unit 301(1).

[0038] In one embodiment, this application proposes a data access method for a memory storage device 12, wherein the memory storage device 12 includes a memory module 122, the memory module 122 includes at least one physical unit 301(E) (E is the address value of the physical unit), the physical unit includes a plurality of physical programming units 41(0) to 41(C), and particularly a data access method for the plurality of physical programming units including a physical programming unit 41(F) in an invalid state (F is the address value of the physical programming unit), such as Figure 5 As shown, the data access method includes:

[0039] Step S501: Perform erase, data write, and data write-read test operations on the entity unit to establish a status bitmap of the entity unit. The status bitmap is used to store the management information of the entity unit. The management information includes the total number of entity programmable units of the entity unit, the number of entity programmable units with a valid status, and the address value of the valid entity programmable units in the entity unit.

[0040] S502: Divide the entity cell into multiple entity windows based on an interval value and a state bitmap, and construct an entity window table for multiple entity windows;

[0041] S503: Establish a logical mapping table to the entity based on the entity window table and the interval value;

[0042] S504: Data is accessed from the host system to the memory storage device based on the logical-to-entity mapping table.

[0043] Specifically, for step S501, in one embodiment, a method for constructing a state bitmap is proposed. Specifically, by performing erase, data write, and data write-read test operations on entity units 301(1)---301(A), a state bitmap of entity units 301(1)---301(A) is constructed. The state bitmap is used to store the management information of the entity units. The management information includes the total number of entity programmable units in the entity unit, the number of entity programmable units in the invalid state, the number of entity programmable units in the valid state, and the address value of the valid entity programmable units in the entity unit. For example, taking an entity unit containing 128 entity programmable units as an example, after performing erase, data write, and data write-read test operations, it can be seen that the following is obtained: Figure 6 The diagram shown is a schematic representation of the state bitmap.

[0044] In one embodiment, "1" represents an entity programmable unit with an invalid state, and "0" represents an entity programmable unit with a valid state, such as... Figure 6 As shown in the image.

[0045] like Figure 6 As shown, the entity unit includes 108 valid entity programmatic units and 20 invalid entity programmatic units.

[0046] In one embodiment, this application also proposes a method for constructing interval values. Specifically, a table of prime numbers less than 50 is established, as shown in Table 1, and the interval values ​​are prime numbers taken from the table.

[0047] Table 1 Prime Number Table

[0048] 13 17 19 23 29 31 37 41 43 47

[0049] In one embodiment, when the total number of entity programmable units of an entity unit is ≤200, the interval value is <10, that is, the interval value is any prime number less than 10; for example, the interval value can be any value among 2, 3, 5, and 7, and preferably, the interval value can be 3.

[0050] In one embodiment, when 200 < the total number of entity programmable units of the entity unit ≤ 500, the interval value < 20, that is, the interval value is any prime number less than 20; for example, the interval value can be any value among 2, 3, 5, 7, 11, 13, 17, and 19; preferably, the interval value can be 11.

[0051] For example, in the above-mentioned entity units with a total of 128 procedural units, the interval value is 11.

[0052] In one embodiment, when 500 < the total number of entity programmable units of the entity unit ≤ 1000, the interval value < 30, that is, the interval value is any prime number less than 30; for example, the interval value can be any value among 2, 3, 5, 7, 11, 13, 17, 19, 23, and 29; preferably, the interval value can be 23.

[0053] In one embodiment, when 1000 < the total number of entity programmable units of the entity unit ≤ 2000, the interval value is any prime number less than 40; for example, the interval value can be any value among 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, and 37; preferably, the interval value can be 31.

[0054] In one embodiment, when the total number of entity programmable units of an entity unit is greater than 2000, the interval value is less than 50, that is, the interval value is any prime number less than 50; for example, the interval value can be any value among 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, and 47; preferably, the interval value can be 43.

[0055] This application chooses prime numbers as the interval value because, regardless of the total number of entity programs, dividing it by a prime number will always result in a non-divisible value. Among the many entity windows constructed, there will always be one entity window containing fewer entity programs than the others. Based on this, entity windows containing fewer entity programs are used to store state bitmaps and entity window tables. That is, entity programs at specific locations within an entity are selected to store state bitmaps and entity window tables, such as the entity programs at the last few address values ​​within the entity; while other entity programs are mainly used to store data from the host system 11. This facilitates the management of entity programs within the entity, and therefore, based on this, the memory storage device 12 and memory module 122 of the entity can improve the speed of data access from the host system 11 to the memory storage device 12 in terms of data storage.

[0056] S502: Divide the entity cell into multiple entity windows based on an interval value and a state bitmap, and construct an entity window table for multiple entity windows.

[0057] In one embodiment, the entity window includes a plurality of entity procedural units, which include valid entity procedural units and / or invalid entity procedural units.

[0058] Establish an entity window table to manage multiple entity windows. The entity window table is used to store the distribution of each entity window, the number of valid entity procedural units in each entity window, and the number of valid entity procedural units from the starting entity window to the current entity window.

[0059] like Figure 7 As shown, Figure 7 It is a entity window table containing 12 entity windows, built based on an interval value of 11. The entity window table includes the following information: the distribution of each entity window: including 12 entity windows; entity windows A0-A10 include 11 entity procedural units, entity window A11 includes 7 entity procedural units, and 5 entity procedural units in entity window A11 (2 invalid ones cannot be used to store data) are used to store the state bitmap and entity window table (the specific entity procedural unit address values ​​stored in the state bitmap and entity window table are not limited); the number of "0"s from the starting entity window to entity windows A0-A11 are: 9, 19, 28, 37, 45, 55, 65, 75, 84, 93, 103, 108 respectively.

[0060] In one embodiment, the number of entity procedural units included in each entity window may be different. For example, such as Figure 7As shown, entity windows A0-A10 include 11 entity programming units, and entity window A11 includes 7 entity programming units; among them, 5 entity programming units in entity window A11: P121, P122, P125, P126, and P127 are used as storage state bitmaps and entity window tables (2 invalid entity programming units P123 and P124 cannot be used to store data).

[0061] In one embodiment, such as Figure 7 As shown, the entity window contains invalid entity programming units and valid entity programming units.

[0062] In another embodiment, the entity window may contain entity programmatic units that are either invalid or valid entity programmatic units; this embodiment does not impose any particular limitation on this.

[0063] S503: Establish a logical-to-entity mapping table based on the entity window table and the interval value.

[0064] Furthermore, the specific operation of step S503 is to establish a logic-to-entity mapping table based on the distribution of each entity window and the number of valid entity procedural units from the starting entity window to the current entity window.

[0065] Specifically, a logic-to-entity mapping table is established based on the distribution of each entity window and the number of valid procedural units from the starting entity window to the current entity window; further operations include... Figure 8 As shown, it includes sub-steps S5031 and S5032.

[0066] Sub-step S5031: Compare the address value of the target logical entity programmed unit with the number of valid entity programmed units from the starting entity window to the current entity window, and take the minimum value among all numbers greater than or equal to the target logical entity programmed unit to determine the target entity window to which the entity programmed unit corresponding to the target logical entity programmed unit belongs.

[0067] For example, taking the entity unit containing 128 entity programmable units as an example, a mapping table for entity programmable unit P80 needs to be established, such as... Figure 6 As shown, given the existence of 12 invalid entity programmatic units (P1, P6, P16, P23, P25, P33, P40, P44, P50, P52, P56, and P69) before P80, the following implementation is achieved: Figure 9 The results shown are from L68 to P80. The specific operation is based on... Figure 7 The entity window table described in the document searches for entity windows with ≥69 "0" characters (this is because Logical68 is actually the 69th valid entity procedural unit). For example... Figure 7As shown, there are 5 entity windows A7, A8, A9, A10, and A11 with the number of "0"s greater than 69, which are 75, 84, 93, 103, and 108 respectively. The entity window A7 with the minimum number of "0"s (75) is taken to determine the target entity window to which Logia68 belongs.

[0068] Sub-step S5032: Calculate the address value of the starting entity programmable unit in the target entity window according to the sequence number and interval value of the entity window, determine the address of the entity programmable unit corresponding to the target logical entity programmable unit, establish a mapping relationship between the target logical entity programmable unit and the corresponding entity programmable unit, and establish a logic-to-entity mapping table between logical entity programmable units in the entity unit and entity programmable units according to the mapping relationship.

[0069] For example, as mentioned above, entity window A7 has a sequence number of 7 and an interval value of 11; 7 * 11 = 77, where 77 is the address value of the starting entity programming unit in entity window A7, i.e., the starting entity programming unit in entity window A7 is P77. Furthermore, based on the interval value of 11, this indicates that entity window A7 has 11 entity programming units, namely P77, P78, P79, P80, P81, P82, P83, P84, P85, P86, and P87, with address values ​​of 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, and 87, respectively. The initial entity programming unit P77 is determined. Mapping management starts from P77 in entity window A7. After four traversals, when traversing to P80, the mapping management from L68 to P80 can be established. The mapping relationship is loaded into the logical-to-entity mapping table. Alternatively, a logical-to-entity mapping table can be constructed using this mapping management method. This is so that when data is accessed from the host system to the memory module, the logical-to-entity mapping table can be used to access the data from the host system to the memory module.

[0070] The above mapping management method first determines the target entity window to which the target logical entity programmed unit belongs, and then performs a finite number of mapping traversals within the target entity window to establish a mapping from the target logical entity programmed unit to the corresponding entity programmed unit. The number of mapping traversals is, of course, less than the specified interval. The logical-to-entity mapping table constructed based on this mapping management method, when used in the memory storage device 12 and memory module 122, can improve the speed of data access from the host system 11 to the memory module 122. Even if the memory storage device 12 and memory module 122 include invalid entity programmed units, using the logical-to-entity mapping table constructed using this mapping management method for data access can still improve the speed of data access from the host system 11 to the memory module 122.

[0071] In one embodiment, the address value of the entity programmable unit in the logic-to-entity mapping table is 1 bit.

[0072] For example, in the data read / write process, the existing solution is to store the physical address value of each entity programmable unit in the buffer memory 1235 to realize data read / write. The physical address value of the entity programmable unit includes the entity unit address and the entity programmable unit address, and the size of each entity programmable unit's physical address value is 5 bytes (40 bits). For example, to implement L68---P80 in the existing technology, the size of the buffer memory 1235 needs to be 5 bytes * 128 = 640 bytes; therefore, to implement data read / write operations under this page mapping mode, it requires 400 bytes of space in the buffer memory 1235.

[0073] In one embodiment, if the buffer memory 1235 is SRAM (Static Random-Access Memory), the size of SRAM is generally 4K-8K bytes. The number of physical programmable units required for data reading and writing in the memory module 122 is much greater than 128. Therefore, the data reading and writing speed of the memory module 122 under this page mapping management mode will be very slow.

[0074] like Figure 6 and 7As shown, in the entity unit status bitmap and entity window table, "1" represents an entity programmable unit in a failed state, and "0" represents an entity programmable unit in a valid state. Furthermore, the mapping management method for logical entity programmable units to entity programmable units in this application's logic-to-entity mapping table determines the physical address of the entity programmable unit corresponding to the logical entity programmable unit by calculating the number of "0"s and finding the address value corresponding to each "0". Since the size of "0" in the mapping table is 1 bit, the address value of the entity programmable unit in the logic-to-entity mapping table is also 1 bit; this reduces the size of the logic-to-entity mapping table.

[0075] In one embodiment, the method for calculating the address value of the starting entity programming unit in the target entity window based on the entity window's sequence number and interval value, and determining the address of the entity programming unit corresponding to the target logical entity programming unit, specifically further includes:

[0076] After determining the target entity window to which the target logical entity programmable unit belongs, the address of the entity programmable unit corresponding to the target logical entity programmable unit is determined by traversing the window a number of times less than or equal to the interval value.

[0077] For example, the number of times the corresponding entity program unit is traversed or queried in L68-P80 is 4, which is less than or equal to 11 (interval value).

[0078] S504: Data is accessed from the host system to the memory storage device based on the logical-to-entity mapping table.

[0079] Furthermore, based on the logic-to-entity mapping table described in this application, data is accessed from the host system to the memory storage device. During the data read / write process, the status bitmap and interval value are stored in the buffer memory 1235. In this embodiment, the size stored in the buffer memory 1235 is the number of "0"s, and the storage capacity required for one "0" is 1 bit. In one embodiment, the buffer memory 1235 is SRAM (Static Random-Access Memory), and its size is half 4K-8K bytes, which can store 32-64K "0"s at a time; that is, 32-64K valid entity programmable units. Assuming a single entity programmable unit (EPU) is 16KB, if 500MB of data (16KB * 32KB) is stored from the host system 11 to the memory storage device 12, even if the SRAM is only 4KB in size, the physical address of the EPU can be loaded into the SRAM in one go, quickly transferring 500MB of data from the host system 11 to the memory storage device 12. Similarly, data can be read from the memory storage device 12 to the host system 11 in one go. Therefore, applying the logical-to-entity mapping table constructed using the above method to the memory storage device 12 and the memory module 122 can significantly improve the speed of accessing large files and large amounts of data from the host system to the memory storage device 12 and the memory module 122.

[0080] The logic-to-entity mapping management method described above makes the mapping management from logic programmatic units to entity programmatic units very fast. When performing target logic-to-entity mapping management, the target entity window to which the entity programmatic unit corresponding to the target logic entity programmatic unit belongs is determined first. Then, the address of the entity programmatic unit corresponding to the target logic entity programmatic unit can be determined after only a limited number of traversals. The entity programmatic unit corresponding to the logic entity programmatic unit can be determined quickly without using the "page-by-page" traversal page mapping method to build the logic-to-entity mapping table.

[0081] Figure 10 This is a schematic diagram of the "multi-page" page mapping method, as shown below. Figure 10As shown, during the mapping management process, when entity programming units 0-3 are all valid entity programming units, the mapping between logical entity programming units 0-3 and entity programming units 0-3 can be very fast. However, when entity programming unit 4 is an invalid entity programming unit, logical entity programming unit 4 must skip the invalid entity programming unit 4 and its next valid entity programming unit, namely entity programming unit 5, for mapping. If entity programming unit 5 is also an invalid entity programming unit, it continues to jump to the next valid entity programming unit until it jumps to an entity programming unit in a valid state. Based on this "page-by-page" traversal page mapping method, it will be affected by invalid entity programming units. If the number of invalid entity programming units in an entity unit is not large compared to the total number of entity units, it will not have a significant impact on the data read and write speed of the memory storage device 12 containing such entity units. However, if the memory storage device 12 contains a large number of such entity units, it will significantly affect the data read and write speed of the memory storage device 12.

[0082] Furthermore, the logic-to-entity interval calculation method proposed in this application calculates the interval value of the entity unit based on the actual situation of the entity unit, such as the total number of entity programmable units; it is understood that the interval value of the entity unit is different depending on the total number of entity units. The logic-to-entity mapping table of the memory module 122 is constructed based on the interval value, thereby improving the speed of data access from the host system 11 to the memory storage device 12.

[0083] In one embodiment, this application also proposes a memory storage device 12, which includes: a connection interface 121 for connecting to a host system 11; a memory module 122 including at least one physical unit; and a memory controller 123 connected to the connection interface 121 and the memory module 122; wherein the memory controller can... Figure 5 and Figure 8 The data access method is applied to the memory controller 123. Figure 5 and Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 5 and Figure 8 Each step can be operated as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 5 and Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0084] In one embodiment, this application also proposes a memory controller 123 for controlling a memory module 122, wherein the memory module 122 includes at least one physical unit, and the memory controller 123 includes: a host interface 1231 for connecting to a host system 11; a memory interface 1232 for connecting to the memory module 122; and a memory control circuit 1233 connected to the host interface 1231 and the memory interface 1232; wherein the memory controller can control the memory module 122. Figure 5 and Figure 8 The data access method is applied to the memory control circuit 1233. Figure 5 and Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 5 and Figure 8 Each step can be operated as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 5 and Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0085] In summary, this application proposes a data access method and a logic-to-entity mapping table construction method. Applying the above method to the memory storage device 12 and the memory module 122 can significantly improve the speed of accessing large files and large data from the host system to the memory storage device 12 and the memory module 122.

[0086] Furthermore, this application also proposes a logic-to-entity interval value calculation method, which calculates the interval value of an entity unit based on the actual situation of the entity unit, such as the total number of entity programmable units. It is understood that the interval value of an entity unit will differ depending on the total number of entity units. The logic-to-entity mapping table of the memory module 122 is constructed based on the interval value, thereby improving the speed of data access from the host system 11 to the memory storage device 12. The memory storage device 12 and memory module 122, applied to the data access method, the logic-to-entity mapping table construction method, and the logic-to-entity interval value calculation model construction method, can significantly improve the speed of large files and large data access from the host system to the memory storage device 12 and memory module 122. Even if the SRAM capacity in the memory storage device 12 and memory module 122 is small, this application embodiment can still improve the speed of data access from the host system to the memory module for large files.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data access method, characterized in that, A memory storage device, wherein the memory storage device includes a memory module, the memory module includes at least one physical unit, the physical unit includes a plurality of physical programmable units, and the data access method includes: The entity unit is subjected to erase, data write, and data read / write test operations to establish a state bitmap of the entity unit. The state bitmap is used to store the management information of the entity unit. The management information includes the total number of entity programmable units of the entity unit, the number of entity programmable units with a valid state, and the address value of the valid entity programmable units in the entity unit. Based on an interval value and the state bitmap, the entity unit is divided into multiple entity windows, and an entity window table of the multiple entity windows is constructed. The address value of the target logical entity programmable unit is compared with the number of valid entity programmable units from the starting entity window to the current entity window. Among all the numbers greater than or equal to the target logical entity programmable unit, the minimum value of the target number is taken to determine the target entity window to which the entity programmable unit corresponding to the target logical entity programmable unit belongs. The address value of the starting entity programmable unit in the target entity window is calculated based on the sequence number of the entity window and the interval value. The address of the entity programmable unit corresponding to the target logical entity programmable unit is determined. A mapping relationship is established between the target logical entity programmable unit and the corresponding entity programmable unit. A logic-to-entity mapping table is established based on the mapping relationship between the logical entity programmable units in the entity unit and the entity programmable units. Data is accessed from the host system to the memory storage device based on the logic-to-entity mapping table.

2. The data access method according to claim 1, characterized in that, In the state bitmap of the entity unit, "1" represents an entity unit that is in a failed state, and "0" represents an entity unit that is in a valid state.

3. The data access method according to claim 1, characterized in that, The entity window comprises multiple entity programming units consisting of valid entity programming units and / or invalid entity programming units.

4. The data access method according to claim 1, characterized in that, The entity window table storage contains the distribution of each entity window and the number of valid entity programmatic units from the starting entity window to the current entity window.

5. The data access method according to claim 1, characterized in that, The specific operation method for calculating the address value of the starting entity programming unit in the target entity window based on the entity window number and the interval value, and determining the address of the entity programming unit corresponding to the target logical entity programming unit, further includes: After determining the target entity window to which the target logical entity programmable unit belongs, the address of the entity programmable unit corresponding to the target logical entity programmable unit is determined by traversing the window a number of times less than or equal to the interval value.

6. The data access method according to claim 1, characterized in that, In the logic-to-entity mapping table, the address value of the entity programmable unit is 1 bit.

7. The data access method according to claim 1, characterized in that, The interval value is a prime number.

8. The data access method according to claim 7, characterized in that, When the total number of entity programmatic units of the entity unit is ≤200, the interval value is <10.

9. The data access method according to claim 7, characterized in that, When 200 < the total number of entity programmatic units of the entity unit ≤ 500, the interval value < 20.

10. The data access method according to claim 7, characterized in that, When 500 < the total number of entity programmatic units of the entity unit ≤ 1000, the interval value < 30.

11. The data access method according to claim 7, characterized in that, When 1000 < the total number of entity programmatic units of the entity unit ≤ 2000, the interval value < 40.

12. The data access method according to claim 7, characterized in that, When the total number of entity programmatic units of the entity unit is greater than 2000, the interval value is less than 50.

13. A memory storage device, comprising: Connection interface, used to connect to the host system; A memory module comprising at least one physical unit; And a memory controller, which is connected to the connection interface and the memory module; The memory controller is characterized in that it is configured to execute the data access method as described in any one of claims 1-12.

14. A memory controller for controlling a memory module, wherein the memory module includes at least one physical unit, and the memory controller includes: Host interface, used to connect to the host system; A memory interface for connecting to the memory module; as well as A memory control circuit connected to the host interface and the memory interface; characterized in that the memory control circuit is used to execute the data access method as described in any one of claims 1-12.

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