Resource allocation method, buffer status control method and related devices

Abstract

Embodiments of the present application provide a resource allocation method, a cache state control method and related devices, the resource allocation scheme groups nodes in a computer architecture, and uses a peripheral controller to evenly allocate the peripheral storage space of peripheral devices in a node group to each node in the node group, thereby ensuring the symmetry of the storage of each node in the node group in the computer architecture, and thereby ensuring the symmetry of the storage of each node in the computer architecture to a certain extent at the premise of increasing the control cost of a small number of peripheral controllers.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, specifically to a resource allocation method, a cache state control method, and related equipment. Background Technology

[0002] NUMA (Non-Uniform Memory Access) architecture is a multi-core chip architecture consisting of several independent nodes connected by a high-speed dedicated network. In a NUMA architecture, the nodes can access each other's data.

[0003] Symmetry in node storage refers to the fact that, in a NUMA architecture, the storage resources (i.e., the storage space allocated to each node) tend to be equal across all nodes. By ensuring the symmetry of node storage, hardware support is provided for the even distribution of data across all nodes in a NUMA architecture, thereby ensuring the evenness of data access across all nodes and avoiding data access congestion caused by multiple nodes accessing a single node simultaneously.

[0004] However, in NUMA architectures that include peripheral devices supporting the CXL (Compute Express Link) protocol, the symmetry of node storage is difficult to guarantee. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a resource allocation method, a cache state control method, and related devices, which can ensure the symmetry of node storage to a certain extent.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] This invention provides a computer architecture, including:

[0008] Multiple nodes, the multiple nodes are divided into at least one node group, and at least one peripheral controller and peripheral devices configured to the peripheral controller are configured in a node group, the peripheral devices having peripheral storage space;

[0009] The peripheral controller is used to evenly distribute the peripheral storage space to each node in the node group, so that each node is allocated a set of peripheral subspaces.

[0010] Optionally, the peripheral controller divides its configured peripheral storage space into a preset number of peripheral subspaces, the preset number of peripheral subspaces corresponding to a preset number of system addresses, wherein the preset number is equal to the number of nodes in the node group, and one group of system addresses corresponds to one node.

[0011] Optionally, each node is configured with a computing core, a memory controller, and a listening detector, wherein the listening detector arbitrates and selects the state processing request to be processed based on the storage space source corresponding to the state processing request.

[0012] The storage space sources corresponding to the state processing request include the memory storage space managed by each memory controller configured on the node, and the peripheral subspace maintained by each peripheral controller configured in the node group for that node; wherein, a peripheral controller maintains a set of peripheral subspaces for a node in the node group.

[0013] Optionally, there may be multiple node groups, and the multiple nodes may be evenly distributed among multiple node groups.

[0014] Optionally, the access latency between nodes assigned to a node group is less than or equal to a preset value.

[0015] Optionally, within the node group, the number of peripheral controllers is determined based on the number of nodes corresponding to the hardware where the peripheral device is located.

[0016] Optionally, the peripheral controller is evenly distributed among multiple node groups.

[0017] This invention also provides a resource allocation method applied to a peripheral controller in a computer architecture. The peripheral controller is configured with peripheral devices, and the peripheral devices have peripheral storage space. The computer architecture includes multiple nodes, which are divided into at least one node group. At least one peripheral controller is configured in each node group. The method includes:

[0018] Obtain peripheral storage space information of peripheral devices configured to the peripheral controller. The peripheral storage space information is used to indicate the attribute information of the peripheral storage space, and the attribute information includes the identification information and capacity information of the peripheral storage space.

[0019] Based on the peripheral storage space information, the peripheral storage space is evenly distributed to each node in this node group so that each node is allocated a set of peripheral subspaces.

[0020] Optionally, the step of evenly distributing the peripheral storage space among the nodes in this node group includes:

[0021] Determine the number of nodes within the node group;

[0022] The peripheral storage space is divided into a preset number of peripheral subspaces, and the preset number of peripheral subspaces correspond to a preset number of system addresses. The preset number is equal to the number of nodes in the node group, and one system address corresponds to one node, so that each node is assigned a peripheral subspace corresponding to a set of system addresses of the corresponding peripheral controller.

[0023] This invention also provides a cache state control method applied to a listening detector in a computer architecture. The listening detector maintains a storage state record table, which records the cache state of data in the storage space corresponding to the computing core. The storage space has multiple storage space sources, including memory storage space managed by memory controllers configured on nodes, and peripheral subspaces maintained by peripheral controllers configured within a node group for that node. Each peripheral controller allocates a set of storage space evenly to a node within the node group. The method includes:

[0024] Get status processing request;

[0025] Based on the storage space source corresponding to the status processing request, the arbitration selects the status processing request to be processed.

[0026] Process the selected pending status processing requests.

[0027] Optionally, the arbitration to select pending status processing requests can be specifically based on a polling algorithm or a weighted polling algorithm.

[0028] Optionally, the pending status processing request is a status query request, and the selected pending status processing request includes:

[0029] Based on the target address and original command type information in the status query request, query the status of the target address recorded in the storage status record table;

[0030] The response returns the status of the target address in the cache.

[0031] Optionally, the pending state processing request is a state update request, and the pending state processing request selected by the processing includes:

[0032] Based on the target address and the update status information to be updated in the status update request, the status recorded in the storage status record table of the target address is updated to the status corresponding to the update status information.

[0033] The response returns the update result, which indicates whether the update was successful.

[0034] This invention also provides a resource allocation device applied to a peripheral controller in a computer architecture. The peripheral controller is configured with peripheral devices, and the peripheral devices have peripheral storage space. The computer architecture includes multiple nodes, which are divided into at least one node group. At least one peripheral controller is configured in each node group. The resource allocation device includes:

[0035] The information acquisition module is used to acquire peripheral storage space information of peripheral devices configured to the peripheral controller. The peripheral storage space information is used to indicate the attribute information of the peripheral storage space, and the attribute information includes the identification information and capacity information of the peripheral storage space.

[0036] The resource allocation module is used to evenly distribute the peripheral storage space to each node in the node group based on the peripheral storage space information, so that each node is allocated a set of peripheral subspaces.

[0037] This invention also provides a cache state control device applied to a listening detector in a computer architecture. The listening detector maintains a storage state record table, which records the cache state of data in the storage space corresponding to the computing core. The storage space has multiple storage space sources, including memory storage space managed by memory controllers configured on nodes, and peripheral subspaces maintained by peripheral controllers configured within a node group for that node. Each peripheral controller allocates a set of storage space evenly to a node within the node group. The cache state control device includes:

[0038] An arbitration unit is used to obtain a status processing request and, based on the storage space source corresponding to the status processing request, arbitrate and select a status processing request to be processed.

[0039] The request processing unit is used to process the selected pending status processing requests.

[0040] Optionally, the request arbitration unit is a multi-choice arbitrator, which is determined based on the number of storage space sources.

[0041] This invention also provides a storage medium that stores one or more executable instructions, which are used to execute the resource allocation method provided in this invention, or to execute the cache state control method provided in this invention.

[0042] This invention provides a resource allocation method, a cache state control method, and related devices. The resource allocation scheme groups the nodes in the computer architecture and uses a peripheral controller to evenly distribute the peripheral storage space of the peripheral devices in the node group to each node in the node group, thereby ensuring the symmetry of storage of each node in the node group in the computer architecture. Thus, under the premise of increasing the control cost of a small number of peripheral controllers, the symmetry of storage of each node in the computer architecture is guaranteed to a certain extent.

[0043] Meanwhile, based on the resource allocation scheme within the node group, access to the storage space allocated to the node can be achieved by controlling access to the storage status record table that records the access status of the storage space. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0045] Figure 1 An optional structural diagram of a computer architecture provided in an embodiment of the present invention;

[0046] Figure 2 An optional flowchart of a resource allocation method provided in an embodiment of the present invention;

[0047] Figure 3 A schematic diagram illustrating the resource allocation process of a peripheral controller provided in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the structure of the storage status record table provided in an embodiment of the present invention;

[0049] Figure 5 An optional flowchart of a cache state control method provided in an embodiment of the present invention;

[0050] Figure 6 This is an optional block diagram of a resource allocation device provided in an embodiment of the present invention;

[0051] Figure 7 This is an optional block diagram of a cache state control device provided in an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] As described in the background section, in a NUMA architecture that includes peripheral devices supporting the CXL protocol, the symmetry of node storage is difficult to guarantee. The inventors point out that this is because the CXL protocol, which supports hot-swapping, is used by peripheral devices supporting the CXL protocol. Therefore, the number of peripheral devices inserted into different nodes in a NUMA architecture is variable, and the hardware parameters (e.g., storage capacity, bandwidth) of different peripheral devices are also uncertain. Under these circumstances, ensuring the symmetry of storage across nodes in a NUMA architecture has become a technical problem that urgently needs to be solved by those skilled in the art.

[0054] The inventors believe that the peripheral storage space of peripheral devices can be evenly distributed to each node of the NUMA architecture through the peripheral controller to ensure the symmetry of storage among the nodes in the NUMA architecture. However, considering that there are too many nodes in the NUMA architecture, if the peripheral storage space of peripheral devices is directly allocated, the control cost of the peripheral controller will be too high, which will seriously affect the access efficiency of the peripheral storage space. Obviously, this resource allocation method is unreasonable.

[0055] Therefore, the inventors further propose the resource allocation scheme of the present invention, that is, to group the nodes in the computer architecture and use the peripheral controller to evenly distribute the peripheral storage space of the peripheral devices in the node group to each node in the node group, thereby ensuring the symmetry of the storage of each node in the node group in the computer architecture. Thus, under the premise of increasing the control cost of the peripheral controller by a small amount, the symmetry of the storage of each node in the computer architecture is guaranteed to a certain extent.

[0056] Meanwhile, based on the resource allocation scheme within the node group, access to the storage space allocated to the node can be achieved by controlling access to the storage status record table that records the access status of the storage space.

[0057] Below, in conjunction with Figure 1 The illustrated optional computer architecture diagram provides a detailed explanation of the resource allocation scheme of this embodiment of the invention.

[0058] For details, please refer to Figure 1The computer architecture shown includes multiple nodes, which are divided into at least one node group. This example illustrates an architecture with 8 nodes divided into 2 node groups. It should be noted that in other examples, when the number of nodes in the computer architecture is small, it can be divided into one node group; when the number of nodes is large, it can be divided into multiple node groups. This invention does not impose a specific limitation here. The number of nodes within a node group can be determined based on the control cost of the peripheral controller in the computer architecture and the data processing cost of the listening detector on the storage state record table. The storage state record table is used to record the access status of storage space in the cache. The storage space includes memory storage space, peripheral storage space, etc., and the access status of storage space in the cache is also called space access status.

[0059] The node grouping can be based on the access latency between nodes. Nodes with shorter access latency can be grouped into one node group, while nodes with longer access latency can be grouped into different node groups. Specifically, the access latency between nodes assigned to a node group can be less than or equal to a preset value. This preset value can be determined based on the range of access latency between nodes; for example, the preset value can be the average duration of the access latency between nodes. This invention does not impose a specific limitation on this.

[0060] Dividing node groups based on the access latency between nodes can avoid excessive latency in accessing the peripheral storage space of peripheral devices (not shown in the figure) between nodes, thereby improving the access efficiency of the computing system.

[0061] In this embodiment of the invention, the node groups are divided into equal groups, meaning the number of nodes assigned to each group is equal. For example, when there are 16 nodes, they can be divided into 2 or 4 node groups, with each group containing the same number of nodes. When the 16 nodes are divided into 2 node groups, each group may contain 8 nodes; when the 16 nodes are divided into 4 node groups, each group may contain 4 nodes.

[0062] In the aforementioned computer architecture, each node is configured with a computing core, a memory controller, and a listening detector, as shown in the reference. Figure 1 The computer architecture shown comprises 8 nodes, which are divided into 2 node groups, each containing 4 nodes. In terms of hardware, the computer architecture consists of 2-way CPUs, each containing 32 computing cores, an 8-channel memory controller, a 4-channel I / O (input / output) controller, and a 4-channel peripheral controller.

[0063] It should be noted that the number of peripheral controllers within a node group can be determined based on the number of nodes corresponding to the hardware where the configured peripheral device resides. When there is only one node corresponding to the hardware where the peripheral device resides, only one peripheral controller can be configured. When there are multiple nodes corresponding to the hardware where the peripheral device resides, multiple peripheral controllers can be configured. In this example, we will illustrate the concept by assuming that each node is configured with a peripheral controller.

[0064] In specific examples, if there are multiple node groups, the peripheral controllers can be evenly distributed among the multiple node groups from an overall perspective, thereby further improving the symmetry of the computer architecture in terms of hardware resources.

[0065] In this embodiment of the invention, each peripheral controller (i.e., each peripheral controller) divides its configured peripheral storage space into a preset number of peripheral subspaces, thereby evenly distributing the peripheral storage space to each node within the node group, so that each node is allocated a set of peripheral subspaces (not shown in the figure). The preset number of peripheral subspaces corresponds to a preset number of system address arrays, wherein the preset number is equal to the number of nodes in the node group, and one set of system addresses corresponds to one node. In this example, each peripheral controller maintains 4 sets of system addresses, and each set of system addresses corresponds to one node.

[0066] In terms of node allocation, each CPU can be assigned to a node group. Each node group includes 4 nodes (nodes 0, 1, 2 and 3 in the diagram form one node group, and nodes 4, 5, 6 and 7 form another node group). Each node can include 8 computing cores (shown as 8xCPU in the diagram), 2 memory controllers, 1 I / O controller, and 4 sets of peripheral controllers maintaining system addresses (in this example, the node group includes 4 peripheral controllers, and each peripheral controller maintains 1 set of system addresses for one node, thus corresponding to 4 sets of system addresses).

[0067] For details, please refer to Figure 2 The flowchart shown represents an optional resource allocation method, corresponding to a peripheral controller. The corresponding resource allocation method may include:

[0068] Step S100: Obtain peripheral storage space information of peripheral devices configured to the peripheral controller;

[0069] The peripheral device is configured to the peripheral controller, which enables data interaction between the peripheral device and the computer architecture. The peripheral controller and the peripheral device are associated through corresponding configuration relationships.

[0070] When the computer architecture configures peripheral devices for the peripheral controller, the peripheral controller can first obtain the peripheral storage space information corresponding to the peripheral device. The peripheral storage space information is used to indicate the attribute information of the peripheral storage space. The attribute information includes the identification information, capacity information, etc. of the peripheral storage space, so as to determine the attribute information corresponding to the peripheral storage space of the peripheral device.

[0071] Taking the example of a peripheral controller mounting X memory devices (i.e., configuring X peripheral storage devices for the peripheral controller), the peripheral controller can determine the X memory devices based on the identification information and determine the capacity information of the peripheral storage space of the X memory devices based on the capacity information.

[0072] Step S110: Based on the peripheral storage space information, the peripheral storage space is evenly distributed to each node in this node group so that each node is allocated a set of peripheral subspaces;

[0073] After obtaining the peripheral storage space information of the corresponding peripheral device, the peripheral controller can evenly distribute the peripheral storage space to each node in the node group, thereby ensuring the symmetry of node storage to a certain extent.

[0074] In a specific example, the peripheral controller can first determine the number Y of nodes within the node group, and then refer to... Figure 3 The diagram illustrates the resource allocation process of the peripheral controller. The peripheral storage space (using X peripheral storage devices configured on the peripheral controller as an example) is evenly distributed into Y groups of peripheral subspaces matching the number of nodes. The addresses corresponding to the Y groups of peripheral subspaces are configured with Y groups of system addresses, ensuring that each node is assigned a peripheral subspace corresponding to one group of system addresses for its peripheral controller. Address mapping can be used to convert between the physical addresses and system addresses of the peripheral storage space.

[0075] It should be noted that, in order to improve the efficiency of storage access, when accessing data within a node, the system addresses maintained by the two memory controllers within the node can be accessed in an interleaved manner, and the system addresses maintained by the four sets of peripheral controllers within the node can also be accessed in an interleaved manner.

[0076] Meanwhile, in the computer architecture, based on the resource allocation scheme within the node group, the node can control the cache status through a storage status record table that records the space access status, thereby realizing access control over the storage space allocated to the node.

[0077] The computing architecture may also include a snoop filter. Each node is configured with a snoop filter to control access to the storage space allocated to that node. Specifically, the snoop filter records the state of the storage space allocated to the node in the cache. This storage space may include memory storage space managed by the memory controller and peripheral subspace managed by the peripheral controller.

[0078] Specifically, the eavesdropping detector may include a storage state record table. This table records the cache status of data from different storage sources within the computing core, thereby determining the data access process based on the corresponding cache status. For example, when data in different storage spaces is shared in the computing core's cache, the data access process can retrieve the cached data from that storage space, eliminating the need to transfer the data to the storage space. Since the speed of reading data between caches is much higher than reading from the storage space, retrieving cached data from the cache reduces data access latency and increases data access speed compared to transferring the data to the storage space.

[0079] refer to Figure 4 The diagram illustrates the structure of the storage state record table. This table can record information including a data identifier, a data owner ID, and a cache state. The data identifier records the system address of the storage space where the data resides; the data owner ID records the identifier of the computing core on which the data is cached; and the cache state records the status of the data in the cache. The cache state records support MESI 4-state cache states: I (Invalid), S (Shared), E (Exclusive), and M (Modified). I indicates that the corresponding data is invalid; S indicates that the corresponding data is shared (shared by multiple computing cores); E indicates that the corresponding data is exclusively used (exclusively used by a single computing core); and M indicates that the corresponding data is modified (modified by a single computing core). Each system address corresponds to one state entry, and each state entry records the corresponding information. Multiple state entries form a storage array, serving as the storage state record table.

[0080] In a specific example, the system address can be identified using 40 bits, each listener tracks and records 8 MBytes of cache space, and the system cache line size is 64 bytes. Correspondingly, in the storage state record table, 18 bits can be used to record the 22nd to 5th bits of the system address of the current cache line (the system address is 40 bits in total; since the cache line size is 64 bytes, the lower 5 bits are not recorded), 5 bits can be used to record the core ID corresponding to the data owner of the current cache line (there are 64 cores in total, which can be fully identified with 5 bits), and 2 bits can be used to record the state of the current cache line (there are 4 states in total, which can be fully identified with 2 bits). Therefore, the width of the storage device used in the listener to record the storage state record table can be configured to 25 bits, and the depth can be configured to 131072 (128K = 128 * 1024).

[0081] Accordingly, refer to Figure 5 The diagram illustrates an optional flowchart of a cache state control method. In this embodiment of the invention, during the data access process, a listening detector is used to execute the cache state control method, which includes:

[0082] Step S200: Obtain the status processing request;

[0083] The state processing request is an intra-node state processing request, which may include a state query request and a state update request. The state query request checks whether the data corresponding to the required storage space exists in the storage state record table, and executes the corresponding access process based on the query result. The state update request updates the record of the data corresponding to the accessed storage space in the storage state record table based on the access result. For example, when a computing core exclusively uses certain data, it needs to update the cache status of the corresponding data in the storage state record table to an exclusive status.

[0084] It should be noted that in the data access process, data access is generally processed in parallel with multiple instructions. Accordingly, multiple status processing requests can be obtained at the same time.

[0085] Step S210: Based on the storage space source corresponding to the state processing request, the arbitration selects the state processing request to be processed;

[0086] The storage space source corresponding to the state processing request may include the memory storage space managed by each memory controller configured on the node, and the peripheral subspace maintained by each peripheral controller configured in the node group for the node; wherein, a peripheral controller allocates a set of peripheral subspaces equally to a node in the node group.

[0087] Specifically, in the computer architecture provided in this invention example, the storage space source may include the memory storage space of two memory controllers and the peripheral subspace corresponding to four sets of system addresses maintained by four peripheral controllers. Correspondingly, the arbitration selection of the pending status processing request can be based on a 6-to-1 arbitrator.

[0088] The arbitration selection can be based on a round-robin algorithm or a weighted round-robin algorithm, that is, different weights are set for different sources, and the larger the weight, the greater the probability of arbitration selection.

[0089] Step S220: Process the selected pending status processing requests;

[0090] After selecting a status processing request to be processed, the status processing request can be processed.

[0091] If the status processing request to be processed is a status query request, then the status of the target address recorded in the storage status record table can be queried based on the target address and original command type information in the status query request, and after the query, the status of the target address in the cache can be returned in the response.

[0092] In a specific example, corresponding to a status query request, the high 17 bits of the target address can be used as the valid address bits to query the stored status record table. Simultaneously, based on the query results and the original command type information, a status update request can be further issued to update the recorded cached status.

[0093] If the status processing request is a status update request, then based on the target address and the update status information to be updated in the status update request, the status recorded in the storage status record table of the target address can be updated to the status corresponding to the update status information. After the update, the response returns the update result, which is used to indicate whether the update was successful.

[0094] In a specific example, if the updated state is I, i.e. invalid state, the listening detector can further delete the record corresponding to the target address; otherwise, the cache state is updated to the state corresponding to the updated state information.

[0095] As can be seen, the embodiments of the present invention, based on the resource allocation scheme within the node group, can achieve access to the storage space allocated to the node by controlling access to the storage status record table that records the access status of the storage space.

[0096] The resource allocation device and cache state control device provided in the embodiments of the present invention will be described below. The resource allocation device and cache state control device described below can be considered as functional modules required to implement the resource allocation method and cache state control method provided in the embodiments of the present invention. The contents of the cache state recording device and data access device described below can be referred to in correspondence with the method contents described above.

[0097] In the optional implementation, Figure 6 This diagram illustrates an optional block diagram of a resource allocation device provided in an embodiment of the present invention. This resource allocation device can be applied to a peripheral controller in a computer architecture. The peripheral controller is configured with peripheral devices, and the peripheral devices have peripheral storage space. The computer architecture includes multiple nodes, which are divided into at least one node group. At least one peripheral controller is configured within each node group. Figure 6 As shown, the resource allocation device may include:

[0098] The information acquisition module 100 is used to acquire peripheral storage space information of peripheral devices configured to the peripheral controller. The peripheral storage space information is used to indicate the attribute information of the peripheral storage space. The attribute information includes the identification information and capacity information of the peripheral storage space.

[0099] The resource allocation module 110 is used to allocate the peripheral storage space equally to each node in the node group based on the peripheral storage space information, so that each node is allocated a set of peripheral subspaces.

[0100] Optionally, the resource allocation module 110 is used to evenly distribute the peripheral storage space among the nodes in the node group, including:

[0101] Determine the number of nodes within the node group;

[0102] The peripheral storage space is divided into a preset number of peripheral subspaces, and the preset number of peripheral subspaces correspond to a preset number of system addresses. The preset number is equal to the number of nodes in the node group, and one system address corresponds to one node, so that each node is assigned a peripheral subspace corresponding to a set of system addresses of the corresponding peripheral controller.

[0103] In the optional implementation, Figure 7An optional block diagram of a cache state control device provided in an embodiment of the present invention is shown. This cache state control device can be applied to a listening detector in a computer architecture. The listening detector maintains a storage state record table, which records the cache state of data in the storage space corresponding to the data in the computing core. The storage space has multiple storage space sources, including memory storage space managed by memory controllers configured on nodes, and peripheral subspaces maintained by peripheral controllers configured within a node group for that node. Each peripheral controller allocates a set of peripheral subspaces evenly to a node within the node group. Figure 7 As shown, the cache state control device may include:

[0104] Arbitration unit 200 is used to obtain status processing requests and, based on the storage space source corresponding to the status processing request, arbitrate and select a status processing request to be processed.

[0105] The request processing unit 210 is used to process the selected pending status processing request.

[0106] Optionally, the arbitration request unit is a multiple-choice arbitrator, which is determined based on the number of storage space sources. Specifically, in the computer architecture provided in this invention example, the storage space sources may include the memory storage space of two memory controllers and the peripheral subspaces corresponding to four sets of system addresses maintained by four peripheral controllers. Correspondingly, the multiple-choice arbitrator can be a 6-to-1 arbitrator.

[0107] Optionally, the request arbitration unit 200 is used to arbitrate and select pending status processing requests, specifically, to arbitrate and select pending status processing requests based on a polling algorithm, or to arbitrate and select pending status processing requests based on a weighted polling algorithm.

[0108] Optionally, the pending status processing request is a status query request, and the request processing unit 210 is used to process the selected pending status processing request, including:

[0109] Based on the target address and original command type information in the status query request, query the status of the target address recorded in the storage status record table;

[0110] The response returns the status of the target address in the cache.

[0111] Optionally, the request processing unit 210 is used for processing state processing requests that are state update requests, and processing the selected state processing requests includes:

[0112] Based on the target address and the update status information to be updated in the status update request, the status recorded in the storage status record table of the target address is updated to the status corresponding to the update status information.

[0113] The response returns the update result, which indicates whether the update was successful.

[0114] This invention also provides a storage medium that stores one or more executable instructions, which are used to execute the resource allocation method provided in this invention, or to execute the cache state control method provided in this invention.

[0115] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0116] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A computer architecture, characterized in that, include: Multiple nodes, the multiple nodes are divided into at least one node group, and at least one peripheral controller and peripheral devices configured to the peripheral controller are configured in a node group, the peripheral devices having peripheral storage space; The peripheral controller is used to evenly distribute the peripheral storage space to each node in the node group, so that each node is allocated a set of peripheral subspaces. Each node is configured with a computing core, a memory controller, and a listening detector. The listening detector is used to maintain a storage state record table, which records the cache state of the data in the storage space corresponding to the computing core. The storage space has multiple storage space sources, including the memory storage space managed by each memory controller configured on the node, and the peripheral subspaces maintained by each peripheral controller in the node group for that node. A peripheral controller maintains a set of peripheral subspaces for one node in the node group.

2. The computer architecture as described in claim 1, characterized in that, The peripheral controller divides its configured peripheral storage space into a preset number of peripheral subspaces. The preset number of peripheral subspaces corresponds to a preset number of system addresses, wherein the preset number is equal to the number of nodes in a node group, and a group of system addresses corresponds to one node.

3. The computer architecture as described in any one of claims 1 to 2, characterized in that, There are multiple node groups, and the multiple nodes are evenly distributed among the multiple node groups.

4. The computer architecture as described in claim 3, characterized in that, The access latency between nodes assigned to a node group is less than or equal to a preset value.

5. The computer architecture as described in claim 3, characterized in that, Within the node group, the number of peripheral controllers is determined based on the number of nodes corresponding to the hardware where the peripheral device is located.

6. The computer architecture as described in claim 3, characterized in that, The peripheral controllers are evenly distributed among multiple node groups.

7. A resource allocation method, characterized in that, A peripheral controller is used in a computer architecture. The peripheral controller is configured with peripheral devices, and the peripheral devices have peripheral storage space. The computer architecture includes multiple nodes, and each node is configured with a computing core, a memory controller, and a listening detector. The listening detector is used to maintain a storage state record table, which records the cache state of data in the storage space corresponding to the computing core. The storage space has multiple storage space sources, including memory storage space managed by memory controllers configured on the nodes, and peripheral subspaces maintained by peripheral controllers configured on the nodes within the node group. The multiple nodes are divided into at least one node group, and each node group has at least one peripheral controller configured. Each peripheral controller maintains a set of peripheral subspaces for one node within the node group. The method includes: Obtain peripheral storage space information of peripheral devices configured to the peripheral controller. The peripheral storage space information is used to indicate the attribute information of the peripheral storage space, and the attribute information includes the identification information and capacity information of the peripheral storage space. Based on the peripheral storage space information, the peripheral storage space is evenly distributed to each node in this node group so that each node is allocated a set of peripheral subspaces.

8. The resource allocation method as described in claim 7, characterized in that, The step of evenly distributing the peripheral storage space to each node within the node group includes: Determine the number of nodes within the node group; The peripheral storage space is divided into a preset number of peripheral subspaces, and the preset number of peripheral subspaces correspond to a preset number of system addresses. The preset number is equal to the number of nodes in the node group, and one system address corresponds to one node, so that each node is assigned a peripheral subspace corresponding to a set of system addresses of the corresponding peripheral controller.

9. A cache state control method, characterized in that, A listening detector applied in a computer architecture is used to maintain a storage state record table, which records the cache state of data in the storage space corresponding to the computing core. The storage space has multiple storage sources, including memory storage space managed by memory controllers configured on nodes, and peripheral subspaces maintained by peripheral controllers configured within a node group for that node. Each peripheral controller maintains a set of peripheral subspaces for one node within the node group. Each node is configured with a computing core, a memory controller, and a listening detector. The method includes: Get status processing request; Based on the storage space source corresponding to the status processing request, the arbitration selects the status processing request to be processed. Process the selected pending status processing requests.

10. The cache state control method as described in claim 9, characterized in that, The arbitration to select pending status processing requests specifically refers to selecting pending status processing requests based on a round-robin algorithm, or selecting pending status processing requests based on a weighted round-robin algorithm.

11. The cache state control method as described in claim 9, characterized in that, The pending status processing request is a status query request, and the pending status processing requests selected by the processing include: Based on the target address and original command type information in the status query request, query the status of the target address recorded in the storage status record table; The response returns the status of the target address in the cache.

12. The cache state control method as described in claim 9, characterized in that, The pending state processing request is a state update request, and the pending state processing requests selected by the processing include: Based on the target address and the update status information to be updated in the status update request, the status recorded in the storage status record table of the target address is updated to the status corresponding to the update status information. The response returns the update result, which indicates whether the update was successful.

13. A resource allocation device, characterized in that, A peripheral controller is used in a computer architecture. The peripheral controller is configured with peripheral devices, and the peripheral devices have peripheral storage space. The computer architecture includes multiple nodes, and each node is configured with a computing core, a memory controller, and a listening detector. The listening detector is used to maintain a storage state record table, which records the cache state of data in the storage space corresponding to the computing core. The storage space has multiple storage space sources, including memory storage space managed by memory controllers configured on the nodes, and peripheral subspaces maintained by peripheral controllers configured on the nodes within the node group for that node; wherein, a peripheral controller maintains a set of peripheral subspaces for a node within the node group. The multiple nodes are divided into at least one node group, and at least one peripheral controller is configured in a node group. The resource allocation device includes: The information acquisition module is used to acquire peripheral storage space information of peripheral devices configured to the peripheral controller. The peripheral storage space information is used to indicate the attribute information of the peripheral storage space, and the attribute information includes the identification information and capacity information of the peripheral storage space. The resource allocation module is used to evenly distribute the peripheral storage space to each node in the node group based on the peripheral storage space information, so that each node is allocated a set of peripheral subspaces.

14. A buffer state control device, characterized in that, A listening detector is applied in a computer architecture. The listening detector maintains a storage state record table, which records the cache state of data in the storage space corresponding to the data in the computing core. The storage space has multiple storage sources, including memory storage space managed by memory controllers configured on nodes, and peripheral subspaces maintained by peripheral controllers configured within a node group for that node. Each peripheral controller maintains a set of peripheral subspaces for one node within the node group. Each node is configured with a computing core, a memory controller, and a listening detector. The cache state control device includes: An arbitration unit is used to obtain a status processing request and, based on the storage space source corresponding to the status processing request, arbitrate and select a status processing request to be processed. The request processing unit is used to process the selected pending status processing requests.

15. A storage medium, characterized in that, The storage medium stores one or more executable instructions, which are used to execute the resource allocation method as described in any one of claims 7 to 8, or to execute the cache state control method as described in any one of claims 9 to 12.

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