A two-wire SPI communication system and method

Abstract

The application belongs to the technical field of digital communication, and discloses a two-wire SPI communication system and method, which comprises a master device and a slave device, wherein the master device and the slave device both comprise a CPU, a bus, an SPI module and a GPIO module; under the use scene of SPI, the CPU is used for the configuration of an SPI register; the SPI module is used for converting the transmitted data into the protocol of SPI and sending out through the GPIO module; the SPI communication line of the master device and the slave device is composed of an SCK clock signal line and a DATA data signal line; the SCK clock signal line is used for synchronizing the clock generated by the master device to the slave device; and the DATA data signal line is used for the bidirectional transmission from the master device to the slave device and from the slave device to the master device. The application saves the IO resource, and the handshake communication not only determines the transmission direction, but also guarantees the effectiveness of data transmission.

Description

Technical Field

[0001] This invention belongs to the field of digital communication technology, and particularly relates to a two-wire SPI communication system and method. Background Technology

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex communication bus proposed by Motorola. The SPI protocol specifies four signal lines used for data communication: ① SCK clock signal line ② MOSI master transmit data slave receive data signal line ③ MISO slave transmit data master receive data signal line ④ CS chip select signal line.

[0003] Depending on the transmission method, SPI can be configured to full-duplex mode, half-duplex mode, receive-only mode, and transmit-only mode.

[0004] Depending on the CPOL configuration, the polarity of the SCK signal in the SPI idle state can be selected (high or low); depending on the CPHA configuration, the clock edge for SPI data sampling can be selected (first or second clock edge). Taking full-duplex mode with CPOL=0 and SPHA=0 as an example, the master device's MISO is connected to the slave device's MOSI, and the master device's MOSI is connected to the slave device's MISO. In the SPI idle state, SCK is low, and both the master and slave devices sample data on the rising edge of SCK and output data on the falling edge of SCK.

[0005] The standard SPI protocol requires a total of 4 I / Os to achieve data communication. In some application scenarios and due to packaging constraints, it is necessary to minimize the number of I / Os. Reducing the number of I / Os helps to reduce the chip area, thereby lowering costs.

[0006] Patent application CN112559424A proposes a method to reduce the number of SPI I / Os. This scheme combines the MISO and MOSI of SPI into a single SDA for bidirectional data transmission via time-division multiplexing. The transmission method involves simultaneously outputting data to the MASTER and inputting data to the SLAVE on the edge of the SCK signal, or vice versa. While this method achieves bidirectional data transmission on the data line, it is difficult to complete data transmission and sampling on the same clock edge. During SLAVE output, the SCK signal generated by the MASTER needs to be transmitted to the SLAVE end to generate data, and then the data is transmitted back to the MASTER end for sampling. This path may have a delay of approximately 40ns depending on the manufacturing process. To ensure correct data sampling, a large amount of buffer needs to be inserted into the CK pin of the MASTER register used for data sampling. This implementation not only increases the difficulty of timing constraints but also increases the chip area due to the large amount of buffer. Summary of the Invention

[0007] The purpose of this invention is to provide a two-wire SPI communication system and method to solve the above-mentioned technical problems.

[0008] To solve the above-mentioned technical problems, the specific technical solution of the two-wire SPI communication system and method of the present invention is as follows: A two-wire SPI communication system includes a master device and a slave device. Both the master and slave devices include a CPU, a bus, an SPI module, and a GPIO module. In the SPI usage scenario, the CPU is used for configuring the SPI registers, and the SPI module is used to convert the data to be sent into the SPI protocol and send it through the GPIO module. The SPI communication line between the master and slave devices consists of an SCK clock signal line and a DATA data signal line. The SCK clock signal line is used to synchronize the clock generated by the master device to the slave device; the DATA data signal line is used for bidirectional transmission between the master device and the slave device.

[0009] Furthermore, the master device and the slave device communicate via handshake signals, which include a request signal sent by the master device, a read / write control signal sent by the master device, and a response signal sent by the slave device.

[0010] Furthermore, the SCK signal during the handshake between the master and slave devices is either high or low depending on the CPOL configuration.

[0011] Furthermore, the handshake signal is generated by the SPI clk driver inside the SPI, which is the internal clock of the SPI, derived from the clock of the system bus. The SPI clk of the master device and the slave device are at the same frequency but not synchronized. The handshake signal level width of the two-wire SPI is at least three SPI clk clock cycles, and the handshake signal level width is configured by software.

[0012] This invention also discloses a communication method for a two-wire SPI communication system, comprising the following steps: Step 1: After the master device is enabled, it sends a high-level signal and a low-level signal in sequence, followed by a read / write control signal. A high level indicates that the master device is transmitting to the slave device, and a low level indicates that the slave device is transmitting to the master device. After the master device sends the read / write control signal, it no longer drives the DATA line and waits for the slave device to respond to the request. Step 2: After being enabled, the slave device continuously samples changes on the DATA line. After sampling a high-low level transition, it then samples the read / write control signal. The slave device selects whether to accept the master device's request based on the current state. When the slave device can accept the master device's request, it drives the DATA line to send high-level and low-level signals sequentially. When the slave device cannot accept the master device's request, it drives the DATA line to send low-level and high-level signals sequentially. Step 3: The master device determines whether data transmission can begin based on the sampled response signal. If the slave device can accept it, data transmission will begin on the SCK clock signal line and the DATA data signal line. If the slave device cannot accept it, the master device generates an error interrupt signal and waits for the CPU to process it.

[0013] Furthermore, the GPIO behaves as a tri-state gate. The signals used on the GPIO include an output enable signal oe, a data output signal data out, and a data input signal data in. The output enable signal oe is active high. After the slave device is enabled, the slave device internally pulls the output enable signal oe low and continuously monitors the signal on the DATA line on the data output signal data out, waiting for the master device to send handshake signals and read / write control signals. After the master device is enabled, it pulls the output enable signal oe high and begins sending handshake signals and read / write control signals. After the master device finishes sending, it immediately pulls the output enable signal oe low and receives the response signal from the slave device. After recognizing the handshake signals and read / write control signals, the slave device pulls the output enable signal oe high and sends a response signal. Furthermore, the two-wire SPI is used in the same way as the standard SPI. After the two-wire SPI is configured and enabled, the software only needs to query the non-empty status bit of the transmit FIFO and the non-full status bit of the receive FIFO, and continuously write data into the data register.

[0014] Furthermore, the master device and the slave device communicate via a handshake signal. After being enabled, the master device drives the DATA line to initiate a request to the slave device. The request signal consists of a high level and a low level. After sending the request signal, the master device immediately sends a read / write control signal. The handshake signal has a width of n SPI clk clock cycles, where n ≥ 3. Therefore, the sampling time point is the rising edge of the (n-1)th SPI clk. For the handshake signal on the DATA line, the slave device samples the data on the DATA line on the second clock edge each time. After sampling the master device's request signal, the slave device immediately sends a response signal. When sampling the response signal sent by the slave device, the master device also samples on the second clock edge.

[0015] Furthermore, in the two-wire SPI, the master device first sends a request signal and a read / write control signal before each transmission is initiated. After the slave device responds correctly, the master or slave device uses the SCK and DATA lines to transmit data.

[0016] The two-wire SPI communication system and method of the present invention have the following advantages: 1. Compared with the original SPI standard protocol, the two-wire SPI method only uses two IOs to achieve bidirectional transmission, saving IO resources.

[0017] 2. Handshake communication determines both the direction of transmission and the effectiveness of data transmission.

[0018] 3. In full-duplex mode, the MISO path is the critical path that limits the SPI frequency, and two-wire SPI effectively avoids this problem. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the master-slave device module structure of the present invention; Figure 2 This is a schematic diagram of the SPI master and slave device connection of the present invention; Figure 3 A flowchart illustrating the two-wire SPI software configuration of this invention; Figure 4 This is a schematic diagram of the two-wire SPI handshake of the present invention; Figure 5 This is a diagram of two-wire SPI data transmission according to the present invention. Detailed Implementation

[0020] To better understand the purpose, structure, and function of this invention, a two-wire SPI communication system and method of this invention will be described in further detail below with reference to the accompanying drawings.

[0021] This invention provides a two-wire SPI communication system and method to reduce the I / O required by SPI. The signal lines used in the two-wire SPI are: ① SCK clock signal line ② DATA data signal line. SCK is the clock signal used for data transmission, generated by the SPI master device; DATA is the data line, supporting bidirectional transmission between the master device and the slave device and between the slave device and the master device.

[0022] To determine the transmission direction of the SPI master-slave devices and ensure that both devices are in a transmit-ready state, this invention introduces a master-slave handshake mechanism. The handshake process occurs before each data transmission. The handshake signals include a request signal sent by the master device, a read / write control signal sent by the master device, and a response signal sent by the slave device. During the handshake, the SCK signal between the master and slave devices is either high or low depending on the CPOL configuration.

[0023] The handshake signal is generated by the SPI clock (SPI clk) internally within SPI, which is typically derived from the system bus clock. Since the SPI master and slave devices belong to different systems, their SPI clocks operate at the same frequency but are not synchronized. To ensure that both devices can correctly sample the other's handshake signal, this invention specifies that the two-wire SPI handshake signal width is at least three SPI clock cycles. The handshake signal width can be configured via software.

[0024] The specific handshake method is as follows: After the master device is enabled, it sends a high-level signal followed by a low-level signal, and then sends a read / write control signal. A high level indicates that the master device is transmitting data to the slave device, and a low level indicates that the slave device is transmitting data to the master device. After sending the read / write control signal, the master device stops driving the DATA line and waits for a response from the slave device.

[0025] After being enabled, the slave device continuously samples changes on the DATA line. It samples the read / write control signal only after detecting a high-to-low level transition. The slave device can then choose whether to accept the master device's request based on its current state. When the slave device can accept the master device's request, it drives the DATA line to send high-level and low-level signals sequentially. When the slave device cannot accept the master device's request, it drives the DATA line to send low-level and high-level signals sequentially.

[0026] The master device determines whether data transmission can begin based on the sampled response signal. If the slave device accepts the signal, data transmission immediately begins on the SCK clock signal line and the DATA data signal line. If the slave device cannot accept the signal, the master device can generate an error interrupt signal and wait for the CPU to handle it.

[0027] Figure 1This is a framework diagram of a master-slave device system using SPI, including the CPU, bus, SPI module, GPIO module, and other peripherals. In SPI usage scenarios, the CPU is mainly used for configuring SPI registers, while the SPI module is used to convert the data to be sent into the SPI protocol and send it through the GPIO module.

[0028] like Figure 2 As shown, the behavior of the GPIO module can be abstracted as a tri-state gate. The signals used in the GPIO module are the output enable signal oe (active high), the data output signal data out, and the data input signal data in. According to... Figure 3 The illustrated two-wire SPI configuration process involves the slave device internally pulling its enable signal oe low after being enabled, while continuously monitoring the signal on the DATA line for the data output signal DATA, waiting for the master device to send handshake and read / write control signals. Once enabled, the master device pulls its enable signal oe high and begins sending the handshake and read / write control signals. After sending these signals, the master device immediately pulls its enable signal oe low to receive the slave device's response signal. The slave device, after recognizing the handshake and read / write control signals, pulls its oe signal high and sends its response signal.

[0029] Figure 3 This is the SPI software configuration flowchart. The usage of two-wire SPI is consistent with standard SPI. After the two-wire SPI is configured and enabled, the software only needs to check the transmit FIFO for non-empty status and the receive FIFO for non-full status, and continuously write data to the data register. Compared to standard SPI, two-wire SPI may experience handshake failures. The reasons for handshake failure are as follows: ① The master device requests to receive data from the slave device, but the slave device's transmit FIFO is empty, preventing data transmission, and the slave device sends a handshake failure signal. ② The master device sends data and requests the slave device to receive it, but the slave device's receive FIFO is full, preventing data reception, and the slave device sends a handshake failure signal.

[0030] Figure 4This is an example of a successful SPI handshake. Assume the clock phase (CPHA) is 0, and SCK remains low throughout the IDLE state and handshake period. The diagram shows a handshake process with a handshake signal width of 3 SPI clock cycles. After enabling, the master device drives the DATA line to initiate a request to the slave device. The request signal consists of a high level and a low level; after sending the request signal, the master device immediately sends a read / write control signal. To ensure that the slave device does not sample incorrect request and read / write control signals due to metastability, this invention stipulates that if the handshake signal width is n SPI clock cycles, n≥3, the sampling time is the rising edge of the (n-1)th SPI clock cycle. Taking a handshake signal of three SPI clock cycles as an example, for the handshake signal on the DATA line, the slave device samples the data on the DATA line each time on the second clock edge. Figure 4 (At the 2nd, 5th, and 8th dashed lines). After sampling the master device's request signal, the slave device immediately sends a response signal. The master device also samples the slave device's response signal on the second clock edge.

[0031] Figure 5 This is the process of a two-wire SPI completing a handshake and transmitting data. Before each transmission is initiated, the master device needs to send a request signal and a read / write control signal. After the slave device responds correctly, either the master or slave device can use the SCK and DATA lines to transmit data.

[0032] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A communication method for a two-wire SPI communication system, the two-wire SPI communication system comprising a master device and a slave device, each of the master and slave devices including a CPU, a bus, an SPI module, and a GPIO module. In an SPI usage scenario, the CPU is used for configuring SPI registers, the SPI module is used for converting transmitted data into SPI protocol and sending it through the GPIO module, the SPI communication line between the master and slave devices consists of an SCK clock signal line and a DATA data signal line, the SCK clock signal line being used to synchronize the clock generated by the master device to the slave device; the DATA data signal line being used for bidirectional transmission between the master device and the slave device, characterized in that... The communication method includes the following steps: Step 1: After the master device is enabled, it sends a high-level signal and a low-level signal in sequence, followed by a read / write control signal. A high level indicates that the master device is transmitting to the slave device, and a low level indicates that the slave device is transmitting to the master device. After the master device sends the read / write control signal, it no longer drives the DATA line and waits for the slave device to respond to the request. Step 2: After being enabled, the slave device continuously samples changes on the DATA line. After sampling a high-low level transition, it then samples the read / write control signal. The slave device selects whether to accept the master device's request based on the current state. When the slave device can accept the master device's request, it drives the DATA line to send high-level and low-level signals sequentially. When the slave device cannot accept the master device's request, it drives the DATA line to send low-level and high-level signals sequentially. Step 3: The master device determines whether data transmission can begin based on the sampled response signal. If the slave device can accept it, data transmission will begin on the SCK clock signal line and the DATA data signal line. If the slave device cannot accept it, the master device generates an error interrupt signal and waits for the CPU to process it.

2. The communication method according to claim 1, characterized in that, The master device and the slave device communicate through handshake signals, which include a request signal sent by the master device, a read / write control signal sent by the master device, and a response signal sent by the slave device.

3. The communication method according to claim 2, characterized in that, The SCK signal during the handshake between the master and slave devices is either high or low depending on the CPOL configuration.

4. The communication method according to claim 2, characterized in that, The handshake signal is generated by the SPI clk driver inside the SPI, which is the internal clock of the SPI, derived from the clock of the system bus. The SPI clk of the master device and the slave device are at the same frequency but not synchronized. The handshake signal level width of the two-wire SPI is at least three SPI clk clock cycles, and the handshake signal level width is configured by software.

5. The communication method according to claim 1, characterized in that, The GPIO operates as a tri-state gate. Signals used on the GPIO include an output enable signal (oe), a data output signal (data out), and a data input signal (data in). The output enable signal (oe) is active high. After the slave device is enabled, it pulls the output enable signal (oe) low. The data output signal (data out) continuously monitors the signal on the DATA line, waiting for the master device to send handshake and read / write control signals. After the master device is enabled, it pulls the output enable signal (oe) high and begins sending the handshake and read / write control signals. After the master device finishes sending, it immediately pulls the output enable signal (oe) low to receive the slave device's response signal. After recognizing the handshake and read / write control signals, the slave device pulls the output enable signal (oe) high and sends a response signal.

6. The communication method according to claim 1, characterized in that, The two-wire SPI is used in the same way as the standard SPI. After the two-wire SPI is configured and enabled, the software only needs to query the non-empty status bit of the transmit FIFO and the non-full status bit of the receive FIFO, and continuously write data into the data register.

7. The communication method according to claim 1, characterized in that, The master and slave devices communicate via a handshake signal. After being enabled, the master device drives the DATA line to initiate a request to the slave device. The request signal consists of a high level and a low level. After sending the request signal, the master device immediately sends a read / write control signal. The handshake signal has a width of n SPI clk clock cycles, where n ≥ 3. The sampling time is the rising edge of the (n-1)th SPI clk. For the handshake signal on the DATA line, the slave device samples the data on the DATA line on the second clock edge each time. After sampling the master device's request signal, the slave device immediately sends a response signal. When sampling the response signal sent by the slave device, the master device also samples on the second clock edge.

8. The communication method according to claim 1, characterized in that, Before each transmission is initiated, the master device sends a request signal and a read / write control signal. After the slave device responds correctly, the master or slave device uses the SCK and DATA lines to transmit data.

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