Bus energizing simulation system

Abstract

The application relates to a bus excitation simulation model, which realizes the following steps when performing bus excitation simulation: step C1, obtaining excitation data configuration information and hardware protocol configuration information; step C2, generating an excitation data stream according to the excitation data configuration information and pre-configured register configuration information and in accordance with a preset excitation data transmission data structure; step C3, generating a corresponding hardware protocol structure body in the bus excitation model according to the hardware protocol configuration information; step C4, attaching the hardware protocol structure body to the excitation data stream according to the type of a target output interface to generate a data stream; and step C5, outputting the data stream to target hardware through the target output interface, parsing the data stream, coupling corresponding hardware protocol configuration information and excitation data configuration information based on the type of the target output interface, and then performing corresponding bus excitation simulation operation. The application can support arbitrary excitation data and hardware protocol, can be flexibly configured, and has universality.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a bus-excited simulation system. Background Technology

[0002] Chip verification is a crucial step in chip design. This verification process involves validating the design of the chip's intellectual property (IP), typically requiring the issuance of stimuli—specifically, sending register configurations or bus data to the IP. This process is called bus stimulus. Bus stimulus models are used to generate data stimuli and simulate the issuance of bus stimuli. However, existing bus stimulus models are only designed for a specific hardware protocol, lacking a model compatible with multiple protocols. Different bus stimulus models are often required for different hardware protocols, leading to high costs. Furthermore, existing models often mix stimulus data with hardware protocol control information, resulting in the construction of stimulus data being coupled with a specific hardware protocol, increasing the complexity of stimulus construction, reducing flexibility, and lacking versatility. Therefore, inventing a universal bus stimulus model that supports arbitrary stimulus data and hardware protocols is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a bus-driven simulation system that supports arbitrary stimulus data and hardware protocols, is flexibly configurable, and has versatility.

[0004] According to one aspect of the present invention, a bus excitation simulation system is provided, including a bus excitation model, wherein when performing bus excitation simulation, the following steps are implemented: the bus excitation model includes at least one type of output interface,

[0005] Step C1: Obtain the stimulus data configuration information and hardware protocol configuration information corresponding to the bus stimulus model;

[0006] Step C2: Generate an excitation data stream according to the excitation data configuration information and the pre-configured register configuration information, following a preset excitation data transmission data structure;

[0007] Step C3: Generate the corresponding hardware protocol structure in the bus excitation model according to the hardware protocol configuration information;

[0008] Step C4: Attach the hardware protocol structure to the excitation data stream according to the type of the target output interface to generate a data stream;

[0009] Step C5: Output the data stream to the target hardware through the target output interface, parse the data stream, and couple the corresponding hardware protocol configuration information and stimulus data configuration information based on the target output interface type before performing the corresponding bus stimulus simulation operation.

[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the bus-excitation simulation system provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It possesses at least the following advantages:

[0011] The bus excitation model described in this invention supports arbitrary excitation data and hardware protocols, is flexibly configurable, and has universality, eliminating the need to build specific models for different hardware protocols. The bus excitation model features different types of output interfaces to adapt to various simulation scenarios.

[0012] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0013] Figure 1 A schematic diagram of a bus-excitation simulation system provided in an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of the data flow transmission mode for data flow synchronization within the same bus excitation model is shown.

[0015] Figure 3 A schematic diagram of the data flow transmission mode for data flow synchronization between different bus excitation models is shown.

[0016] Figure 4 This is a schematic diagram of the bus excitation model provided in an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram illustrating synchronization or interruption between bus excitation models provided in an embodiment of the present invention. Detailed Implementation

[0018] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of the specific implementation and effects of a bus excitation simulation system proposed according to the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0019] This invention provides a bus-excitation simulation system, including a bus excitation model, wherein the bus excitation model includes at least one type of output interface, such as... Figure 1 As shown, when performing bus-driven simulation, the following steps are implemented:

[0020] Step C1: Obtain the stimulus data configuration information and hardware protocol configuration information corresponding to the bus stimulus model;

[0021] The bus excitation model can consist of multiple data streams. Users can define multiple data streams independently, each generated based on excitation data configuration information and hardware protocol configuration information. The hardware protocol information of the data stream is determined by the specific hardware protocol, such as the coordinate information of video images or the snoop information of the CHI protocol. Each independently defined combination of hardware protocol information can apply to all data packets of each data stream, or apply to a portion of the data packets of the data stream by means of a user-specified proportion. The bus excitation model will automatically and proportionally distribute the defined hardware protocol information evenly across the data packets of the data stream.

[0022] Step C2: Generate an excitation data stream according to the excitation data configuration information and the pre-configured register configuration information, following a preset excitation data transmission data structure;

[0023] As one embodiment, the preset excitation data transmission data structure includes a total data payload length data segment, a starting address data segment, a data segment representing the size of the transmission address space starting from the starting address, a register read / write type data segment, a bus data width data segment, a beat length (i.e., how many data items the same as the bus width consist of) data segment for each data packet, and an order value data segment. The order value is used to determine the order of excitation data stream transmission. For example, transmission is performed according to the order of the smallest order value, following a preset transmission synchronization mode. It should be noted that corresponding data segments can be added or deleted according to specific application requirements. The preset transmission synchronization modes include a data stream synchronization mode within the bus excitation model and a data stream synchronization mode for multiple bus excitation models.

[0024] Step C3: Generate the corresponding hardware protocol structure in the bus excitation model according to the hardware protocol configuration information;

[0025] It should be noted that the hardware protocol structure refers to the preset data structure of the hardware protocol. This involves setting the corresponding data segment of the hardware protocol within the data structure and then filling in the corresponding hardware protocol data. This can be done directly using existing technology and will not be elaborated further here. The corresponding hardware protocol can also be inserted into the bus excitation model as a plug-in, attached to the data stream via pointers.

[0026] Step C4: Attach the hardware protocol structure to the excitation data stream according to the type of the target output interface to generate a data stream;

[0027] It should be noted that, depending on the type of the target output interface, the data stream can be adapted to the transmission method of the request, such as the AXI (Advanced eXtensible Interface) protocol, and it can also be adapted to the transmission method of the package, such as the axi4 stream and TCP / IP.

[0028] Step C5: Output the data stream to the target hardware through the target output interface, parse the data stream, and couple the corresponding hardware protocol configuration information and stimulus data configuration information based on the target output interface type before performing the corresponding bus stimulus simulation operation.

[0029] The coupling of the corresponding hardware protocol configuration information and stimulus data configuration information based on the target output interface type, and the execution of the corresponding bus stimulus simulation operation based on the coupled hardware protocol configuration information and stimulus data configuration information, can all be implemented directly using existing technologies. That is, the target hardware is configured according to the output interface type and the corresponding hardware protocol configuration information, and then the corresponding bus stimulus simulation operation is executed. This will not be elaborated further here.

[0030] The stimulus data configuration information and hardware protocol configuration information are configured independently, as are the register configuration information. This ensures that the stimulus data configuration information and hardware protocol configuration information are transmitted in a decoupled state during the input phase of the bus stimulus model. During the model output simulation phase, they are coupled based on the output interface type and the corresponding hardware protocol to interact with the target hardware. By customizing the data flow configuration, hardware protocol information configuration, and register configuration, the bus stimulus model can send stimulus data in different data formats adapted to different hardware protocols without needing to build separate models for different hardware protocols. This makes the bus stimulus model universal and flexibly configurable.

[0031] As one example, such as Figure 1As shown, the bus excitation model may include at least one of a TLM (transaction level modeling) output interface, a TCP / IP socket output interface, and a pre-defined third-party API (Application Programming Interface) output interface. The TLM interface refers to the TLM interface of SystemC or SystemVerilog. The third-party API interface includes a third-party VIP interface, a third-party hardware accelerator API interface, or a PCIe-DMA (peripheral component interconnect express-direct memory access) channel API interface. The output interface can implement bandwidth limiting functionality, i.e., sending excitation data according to a pre-configured fixed bandwidth. By setting different types of output interfaces, various simulation scenarios can be adapted, such as co-simulation based on the simulator and hardware accelerator, or co-simulation based on PCIe-DMA technology and FPGA. Step C includes:

[0032] In step C1, the stimulus data and hardware protocol can be configured using the following three embodiments:

[0033] Implementation Method 1

[0034] In the absence of a real replay file, stimulus data and hardware protocol information can be configured directly. The model automatically generates pseudo-data based on the configuration; that is, the data values ​​are meaningless, but equivalent data can be generated based on the configuration. This configuration method ensures that all packets or requests in the same data stream have identical configurations. The replay file, in this context, defines the configuration information, hardware protocol information, and write operation data values ​​for each packet or request. Replay files can be user-written or, more commonly, sampled from system-level simulations.

[0035] Specifically, step C1 includes:

[0036] Step C11: Based on the incentive data information input by the user, set the same incentive data configuration information for all incentive data belonging to the same data stream;

[0037] Step C12: Configure the hardware protocol information based on the hardware protocol information received from the user to obtain the hardware protocol configuration information.

[0038] Implementation Method 2

[0039] Directly configuring stimulus data and hardware protocol information can also be done in the following ways. Specifically, step C1 includes:

[0040] Step C13: Randomly set the read / write type for the stimulus data, and based on the packet payload length, wrap the packet address within the pre-configured address space with increments or randomization based on the preset starting address.

[0041] Among them, wrap increment refers to incrementing within a preset numerical range, and when the upper limit is reached, it returns to the minimum value and starts incrementing again.

[0042] Implementation Method 3

[0043] If a real replay file is available, the stimulus data and hardware protocol information can be configured according to the replay file to ensure that the simulated stimulus data and hardware protocol information are consistent with the data generated by the real host. Specifically, step C1 includes:

[0044] Step C14: Sample the replay file from the system-level simulation, parse the replay file to obtain replay request or replay data packet configuration information, replay hardware protocol configuration information, and write operation data value;

[0045] It should be noted that replay files are not limited to those directly sampled from the system; they can also be pre-written and generated by the user.

[0046] Step C15: Obtain the excitation data configuration information corresponding to each bus excitation model based on the replay request or replay data packet configuration information, and obtain the hardware protocol configuration information corresponding to each bus excitation model based on the replay hardware protocol configuration information.

[0047] The third implementation method configures the stimulus data information and hardware protocol information according to the replay file, so that the bus stimulus model sends the stimulus strictly according to the data packets or requests defined in the replay file.

[0048] It is understandable that, depending on the different application scenarios and application requirements, any of the above methods can be selected to obtain the stimulus data configuration information and hardware protocol configuration information corresponding to each bus stimulus model.

[0049] Step C4 includes:

[0050] Step C41: If the target output interface is a TLM output interface or a preset third-party API output interface, the hardware protocol structure is directly attached to the stimulus data stream to generate a data stream, i.e., it is directly transmitted in the form of a request; if the target output interface is a TCP / IP socket output interface, the hardware protocol structure is attached to the stimulus data stream and packaged to generate a data packet of the data stream.

[0051] As one embodiment, if the data stream transmission mode is a bus-excitation model internal data stream synchronization mode, and for any m-th bus excitation model, the value of m ranges from 1 to M, and the order values ​​to be synchronously issued in the m-th bus excitation model are the same, then step C5, outputting the data stream to the target hardware through the target output interface, includes:

[0052] Step C51: Initialize k=0;

[0053] Step C52: Synchronously send out the data stream of the m-th bus excitation model with order=k. When the reply information corresponding to all data streams with order=k is received, execute step C53.

[0054] Step C53: Determine if k is less than mk, where mk is the maximum value of order in the m-th bus excitation model. If it is less than mk, set k = k + 1 and return to step C52. If k is equal to mk, end the data flow output process of the m-th bus excitation model.

[0055] Data flow synchronization within the same bus excitation model can be achieved through steps C51-C53. Figure 2 This diagram illustrates the data flow transmission mode for data flow synchronization within the same bus excitation model.

[0056] As one embodiment, if the data stream transmission mode is N bus excitation models {G1, G2, ... G...} N In data stream synchronization mode, N is greater than or equal to 2 and equal to M, G n For {G1, G2, ... G... N The nth bus excitation model in {G1, G2, ..., G...}, where n takes values ​​from 1 to N; N If the order values ​​of the data streams that need to be sent synchronously in the process are the same, then step C5, outputting the data stream to the target hardware through the target output interface, includes:

[0057] Step C54: Initialize s=0;

[0058] Step C55: Set {G1, G2, ... G...} NThe data stream with order=s in {G1, G2, ... G} is sent synchronously. When {G1, G2, ... G} is received, the data stream is sent synchronously. N When the response information for all data streams with order=s is received in}, proceed to step C56;

[0059] Step C56: Determine if s is less than Ns, where Ns is {G1, G2, ... G...} N If the maximum value of `order` in {G1, G2, ... G} is less than 1, then set `s = s + 1` and return to step C55. If `s` is equal to `Ns`, then the process ends. N The data flow output process of}.

[0060] Steps C54-C56 enable simulation collaboration between different bus excitation models. Figure 3 This diagram illustrates the data flow transmission mode for data flow synchronization between multiple bus excitation models.

[0061] Based on the above bus excitation model, embodiments of the present invention also provide a bus excitation system, such as... Figure 4 As shown, the system includes M pre-built bus stimulus models, a processor, and a memory storing computer programs, where M is a positive integer greater than or equal to 1. The bus stimulus models are used to generate data stimuli (traffic) to provide various test stimuli for the design under test (DUT). The static logic control simulation of the system's bus stimulus models is divided into three global states to achieve collaborative simulation of the multiple bus stimulus models: the pre-simulation configuration stage, the simulation stage, and the post-simulation configuration stage.

[0062] When the processor executes the computer program, it performs the following steps:

[0063] Step S1: Start the pre-simulation configuration phase of the system and perform pre-simulation configuration operations on each bus excitation model. The pre-simulation configuration operations include register configuration operations and memory data initialization operations. When all M bus excitation models have completed the pre-simulation configuration operations, proceed to step S2.

[0064] The bus excitation model that completes the pre-simulation configuration first will wait in the configured state until all bus excitation models have completed the pre-simulation configuration operation, and then the global state of the system will be switched to the simulation stage.

[0065] Step S2: Switch the system to the simulation stage, obtain the stimulus data configuration information and hardware protocol configuration information corresponding to each bus stimulus model. The stimulus data configuration information and hardware protocol configuration information are configured independently. Input the stimulus data configuration information, hardware protocol configuration information and pre-configured register configuration information corresponding to each bus stimulus model into the bus stimulus model to generate a data stream, and transmit the data stream. When all data streams sent by the M bus stimulus models have received reply information, execute step S3.

[0066] In step S2, for each bus excitation model, the operations in steps C1-C5 can be performed to execute bus excitation simulation. When the simulation operation corresponding to each data stream of the bus excitation model is completed, the corresponding reply information is sent to the corresponding bus excitation model. During the simulation phase, all bus excitation models start sending excitation data streams simultaneously. The bus excitation model that finishes transmitting first will wait in this state until all bus excitation models have completed the transmission of data streams, and the global simulation state will switch to the post-simulation configuration phase. The bus excitation model has finished transmitting because all sent data streams have received reply information.

[0067] Step S3: Switch the system to the post-simulation configuration stage and perform post-simulation configuration operations for each bus excitation model. The post-simulation configuration operations include register configuration operations and data export operations from memory data. When all M bus excitation models have completed the post-simulation configuration operations, the bus excitation simulation process ends.

[0068] In the post-simulation configuration phase, the bus excitation model that has been configured first will wait until all bus excitation models have been configured before the bus excitation simulation process ends.

[0069] As one embodiment, the system can specifically configure stimulus data, hardware protocol information, and register information using tables, data exchange files, or databases to obtain stimulus data configuration information, hardware protocol configuration information, and pre-configured register configuration information. The tables can specifically be Excel spreadsheets, and the data exchange file scripts can be common data exchange script formats such as CSV, YAML, JSON, and XML. By obtaining the stimulus data configuration information, hardware protocol configuration information, and pre-configured register configuration information in the above manner, stimulus data in different data formats adapted to different hardware protocols can be sent through the bus stimulus model, eliminating the need to build dedicated models for different protocols, thus possessing versatility and flexibility.

[0070] As one embodiment, in step S1, the initialization of memory data includes: the bus excitation model writing initialization data into the target address space of the module under test according to a preset starting address. The preset processing address and initialization data can be directly obtained from a preset file.

[0071] As one embodiment, in step S3, the data export operation from memory data includes: writing the data stored in the target address space into the target file according to the preset starting address and address space size.

[0072] As one embodiment, in steps S1 and S3, the register configuration operation includes a register configuration operation type, which includes read operation, write operation, query operation, etc., wherein read operation is a data reading operation, write data is a data writing operation, and query operation is a loop reading of the target address until the target address that is the same as the preset expected value is read.

[0073] As one example, such as Figure 5 As shown in the example, steps S1 and S3 further include inserting a wait-for-synchronization-signal operation and a trigger-for-synchronization-signal operation into the register configuration process corresponding to the bus excitation model, specifically including:

[0074] Step S10: Insert a waiting synchronization signal operation identifier at the preset first configuration point in the register configuration process corresponding to the i-th bus excitation model, and insert a trigger synchronization signal operation identifier at the second preset configuration point in the register configuration process corresponding to the j-th bus excitation model.

[0075] Step C0: When the register configuration process corresponding to the i-th bus excitation model reaches the first configuration point, the corresponding synchronization signal operation is performed, and the register configuration process corresponding to the i-th bus excitation model enters a waiting state.

[0076] Step S30: When the register configuration process corresponding to the j-th bus excitation model is executed to the second preset configuration point, a trigger synchronization signal operation is performed to start the register configuration process of the i-th bus excitation model, where the values ​​of i and j are both from 1 to M, and i and j are not equal.

[0077] It should be noted that, through steps S10-S30, each bus excitation model can be configured with any number of synchronization signals. These synchronization signals can be connected between two bus excitation models to achieve configuration information synchronization. The bus excitation model can simulate multiple hosts on a SOC chip, such as CPUs and GPUs. When so many hosts work simultaneously, it puts significant pressure on the SOC bus and interconnect network. This process requires simulating scenarios of bus competition for hardware resources, followed by performance analysis and functional verification. This process involves the synchronous configuration between multiple hosts, which can be accurately and quickly achieved through steps S10-S30.

[0078] As one embodiment, the system also includes pre-configured interrupt signal information for each bus excitation model, such as... Figure 5 As shown. The interrupt signal configuration information includes an interrupt signal identifier and a corresponding interrupt service operation. The interrupt signal can be a synchronization signal sent by other bus excitation models or a signal sent by the module under test. The interrupt service operation supports register configuration operations and other interrupt operations. In any of the pre-simulation configuration stage, simulation stage, or post-simulation configuration stage, the processor further implements the following steps:

[0079] Step S40: When the m-th bus excitation model receives the corresponding interrupt signal, the m-th bus excitation model suspends the execution of the current global operation;

[0080] Step S50: Retrieve the interrupt signal configuration information to determine the interrupt service operation corresponding to the currently received interrupt signal. The m-th bus excitation model executes the corresponding interrupt service operation. After the execution is completed, the current global operation continues to be executed.

[0081] Steps S40-S50 can simulate CPU interrupt service routine functionality, which can be used in any of the pre-simulation configuration, simulation, and post-simulation configuration stages. The interrupt service routine function, combined with register configuration and register configuration synchronization functions, can simulate synchronous configuration between multiple hosts and CPU-like interrupt service routine functionality, enabling the construction of complex stimulus scenarios related to register configuration.

[0082] The system described in this embodiment of the invention has register configuration functionality, enabling register configuration synchronization and interrupt service functions. It can simulate synchronous configuration between multiple hosts and CPU-like interrupt service routines, and can construct complex stimulus scenarios related to register configuration. The bus stimulus model supports arbitrary stimulus data and hardware protocols, allowing for flexible configuration and versatility, eliminating the need to build specific models for different hardware protocols. The bus stimulus model features different types of output interfaces to adapt to various simulation scenarios.

[0083] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A bus-driven simulation system, characterized in that, The system includes a bus-driven model, a processor, and a memory storing a computer program. The bus-driven model includes at least one type of output interface. When the processor executes the computer program, it performs the following steps: Step C1: Obtain the stimulus data configuration information and hardware protocol configuration information corresponding to the bus stimulus model; Step C2: Generate an excitation data stream according to the excitation data configuration information and the pre-configured register configuration information, following a preset excitation data transmission data structure; Step C3: Generate the corresponding hardware protocol structure in the bus excitation model according to the hardware protocol configuration information; Step C4: Attach the hardware protocol structure to the excitation data stream according to the type of the target output interface to generate a data stream; Step C5: Output the data stream to the target hardware through the target output interface, parse the data stream, and couple the corresponding hardware protocol configuration information and stimulus data configuration information based on the target output interface type before performing the corresponding bus stimulus simulation operation.

2. The bus-excited simulation system according to claim 1, characterized in that, The preset excitation data transmission data structure includes a total data payload length data segment, a starting address data segment, a data segment showing the size of the transmission address space starting from the starting address, a register read / write type data segment, a bus data width data segment, a beat length data segment for each data packet, and an order value data segment, wherein the order value is used to determine the order of excitation data stream transmission.

3. The bus-excitation simulation system according to claim 1, characterized in that, Step C1 includes: Step C11: Based on the incentive data information input by the user, set the same incentive data configuration information for all incentive data belonging to the same data stream; Step C12: Configure the hardware protocol information based on the hardware protocol information received from the user to obtain the hardware protocol configuration information.

4. The bus-excited simulation system according to claim 1, characterized in that, Step C1 includes: Step C13: Randomly set the read / write type for the stimulus data. Based on the packet payload length, the packet address is wrapped and incremented or randomly set within the pre-configured address space based on the preset starting address. Here, wrapping increment refers to incrementing within a preset value range. When the upper limit is reached, it returns to the minimum value and starts incrementing again.

5. The bus-excited simulation system according to claim 1, characterized in that, Step C1 includes: Step C14: Sample the replay file from the system-level simulation, parse the replay file to obtain replay request or replay data packet configuration information, replay hardware protocol configuration information, and write operation data value; Step C15: Obtain the excitation data configuration information corresponding to each bus excitation model based on the replay request or replay data packet configuration information, and obtain the hardware protocol configuration information corresponding to each bus excitation model based on the replay hardware protocol configuration information.

6. The bus-excited simulation system according to claim 1, characterized in that, The bus excitation model includes at least one of a TLM output interface, a TCP / IP socket output interface, and a preset third-party API output interface. Step C4 includes: Step C41: If the target output interface is a TLM output interface or a preset third-party API output interface, the hardware protocol structure is directly attached to the excitation data stream to generate a data stream; if the target output interface is a TCP / IP socket output interface, the hardware protocol structure is attached to the excitation data stream and packaged to generate data packets of the data stream.

7. The bus-excited simulation system according to claim 2, characterized in that, If the data stream transmission mode is the internal data stream synchronization mode of the bus excitation model, for any m-th bus excitation model, the value of m ranges from 1 to M, where M represents the number of bus excitation models and M is a positive integer greater than or equal to 1. In the m-th bus excitation model, if the order values ​​to be synchronously transmitted are the same, then step C5, outputting the data stream to the target hardware through the target output interface, includes: Step C51: Initialize k=0; Step C52: Synchronously send out the data stream of the m-th bus excitation model with order=k. When the reply information corresponding to all data streams with order=k is received, execute step C53. Step C53: Determine if k is less than mk, where mk is the maximum value of order in the m-th bus excitation model. If it is less than mk, set k = k + 1 and return to step C52. If k is equal to mk, end the data flow output process of the m-th bus excitation model.

8. The bus-excited simulation system according to claim 2, characterized in that, If the data stream transmission mode is N bus excitation models {G1, G2, ... G...} N In the data flow synchronization mode, N is greater than or equal to 2 and equal to M, where M represents the number of bus excitation models, and M is a positive integer greater than or equal to 1. n For {G1, G2, ... G... N The nth bus excitation model in {G1, G2, ..., G...}, where n takes values ​​from 1 to N; N If the order values ​​of the data streams that need to be sent synchronously in the process are the same, then step C5, outputting the data stream to the target hardware through the target output interface, includes: Step C54: Initialize s=0; Step C55: Set {G1, G2, ... G...} N The data stream with order=s in {G1, G2, ... G} is sent synchronously. When {G1, G2, ... G} is received, the data stream is sent synchronously. N When the response information for all data streams with order=s is received in}, proceed to step C56; Step C56: Determine if s is less than Ns, where Ns is {G1, G2, ... G...} N If the maximum value of `order` in {G1, G2, ... G} is less than 1, then set `s = s + 1` and return to step C55. If `s` is equal to `Ns`, then the process ends. N The data stream output process.

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