An ion implantation method

Abstract

The present application provides a kind of ion implantation method, it is difficult to solve the problem that traditional process cannot realize ideal P+ ion implantation junction depth on silicon carbide wafer.The ion implantation method includes: providing a wafer;Formed with patterned etching mask layer on the wafer;Etching is carried out to the wafer based on the etching mask layer to form groove;Form first injection mask layer on the side of the etching mask layer away from the wafer and the side wall and bottom of the groove;Form metal layer on part or all of the side wall of the groove;Second injection mask layer is formed on the surface of the injection mask layer away from the side of the etching mask layer, part of the side wall of the groove and / or the bottom of the groove;Carrying out at least twice ion oblique implantation, to form the injection structure of first conductive type on the side wall and / or groove bottom of the groove.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an ion implantation method. Background Technology

[0002] Silicon carbide (SiC) materials possess advantages such as wide bandgap, high thermal conductivity, high breakdown field strength, and high saturation velocity, making them ideal for fabricating high-temperature, high-power semiconductor devices. SiC-based power devices can fully leverage their high-temperature, high-frequency, and low-loss characteristics, making them highly promising for applications in high-voltage, high-temperature, high-frequency, high-power, and high-radiation environments.

[0003] To further increase current density, silicon carbide chips are gradually evolving from traditional planar structures to trench structures. Trench-structured devices typically undergo high-energy P+ ion implantation at the bottom of the trench to protect the trench bottom and simultaneously achieve an ideal breakdown voltage, such as... Figure 1 As shown. However, the traditional method of first implanting P+ ions and then etching trenches is difficult to achieve the ideal P+ ion implantation depth. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an ion implantation method that solves the problem that traditional processes are unable to achieve the ideal P+ ion implantation junction depth.

[0005] An embodiment of the present invention provides an ion implantation method comprising:

[0006] Provide one wafer;

[0007] A patterned etching mask layer is formed on the wafer;

[0008] The wafer is etched based on the etching mask layer to form trenches;

[0009] A first injection mask layer is formed on the side of the etching mask layer away from the wafer, as well as on the sidewalls and bottom of the trench;

[0010] A metal layer is formed on part or all of the sidewalls of the trench;

[0011] A second injection mask layer is formed on the surface of the injection mask layer away from the etching mask layer, on a portion of the sidewall of the trench, and / or at the bottom of the trench;

[0012] At least two ion tilt implantations are performed to form an implantation structure of a first conductivity type on the sidewalls and / or bottom of the trench.

[0013] In one embodiment, forming a metal layer on some or all of the sidewalls of the trench includes:

[0014] A metal layer is formed on the surface of the first injection mask layer away from the etching mask layer, the bottom of the trench, and part or all of the sidewalls of the trench;

[0015] Remove the metal layer on the surface of the first injection mask layer away from the etching mask layer and the metal layer at the bottom of the trench.

[0016] In one embodiment, forming a metal layer on the surface of the first implantation mask layer away from the etching mask layer, the bottom of the trench, and part or all of the sidewalls of the trench includes: rotating the wafer by a first preset angle so that no metal layer is formed on the side of the trench to be ion implanted.

[0017] In one embodiment, performing at least two ion tilt implantations to form an implantation structure of a first conductivity type on the sidewall and / or bottom of the trench includes: rotating the wafer by a second preset angle and performing at least two ion implantations; the second preset angle is adjusted based on the thickness of the etch mask layer, the thickness of the first implantation mask layer, and the thickness of the second implantation mask layer.

[0018] In one embodiment, performing at least two ion tilt implantations includes:

[0019] The wafer is rotated by a third preset angle to perform the first ion implantation, wherein the third preset angle is 31° to 42°.

[0020] The wafer is rotated at a fourth preset angle for a second ion implantation, the fourth preset angle being 77° to 85°.

[0021] In one embodiment, performing at least two ion tilt implantations further includes rotating the wafer by a fifth preset angle and performing a third ion implantation, wherein the fifth preset angle is 42° to 77°.

[0022] In one embodiment, after the step of performing at least two ion tilt implantations to form an implantation structure of a first conductivity type on the sidewalls and / or bottom of the trench, the method further includes: removing the etch mask layer, the first implantation mask layer, the metal layer, and the second implantation mask layer.

[0023] In one embodiment, the thickness of the first injection mask layer located on the sidewall of the trench and / or the thickness of the second injection mask layer is 30 nm to 100 nm.

[0024] In one embodiment, the metal layer is made of copper.

[0025] In one embodiment, the thickness of the metal layer ranges from 50 nm to 200 nm.

[0026] The ion implantation method provided in this invention has the following advantages compared with the prior art:

[0027] 1. The present invention performs P+ implantation after trench etching, which can achieve a deeper P+ implantation junction under the same implantation energy conditions, providing better protection for the trench and gate oxide and improving device reliability.

[0028] 2. The present invention forms a high-density composite injection mask on one side of the trench channel through a self-aligned process, which can resist P+ reflection ions during tilted injection and prevent the current path on one side of the channel from being blocked by P+ reflection ions.

[0029] 3. The present invention can adjust the lateral width of the P+ ion implantation region at the bottom of the trench by adjusting the thickness of the high-density composite implantation mask on the trench sidewall, thereby controlling the trade-off between the forward conduction characteristics and the reverse breakdown characteristics of the device.

[0030] 4. This invention achieves a more complete P+ implantation structure and has a better electric field shielding effect by implanting P+ ions at two different angles.

[0031] 5. This invention integrates trench etching and P+ ion implantation into a single process, simplifying the entire process and saving on photolithography steps for the P+ implantation layer, thus significantly reducing manufacturing costs. Attached Figure Description

[0032] Figure 1 The diagram shows a schematic of a single-channel trench MOSFET (metal-oxide-semiconductor field-effect transistor) structure in the prior art.

[0033] Figure 2 The diagram shown is a flowchart of an ion implantation method according to an embodiment of the present invention.

[0034] Figures 3 to 15 The diagram shown is a flowchart of an ion implantation method according to an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] This embodiment provides an ion implantation method, such as Figure 2 As shown, the ion implantation method includes:

[0037] Step 01: Provide a wafer 001.

[0038] Wafer 001 is prepared for trench etching and ion implantation. The prepared wafer 001 has already completed a series of ion implantations to form the basic structure such as the trench.

[0039] Optionally, wafer 001 is a silicon carbide wafer.

[0040] Step 02: Form a patterned etch mask layer 002 on the wafer 001.

[0041] like Figure 3 As shown, an etching mask material is prepared on the surface of SiC wafer 001, and holes are made in the etching mask material by combining photolithography and etching processes to form a patterned etching mask layer 002.

[0042] Optionally, the etching mask material is SiO2.

[0043] Optionally, the thickness of the etch mask layer 002 is greater than 2 μm.

[0044] Step 03: Etch the wafer 001 based on the etching mask layer 002 to form trenches.

[0045] right Figure 3 The structure shown is subjected to SiC trench etching to form trenches, such as... Figure 4 As shown.

[0046] Step 04: A first injection mask layer 003 is formed on the side of the etching mask layer 002 away from the wafer 001, as well as on the sidewall and bottom of the trench.

[0047] exist Figure 4 Based on the structure, a layer of SiO2 is deposited as the first implantation mask layer 003, such as Figure 5 As shown. Optionally, the thickness of the first injection mask layer 003 at the trench sidewall location ranges from 30 nm to 100 nm.

[0048] Step 05: Form a metal layer 004 on part or all of the sidewalls of the trench.

[0049] Specifically, forming a metal layer 004 on part or all of the sidewalls of the trench includes:

[0050] Step 051: A metal layer 004 is formed on the surface of the first injection mask layer 003 away from the etching mask layer 002, the bottom of the trench, and part or all of the sidewalls of the trench.

[0051] The step of forming a metal layer 004 on the surface of the first implantation mask layer 003 away from the etching mask layer 002, the bottom of the trench, and part or all of the sidewalls of the trench includes: rotating the wafer 001 by a first preset angle so that the metal layer 004 is not formed on the side of the trench that needs to be ion implanted.

[0052] Through sputtering process, Figure 5 Structurally, a metal layer 004 is formed. During the fabrication process, in one scenario, the wafer 001 needs to be rotated at a first predetermined angle to ensure that no high-density material forms on the side of the trench requiring P+ ion implantation. Figure 6 As shown. In the second case, a metal layer 004 is formed on the surface of the first injection mask layer 003 away from the etching mask layer 002, the bottom of the trench, and all sidewalls of the trench, as shown. Figure 7 As shown.

[0053] Optionally, the metal layer 004 may be a high-density material such as a metal or alloy; preferably, the material of the metal layer 004 is Cu metal.

[0054] Optionally, the thickness of the metal layer 004 on the trench sidewall ranges from 50 nm to 00 nm.

[0055] Step 052: Remove the metal layer 004 on the surface of the first injection mask layer 003 away from the etching mask layer 002 and the metal layer 004 at the bottom of the trench.

[0056] For high-density materials such as metals or alloys, a self-aligned etching process is performed to remove the high-density material on the surface and bottom of the trench, leaving only the high-density material on one side of the trench channel. Similarly, for the metal layer 004, a self-aligned etching process is performed to remove the high-density material on the surface of the first injection mask layer 003 away from the etching mask layer 002, as well as the high-density material at the bottom of the trench, leaving only the high-density material on the sidewalls of the trench channel. Figure 6 The structure shown is as follows after removing part of the metal layer 004. Figure 8 As shown; Figure 7 The structure shown is as follows after removing part of the metal layer 004. Figure 9 As shown.

[0057] Step 06: A second injection mask layer 005 is formed on the surface of the injection mask layer away from the etching mask layer 002, on a portion of the sidewall of the trench, and / or at the bottom of the trench.

[0058] Deposit a second layer of SiO2 as a second implantation mask, in Figure 8 The result after depositing the second injection mask layer 005 on the structure is as follows Figure 10 As shown; in Figure 9The result after depositing the second injection mask layer 005 on the structure is as follows Figure 11 As shown.

[0059] Optionally, the thickness of the second injection mask layer 005 at the trench sidewall ranges from 30 nm to 100 nm.

[0060] The second implantation mask layer 005 prepared in this step, together with the first implantation mask layer 003 prepared in step 04, can completely encapsulate the high-density material on the trench sidewalls, preventing metal or alloy from diffusing into the SiC body during high-temperature ion implantation.

[0061] Step 07: Perform at least two ion tilt implantations to form an implantation structure 006 of the first conductivity type on the sidewalls and / or bottom of the trench.

[0062] Specifically, performing at least two ion tilt implantations to form an implantation structure 006 of a first conductivity type on the sidewall and / or bottom of the trench includes: rotating the wafer 001 by a second preset angle and performing at least two ion implantations; the second preset angle is adjusted based on the thickness of the etching mask layer 002, the thickness of the first implantation mask layer 003, and the thickness of the second implantation mask layer 005.

[0063] Furthermore, the at least two ion tilt implantations include:

[0064] The wafer 001 is rotated by a third preset angle to perform the first ion implantation, wherein the third preset angle is 31° to 42°.

[0065] The wafer 001 is rotated by a fourth preset angle for a second ion implantation, the fourth preset angle being 77° to 85°.

[0066] To obtain a better P+ ion implantation structure 006, i.e. a better electric field shielding effect, the number of tilt implantations can be increased on the basis of two tilt implantations. That is, in addition to performing at least two tilt implantations, the wafer 001 is rotated by a fifth preset angle to perform a third ion implantation. The fifth preset angle is 42° to 77°.

[0067] Optionally, the preset tilt angle needs to be adjusted according to the thickness of the etching mask layer 002, the first implantation mask layer 003, and the second implantation mask layer 005. The preset angle during tilt implantation refers to the angle formed between the wafer 001 and the horizontal plane.

[0068] Then on Figure 10 The structure undergoes two or more tilted P+ ion implantations to achieve the 006 P+ implantation structure at the bottom of the trench. For example... Figure 12 As shown. Then... Figure 11The structure undergoes two or more P+ ion implantations. Optionally, the ion implantation can be vertical, achieving a P+ implantation structure 006 at the bottom of the trench. Figure 13 As shown.

[0069] In addition to the steps described above, after performing at least two ion tilt implantations to form an implantation structure 006 of the first conductivity type on the sidewalls and / or bottom of the trench, step 08 is further included: removing the etching mask layer 002, the first implantation mask layer 003, the metal layer 004, and the second implantation mask layer 005.

[0070] After implantation, a wet etching process can be used to remove the composite implantation mask. Since the high-density material is encapsulated by SiO2, the high-density metal or alloy material is also stripped away along with the SiO2. Figure 4 and Figure 15 As shown.

[0071] Subsequently, the SiC wafer 001 can be subjected to RCA cleaning to further ensure the cleanliness of the SiC wafer 001.

[0072] Continue with other processes, such as carbon film protection, activation annealing, field oxide, gate oxide, POLY gate, metal electrode, etc.

[0073] This invention provides a method for P+ ion tilting implantation that combines trench etching with different angles, achieving a deeper P+ ion implantation junction under the same implantation energy. Simultaneously, this invention employs a high-density composite implantation mask on one side of the trench channel to prevent P+ ions from reflecting back to the channel and blocking the current path during tilting implantation. Furthermore, this invention integrates trench etching and P+ ion implantation processes, simplifying the entire process, saving on photolithography steps for the P+ implantation layer, and significantly reducing manufacturing costs.

[0074] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention. It will be clearly understood by those skilled in the art that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0075] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0076] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program checksums.

[0077] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0078] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner.

[0079] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0080] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0081] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, top, bottom, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the figures). If the specific posture changes, the directional indication will also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0082] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0083] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An ion implantation method, characterized in that, include: Provide one wafer; A patterned etching mask layer is formed on the wafer; The wafer is etched based on the etching mask layer to form trenches; A first implantation mask layer is formed on the side of the etching mask layer away from the wafer, as well as on the sidewalls and bottom of the trench; Forming a metal layer on part or all of the sidewalls of the trench includes: forming a metal layer on the surface of the first implantation mask layer facing the inside of the trench, which covers part or all of the sidewalls of the trench, wherein the metal layer only covers the sidewall area of ​​the trench and does not cover the bottom area of ​​the trench, and the metal layer is used to block reflected ions generated during the tilting ion implantation process, so as to prevent the current path in the trench area from being blocked by reflected ions. A second injection mask layer is formed on the surface of the injection mask layer away from the etching mask layer, on a portion of the sidewall of the trench, and / or at the bottom of the trench. The second injection mask layer covers the surface of the metal layer and, together with the first injection mask layer, completely covers the metal layer. At least two ion tilt implantations are performed to form an implantation structure of a first conductivity type on the sidewalls and / or bottom of the trench.

2. The ion implantation method according to claim 1, characterized in that, The formation of a metal layer on part or all of the sidewalls of the trench includes: A metal layer is formed on the surface of the first injection mask layer away from the etching mask layer, the bottom of the trench, and part or all of the sidewalls of the trench; Remove the metal layer on the surface of the first injection mask layer away from the etching mask layer and the metal layer at the bottom of the trench.

3. The ion implantation method according to claim 2, characterized in that, The step of forming a metal layer on the surface of the first implantation mask layer away from the etching mask layer, the bottom of the trench, and part or all of the sidewalls of the trench includes: rotating the wafer by a first preset angle so that no metal layer is formed on the side of the trench that needs to be ion implanted.

4. The ion implantation method according to claim 2, characterized in that, The step of performing at least two ion tilt implantations to form an implantation structure of a first conductivity type on the sidewall and / or bottom of the trench includes: rotating the wafer by a second preset angle and performing at least two ion implantations; the second preset angle is adjusted based on the thickness of the etch mask layer, the thickness of the first implantation mask layer, and the thickness of the second implantation mask layer.

5. The ion implantation method according to claim 4, characterized in that, The process of performing at least two ion tilt implantations includes: The wafer is rotated by a third preset angle to perform the first ion implantation, wherein the third preset angle is 31° to 42°. The wafer is rotated at a fourth preset angle for a second ion implantation, the fourth preset angle being 77° to 85°.

6. The ion implantation method according to claim 4, characterized in that, The process of performing at least two ion tilt implantations further includes rotating the wafer by a fifth preset angle and performing a third ion implantation, wherein the fifth preset angle is 42° to 77°.

7. The ion implantation method according to claim 1, characterized in that, After performing at least two ion tilt implantations to form an implantation structure of a first conductivity type on the sidewalls and / or bottom of the trench, the method further includes: removing the etch mask layer, the first implantation mask layer, the metal layer, and the second implantation mask layer.

8. The ion implantation method according to claim 1, characterized in that, The thickness of the first injection mask layer located on the sidewall of the trench and / or the thickness of the second injection mask layer is 30nm to 100nm.

9. The ion implantation method according to claim 1, characterized in that, The metal layer is made of copper.

10. The ion implantation method according to claim 1, characterized in that, The thickness of the metal layer ranges from 50 nm to 200 nm.

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