Methods to improve the uniformity of metal silicides

Abstract

This invention provides a method for improving the uniformity of metal silicides. A substrate is provided, on which a gate layer, a first sidewall located on the sidewall of the gate layer, and a second sidewall located on the first sidewall are formed. Ion implantation of source / drain regions is performed on the substrate. The second sidewall is composed of first and second stacked layers from the inside out. The second stacked layer is removed, increasing the spacing between the gate layers. A metal layer is formed on the substrate, followed by annealing and etching processes to form metal silicides on the substrate between the gate layers. This invention increases the gate spacing, significantly reducing the fill aspect ratio, thereby improving the thickness uniformity of metal sputtered films in designs with smaller gate spacing, achieving the goal of improving in-plane uniformity of contact resistance, increasing the window for subsequent via processes, and improving product process stability and yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the uniformity of metal silicides. Background Technology

[0002] Metal silicides (Salicides) are metal silicides (NiSi) formed by the reaction of a metal and a Si substrate. Their main function is to provide an ohmic metal-metal and metal-semiconductor contact between the subsequent contact holes and Si, thereby reducing resistance.

[0003] NiSi is generally formed by sputtering an excess of NiPt alloy after the source-drain junction is formed, followed by two low-temperature heat treatments to form a low-resistivity NiSi crystal phase.

[0004] The resistance of NiSi significantly affects the performance of CMOS devices, especially after the 28nm process node, and its resistance value is mainly affected by the NiSi morphology formed during the process.

[0005] In actual production, it was found that the patterning effect has a huge impact on the morphology of NiSi: the smaller the gate spacing, the smaller the NiSi volume formed, the worse the morphology, resulting in greater contact resistance. In severe cases, it can cause abnormal landing of subsequent via etching, forming punch-through problems and direct device failure.

[0006] To address the aforementioned issues, a novel method for improving the uniformity of metal silicides is needed. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the uniformity of metal silicides, in order to solve the problem that the patterning effect has a huge impact on the morphology of metal silicides in the prior art: the smaller the gate spacing, the smaller the volume of the metal silicide formed, the worse the morphology, resulting in greater contact resistance, and in severe cases, it can cause abnormal landing of subsequent via etching, forming punch-through, leading to direct device failure.

[0008] To achieve the above and other related objectives, the present invention provides a method for improving the uniformity of metal silicides, comprising:

[0009] Step 1: Provide a substrate on which a gate layer, a first sidewall located on the sidewall of the gate layer, and a second sidewall located on the first sidewall are formed. Perform ion implantation on the source / drain regions of the substrate. The second sidewall is composed of a first and a second stacked layer from the inside out.

[0010] Step 2: Remove the second stacked layer to increase the spacing between the gate layers;

[0011] Step 3: A metal layer is formed on the substrate, and then metal silicide is formed on the substrate between the gate layers using annealing and etching processes.

[0012] Preferably, the substrate in step one is a silicon substrate.

[0013] Preferably, the material of the first sidewall in step one is SiCN.

[0014] Preferably, the material of the first stack in step one is silicon dioxide.

[0015] Preferably, the material of the second stack in step one is silicon nitride.

[0016] Preferably, in step two, the second stack is removed using a wet etching method.

[0017] Preferably, the metal layer is formed by sputtering in step three.

[0018] Preferably, the material of the metal layer in step three is NiPt.

[0019] Preferably, the method for forming metal silicide on the substrate between the gate layers using annealing and etching processes in step three includes: forming Ni2Si on the substrate between the gate layers using a first annealing process; then removing unreacted NiPt using wet etching; and then forming NiSi on the substrate between the gate layers using a second annealing process.

[0020] As described above, the method for improving the uniformity of metal silicides according to the present invention has the following beneficial effects:

[0021] This invention expands the gate pitch, which can significantly reduce the fill depth-to-width ratio, thereby improving the thickness uniformity of metal sputtered films in designs with smaller gate pitches, achieving the goal of improving the in-plane uniformity of contact resistance, improving the subsequent via process window, and improving product process stability and yield. Attached Figure Description

[0022] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0023] Figure 2 The diagram shown is a schematic diagram of the gate layer and sidewall structure of the present invention.

[0024] Figure 3 The diagram shown illustrates the removal of the second layer according to the present invention.

[0025] Figure 4 The diagram shown illustrates the formation of the metal layer according to the present invention.

[0026] Figure 5The diagram shown is a schematic diagram of the first annealing process of the present invention.

[0027] Figure 6 The diagram shown illustrates the removal of unreacted NiPt according to the present invention.

[0028] Figure 7 The diagram shown is a schematic diagram of the second annealing process of this invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please see Figure 1 The present invention provides a method for improving the uniformity of metal silicides, comprising:

[0031] Step 1, please refer to Figure 2 A substrate is provided, on which a gate layer 101 is formed, a first sidewall 102 located on the sidewall of the gate layer 101, and a second sidewall located on the first sidewall 102. Ion implantation of the source and drain regions is performed on the substrate; wherein, the second sidewall is composed of a first and a second stacked layer from the inside to the outside.

[0032] The spacing of the gate layer 101 is mainly related to three factors: the critical dimension of the gate layer 101, the width of the first sidewall 102, and the width of the second sidewall. The critical dimension is design-dependent and cannot be adjusted; the two sidewalls are related to process integration and are adjustable. However, in reality, the first sidewall 102 affects the shallow doped implantation region, and the second sidewall affects the source / drain implantation region. Both have a significant impact on device characteristics and reliability, and direct adjustment is difficult to eliminate the negative impact, with limited adjustability and limited improvement on NiSi growth morphology. Therefore, a stacked design is adopted for the second sidewall. The spacing of the gate layer 101 can be expanded by removing the second stacked layer 104 in the second sidewall, while the retained first stacked layer 103 serves as a metal silicide barrier layer.

[0033] Preferably, the substrate in step one is a silicon substrate.

[0034] Preferably, the material of the first sidewall 102 in step one is SiCN.

[0035] Preferably, the material of the first stack 103 in step one is silicon dioxide.

[0036] Preferably, the material of the second stack 104 in step one is silicon nitride.

[0037] Step 2: Remove the second stacked layer 104 to increase the spacing between the gate layers 101, forming a structure as shown in the figure. Figure 3 The structure shown increases the spacing from X to X', adding a metal layer 105 sputtering film filling window and a subsequent interlayer dielectric layer filling window;

[0038] Preferably, in step two, the second layer 104 is removed using a wet etching method. It should be noted that other methods, such as dry etching, can also be used to remove the second layer 104; no specific limitation is made here.

[0039] Preferably, the material of the second stack 104 in step one is silicon nitride.

[0040] Step 3: Form a metal layer 105 on the substrate, forming a structure as shown in the figure. Figure 4 The structure shown is followed by the formation of metal silicide on the substrate between the gate layers 101 using annealing and etching processes, forming a structure as shown. Figure 7 The structure shown.

[0041] Preferably, in step three, the metal layer 105 is formed by sputtering.

[0042] Preferably, the material of the metal layer 105 in step three is NiPt.

[0043] Preferably, the method for forming metal silicides on the substrate between the gate layers 101 using annealing and etching processes in step three includes: forming Ni2Si106 on the substrate between the gate layers 101 using a first low-temperature annealing process, forming as shown in the figure. Figure 5 The structure shown is then removed using wet etching to form a structure as shown. Figure 6 The structure shown is followed by a second high-temperature annealing process to form NiSi107 on the substrate between the gate layers 101, resulting in a structure as shown. Figure 7 The structure shown.

[0044] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] In summary, this invention expands the gate pitch, significantly reducing the fill aspect ratio, thereby improving the thickness uniformity of metal sputtered films in designs with smaller gate pitches. This achieves the goal of improving in-plane uniformity of contact resistance, extends the subsequent via process window, and improves product process stability and yield. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the uniformity of metal silicides, characterized in that, At least including: Step 1: Provide a substrate on which a gate layer, a first sidewall located on the sidewall of the gate layer, and a second sidewall located on the first sidewall are formed. Perform ion implantation on the substrate for the source and drain regions. The second sidewall is composed of a first and a second stacked layer from the inside out. The material of the first sidewall is SiCN, the material of the first stacked layer is silicon dioxide, and the material of the second stacked layer is silicon nitride. Step 2: Remove the second stacked layer to increase the spacing between the gate layers; Step 3: Form a metal layer on the substrate, and then use annealing and etching processes to form metal silicide on the substrate between the gate layers.

2. The method for improving the uniformity of metal silicides according to claim 1, characterized in that: The substrate mentioned in step one is a silicon substrate.

3. The method for improving the uniformity of metal silicides according to claim 1, characterized in that: In step two, the second stack is removed using a wet etching method.

4. The method for improving the uniformity of metal silicides according to claim 1, characterized in that: In step three, the metal layer is formed using a sputtering method.

5. The method for improving the uniformity of metal silicides according to claim 1, characterized in that: The metal layer in step three is made of NiPt.

6. The method for improving the uniformity of metal silicides according to claim 5, characterized in that: Step 3 involves forming metal silicides on the substrate between the gate layers using annealing and etching processes. This includes: forming Ni2Si on the substrate between the gate layers using a first annealing process; removing unreacted NiPt using wet etching; and then forming NiSi on the substrate between the gate layers using a second annealing process.

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