A method for replacing a schottky diode substrate with a gallium arsenide substrate retained

Abstract

This application discloses a method for replacing the substrate of a Schottky diode while retaining the gallium arsenide substrate, comprising the following steps: growing an epitaxial film: sequentially depositing undoped indium gallium phosphide (InGaP) on the gallium arsenide substrate using molecular beam epitaxy. 0.48 Ga 0.52 An epitaxial thin film is formed from a P-layer, a nano-silicon highly doped N-type gallium arsenide (N+GaAs) layer, and a nano-silicon lightly doped N-type gallium arsenide (N-GaAs) layer; cathode and anode metals are fabricated; isolation etching is performed: a diode pattern is photolithographically etched, and all N+GaAs and N-GaAs layers outside the diode pattern are removed using a first etching solution, then the exposed In... 0.48 Ga 0.52 In was photolithographically etched onto the P layer 0.48 Ga 0.52 P-layer graphics, making In 0.48 Ga 0.52 The P layer is easily removed by complete etching; In is removed using a second etching solution. 0.48 Ga 0.52 All In within the P-layer graph 0.48 Ga 0.52 P; Fabrication of a protective silicon oxide layer and completion of air bridge metal connections; substrate separation and replacement. Undoped indium gallium phosphide (InGaP) is grown between a gallium arsenide substrate and a nano-silicon-doped gallium arsenide layer. 0.48 Ga 0.52 The P-layer allows for the retention of the gallium arsenide substrate, thereby enabling resource reuse and promoting energy conservation and environmental protection.

Description

Technical Field

[0001] This application relates to the field of semiconductor process technology, and in particular to a method for replacing the substrate of a Schottky diode while retaining the gallium arsenide substrate. Background Technology

[0002] Planar gallium arsenide (GaAs) Schottky diodes have been widely used in the terahertz (THz) band and are core solid-state electronic devices in the THz technology field. To achieve higher operating frequencies for planar GaAs Schottky diodes, the parasitic parameters of the diode device must be considered. Without changing the diode's structure, the most significant factor affecting the cutoff frequency is the parasitic capacitance introduced between the electrodes through the substrate. Therefore, current technology uses a quartz substrate with a lower dielectric constant to replace the original substrate to obtain superior frequency characteristics.

[0003] However, existing large Schottky diodes are often manufactured by etching away the original gallium arsenide substrate and then transferring it to a quartz substrate for bonding during substrate replacement. At the same time, this manufacturing method is still used in the manufacturing of individual small Schottky diodes. In fact, for the substrate replacement of small Schottky diodes with independent diode layouts, since there is a possibility of retaining and reusing the gallium arsenide substrate, the use of the substrate replacement method for large Schottky diodes results in a waste of resources in the substrate replacement of small Schottky diodes. Summary of the Invention

[0004] Technical problems to be solved:

[0005] The existing method for replacing the substrate of large Schottky diodes results in resource waste when replacing the substrate of small Schottky diodes. Therefore, the purpose of this invention is to provide a method for replacing the substrate of Schottky diodes while retaining the gallium arsenide substrate.

[0006] Technical solution:

[0007] This application discloses a method for replacing the substrate of a Schottky diode while retaining the gallium arsenide substrate, including the following steps:

[0008] (1) Growth of epitaxial films: Undoped indium gallium phosphide (InGaP) films with a thickness of 135–165 nm were sequentially deposited on gallium arsenide substrates using molecular beam epitaxy. 0.48 Ga 0.52 An epitaxial thin film is formed by a P-layer, a 720–880 nm nano-silicon highly doped N-type gallium arsenide (N+GaAs) layer, and a 90–110 nm nano-silicon lightly doped N-type gallium arsenide (N-GaAs) layer.

[0009] (2) Fabrication of cathode metal: Photolithography of cathode metal pattern on N-GaAs layer, etching of epitaxial thin film material in cathode metal pattern into N+GaAs layer using first etching solution, etching depth of 225-275nm, and sequentially evaporation of titanium / platinum / gold cathode metal with total thickness of 270-330nm.

[0010] (3) Fabrication of anode metal: A passivated silicon oxide layer of 45-55 nm is grown on the epitaxial film outside the cathode metal pattern after evaporation; an anode metal pattern is photolithographically patterned on the passivated silicon oxide layer; all passivated silicon oxide layers within the ICP-RIE anode metal pattern are etched using plasma-enhanced reactive ion etching; and a titanium / platinum / gold anode metal with a total thickness of 135-165 nm is deposited within the pattern.

[0011] (4) Isolation etching: A diode pattern is photolithographically patterned on the upper surface of the epitaxial film, and all N+GaAs and N-GaAs layers outside the diode pattern are removed with the first etching solution. Then, the exposed In... 0.48 Ga 0.52 In was photolithographically formed on the P layer 0.48 Ga 0.52 P-layer graph, In within this graph 0.48 Ga 0.52 The P-layer, viewed from above, includes several directly visible contact areas. Among these contact areas, two contact areas are respectively connected to two In-layer areas that are obscured by the diode pattern. 0.48 Ga 0.52 The P-layer regions are connected, making In 0.48 Ga 0.52 The P layer is easily removed by complete etching; In is removed using a second etching solution. 0.48 Ga 0.52 All In within the P-layer graph 0.48 Ga 0.52 P;

[0012] (5) Fabrication of a protective silicon oxide layer and completion of air bridge metal connection: A 45-55 nm protective silicon oxide layer is grown on the surface of the epitaxial thin film after isolation etching; a protective silicon oxide layer pattern is photolithographically patterned, the pattern including a plate structure for fixing and completely shielding the thin film material within the diode pattern, and at least four connection structures connecting the gallium arsenide substrate and the plate structure, and through holes for connection above the anode metal and cathode metal; the protective silicon oxide layer pattern does not shield In 0.48 Ga 0.52 The contact area of ​​the P layer in the top view; all protective silicon oxide material outside the pattern of the protective silicon oxide layer is etched using plasma-enhanced reactive ion etching (ICP-RIE); after the air bridge metal connection between the cathode metal and the anode metal is completed by photolithography and electroplating, the first Schottky diode structure is formed.

[0013] (6) Substrate separation: The fabricated Schottky diode is immersed in a second etching solution, and then completely etched in In... 0.48 Ga 0.52 After layer P, In is removed. 0.48 Ga 0.52 The second Schottky diode in the P-layer was immersed and cleaned with deionized water.

[0014] (7) Substrate replacement: A glass solution SOG is spin-coated onto a quartz substrate to form a polymer thin layer; the van der Waals forces of the microstructured polymer material are used to adsorb the second Schottky diode, thereby separating it from the gallium arsenide substrate and obtaining a product with removed In. 0.48 Ga 0.52 The third Schottky diode is formed by the P-layer and gallium arsenide substrate. After the third Schottky diode is transferred to a polymer thin layer on a quartz substrate, a fourth Schottky diode is obtained. The microstructure polymer material is removed, and finally the fourth Schottky diode is heated in a nitrogen atmosphere to complete the bonding.

[0015] Preferably, the first corrosive liquid is a mixture of phosphoric acid solution (wt90%), hydrogen peroxide solution (wt30%), and water in a volume ratio of 3:1:8; the corrosion time in step (2) is 50 to 70 seconds; and the corrosion time in step (4) is 270 to 330 seconds.

[0016] Preferably, the second corrosive solution is a mixed solution of phosphoric acid solution (90% wt) and hydrochloric acid solution (30% wt) in a volume ratio of 1:5; the corrosion time in step (4) is 27 to 33 seconds; and the corrosion time in step (6) is 324 to 366 minutes.

[0017] Preferably, in step (2), the titanium layer thickness in the titanium / platinum / gold cathode metal is 18-22 nm, the platinum layer thickness is 36-44 nm, and the gold layer thickness is 216-264 nm.

[0018] Preferably, in step (3), the titanium layer thickness in the titanium / platinum / gold anode metal is 18-22 nm, the platinum layer thickness is 36-44 nm, and the gold layer thickness is 81-99 nm.

[0019] Preferably, the deionized water soaking and rinsing in step (6) includes three soaking and rinsing sessions, each lasting 30 minutes.

[0020] Preferably, the spin-coating glass glue solution SOG described in step (7) involves maintaining a rotation speed of 2000 rpm for 40 seconds.

[0021] Preferably, the heating in nitrogen environment in step (7) includes raising the temperature from room temperature (20°C) to 300°C at a rate of 1°C / minute, maintaining the temperature for 2 hours, and then lowering the temperature from 300°C to 50°C at a rate of 1°C / minute.

[0022] Beneficial effects:

[0023] Resource recycling, energy conservation and environmental protection: Undoped indium gallium phosphide (IGaP) is grown between a gallium arsenide substrate and a nano-silicon-doped gallium arsenide layer. 0.48 Ga 0.52 The P-layer allows for the separation of the gallium arsenide substrate and the nano-silicon-doped gallium arsenide layer after the removal of the indium gallium phosphide layer, while retaining the gallium arsenide substrate for secondary use, thus achieving resource reuse and energy conservation and environmental protection. Attached Figure Description

[0024] Figure 1 This is a flowchart of the substrate replacement method in this application;

[0025] Figure 2 This is a cross-sectional view of the first Schottky diode;

[0026] Figure 3 This is a top view of the first Schottky diode.

[0027] Figure 4 This is a cross-sectional view of the second Schottky diode;

[0028] Figure 5 Operation diagram for replacing the substrate of the third Schottky diode;

[0029] 1 gallium arsenide substrate, 2 In 0.48 Ga 0.52 P layer, 3 N-type gallium arsenide (GaAs) N+ layer, 4 N-type gallium arsenide (GaAs) N- layer, 5 cathode metal, 6 passivated silicon oxide layer, 7 anode metal, 8 first contact region, 9 second contact region, 10 third contact region, 11 fourth contact region, 12 protective silicon oxide layer, 13 plate structure, 14 connection structure, 15 air bridge metal, 16 quartz substrate, 17 polymer thin layer, 18 polydimethylsiloxane for transfer. Detailed Implementation

[0030] The technical solution of this application will be further described below with reference to the accompanying drawings.

[0031] like Figure 1 The embodiment shown provides a method for fabricating a planar gallium arsenide Schottky diode on a quartz substrate, specifically including the following:

[0032] First, undoped indium gallium phosphide (InGaP) with a thickness of 150 nm was sequentially deposited on a 620 μm thick semi-insulating gallium arsenide substrate 1 using molecular beam epitaxy (MBE). 0.48 Ga 0.52 P layer 2, with a thickness of 800 nm and a Si doping concentration of 8 × 10⁻⁶. 18 cm -3The N-type gallium arsenide (GaAs) layer 3 has a thickness of 100 nm and a Si doping concentration of 2 × 10⁻⁶. 17 cm -3 A low-doped N-type gallium arsenide (N-GaAs) layer 4 is formed as an epitaxial thin film;

[0033] The following steps were performed sequentially on the epitaxially grown film: First, a cathode pattern was defined on the N-GaAs layer using ultraviolet lithography. Then, a mixture of phosphoric acid solution (wt90%), hydrogen peroxide solution (wt30%), and water (volume ratio 3:1:8) was used for etching for 1 minute to etch the epitaxial material within the cathode pattern into the N+ GaAs layer to a depth of 250 nm. Next, titanium, platinum, and gold were sequentially evaporated and deposited using an electron beam to form cathode metal 5 (specific thickness: titanium / platinum / gold = 20 nm / 40 nm / 240 nm), with a total thickness of 300 nm. After the preparation and lift-off of cathode metal 5, a passivated silicon oxide layer 6 with a thickness of 50 nm was grown using inductively coupled plasma-enhanced chemical vapor deposition (ICP-PECVD) at a growth temperature of 200 °C. Finally, an anode pattern was defined on the passivated silicon oxide layer using ultraviolet lithography. Subsequently, inductively coupled plasma-enhanced reactive ion etching (ICP-RIE) was used to completely etch the 50 nm passivated silicon oxide within the anode pattern. Then, titanium, platinum, and gold were sequentially evaporated and deposited in the anode pattern area using electron beam evaporation to form anode metal 7 (specific thickness: titanium / platinum / gold = 20 nm / 40 nm / 90 nm), with a total thickness of 150 nm.

[0034] After the cathode metal 5 and anode metal 7 are fabricated, anode metal 7 is stripped off, and then the diode pattern is defined by ultraviolet lithography. This diode pattern can be divided into two independent, non-contact left and right parts. A mixture of phosphoric acid solution (wt90%), hydrogen peroxide solution (wt30%), and water (volume ratio 3:1:8) is used to etch all epitaxial GaAs layers outside the diode pattern, namely N+ GaAs layer 3 and N- GaAs layer 4, down to the undoped In. 0.48 Ga 0.52 P-layer 2 etching stopped, etching time 5 minutes; then UV lithography defined In 0.48 Ga 0.52 P-layer graphics, such as Figure 3 As shown: In including the In which the diode pattern on the left of the figure is obscured. 0.48 Ga 0.52 The first contact area 8 connected to the P-layer region, and the In region obscured by the diode pattern on the right side of the diagram. 0.48 Ga 0.52 The second contact area 9 and the third contact area 10 are connected by the P-layer region, and a plurality of fourth contact areas 11 are distributed around it.

[0035] Using a mixed solution of phosphoric acid solution (90% wt) and hydrochloric acid solution (35% wt) at a volume ratio of 1:5, etch for 30 seconds; wait for In 0.48 Ga 0.52 After the P-layer pattern is completely etched and formed, a 50nm protective silicon oxide layer 12 is grown by ICP-PECVD; subsequently, ultraviolet lithography is used to define the pattern of the protective silicon oxide layer, as shown in the figure. Figure 3 As shown: It includes a plate structure 13 that shields the entire Schottky diode from a top view to prevent the gallium arsenide material from being corroded; it also includes several connecting structures 14 that connect the plate structure 13 and the gallium arsenide substrate 1, the number of which must meet the requirement that there is at least one in each direction, and the position must meet the requirement that the contact areas mentioned above are exposed from a top view; the plate structure 13 also has through holes located above the cathode metal 5 and the anode metal 7 for bridging the cathode metal 5 and the anode metal 7.

[0036] The protective silicon oxide layer 12 outside the pattern was completely etched using ICP-RIE; finally, the air bridge metal 15 of the diode was connected by ultraviolet lithography and electroplating, completing the fabrication of the first Schottky diode. Figure 2 As shown.

[0037] The obtained first Schottky diode was then placed in a mixed solution of phosphoric acid solution (90% wt) and hydrochloric acid solution (35% wt) at a volume ratio of 1:5 and allowed to stand for 6 hours. The immersed structure was then removed and cleaned by immersion in deionized water three times for half an hour each, yielding the desired result. Figure 4 The structure shown is the second Schottky diode;

[0038] A glass SOG solution was spin-coated onto a quartz substrate 16 at a speed of 2000 rpm for 40 seconds to form a polymer thin layer 17. Figure 5 As shown in (left), the second Schottky diode is completely separated from the gallium arsenide substrate 1 of the second Schottky diode by van der Waals forces adsorption through a microstructured polymer material, namely polydimethylsiloxane 18 for transfer, to obtain the third Schottky diode; then the third Schottky diode is transferred to the aforementioned polymer thin layer 17 to obtain the fourth Schottky diode, the mechanism as follows. Figure 5 (Right) As shown, remove the polydimethylsiloxane 18 used for transfer. Place the fourth Schottky diode in an oven and heat it from room temperature (20°C) to 300°C at a rate of 1°C / min under a nitrogen atmosphere, hold for 2 hours, and then cool it back to 50°C at a rate of 1°C / min to complete the permanent curing and bonding of the interface thin layer.

[0039] Thus, the Schottky diode substrate replacement described in this invention is completed.

Claims

1. A method for replacing a Schottky diode substrate while retaining a gallium arsenide substrate, characterized in that, Includes the following steps: (1) Growth of epitaxial films: Undoped indium gallium phosphide (InGaP) films with a thickness of 135–165 nm were sequentially deposited on gallium arsenide substrates using molecular beam epitaxy. 0.48 Ga 0.52 An epitaxial thin film is formed by a P-layer, a 720–880 nm nano-silicon highly doped N-type gallium arsenide (N+GaAs) layer, and a 90–110 nm nano-silicon lightly doped N-type gallium arsenide (N-GaAs) layer. (2) Fabrication of cathode metal: Photolithography of cathode metal pattern on N-GaAs layer, etching of epitaxial thin film material in cathode metal pattern into N+GaAs layer using first etching solution, etching depth of 225-275nm, and sequentially evaporation of titanium / platinum / gold cathode metal with total thickness of 270-330nm. (3) Fabrication of anode metal: A passivated silicon oxide layer of 45-55 nm is grown on the epitaxial film outside the cathode metal pattern after evaporation; an anode metal pattern is photolithographically patterned on the passivated silicon oxide layer; all passivated silicon oxide layers within the ICP-RIE anode metal pattern are etched using plasma-enhanced reactive ion etching; and a titanium / platinum / gold anode metal with a total thickness of 135-165 nm is deposited within the pattern. (4) Isolation etching: A diode pattern is photolithographically patterned on the upper surface of the epitaxial film, and all N+GaAs and N-GaAs layers outside the diode pattern are removed with the first etching solution. Then, the exposed In... 0.48 Ga 0.52 In was photolithographically formed on the P layer 0.48 Ga 0.52 P-layer graph, In within this graph 0.48 Ga 0.52 The P-layer, viewed from above, includes several directly visible contact areas. Among these contact areas, two contact areas are respectively connected to two In-layer areas that are obscured by the diode pattern. 0.48 Ga 0.52 The P-layer regions are connected, making In 0.48 Ga 0.52 The P layer is easily removed by complete etching; In is removed using a second etching solution. 0.48 Ga 0.52 All In within the P-layer graph 0.48 Ga 0.52 P; (5) Fabrication of a protective silicon oxide layer and completion of air bridge metal connection: A 45-55 nm protective silicon oxide layer is grown on the surface of the epitaxial thin film after isolation etching; a protective silicon oxide layer pattern is photolithographically patterned, the pattern including a plate structure for fixing and completely shielding the thin film material within the diode pattern, and at least four connection structures connecting the gallium arsenide substrate and the plate structure, and through holes for connection above the anode metal and cathode metal; the protective silicon oxide layer pattern does not shield In 0.48 Ga 0.52 Contact area of ​​layer P in top view; All protective silicon oxide material outside the patterned protective silicon oxide layer is etched using plasma-enhanced reactive ion etching (ICP-RIE); after the air bridge metal connection between the cathode metal and the anode metal is completed by photolithography and electroplating, the first Schottky diode structure is formed. (6) Substrate separation: The fabricated Schottky diode is immersed in a second etching solution, and then completely etched in In... 0.48 Ga 0.52 After layer P, In is removed. 0.48 Ga 0.52 The second Schottky diode of the P-layer was soaked and cleaned with deionized water. (7) Substrate replacement: A glass glue solution SOG is spin-coated onto a quartz substrate to form a polymer thin layer; the van der Waals forces of the microstructured polymer material are used to adsorb the second Schottky diode, thereby separating it from the gallium arsenide substrate and obtaining a product with removed In. 0.48 Ga 0.52 The third Schottky diode is formed by the P-layer and gallium arsenide substrate. After the third Schottky diode is transferred to a polymer thin layer on a quartz substrate, a fourth Schottky diode is obtained. The microstructure polymer material is removed, and finally the fourth Schottky diode is heated in a nitrogen atmosphere to complete the bonding.

2. The substrate replacement method according to claim 1, characterized in that, The first corrosive solution is a mixture of phosphoric acid solution (wt90%), hydrogen peroxide solution (wt30%), and water in a volume ratio of 3:1:8; the corrosion time in step (2) is 50 to 70 seconds; the corrosion time in step (4) is 270 to 330 seconds.

3. The substrate replacement method according to claim 1, characterized in that, The second corrosive solution is a mixed solution of phosphoric acid solution (wt90%) and hydrochloric acid solution (wt30%) in a volume ratio of 1:5; the corrosion time in step (4) is 27 to 33 seconds; the corrosion time in step (6) is 324 to 366 minutes.

4. The substrate replacement method according to claim 1, characterized in that, In step (2), the titanium layer in the titanium / platinum / gold cathode metal has a thickness of 18-22 nm, the platinum layer has a thickness of 36-44 nm, and the gold layer has a thickness of 216-264 nm.

5. The substrate replacement method according to claim 1, characterized in that, In step (3), the titanium layer thickness in the titanium / platinum / gold anode metal is 18-22 nm, the platinum layer thickness is 36-44 nm, and the gold layer thickness is 81-99 nm.

6. The substrate replacement method according to claim 1, characterized in that, The deionized water soaking and rinsing described in step (6) includes three rinsing sessions, each lasting 30 minutes.

7. The substrate replacement method according to claim 1, characterized in that, The spin coating of the glass glue solution SOG in step (7) involves maintaining a rotation speed of 2000 rpm and spin coating for 40 seconds.

8. The substrate replacement method according to claim 1, characterized in that, The heating in nitrogen environment described in step (7) includes raising the temperature from room temperature (20°C) to 300°C at a rate of 1°C / minute, holding it for 2 hours, and then lowering it back to 50°C from 300°C at a rate of 1°C / minute.

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