Method for avoiding arcing during etching of a top metal layer

Abstract

The application provides a method for avoiding arc discharge when etching a top metal layer, comprising the following steps: S1, providing a substrate, and sequentially forming a dielectric layer and a photoresist layer on the substrate; S2, when forming a top layer via hole pattern by performing photoetching on the photoresist layer, the area with a cut corner on the wafer is not exposed; S3, etching the dielectric layer to form a top layer via hole in the dielectric layer; and S4, forming a top metal layer on the substrate after filling metal in the top layer via hole. In step S2, the photoresist layer on the area with the cut corner on the wafer is not exposed, and in step S3, the dielectric layer in the area is not formed with the top layer via hole. When etching the top metal layer to form a pad layer, the charged etching gas will not contact the internal charge of the wafer, so that arc discharge is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for avoiding arc discharge when etching the top metal layer. Background Technology

[0002] Integrated circuits on semiconductor wafers are mainly connected to external circuits through the top metal layer, that is, the connection between the device and the subsequent packaging process is achieved through the pad layer. Currently, the most common pad is the aluminum pad.

[0003] In the manufacturing process of semiconductor devices, arcing is an undesirable phenomenon. The top metal layer formed on the wafer is usually an aluminum film layer. When etching the aluminum film layer to form aluminum pads, if the charged etching gas comes into contact with the wafer, the resulting charge often causes arcing, which can lead to the device being broken down by the arc and thus damaged. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method to avoid arc discharge when etching the top metal layer, so as to solve the problem of device damage caused by arc discharge when etching the top metal layer to form a pad in the prior art.

[0005] To achieve the above and other related objectives, this application provides a method for avoiding arc discharge during etching of the top metal layer, comprising:

[0006] Step S1: Provide a substrate, and sequentially form a dielectric layer and a photoresist layer on the substrate;

[0007] In step S2, when photolithography is performed on the photoresist layer to form the top layer via pattern, the area on the wafer where the chamfer is formed is not exposed;

[0008] Step S3: Etch the dielectric layer to form a top-level via in the dielectric layer;

[0009] Step S4: After filling the top-layer via with metal, a top-layer metal layer is formed on the substrate.

[0010] Preferably, no top-layer vias are formed in the dielectric layer of the region where the chamfer is formed on the wafer.

[0011] Preferably, in step S3, a photoresist layer with a top-level via pattern is used as a mask to etch a dielectric layer to form a top-level via in the dielectric layer.

[0012] Preferably, after forming the top-level via in the dielectric layer by etching, the photoresist layer with the top-level via pattern is removed by an ashing process.

[0013] Preferably, a chemical vapor deposition or atomic layer deposition process is used to fill the top-layer vias with metal.

[0014] Preferably, the metal is tungsten.

[0015] Preferably, after the deposition process is completed, a chemical mechanical polishing process is performed to remove the metal outside the top layer through-holes.

[0016] Preferably, the top metal layer is an aluminum film layer.

[0017] Preferably, the aluminum film layer is formed using physical vapor deposition, chemical vapor deposition, or metal sputtering deposition.

[0018] Preferably, after forming the top metal layer, the method further includes the step of etching the top metal layer to form a backing layer.

[0019] As described above, the method for avoiding arc discharge when etching the top metal layer provided in this application has the following beneficial effects: in step S2, the photoresist layer on the area where the chamfer is formed on the wafer is not exposed; in step S3, the top via is not formed in the dielectric layer located in the area; when the top metal layer is etched to form the pad layer, the charged etching gas will not come into contact with the charge inside the wafer, thereby avoiding arc discharge. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 The flowchart shown is a method for avoiding arc discharge when etching the top metal layer according to an embodiment of this application.

[0022] Figure 2 The diagram shown is a schematic diagram of the process of exposing a wafer to form a top-layer via pattern in an embodiment of this application;

[0023] Figure 3 Displayed as Figure 2 A schematic diagram of the cross-sectional structure after the top metal layer is formed in the unexposed area. Detailed Implementation

[0024] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0025] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0029] In semiconductor back-end processes, multilayer metal interconnect structures can be fabricated on a semiconductor substrate according to different needs. Each metal interconnect structure includes metal interconnects and an insulating layer. Trenches and vias are formed within the insulating layer, and then metal is deposited within the trenches and vias. The deposited metal forms the metal interconnects, typically copper. Next, a top metal layer (usually an aluminum film) is deposited on top of this structure, and a pad is formed through photolithography and etching. The top interconnect structure bonds to the pad, preparing for subsequent packaging processes.

[0030] Top-level vias are typically formed between the top-level interconnect structure and the pads. Tungsten filling these vias enables communication between the top-level interconnect structure and the pads. Forming the metal interconnect structure and top-level vias requires multiple plasma etching processes. The continuous action of the plasma causes a large amount of charge to accumulate inside the wafer. After exposing the photoresist layer on the top metal layer, during the etching of the exposed areas, some areas with thinner photoresist layers are etched away first. Then, the charged etching gas contacts the tungsten charge in the exposed aluminum vias, causing wafer discharge. This discharge can break down the film layer (e.g., dielectric layer) on the substrate surface, potentially leading to substrate breakdown and device damage.

[0031] To address this issue, this application provides a method for avoiding arc discharge during the etching of the top metal layer.

[0032] Please see Figure 1 The flowchart illustrates a method for avoiding arc discharge when etching the top metal layer according to an embodiment of this application.

[0033] like Figure 1 As shown, the method for avoiding arc discharge during etching of the top metal layer includes the following steps:

[0034] Step S1: Provide a substrate, and sequentially form a dielectric layer and a photoresist layer on the substrate;

[0035] In step S2, when photolithography is performed on the photoresist layer to form the top layer via pattern, the area on the wafer where the chamfer is formed is not exposed;

[0036] Step S3: Etch the dielectric layer to form a top-level via in the dielectric layer;

[0037] Step S4: After filling the top-layer via with metal, a top-layer metal layer is formed on the substrate.

[0038] In step S1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the substrate material may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material according to the type of device structure formed on the substrate, therefore the type of substrate should not limit the scope of protection of this invention.

[0039] Multiple isolation components are formed on the substrate, dividing the substrate into multiple regions. The isolation components can be composed of any insulating material such as silicon dioxide (SiO2), or a "high-k" dielectric with a high dielectric constant, for example, greater than 3.9. In some cases, the isolation components can be composed of oxide materials. Suitable materials for constituting the isolation components include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), bauxite (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties, either currently known or developed later.

[0040] For example, the isolation component is formed by a shallow trench isolation process (STI), which includes, but is not limited to, shallow trench etching, oxide filling, and oxide planarization.

[0041] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.

[0042] Various semiconductor devices, such as MOSFETs and diodes, are formed in different regions of the substrate.

[0043] An interlayer dielectric layer is formed on the substrate. Optionally, the material of the interlayer dielectric layer is, for example, but not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ether, or other materials with low dielectric constant (<3.9).

[0044] The number of interlayer dielectric layers can be any, and each interlayer dielectric layer contains vias and conductors, including any conventional structure. The vias and conductors in the interlayer dielectric layers can be formed using any known or future developed techniques, such as dielectric deposition, patterning, etching, refractory metal pad deposition, conductor deposition, planarization, capping deposition, etc.

[0045] In this embodiment, the dielectric layer is also considered as the top dielectric layer. Optionally, the material of the dielectric layer may include, but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).

[0046] For example, a chemical vapor deposition process is used to form the dielectric layer.

[0047] For example, a photoresist layer is formed using a coating process.

[0048] In step S2, when photolithography is performed on the photoresist layer to form the top layer via pattern, such as... Figure 2 As shown, the area 200 (the black bold square area) on the wafer where the chamfer is formed is not exposed.

[0049] When cutting silicon rods to obtain wafers, the wafer will be... Figure 2 The indicated position (usually the edge position of the 110 or 100 crystal orientation) forms a chamfer, one of the functions of which is to serve as an alignment mark in subsequent processes.

[0050] In step S3, using a photoresist layer with a top-level via pattern as a mask, the dielectric layer is etched to form the top-level via in the dielectric layer. Exemplarily, the etching gases include trifluoromethane (CHF3), chlorine (Cl2), oxygen (O2), and methane (CH4).

[0051] After forming top-level vias in the dielectric layer by etching, the photoresist layer with the top-level via pattern is removed by an ashing process.

[0052] In step S4, for example, a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the top via with metal. This metal is typically tungsten.

[0053] After the above deposition process is completed, a chemical mechanical polishing process is performed to remove the metal outside the top layer through-holes.

[0054] Next, a top metal layer is formed on the substrate through a deposition process, covering the dielectric layer and the metal filling the top via.

[0055] The top metal layer is typically an aluminum film. For example, the aluminum film layer is formed using physical vapor deposition, chemical vapor deposition, or metal sputtering deposition processes.

[0056] Before forming the aluminum film layer, an adhesive layer is first formed on the substrate by a deposition process. For example, the material of the adhesive layer is any one or a mixture of several of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), and tantalum (Ta).

[0057] After the top metal layer is formed, it is etched to form a backing layer.

[0058] Taking an aluminum film layer as the top metal layer as an example, a photoresist layer is first formed on the aluminum film layer through a coating process. Then, a photolithography process is used to sequentially etch the other photoresist layer, the aluminum film layer, and the adhesive layer in the corresponding exposed area. For example, the gases used for etching include chlorine (Cl2), boron trichloride (BCl3), nitrogen (N2), and helium (He). After etching is completed, the other photoresist layer is removed through an ashing process.

[0059] In step 2, the photoresist layer in the region where the chamfer is formed on the wafer is not exposed. Therefore, in step S3, no top-layer via is formed in the dielectric layer located in this region. After forming another photoresist layer on the top metal layer, the cross-sectional structure of the region where the chamfer is formed on the wafer is as follows. Figure 3 As shown, a dielectric layer 301, an adhesive layer 302, a top metal layer 303, and another photoresist layer 305 are sequentially formed on the substrate 300.

[0060] The thickness of another photoresist layer 305 forming the chamfered area on the wafer is thinner than the thickness of another photoresist layer 305 in other areas of the wafer. Since no top-layer via is formed in this area, it is not necessary to form a backing layer in this area. This avoids the situation where, in the prior art, when a backing layer is formed in this area, the photoresist layer in this area is etched away first, causing the charged etching gas to come into contact with the wafer charge led out by the exposed top-layer metal layer and the metal filled in the top-layer via, resulting in arc discharge. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0061] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for avoiding arc discharge during etching of the top metal layer, characterized in that, The method includes: Step S1: Provide a substrate, and sequentially form a dielectric layer and a photoresist layer on the substrate; In step S2, when photolithography is performed on the photoresist layer to form the top-layer via pattern, the area on the wafer where the chamfer is formed is not exposed; Step S3: Etch the dielectric layer to form the top-layer via in the dielectric layer; the top-layer via is not formed in the dielectric layer in the region where the chamfer is formed on the wafer. Step S4: After filling the top-layer via with metal, a top-layer metal layer is formed on the substrate.

2. The method according to claim 1, characterized in that, In step S3, the dielectric layer is etched using a photoresist layer with the top via pattern as a mask to form the top via in the dielectric layer.

3. The method according to claim 2, characterized in that, After forming the top-level via in the dielectric layer by etching, the photoresist layer with the top-level via pattern is removed by an ashing process.

4. The method according to claim 1, characterized in that, The top-layer vias are filled with metal using chemical vapor deposition or atomic layer deposition.

5. The method according to claim 4, characterized in that, The metal is tungsten.

6. The method according to claim 4, characterized in that, After the deposition process is completed, a chemical mechanical polishing process is performed to remove the metal outside the top layer through-hole.

7. The method according to claim 1, characterized in that, The top metal layer is an aluminum film layer.

8. The method according to claim 7, characterized in that, The aluminum film layer is formed using physical vapor deposition, chemical vapor deposition, or metal sputtering deposition.

9. The method according to claim 1, characterized in that, After forming the top metal layer, the process further includes etching the top metal layer to form a backing layer.

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