Semiconductor package including a connection pad comprising a trench pattern

Abstract

The present disclosure relates to a semiconductor package including a connection pad including a groove pattern. The semiconductor package includes a package substrate, a connection pad including a recessed portion disposed on one surface of the package substrate, and an insulating pattern disposed on the one surface of the package substrate to be spaced apart from the connection pad. The connection pad includes an outer sidewall, an inner sidewall located in the recessed portion and inclined in an inward direction from an upper portion, and a groove pattern formed on the inner sidewall.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor packages including connection pads containing a groove pattern. Background Technology

[0002] Semiconductor package manufacturing processes may include: separating a wafer that has completed semiconductor integration processes into chip units; mounting the separated chips onto a package substrate and electrically connecting the chips to the package substrate; molding the chips on the package substrate; and forming solder connection structures on connection pads disposed on the surface of the package substrate.

[0003] Solder connection structures can perform the function of electrically connecting a package substrate to an external system. The process of forming a solder connection structure may include: mounting separately prepared solder balls onto connection pads, reflowing the solder balls using heat, and attaching the reflowed solder balls to the connection pads. Summary of the Invention

[0004] A semiconductor package according to an embodiment of the present disclosure includes: a package substrate; a bonding pad including a recessed portion and disposed on one surface of the package substrate; and an insulating pattern disposed on the one surface of the package substrate and spaced apart from the bonding pad. The bonding pad includes: an outer sidewall; an inner sidewall located in the recessed portion and inclined in an inward direction from the upper portion; and a trench pattern formed on the inner sidewall.

[0005] A semiconductor package according to another embodiment of the present disclosure includes: a package substrate; a bonding pad including a recessed portion and configured to protrude from a surface of the package substrate; and a solder connection structure disposed on the bonding pad. The bonding pad includes: an outer sidewall; an inner sidewall located in the recessed portion and inclined in an inward direction from the upper portion; an inner upper surface connected to the inner sidewall; and a trench pattern forming a spiral path along the perimeter of the inner sidewall in a plan view. Attached Figure Description

[0006] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 2 This is a schematic plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 3 This is a perspective view schematically illustrating the connection pads of a semiconductor package according to an embodiment of the present disclosure.

[0009] Figure 4 It is an illustrative example. Figure 3 A plan view of the groove pattern of the connection pads.

[0010] Figure 5 It is intercepted along line I-I' Figure 3 Cross-sectional view of the connection pads.

[0011] Figures 6 to 10 This is a schematic illustration of a method for forming a solder joint structure using connection pads according to embodiments of the present disclosure.

[0012] Figure 11 and Figure 12 This is a schematic illustration of a method for forming a solder joint structure using connection pads according to a comparative example of the present disclosure. Detailed Implementation

[0013] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (such as the width and thickness of the components) are enlarged to clearly show the components of each device. The terms used herein may correspond to words chosen in consideration of their function in the embodiments, and the meanings of these terms may be interpreted differently according to those skilled in the art to which the embodiments pertain. If a term is clearly defined in detail, it may be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0014] Furthermore, the singular form of a word should be understood to include the plural form of the word, unless otherwise explicitly used in the context. It should be understood that the terms "comprising," "including," or "having" are intended to specify the presence of a feature, number, step, operation, component, element, part, or combination thereof, but are not intended to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0015] Semiconductor packages can include electronic devices such as semiconductor chips, and semiconductor chips can include semiconductor substrates on which electronic circuitry is integrated, the semiconductor substrates being diced and processed in chip form. A semiconductor chip can refer to a memory chip in which memory integrated circuits such as DRAM, SRAM, NAND FLASH, NOR FLASH, MRAM, ReRAM, FeRAM, or PCRAM are integrated, or a logic chip in which logic circuitry is integrated on a semiconductor substrate, or an ASIC chip. Additionally, a semiconductor chip can be referred to as a semiconductor die.

[0016] A semiconductor package may include a printed circuit board (PCB) on which a semiconductor chip is mounted. The PCB may include at least one or more layers of integrated circuit patterns and may be referred to herein as a package substrate. For communication between the package substrate and the semiconductor chip, connection methods such as wire bonding may be applied.

[0017] Semiconductor packages can be used in a variety of electronic information processing devices, such as information communication devices (e.g., portable terminals), biological or health-related electronic devices, and wearable electronic devices.

[0018] Throughout this specification, the same reference numerals denote the same devices. Even if a reference numeral is not mentioned or described with reference to one drawing, it may be mentioned or described with reference to another drawing. Furthermore, even if a reference numeral is not shown in one drawing, it may be shown in another drawing.

[0019] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 2 This is a schematic plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 2 An illustrative example Figure 1 The connection pads and insulating patterns disposed on the surface of the package substrate in a semiconductor package. For ease of description, in Figure 2 The middle part is omitted Figure 1 A diagram of the solder joint structure.

[0020] Reference Figure 1 The semiconductor package 1 may include a package substrate 110 on which a semiconductor chip 200 is mounted. The package substrate 110 may have a first surface 110S1 and a second surface 110S2 on the opposite side of the first surface 110S1. Connecting pads 120 and insulating patterns 130 may be provided on the first surface 110S1 of the package substrate 110. The semiconductor chip 200 may be mounted on the second surface 110S2 of the package substrate 110. When the chip connecting pads 160 of the package substrate 110 and the chip pads 220 of the semiconductor chip 200 are connected to each other by bonding leads 230, the package substrate 110 and the semiconductor chip 200 may be electrically connected to each other.

[0021] Although not illustrated, the package substrate 110 may include at least one layer of integrated circuit pattern. This at least one layer of integrated circuit pattern can electrically connect the connection pads 120 on the first surface 110S1 and the chip connection pads 160 on the second surface 110S2 of the package substrate 110 to each other.

[0022] Reference Figure 1 and Figure 2The connecting pads 120 and the insulating pattern 130 can be configured to be spaced apart from each other on the first surface 110S1 of the package substrate 110. The connecting pads 120 and the insulating pattern 130 can be configured to be spaced apart from each other by a first width W1.

[0023] The connection pads 120 can be configured to protrude from the first surface 110S1 of the package substrate 110. Each of the connection pads 120 can be a pillar structure. (See reference...) Figure 1 Each of the bonding pads 120 may include an outer sidewall 120S1, an inner sidewall 120S2, and an inner upper surface 120S3 connected to the inner sidewall 120S2. (See later...) Figures 3 to 5 The connection pad 120 may include a groove pattern formed along the circumference of the inner sidewall 120S2, the circumference being based on the connection pad 120 having a substantially circular shape in a plan view.

[0024] Each of the connection pads 120 may include a conductive material such as copper (Cu). Solder connection structures 410 may be disposed on the connection pads 120. In one embodiment, each of the solder connection structures 410 may be configured to cover the outer sidewall 120S1, inner sidewall 120S2, and inner upper surface 120S3 of a corresponding one of the connection pads 120.

[0025] The solder joint structure 410 serves to electrically connect the solder pad 120 to an external device. The external device may include, for example, hardware comprising circuitry. The external device may include, for example, a package module, a package card, etc.

[0026] like Figure 2 As shown, the connection pads 120 can be aligned along the x and y directions on the first surface 110S1 of the package substrate 110. Although not illustrated, the connection pads 120 can be electrically connected to at least one layer of integrated circuit pattern on the package substrate 110.

[0027] Reference Figure 1 and Figure 2 The insulating pattern 130 may be configured to protrude from the first surface 110S1 of the package substrate 110. The insulating pattern 130 may be configured to surround and be spaced apart from the connection pad 120. The insulating pattern 130 may include, for example, solder resist or polymer.

[0028] Reference Figure 1The semiconductor chip 200 can be mounted on the second surface 110S2 of the packaging substrate 110. The semiconductor chip 200 may include a chip body 210 and chip pads 220 disposed on the surface 210S of the chip body 210. The chip pads 220 may be disposed in the edge region of the surface 210S of the chip body 210. The chip pads 220 can be electrically connected to chip connection pads 160 disposed on the second surface 110S2 of the packaging substrate 110 via bonding leads 230.

[0029] At the same time, Figure 1 In some embodiments, the package substrate 110 and the semiconductor chip 200 are electrically connected to each other via wire bonding, but this disclosure is not limited to this. In some embodiments not illustrated, the semiconductor chip 200 may be electrically connected to the package substrate 110 via flip-chip bonding using conductive bumps.

[0030] Reference Figure 1 A molding layer 240, which buries the semiconductor chip 200, chip connection pads 160, chip pads 220, and bonding leads 230, can be disposed on the second surface 110S2 of the packaging substrate 110. The molding layer 240 may include an electrically insulating material. The molding layer 240 can be used to protect the semiconductor chip 200 from the influence of the external environment.

[0031] Figure 3 This is a perspective view schematically illustrating the connection pads of a semiconductor package according to an embodiment of the present disclosure. Figure 4 It is an illustrative example. Figure 3 A plan view of the groove pattern of the connection pads. Figure 5 It is intercepted along line I-I' Figure 3 Cross-sectional view of the connection pads.

[0032] Reference Figures 3 to 5 The connecting pad 120 can be a column structure including a recessed portion R. In one embodiment, the depth d of the recessed portion R can be greater than 0 and less than or equal to half the height h of the connecting pad 120. Figure 3 and Figure 5 An example is shown where the depth d of the recessed portion R is half the height h of the connecting pad 120.

[0033] The connection pad 120 may include an outer sidewall 120S1 corresponding to the perimeter surface of the column structure. Additionally, the connection pad 120 may include an inner sidewall 120S2 located within the recessed portion R. For example, the connection pad 120 may include an inner sidewall 120S2 configured to slope inwards or downwards from the upper portion of the column structure, and an inner upper surface 120S3 of the column structure connected to the inner sidewall 120S2. The inner upper surface 120S3 of the column structure may be parallel to... Figure 1 The first surface 110S1 of the packaging substrate 110. The inner sidewall 120S2 and the inner upper surface 120S3 may be located inside the recessed portion R.

[0034] Additionally, the connection pad 120 may include a groove pattern 125 formed along the perimeter of the inner sidewall 120S2. The groove pattern 125 may be perpendicular to... Figure 1 The packaging substrate 110 has a stepped pattern with a step difference on its first surface 110S1 in the direction (i.e., the z-direction). (Refer to...) Figure 5 The trench pattern 125 may include a bottom surface 125B parallel to the first surface 110S1 of the package substrate 110, and an inclined surface 125W having a predetermined tilt angle θ relative to the bottom surface 125B. For example, the tilt angle θ may be greater than 0 degrees and less than or equal to 90 degrees.

[0035] Reference Figure 4 In the plan view, the trench pattern 125 can be a vortex pattern formed on the inner sidewall 120S2. The trench pattern 125 can be configured to form a spiral path along the inner sidewall 120S2 in the plan view. The spiral path can be formed from the top to the bottom of the inner sidewall 120S2 and can reach the inner upper surface 120S3 of the connecting pad 120. The trench pattern 125 can be configured to surround the inner upper surface 120S3.

[0036] Figures 6 to 10 This diagram schematically illustrates a method for forming a solder joint structure using connection pads according to embodiments of the present disclosure. References may be used. Figures 3 to 5 The packaging substrate 110 with the connection pad 120 is described in terms of bonding. Figures 6 to 10 The method described is for forming a solder joint structure.

[0037] Reference Figure 6 The bonding pads 120 and the insulating pattern 130 can be configured to be spaced apart from each other on the first surface 110S1 of the package substrate 110. The bonding pads 120 and the insulating pattern 130 can be configured to protrude from the first surface 110S1.

[0038] The connection pad 120 may include a recessed portion R. The connection pad 120 may include an outer sidewall 120S1, an inner sidewall 120S2, and an inner upper surface 120S3 connected to the inner sidewall 120S2. An insulating pattern 130 may be configured to surround the connection pad 120 while being spaced apart from the connection pad 120 by a predetermined distance W1. Therefore, an empty space O can be formed on the first surface 110S1 between the connection pad 120 and the insulating pattern 130.

[0039] Reference Figure 7 Flux 310 can be supplied to the bonding pads 120 to remove the oxide film formed on the bonding pads 120. The flux 310 can be a viscous material and can be transferred over and supplied to the bonding pads 120 via the flux supply device 300. Sufficient amount of flux 310 can be supplied to adequately cover the exposed surfaces of the bonding pads 120 on the first surface 110S1.

[0040] Additionally, in some cases, when errors occur in the equipment or processes related to the supply of flux 310, flux 310 may be supplied at a location deviating from the designated position on the connecting pad 120. Figure 7 An example is illustrated where a positional error occurs between the reference position of the connection pad 120 and the reference position of the flux supply device 300. Figure 7 An example is given in which the first axis CX1, which is perpendicular to the reference position of the connecting pad 120, and the second axis CX2, which is perpendicular to the reference position of the flux supply device 300, do not coincide with each other, and an error corresponding to the distance D occurs.

[0041] According to embodiments of this disclosure, even if the flux 310 is provided at a location offset from a designated location on the connecting pad 120, the flux 310 can still flow to cover the inner sidewall 120S2 and the inner upper surface 120S3 of the connecting pad 120 if the flux 310 can at least cover the inner sidewall 120S2 of the connecting pad 120 at the offset location.

[0042] In a specific example, the flux 310 supplied to the inner sidewall 120S2 of the connecting pad 120 can move to the lower portion of the inner sidewall 120S2 while traveling along a helical path of the groove pattern 125 around the inner sidewall 120S2. The helical path can be formed such that the fluid flux 310 can move along the groove pattern 125 to the lower portion of the inner sidewall 120S2 at least based on gravity. The flux 310 can flow along the groove pattern 125 to reach the inner upper surface 120S3 of the connecting pad 120. That is, the helical path of the groove pattern 125 formed on the inclined inner sidewall 120S2 can provide a path through which the flux 310 can flow to the inner upper surface 120S3 of the connecting pad 120.

[0043] Reference Figure 7 Because the insulating pattern 130 is configured to surround the connection pad 120, the empty space O can be a closed space. Therefore, when flux 310 is supplied to the empty space O, the flux 310 can flow into the closed space, thereby fully filling the empty space O. As a result, the flux 310 can cover the entire outer sidewall 120S1 of the connection pad 120.

[0044] Figure 8 An example is shown by reference. Figure 6 and Figure 7 The described operation involves flux 310 covering the outer sidewall 120S1, inner sidewall 120S2, and inner upper surface 120S3 of the bonding pad 120. (Refer to...) Figure 9 Individual solder balls 400 can be mounted on the connection pads 120 to which flux 310 has been applied.

[0045] Reference Figure 10 Heat can be applied to reflow the solder balls 400. In this case, the applied heat can allow the flux 310 to chemically react with the bonding pads 120 to remove oxides formed on the bonding pads 120. Alternatively, the applied heat can evaporate and remove the flux 310.

[0046] The reflowed solder balls 400 can cover the surface of the connection pads 120 from which oxides have been removed to form a solder connection structure 410. The solder connection structure 410 can contact the outer sidewall 120S1, the inner sidewall 120S2, and the inner upper surface 120S3 of the connection pads 120. Because the solder connection structure 410 contacts all of the outer sidewall 120S1, the inner sidewall 120S2, and the inner upper surface 120S3 of the connection pads 120, the electrical contact resistance between the solder connection structure 410 and the connection pads 120 can be significantly reduced.

[0047] Figure 11 and Figure 12This diagram schematically illustrates a method for forming a solder joint structure using connection pads according to a comparative example of the present disclosure. The connection pads according to the comparative example may have a different shape than the connection pads according to the embodiments of the present disclosure.

[0048] Reference Figure 11 The connection pad 1200 can be a column structure. The connection pad 1200 may include an outer sidewall 1200S1 as the outer perimeter surface of the column structure, and an upper surface 1200S2 connected to the outer sidewall 1200S1. (This is in contrast to the connection pads according to embodiments of this application.) Figure 6 Compared to 120), the connection pad 1200 does not include the recessed portion R. Furthermore, the connection pad 1200 does not have internal sidewalls or groove patterns formed on the internal sidewalls. The insulating pattern 130 is positioned at a predetermined distance from the connection pad 1200. The insulating pattern 130 is positioned around the connection pad 1200.

[0049] Reference Figure 11 , as reference Figure 7 The flux 310 may be provided at a location that deviates from a designated position on the connecting pad 1200 due to equipment or process errors. Figure 11 An example of a positional error is illustrated, which corresponds to the distance D' between a first axis CX1' perpendicular to the reference position on the connecting pad 1200 and a second axis CX2 perpendicular to the reference position on the flux supply device 300.

[0050] According to the comparative examples of this disclosure, such as Figure 11 As shown, when flux 310 is provided at a location offset from the designated position on the connection pad 1200, flux 310 may have difficulty completely covering the upper surface 1200S2 of the connection pad 1200.

[0051] Reference Figure 12 The flux 310 provided on a portion of the upper surface 1200S2 of the connecting pad 1200 may not flow over the entire flat upper surface 1200S2. According to an embodiment of this application, the connecting pad 1200 does not have the inclined inner sidewalls of the connecting pad 120 and the spiral path of the groove pattern 125 formed on the inner sidewalls. Therefore, the driving force for causing the flux 310 to flow from a portion of the flat upper surface 1200S2 to the entire surface may be insufficient.

[0052] Therefore, oxides may not be adequately removed from the non-contact flux 310 portions of the upper surface 1200S2. As a result, after the reflow process of the solder balls is completed, the adhesion in the contact surfaces of the solder joint structure and the connecting pad 1200 in areas where oxides were not adequately removed may be reduced, leading to poor contact. Poor contact may result in deterioration of the electrical reliability between the connecting pad 1200 and the solder joint structure.

[0053] As described above, according to embodiments of the present disclosure, a semiconductor package may include: a package substrate; bonding pads disposed on a surface of the package substrate; and an insulating pattern disposed on the surface, spaced apart from the bonding pads in a lateral direction. The bonding pads may include: an outer sidewall; an inner sidewall configured to slope inward from an upper portion or downward; and a trench pattern formed along the perimeter of the inner sidewall.

[0054] According to embodiments of this disclosure, when performing a process to remove oxides formed on the bonding pads by providing flux to the surface of the bonding pads, even if the flux is provided at a location offset from a designated position on the upper surface of the bonding pads, the flux flows along the groove pattern formed on the inner sidewalls of the bonding pads, so that the flux completely covers the upper surface. Therefore, after the subsequent solder joint structure formation process, the bonding reliability between the bonding pads and the solder joint structure can be improved.

[0055] Embodiments of this disclosure have been disclosed for illustrative purposes. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure and the appended claims.

[0056] Cross-references to related applications

[0057] This application claims priority to Korean Application No. 10-2021-0157050, filed on November 15, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package, the semiconductor package comprising: Packaging substrate; Connecting pads, the connecting pads including recessed portions and disposed on one surface of the package substrate; as well as An insulating pattern is disposed on one surface of the packaging substrate. The connecting pads include: External sidewalls; An inner sidewall, located within the recessed portion, is inclined inwardly from the upper portion; and A groove pattern is formed on the inner sidewall. The connecting pads and the insulating pattern are spaced apart from each other in the lateral direction to form an empty space on one surface of the packaging substrate.

2. The semiconductor package according to claim 1, wherein the semiconductor package further comprises a semiconductor chip mounted on another surface of the package substrate opposite to the one surface.

3. The semiconductor package according to claim 1, wherein, The connection pads are configured to protrude from one of the surfaces of the package substrate.

4. The semiconductor package according to claim 1, wherein, The connecting pad is a column structure having the recessed portion.

5. The semiconductor package according to claim 4, wherein, The depth of the recessed portion of the connecting pad is greater than 0 and less than or equal to 1 / 2 of the height of the connecting pad.

6. The semiconductor package according to claim 1, wherein, The trench pattern is a stepped pattern having a step difference in a direction perpendicular to one surface of the packaging substrate.

7. The semiconductor package according to claim 1, wherein, In the plan view, the groove pattern is formed along the perimeter of the inner sidewall to form a vortex pattern on the inner sidewall.

8. The semiconductor package according to claim 1, wherein, In the plan view, the groove pattern is formed along the perimeter of the inner sidewall to form a spiral path along the inner sidewall.

9. The semiconductor package according to claim 8, wherein, The spiral path is formed from the top of the inner sidewall to the bottom of the inner sidewall.

10. The semiconductor package according to claim 1, wherein, The connecting pads also include an inner upper surface connected to the inner sidewall.

11. The semiconductor package of claim 10, wherein, In the plan view, the groove pattern is provided on the inner sidewall to surround the inner upper surface.

12. The semiconductor package according to claim 1, wherein, In the plan view, the insulating pattern is arranged to surround the connection pad while being spaced apart from the connection pad.

13. The semiconductor package according to claim 1, wherein the semiconductor package further comprises a solder connection structure disposed on the connection pad.

14. A semiconductor package, the semiconductor package comprising: Packaging substrate; Connecting pads, the connecting pads including recessed portions and configured to protrude from one surface of the package substrate; An insulating pattern is disposed on one surface of the packaging substrate; as well as A solder joint structure is disposed on the connecting pad. The connecting pads include: External sidewalls; An inner sidewall, located within the recessed portion, is inclined inwardly from the upper portion; The inner upper surface, which is connected to the inner sidewall; and A groove pattern, wherein the groove pattern forms a spiral path along the perimeter of the inner sidewall in a plan view. The connecting pads and the insulating pattern are spaced apart from each other in the lateral direction to form an empty space on one surface of the packaging substrate.

15. The semiconductor package of claim 14, wherein, The connecting pad is a column structure having the recessed portion.

16. The semiconductor package of claim 14, wherein, The trench pattern is a stepped pattern having a step difference in a direction perpendicular to one surface of the packaging substrate.

17. The semiconductor package of claim 14, wherein, In the plan view, the groove pattern is a vortex pattern formed on the inner sidewall.

18. The semiconductor package of claim 14, wherein, The spiral path is formed from the top of the inner sidewall to the bottom of the inner sidewall.

19. The semiconductor package of claim 14, wherein, In the plan view, the groove pattern is provided on the inner sidewall to surround the inner upper surface.

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