Display panel and manufacturing method, mother board and mini LED display device

Abstract

Embodiments of the present application provide a display panel and a manufacturing method, a mother board and a mini LED display device, which relate to the technical field of display and avoid short circuit and other problems during testing. The display panel comprises: a panel edge extending along a first direction; a display area and a test area arranged along a second direction, the test area being located between the display area and the panel edge; the test area comprises a plurality of test pads, at least part of the test pads are arranged along the first direction, and a plurality of first electrostatic protection wires are arranged between at least two adjacent test pads in the first direction, the first electrostatic protection wires extending from a side of the display area close to the test area to the panel edge; the first electrostatic protection wires comprise a first segment between the adjacent two test pads and a second segment adjacent to the panel edge, and the interval of the adjacent first segments between the adjacent two test pads in the first direction is smaller than the interval of the adjacent second segments in the first direction.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and in particular to a display panel and its manufacturing method, a motherboard, and a mini LED display device. [Background Technology]

[0002] In the manufacturing process of display panels, in order to save costs and avoid material waste, after the motherboard is cut into the display panel to be tested, it is necessary to test the display panel to be tested to check whether the display panel can emit light normally before bonding the driver chip or printed circuit board.

[0003] Therefore, multiple test pads are set in the display panel to be tested. The test pads need to occupy a lot of space in the lower bezel and are arranged closely with other traces, which may lead to problems such as short circuits during testing. [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and manufacturing method, a motherboard, and a mini LED display device to avoid problems such as short circuits during testing.

[0005] On one hand, embodiments of the present invention provide a display panel, including:

[0006] The edge of the panel extending along the first direction;

[0007] A display area and a test area are arranged along a second direction, the test area being located between the display area and the edge of the panel, the first direction intersecting the second direction; the test area includes a plurality of test pads, at least a portion of the test pads being arranged along the first direction, and a plurality of first electrostatic discharge (ESD) protection traces are included between at least two adjacent test pads in the first direction, the first ESD protection traces extending from the side of the display area closer to the test area to the edge of the panel;

[0008] The first electrostatic discharge protection trace includes a first segment and a second segment. The first segment is located between two adjacent test pads, and the second segment is adjacent to the edge of the panel. Furthermore, the spacing between adjacent first segments in the first direction between two adjacent test pads is smaller than the spacing between adjacent second segments in the first direction.

[0009] On the other hand, embodiments of the present invention provide a motherboard including multiple panel areas, each panel area corresponding to a display panel to be tested, and each panel area including:

[0010] The first edge extending along the first direction;

[0011] A display area and a test area are arranged along a second direction, the test area being located between the display area and the first edge, the first direction intersecting the second direction; the test area includes a plurality of test pads, at least a portion of the test pads being arranged along the first direction, and a plurality of first electrostatic discharge (ESD) protection traces are included between at least two adjacent test pads in the first direction, the first ESD protection traces extending at least from the side of the display area closer to the test area to the first edge;

[0012] The first electrostatic discharge protection trace includes a first segment and a second segment. The first segment is located between two adjacent test pads, and the second segment is connected to the first segment. Furthermore, the spacing between adjacent first segments in the first direction between two adjacent test pads is less than the spacing between adjacent second segments in the first direction.

[0013] In another aspect, embodiments of the present invention provide a method for manufacturing a display panel, comprising:

[0014] Form the aforementioned motherboard;

[0015] The motherboard is cut into multiple independent display panels to be tested;

[0016] A test voltage is applied to the test pads in each of the display panels to be tested, and each of the display panels to be tested is tested.

[0017] A display panel is formed using the display panel to be tested.

[0018] In another aspect, embodiments of the present invention also provide a display panel, which is formed by the above-described display panel manufacturing method.

[0019] In another aspect, embodiments of the present invention also provide a mini LED display device, including the aforementioned display panel.

[0020] One of the above technical solutions has the following beneficial effects:

[0021] In this embodiment of the invention, when designing the first electrostatic discharge (ESD) protection trace, by setting a larger spacing between the second line segments near the edge of the panel, even if metal debris from the cutting process falls between adjacent second line segments when the motherboard is cut along the first cutting line to form the display panel to be tested, the metal debris is unlikely to simultaneously contact both second line segments, thus preventing short circuits between adjacent second line segments. Consequently, in the formed display panel to be tested, each second line segment is independent of the others. Especially when the first ESD protection trace is connected to a pin, short circuits between pins due to short circuits in the second line segments can be avoided, thus preventing false detections caused by signal transmission errors when testing the display panel to be tested.

[0022] Meanwhile, this embodiment of the invention reduces the spacing between adjacent first line segments by narrowing the first line segments. This reduces the total width required by these first line segments in the first direction, thus increasing the distance between the first line segments and the test pads when the interval between two adjacent test pads is constant. This prevents the probes from touching the first line segments during the testing of the display panel under test, avoiding short circuits between the test pads and the first line segments, or between adjacent first line segments. Especially when the first electrostatic discharge (ESD) protection trace in the display panel under test is connected to a pin, short circuits between pins caused by short circuits between the test pads and the first line segments, or between adjacent first line segments, are further avoided, thus preventing false detections during testing of the display panel under test.

[0023] Furthermore, when there are a large number of test pads in the display panel, narrowing the first line segment can reduce the spacing between two adjacent test pads to a certain extent, while ensuring that the first line segment and the test pads are spaced sufficiently apart. This reduces the total width required by the test pads in the first direction and optimizes the arrangement of the test pads on the lower border. [Attached Image Description]

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0026] Figure 2A schematic diagram of the arrangement of the test pad and the first electrostatic protection trace provided in an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a pin connection provided in an embodiment of the present invention;

[0029] Figure 5 This is another schematic diagram of pin connections provided in an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram illustrating a connection between a data cable and a first pad provided in an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram illustrating another connection between the data cable and the first pad provided in an embodiment of the present invention;

[0033] Figure 9 This is a schematic diagram illustrating another connection between the data cable and the first pad provided in an embodiment of the present invention;

[0034] Figure 10 This is another schematic diagram of the connection between the data cable and the first pad provided in an embodiment of the present invention;

[0035] Figure 11 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0036] Figure 12 This is a schematic diagram illustrating another connection between the power signal line and the second pad provided in an embodiment of the present invention;

[0037] Figure 13 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0038] Figure 14 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0039] Figure 15 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0040] Figure 16 This is a schematic diagram of the arrangement of the test pad and the first electrostatic protection trace provided in an embodiment of the present invention.

[0041] Figure 17This is a schematic diagram of the arrangement of the test pad and the first electrostatic protection trace provided in an embodiment of the present invention.

[0042] Figure 18 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0043] Figure 19 This is a schematic diagram of a motherboard structure provided in an embodiment of the present invention;

[0044] Figure 20 This is a schematic diagram of a motherboard structure provided in an embodiment of the present invention;

[0045] Figure 21 for Figure 20 A schematic diagram of the structure of a single display panel to be tested;

[0046] Figure 22 This is a partial structural diagram of the motherboard provided in an embodiment of the present invention;

[0047] Figure 23 for Figure 22 A partially enlarged schematic diagram;

[0048] Figure 24 This is a schematic diagram of another structure of the motherboard provided in an embodiment of the present invention;

[0049] Figure 25 for Figure 24 A corresponding enlarged partial schematic diagram;

[0050] Figure 26 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0051] Figure 27 for Figure 24 Another corresponding enlarged view;

[0052] Figure 28 This is a schematic diagram of another structure of the motherboard provided in an embodiment of the present invention;

[0053] Figure 29 This is a schematic diagram of a panel area provided in an embodiment of the present invention;

[0054] Figure 30 This is another structural schematic diagram of the panel area provided in an embodiment of the present invention;

[0055] Figure 31 This is another structural schematic diagram of the panel area provided in an embodiment of the present invention;

[0056] Figure 32 This is another structural schematic diagram of the motherboard provided in an embodiment of the present invention;

[0057] Figure 33 This is another structural schematic diagram of the motherboard provided in an embodiment of the present invention;

[0058] Figure 34 This is another structural schematic diagram of the motherboard provided in an embodiment of the present invention;

[0059] Figure 35 This is another structural schematic diagram of the motherboard provided in an embodiment of the present invention;

[0060] Figure 36 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention;

[0061] Figure 37 A structural flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention;

[0062] Figure 38 This is another structural flowchart of the method for manufacturing a display panel provided in an embodiment of the present invention;

[0063] Figure 39 This is a schematic diagram of a mini LED display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0064] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0065] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0066] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0067] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0068] Before describing the specific structure of the display panel 100 provided in the embodiments of the present invention, the present invention first describes the manufacturing process of the display panel 100, so as to have a clearer understanding of the structure of the panel edge 1, the first electrostatic protection trace 5, etc. in the display panel 100.

[0069] Typically, display panels are formed by cutting a motherboard. See also Figure 19 The motherboard 200 provided in this embodiment of the invention includes multiple panel areas 300, one panel area 300 corresponds to one display panel 600 to be tested, and the panel area 300 includes structures such as test pads 4.

[0070] Combination Figure 37 and Figure 38 In the process of cutting the motherboard 200 into the display panel 100, firstly, the motherboard 200 is cut along the cutting line 500 to form multiple independent display panels 600 to be tested. The cutting line 500 includes a first cutting line 501, and the edge of the display panel 600 to be tested formed after cutting the motherboard 200 along the first cutting line 501 is the first edge 400. Then, each display panel 600 to be tested is tested. During the test, a test voltage is applied to the test pad 4 in the display panel 600 to be tested. The test voltage is transmitted to various signal lines to control the display panel 600 to display a test image. Based on the displayed test image, the display performance of the display panel 600 to be tested is determined to be normal, thus avoiding material waste caused by directly bonding driver chips or printed circuit boards to defective products. After the test of the display panel 600 to be tested is completed, the display panel is further formed using the display panel 600 to be tested.

[0071] It should be noted that when the display panel is a mini LED display panel, after the motherboard 200 is cut into multiple independent display panels 600 to be tested, a component assembly operation is required to place the mini LEDs on the display panels 600 to be tested, and then the display panels 600 to be tested are tested.

[0072] When further forming a display panel using the display panel 600 to be tested, embodiments of the present invention provide two feasible process methods:

[0073] In the first feasible process, see Figure 37 Instead of cutting the display panel 600 to be tested, the connection between the test pad 4 and various signal lines in the display panel 600 to be tested is directly severed (a break is formed on the connection line 11 between the test pad 4 and the pin 9). That is, using this process, the sub-step structure where the test pad 4 is located is retained in the final structure of the display panel 100, and the display panel 100 contains the test pad 4.

[0074] In the second feasible process, see Figure 38 The test display panel 600 was further cut along the second cutting line 502. This process cuts away the sub-step structure where the test pad 4 is located, so the final display panel 100 does not contain the test pad 4.

[0075] In addition, see Figure 19 In each panel area 300 of the motherboard 200, multiple first electrostatic discharge (ESD) protection traces 5 are provided, with at least some of the first ESD protection traces 5 extending between two adjacent test pads 4. The first ESD protection traces 5 in each panel area 300 further extend outside the panel area 300 and are short-circuited together, then led to the outer edge of the motherboard 200 via leads, thereby releasing static electricity generated during the motherboard 200 manufacturing process to the outside of the motherboard 200, thus providing ESD protection for the motherboard 200. When the motherboard 200 is cut to form the display panel 600 to be tested, the first ESD protection traces 5 are cut at the first edge 400 of the display panel 600 to be tested. During the testing of the display panel 600 to be tested, the first ESD protection traces 5 can still release static electricity to the outside of the display panel 600 to be tested, preventing the circuits in the display panel 600 to be electrostatically damaged, thus also providing ESD protection for the display panel 600 to be tested.

[0076] Based on this, the present invention provides a display panel 100, which can be formed by the first feasible process described above, that is, the sub-step structure where the test pad 4 is located is retained in the display panel 100.

[0077] like Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of a display panel 100 provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the arrangement of the test pad 4 and the first electrostatic discharge protection trace 5 provided in an embodiment of the present invention. The display panel 100 includes a panel edge 1 extending along a first direction x and a display area 2 and a test area 3 arranged along a second direction y. The test area 3 is located between the display area 2 and the panel edge 1, and the first direction x and the second direction y intersect. The panel edge 1 coincides with the first edge 400 of the display panel 600 to be tested, and this edge is formed by cutting the mother plate 200 along the first cutting line 501.

[0078] The test area 3 includes multiple test pads 4, at least some of which are arranged along a first direction x. Furthermore, multiple first electrostatic discharge (ESD) protection traces 5 are included between at least two adjacent test pads 4 along the first direction x. These first ESD protection traces 5 extend from the side of the display area 2 closest to the test area 3 to the panel edge 1. Based on the above description of the manufacturing process of the display panel 100, when the motherboard 200 is cut along the first cutting line 501 to form the display panel 600 to be tested, the first ESD protection traces 5 are cut at the first cutting line 501. Therefore, when the display panel 600 to be tested is further formed into the display panel 100 using the first feasible process, the first ESD protection traces 5 extend from the side of the display area 2 closest to the test area 3 to the panel edge 1 within the display panel 100.

[0079] Among them, see Figure 2 The first electrostatic discharge (ESD) protection trace 5 includes a first segment 6 and a second segment 7. The first segment 6 is located between two adjacent test pads 4, and the second segment 7 is adjacent to the panel edge 1. Furthermore, the spacing d1 between adjacent first segments 6 in the first direction x between two adjacent test pads 4 is smaller than the spacing d2 between adjacent second segments 7 in the first direction x.

[0080] In this embodiment of the invention, when designing the first electrostatic discharge (ESD) protection trace 5, by setting a larger spacing between the second segments 7 near the panel edge 1, when cutting the motherboard 200 along the first cutting line 501 to form the display panel 600 to be tested, even if metal debris generated during cutting falls between adjacent second segments 7, the metal debris is unlikely to simultaneously contact these two second segments 7, thus avoiding short circuits between adjacent second segments 7. Consequently, in the formed display panel 600 to be tested, each second segment 7 is independent of the others. Especially when the first ESD protection trace 5 is connected to a pin, short circuits between pins caused by short circuits in the second segments 7 can be avoided. Therefore, when testing the display panel 600 to be tested, signal transmission errors leading to false detections can be avoided.

[0081] Meanwhile, in this embodiment of the invention, by designing the spacing d1 between adjacent first line segments 6 to be smaller, that is, by narrowing the design of this part of the first line segment 6, the total width required by this part of the first line segment 6 in the first direction x can be reduced. Therefore, when the interval between two adjacent test pads 4 is constant, the distance d3 between the first line segment 6 and the test pad 4 can be increased, thus widening the distance between the first line segment 6 and the test pad 4. In this way, during the testing of the display panel 600 under test, when applying test voltage to the test pad 4 using a probe, the probe can be prevented from touching the adjacent first line segment 6, thereby preventing short circuits between the test pad 4 and the first line segment 6, and between two adjacent first line segments 6. Especially when the first electrostatic discharge protection trace 5 is connected to the pin, short circuits between pins caused by short circuits between the test pad 4 and the first line segment 6, and between two adjacent first line segments 6, can be further avoided. Therefore, during the testing of the display panel 600 under test, false positives due to signal transmission errors can be further avoided.

[0082] Furthermore, when there are a large number of test pads 4 provided in the display panel 100, after narrowing the first line segment 6, while ensuring that the first line segment 6 and the test pad 4 are spaced sufficiently apart, the two adjacent test pads 4 can be placed closer to a certain extent, thereby reducing the total width required by the test pads 4 in the first direction x, optimizing the arrangement of the test pads 4 on the lower bezel, in other words, reducing the total space required by the test pads 4 on the lower bezel, which helps to optimize the narrow bezel design of the display panel 100.

[0083] Furthermore, see again Figure 2 The distance d3 between the test pad 4 and the adjacent first line segment 6 in the first direction x is greater than the distance d1 between the adjacent first line segments 6 in the first direction x between two adjacent test pads 4, so as to ensure that there is a sufficient distance between the test pad 4 and the nearest first line segment 6, and to avoid the probe from scratching the first line segment 6 during the test.

[0084] It should be noted that, in practical applications, the values ​​of the spacing d1 between adjacent first line segments 6 in the first direction x, the spacing d2 between adjacent second line segments 7 in the first direction x, and the spacing d3 between the test pad 4 and its adjacent first line segment 6 in the first direction x can be adjusted according to design parameters such as the design spacing between two adjacent test pads 4 in the display panel, the design number of first electrostatic protection traces 5 between two adjacent test pads 4, and the design line width of the first electrostatic protection traces 5.

[0085] For example, when the design spacing between two adjacent test pads 4 is large and the number of first electrostatic discharge (ESD) protection traces 5 between two adjacent test pads 4 is small, then the values ​​of d1, d2, and d3 can be designed to be larger. Conversely, if the design spacing between two adjacent test pads 4 is small and the number of first ESD protection traces 5 between two adjacent test pads 4 is large, then the values ​​of d1, d2, and d3 can be designed to be smaller, provided that the aforementioned short circuit phenomenon is avoided. That is, the specific values ​​of d1, d2, and d3 can be adaptively adjusted according to the structure of different display panels. This embodiment of the invention does not specifically limit the values ​​of d1, d2, and d3.

[0086] In one feasible implementation, such as Figure 3 and Figure 4 As shown, Figure 3 This is a schematic diagram of another structure of the display panel 100 provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of a connection of pins 9 provided in an embodiment of the present invention. The display panel 100 further includes a bonding area 8 located between the display area 2 and the test area 3. The bonding area 8 includes a plurality of pins 9, which are used to bond with a driver chip or a printed circuit board. At least some of the first ends of the pins 9 are connected to the drive signal line 10, and at least some of the second ends of the pins 9 are connected to the first end 12 of the connecting line 11. The second end 13 of the connecting line 11 is connected to the test pad 4. A break 14 is provided between the first end 12 and the second end 13 of each connecting line 11, and the connecting line 11 is broken at the break 14.

[0087] It should be noted that, in combination Figure 19 and Figure 37 There is no break 14 in the connecting line 11 between the motherboard 200 and the display panel 600 to be tested formed by cutting the motherboard 200. In the display panel 600 to be tested, there is a connection between the drive signal line 10, the pin 9, the connecting line 11 and the test pad 4. In this way, when the test voltage is applied to the test pad 4, the test voltage can be transmitted to the drive signal line 10 through the connecting line 11 and the pin 9, thereby driving the test screen of the display panel 100.

[0088] However, after the test of the display panel 600 is completed, when forming the display panel 100 using the test display panel 600, a break 14 can be formed on the connecting line 11 to cut off the connection between the test pad 4 and the pin 9. In this way, after the display panel 100 is put into use, the connection between the test pad 4 and the drive signal line 10 is disconnected, which can improve the display reliability. In this embodiment of the invention, a laser cutting process can be used to cut the connecting line 11, which reduces the risk of electrostatic discharge, is less likely to generate cutting metal debris, and avoids short circuits between adjacent traces.

[0089] Furthermore, it should be noted that in the embodiments of the present invention, see... Figure 4 When using laser welding and cutting technology, only the connecting line 11 can be laser-cut without cutting the first electrostatic discharge (ESD) protection trace 5. In this way, the first ESD protection trace 5 remains continuous in the final display panel 100, and thus can still be used to release static electricity to the first edge 1. Alternatively, as... Figure 5 As shown, Figure 5 This is another connection diagram of pin 9 provided in an embodiment of the present invention. When using laser welding and cutting process, the first electrostatic discharge protection trace 5 can also be laser cut at the same time, which reduces the requirements for process accuracy and reduces the process difficulty.

[0090] In one feasible implementation, see again Figure 4 and Figure 5 At least some of the second ends of pins 9 are also connected to the first electrostatic discharge (ESD) protection trace 5. Thus, there is a connection between the first ESD protection trace 5 and pins 9. When testing the display panel 600 under test, static electricity in the display panel 600 is more easily conducted away via the first ESD protection trace 5. Furthermore, see... Figure 5 When the first electrostatic discharge protection trace 5 is not broken by laser, the static electricity in the display panel 100 is more easily conducted away through the first electrostatic discharge protection trace 5 after the display panel 100 is put into use.

[0091] In one feasible implementation, such as Figure 6 and Figure 7 As shown, Figure 6 This is another structural schematic diagram of the display panel 100 provided in an embodiment of the present invention. Figure 7 This is a schematic diagram illustrating a connection between the data line Data and the first pad 17 provided in an embodiment of the present invention. Pin 9 includes a first pin 15, drive signal line 10 includes the data line Data located in display area 2, and connecting line 11 includes a first connecting line 16. Specifically, the first end of the first pin 15 is connected to the data line Data, and the second end of the first pin 15 is connected to the first end 12 of the first connecting line 16. It should be noted that the first end of the first pin 15 can be specifically connected to the data line Data in display area 2 via a fan-out line located on the lower bezel.

[0092] The test pad 4 includes at least two first pads 17, each first pad 17 being connected to the second end 13 of a plurality of first connecting lines 16, with a break 14 between the first end 12 and the second end 13 of the first connecting lines 16. Furthermore, the data lines (Data) corresponding to the first connecting lines 16 connected to different first pads 17 are different. At least some of the first pads 17 are arranged along a first direction x, and a plurality of first electrostatic discharge (ESD) protection traces 5 are included between at least two adjacent first pads 17 in the first direction x.

[0093] In one related design, all the data lines (Data) in display area 2 are connected to only one test pad 4. When a data test voltage is applied to the test pad 4, all the sub-pixels in display area 2 emit light simultaneously, displaying only a single test image. However, because display area 2 has a large number of sub-pixels and a high pixel density, with the sub-pixels arranged very closely together, there is a high probability of false detections and false negatives during testing, resulting in some sub-pixels that cannot emit light normally not being identified.

[0094] In this embodiment of the invention, by dividing the data line Data into at least two groups, each group corresponding to a single first pad 17, when testing the display panel 600 under test, a data test voltage can be applied to these at least two first pads 17 at different times, causing the display panel 600 under test to display multiple test screens at different times. When one of the first pads 17 receives the data test voltage, only the sub-pixels corresponding to the portion of the data line Data connected to the first pad 17 display the test screen. The number of luminous sub-pixels in this test screen is relatively small, thus greatly reducing the probability of false detection and missed detection during testing.

[0095] Furthermore, in this embodiment of the invention, multiple first electrostatic protection traces 5 are included between at least two adjacent first pads 17 in the first direction x. The width of the required interval between adjacent first pads 17 can be compressed based on the narrowing design of the first line segment 6 in the first electrostatic protection traces 5 in this embodiment of the invention, thereby compressing the overall space required by all the first pads 17 in the first direction x and optimizing the arrangement of the first pads 17 on the lower frame.

[0096] When one first pad 17 corresponds to multiple data lines (Data), in one possible implementation, see [link to relevant documentation]. Figure 7 The display panel 100 also includes a plurality of pixel columns 19 arranged along a first direction x in the display area 2. Each pixel column 19 includes a plurality of sub-pixels 18 arranged along a second direction y. The data lines Data include a first data line Data1 connected to the (2n-1)th pixel column 19 and a second data line Data2 connected to the 2nth pixel column 19, where n takes values ​​of 1, 2, 3… (For clarity,) Figure 7 The i-th pixel column is denoted by the attached figure label 19_i.

[0097] The first connecting line 16 includes a first sub-connecting line 16_1 and a second sub-connecting line 16_2. The first end of the first sub-connecting line 16_1 is connected to the first data line Data1, and the first end of the second sub-connecting line 16_2 is connected to the second data line Data2.

[0098] The first pad 17 includes at least one first sub-pad 17_1 and at least one second sub-pad 17_2. The first sub-pad 17_1 is connected to a plurality of first sub-connecting lines 16_1, and the second sub-pad 17_2 is connected to a plurality of second sub-connecting lines 16_2.

[0099] Taking the first sub-pad 17_1 as an example, in the display panel 600 under test, when a data test voltage is applied to the first sub-pad 17_1, only the sub-pixels 18 in a plurality of odd-numbered pixel columns 19 emit light to form a test image. Between any two adjacent emitting odd-numbered pixel columns 19, there will be at least one non-emitting even-numbered pixel column 19. Therefore, in each test image, there will be a certain distance between every two adjacent emitting pixel columns 19. When some of the sub-pixels 18 that should emit light do not emit light, it can be easily identified.

[0100] Furthermore, such as Figure 8 As shown, Figure 8 This is another schematic diagram illustrating the connection between the data line (Data) and the first pad 17 provided in an embodiment of the present invention. The display area 2 includes at least two sub-areas 20 arranged along a first direction x. The number of first sub-pads 17_1 is at least two, and the pixel columns 19 corresponding to the first sub-connecting lines 16_1 connected to the at least two first sub-pads 17_1 are respectively located in at least two different sub-areas 20. And / or, the number of second sub-pads 17_2 is at least two, and the pixel columns 19 corresponding to the second sub-connecting lines 16_2 connected to the at least two second sub-pads 17_2 are respectively located in at least two sub-areas 20.

[0101] Taking the first sub-pad 17_1 as an example, in the above setting, the odd number of pixel columns 19 are further divided into at least two groups, and each group is located in a sub-area 20. In this way, when the display panel 600 to be tested is tested, when a data test voltage is applied to one of the first sub-pads 17_1, only the odd number of pixel columns 19 in that sub-area 20 will display the test screen. This ensures that there is a gap between any two light-emitting pixel columns 19, and also makes the light-emitting pixel columns 19 not too scattered in the entire display area 2, which is easy to identify.

[0102] It should be noted that, Figure 8The illustration shows that the display area 2 is divided into two sub-areas 20, and the data lines Data in each sub-area 20 are divided into two groups, one group corresponding to a first sub-pad 17_1 and the other group corresponding to a second sub-pad 17_2. However, in other optional embodiments of the present invention, the sub-areas 20 and the data lines Data can also adopt other division methods. For example, the display area 2 can be divided into three sub-areas 20, and the data lines Data in each sub-area 20 are divided into two groups corresponding to a first sub-pad 17_1 and a second sub-pad 17_2, respectively. Alternatively, for the same sub-area 20, the data lines Data corresponding to the odd number of pixel columns 19 in the sub-area 20 can be divided into two groups corresponding to the two first sub-pads 17_1, while the even number of pixel columns 19 in the sub-area 20 can be divided into only one group corresponding to the second sub-pad 17_2. The embodiments of the present invention will not be illustrated one by one.

[0103] When one first pad 17 corresponds to multiple data lines, in another feasible implementation, such as Figure 9 As shown, Figure 9 This is another schematic diagram of the connection between the data line Data and the first pad 17 provided in an embodiment of the present invention. The display panel 100 also includes a plurality of pixel columns 19 arranged along the first direction x in the display area 2.

[0104] Display area 2 includes at least two sub-areas 20 arranged along a first direction x, wherein the pixel columns 19 corresponding to the first connecting lines 16 connected by at least two first pads 17 are respectively located in at least two sub-areas 20.

[0105] In the above configuration, the data lines Data in each sub-area 20 are divided into groups corresponding to one first pad 17. When testing the display panel 600 to be tested, data test voltages can be applied to at least two first pads 17 at different times, controlling the sub-pixels 18 in at least two sub-areas 20 to present the test screen at different times. This reduces the number of sub-pixels 18 that need to be tested in the test screen, thus reducing the risk of false detections and missed detections. Moreover, the number of first pads 17 in this configuration is also smaller, which reduces the difficulty of manufacturing the test fixture.

[0106] In a feasible real-time approach, such as Figure 10 As shown, Figure 10 This is another schematic diagram of the connection between the data line Data and the first pad 17 provided in an embodiment of the present invention. The pin 9 includes a first pin 15, the drive signal line 10 includes the data line Data located in the display area 2, and the connecting line 11 includes a first connecting line 16. The first end of the first pin 15 is connected to the data line Data, and the second end of the first pin 15 is connected to the first end 12 of the first connecting line 16.

[0107] The test pad 4 includes a plurality of first pads 17, which are connected one-to-one with the second ends 13 of a plurality of first connecting lines 16. At least some of the first pads 17 are arranged along a first direction x, and a plurality of first electrostatic discharge protection lines 5 are included between at least two adjacent first pads 17 in the first direction x.

[0108] In the above setup, when testing the display panel 600 to be tested, data test voltages can be applied to multiple first pads 17 in a time-division manner, so that only one data line Data corresponding to the pixel column 19 illuminates and presents the test screen at the same time. Alternatively, data test voltages can be applied to several first pads 17 simultaneously, so that several data lines Data corresponding to the pixel columns 19 illuminate and present the test screen at the same time. This makes the number of sub-pixels 18 that need to be tested in the test screen very small. When a sub-pixel 18 fails to illuminate normally, it can be easily identified, greatly reducing the probability of false detection or missed detection.

[0109] Furthermore, in this embodiment of the invention, multiple first electrostatic protection traces 5 are included between at least two adjacent first pads 17 in the first direction x. The width of the required interval between adjacent first pads 17 can be compressed based on the narrowing design of the first line segment 6 in the first electrostatic protection traces 5 in this embodiment of the invention, thereby compressing the overall space required by all the first pads 17 in the first direction x and optimizing the arrangement of the first pads 17 on the lower frame.

[0110] In addition, it should be noted that when setting the first pad 17 corresponding to the data line Data, in one setting method, the first pad 17 can be centrally set in the middle area of ​​the lower frame, thereby freeing up some setting space for the test pad 4 connected to other signal lines.

[0111] In one feasible implementation, such as Figure 11 As shown, Figure 11 This is another schematic diagram of the display panel 100 provided in an embodiment of the present invention. Pin 9 includes a second pin 21, drive signal line 10 includes a power signal line 22 located in display area 2, and connecting line 11 includes a second connecting line 23. A first end of one second pin 21 is connected to a power signal line 22, and a second end of one second pin 21 is connected to a first end 12 of a second connecting line 23. A pad includes a second pad 24, which is connected to the second ends 13 of all the second connecting lines 23. A break 14 is provided between the first end 12 and the second end 13 of the second connecting line 23.

[0112] Unlike the connection method between the data line 22 and the first pad 17, this embodiment of the invention does not group the power signal lines 22 when designing the connection method between the power signal lines 22 and the second pad 24. Instead, all power signal lines 22 are connected to the second pad 24. During testing, when a power test voltage is applied to the second pad 24, regardless of which part of the pixel column 19 is currently driving to display the test screen, the sub-pixels 18 in the pixel column 19 can receive the power test voltage.

[0113] Since there are many types of drive signal lines 10 in the display panel 100, it would be difficult to balance test accuracy and space saving if a consistent grouping and testing method were used for all types of drive signal lines 10. This arrangement can reduce the number of corresponding second pads 24 required for the power signal lines 22, thereby reducing the total number of test pads 4 required in the display panel 100.

[0114] Furthermore, in one related design, a power bus is provided in the bezel area, and multiple power signal lines 22 in the display area 2 are led to the power bus and connected to it, and then the power bus is led to pin 9 and connected to it. However, to avoid electrostatic discharge damage to the power bus, the power bus is generally quite wide, requiring a large bezel space at the bottom, resulting in a larger width of the bottom bezel in the second direction y. The arrangement in this embodiment allows each power signal line 22 to be directly led to the bonding area 8 and connected to the second pin 21, eliminating the need for a separate power bus, thus reducing the design size of the bottom bezel in the second direction y.

[0115] Furthermore, see again Figure 11 The pad includes at least two second pads 24, so that during testing, a power supply test voltage can be applied to at least two second pads 24 simultaneously, thereby transmitting the power supply test voltage on at least two second pads 24 to the power signal line 22 in the display area 2 at the same time, reducing the voltage drop of the power supply test voltage during transmission.

[0116] In one feasible implementation, such as Figure 12 As shown, Figure 12 This is another schematic diagram showing the connection between the power signal line 22 and the second pad 24 provided in an embodiment of the present invention. The second pin 21 includes a first sub-pin 21_1, the power signal line 22 includes a positive power signal line PVDD, and the second connecting line 23 includes a third sub-connecting line 23_1. A first end of one first sub-pin 21_1 is electrically connected to a positive power signal line PVDD, and a second end of one first sub-pin 21_1 is connected to a first end 12 of a third sub-connecting line 23_1. The second pad 24 includes a third sub-pad 24_1, and the third sub-pad 24_1 is connected to the second end 13 of all the third sub-connecting lines 23_1.

[0117] And / or, the second pin 21 includes a second sub-pin 21_2, the power signal line 22 includes a negative power signal line PVEE, the second connection line 23 includes a fourth sub-connection line 23_2, a first end of a second sub-pin 21_2 is electrically connected to a negative power signal line PVEE, and a second end of a second sub-pin 21_2 is connected to the first end 12 of a fourth sub-connection line 23_2. The second pad 24 includes a fourth sub-pad 24_2, and the fourth sub-pad 24_2 is connected to the second end 13 of all fourth sub-connection lines 23_2.

[0118] Sub-pixel 18 may specifically include a pixel circuit and a light-emitting element, wherein the light-emitting element may be a mini LED. The aforementioned positive power signal line PVDD is electrically connected to the pixel circuit and is used to transmit a positive power supply voltage to the pixel circuit, driving the pixel circuit to transmit a driving voltage to the positive terminal of the light-emitting element. The aforementioned negative power signal line PVEE is electrically connected to the light-emitting element and is used to transmit a negative power supply voltage to the negative terminal of the light-emitting element. When the positive terminal of the light-emitting element is connected to the driving voltage, the light-emitting element emits light under the action of the driving voltage and the negative power supply voltage.

[0119] In one feasible implementation, such as Figure 13 As shown, Figure 13 This is another schematic diagram of the display panel 100 provided in an embodiment of the present invention. Pin 9 includes a third pin 25, drive signal line 10 includes a fixed potential signal line 26 surrounding the display area 2, and connection line 11 includes a third connection line 27. The first end of the third pin 25 is connected to the fixed potential signal line 26, and the second end of the third pin 25 is connected to the first end 12 of the third connection line 27. Test pad 4 includes a third pad 28, which is connected to the second end 13 of the third connection line 27.

[0120] When testing the display panel 600, it is generally necessary to test all types of signal lines in the display panel 600. Based on the aforementioned, the data line and power signal line 22 can be directly pulled down to the location of pin 9 and connected to pin 9, and then led to the test pad 4. For the other fixed-potential signal lines 26, this embodiment of the invention does not directly pull them down. Instead, these fixed-potential signal lines 26 are led from the outside around the display area 2 to the location of the third pin 25 and connected to the third pin 25. This reduces the crossing between the third connecting line 27 corresponding to these fixed-potential signal lines 26 and other connecting lines 11, allowing the third connecting line 27 corresponding to these fixed-potential signal lines 26 to be set on the same layer as other connecting lines 11, without the need for an additional metal trace layer.

[0121] Furthermore, see again Figure 13 The two ends of the fixed potential signal line 26 are electrically connected to two third pins 25, and one third pin 25 is connected to a third pad 28 through a third connecting line 27. When testing the display panel 600 under test, a power supply test voltage can be applied to both third pads 28 simultaneously, so that the fixed test voltage on the two third pads 28 is transmitted from both ends of the fixed potential signal line 26 to the middle at the same time, reducing the voltage drop of the fixed test voltage during transmission.

[0122] Furthermore, see again Figure 13 In the second direction y, the third pin 25 does not overlap with the display area 2. In this way, when the fixed potential signal line 26 is connected to the third pin 25, it does not need to cross the connection trace (fan-out line) between the data line Data and the first pin 15, or the connection trace between the power signal line 22 and the second pin 21. These traces can be set on the same layer.

[0123] In a feasible real-time manner, see again Figure 13 The display panel 100 also includes a protection circuit 29. The fixed potential signal line 26 includes a constant voltage signal line 30, which surrounds the display area 2 and is connected to the protection circuit 29. In one configuration, the constant voltage signal line 30 includes a first constant voltage signal line VGH and a second constant voltage signal line VGL. The protection circuit 29 can be electrically connected to the data line Data to protect the data line Data from electrostatic discharge.

[0124] And / or, see again Figure 13 The display panel 100 also includes a first reset signal line Vref1 extending along the second direction y in the display area 2. The first reset signal line Vref1 is electrically connected to the pixel circuit and is used to transmit a reset voltage to the pixel circuit, causing the pixel circuit to perform a reset operation. The fixed potential signal line 26 includes a second reset signal line Vref2, which surrounds the display area 2 and is connected to the end of the first reset signal line Vref1 away from the third pad 28. That is, the second reset signal line Vref2 and the first reset signal line Vref1 are connected at the upper bezel. When a reset test voltage is transmitted on the second reset signal line Vref2, the reset test voltage is quickly transmitted to each reset signal line, thereby quickly writing into the sub-pixels 18 of each pixel column 19.

[0125] Furthermore, it should be noted that in the embodiments of the present invention, such as Figure 14 As shown, Figure 14This is another structural schematic diagram of the display panel 100 provided in an embodiment of the present invention. The bonding area 8 may include a first bonding area 31 and two second bonding areas 32 located on both sides of the first bonding area 31 in the first direction x. The first pin 15 is located in the first bonding area 31, which can be used to bond with a driver chip. The second pin 21 and the third pin 25 are located in the second bonding areas 32, which can be used to bond with a printed circuit board. Correspondingly, to optimize the wiring of the connecting lines 11, the first pads 17 are arranged centrally below the first bonding area 31, the second pads 24 may be located on the outer side of the first pads 17 in the first direction x, and the third pads 28 may be located on the outer side of the second pads 24 in the first direction x.

[0126] Furthermore, in this embodiment of the invention, when the test pad 4 includes a first pad 17, a second pad 24, and a third pad 28, a first electrostatic discharge (ESD) protection trace 5 may be provided between two adjacent first pads 17, between two adjacent second pads 24, and between two adjacent third pads 28. Alternatively, a first ESD protection trace 5 may be provided between two adjacent first pads 17 and second pads 24, or between two adjacent second pads 24 and third pads 28. This embodiment of the invention does not impose specific limitations on this.

[0127] In one feasible setup, such as Figure 15 As shown, Figure 15 This is another structural schematic diagram of the display panel 100 provided in an embodiment of the present invention. The test pad 4 is also connected to the second electrostatic discharge protection trace 33, which extends at least to the edge 1 of the panel.

[0128] By connecting a second electrostatic discharge (ESD) protection trace 33 to the test pad 4, the number of ESD discharge paths can be increased. When testing the display panel 600 under test, the static charge on the test pad 4 can be released through the second ESD protection trace 33, thereby improving the ESD protection capability of the display panel 600 under test during testing.

[0129] In one feasible implementation, such as Figure 16 As shown, Figure 16 This is a schematic diagram of the arrangement of the test pad 4 and the first electrostatic discharge protection trace 5 provided in an embodiment of the present invention. The test area 3 includes at least two pad groups 34 arranged along the second direction y, and the pad group 34 includes a plurality of test pads 4 arranged along the first direction x. For the first line segment 6 between adjacent test pads 4 in each pad group 34, the spacing between adjacent first line segments 6 is smaller than the spacing between adjacent second line segments 7.

[0130] In the above setup, when there are a large number of test pads 4, under the condition that the size of the lower border in the first direction x is fixed, by arranging the test pads 4 in at least two rows, the spacing between two adjacent test pads 4 in the first direction x can be increased, thereby further increasing the distance between the test pad 4 and the adjacent first line segment 6, and reducing the risk of the probe hitting the first line segment 6 and causing a short circuit between the first line segments 6 to a greater extent.

[0131] It should be noted that the test pads 4 in at least two pad groups 34 can be aligned or staggered in the second direction y.

[0132] In one feasible implementation, such as Figure 17 As shown, Figure 17 This is a schematic diagram illustrating the arrangement of the test pad 4 and the first electrostatic discharge (ESD) protection trace 5 according to an embodiment of the present invention. The test area 3 includes a pad group 34, which includes at least two pad units 35 arranged along a first direction x. Each pad unit 35 includes at least two test pads 4 arranged along the first direction x. Specifically, no first ESD protection trace 5 is provided between adjacent test pads 4 in each pad unit 35, but a first ESD protection trace 5 is provided between adjacent pad units 35. Furthermore, for any adjacent pad unit 35, the spacing between adjacent first line segments 6 is less than the spacing between adjacent second line segments 7.

[0133] In the above configuration, some test pads 4 do not have first electrostatic protection traces 5 on one or both sides. Therefore, when applying test voltage to these test pads 4 with a probe, the risk of the probe coming into contact with the first line segment 6 can be reduced.

[0134] Furthermore, it should be noted that in this embodiment of the invention, the number of first electrostatic protection traces 5 can be greater than or equal to the number of test pads 4, and the number of first electrostatic protection traces 5 provided between two adjacent test pads 4 can be equal or unequal, and this embodiment of the invention does not impose specific limitations on this.

[0135] In one feasible implementation, such as Figure 18 As shown, Figure 18This is another schematic diagram of the display panel 100 provided in an embodiment of the present invention. The driving signal line 10 may further include a scan signal line Scan extending along the first direction x within the display area 2. The scan signal line Scan is electrically connected to the pixel circuit in the sub-pixel 18 and is used to transmit scan signals to the pixel circuit to control the pixel circuit to perform reset and charging operations. The pin 9 also includes a fourth pin 36, the connecting line 11 also includes a fourth connecting line 38, and the test pad 4 also includes a fourth pad 40. One or both ends of each scan signal line Scan are respectively connected to the first end of the fourth pin 36, the second end of the fourth pin 36 is connected to the first end 12 of the fourth connecting line 38, and the second end 13 of the fourth connecting line 38 is connected to the fourth pad 40.

[0136] And / or, the drive signal line 10 may further include an emission control signal line Emit extending along the first direction x within the display area 2. The emission control signal line Emit is electrically connected to the pixel circuit in the sub-pixel 18 and is used to transmit emission control signals to the pixel circuit to control the pixel circuit to perform emission control operations. Pin 9 also includes a fifth pin 37, connecting line 11 also includes a fifth connecting line 39, and test pad 4 also includes a fifth pad 41. One or both ends of each emission control signal line Emit are connected to the first end of the fifth pin 37, the second end of the fifth pin 37 is connected to the first end 12 of the fifth connecting line 39, and the second end 13 of the fifth connecting line 39 is connected to the fifth pad 41.

[0137] When testing the display panel 600, the fourth pad 40 applies a scan test voltage to each scan signal line Scan individually, and the fifth pad 41 applies a light emission control test voltage to each light emission control signal line Emit individually.

[0138] It should be noted that the above design is generally used in mini LED display panels. In LCD and OLED display panels, the scan signal line (Scan) and the emission control signal line (Emit) are typically electrically connected to a shift register. Driven by clock signal lines, frame start signal lines, and other signal lines, the shift register sequentially outputs scan signals to the scan signal line (Scan) or emission control signals to the emission control signal line (Emit). Based on this structure, only some test pads (4) are needed to provide test voltages to the clock signal line, frame start signal line, and other signal lines to drive the shift register output signals normally during testing. However, in mini LED display panels, combined with... Figure 18Each scan signal line corresponds to one or two fourth pads 40, and each emission control signal line corresponds to one or two fifth pads 41. This results in the need for a large number of test pads 4 in this type of display panel, meaning that the number of test pads 4 in a mini LED display panel is generally much greater than that in a liquid crystal display panel or an organic light-emitting diode display panel. Therefore, applying the design of the first electrostatic discharge protection trace 5 provided in this embodiment of the invention to a mini LED display panel will have a more significant improvement effect.

[0139] Based on the same inventive concept, this embodiment of the invention also provides a motherboard 200, combined with... Figure 1 and Figure 2 ,like Figure 19 As shown, Figure 19 This is a schematic diagram of a motherboard 200 provided in an embodiment of the present invention. The motherboard 200 includes multiple panel areas 300, and each panel area 300 corresponds to a display panel 600 to be tested.

[0140] The panel area 300 includes a first edge 400 extending along a first direction x, a display area 2 arranged along a second direction y, and a test area 3, wherein the first direction x and the second direction y intersect. The test area 3 is located between the display area 2 and the first edge 400, and includes a plurality of test pads 4, at least some of which are arranged along the first direction x. Furthermore, between at least two adjacent test pads 4 along the first direction x, there are a plurality of first electrostatic discharge (ESD) protection traces 5 extending at least from the side of the display area 2 closest to the test area 3 to the first edge 400.

[0141] Among them, see Figure 2 The first electrostatic discharge protection trace 5 includes a first segment 6 and a second segment 7. The first segment 6 is located between two adjacent test pads 4. The second segment 7 is connected to the first segment 6. Furthermore, the spacing between adjacent first segments 6 in the first direction x between two adjacent test pads 4 is smaller than the spacing between adjacent second segments 7 in the first direction x.

[0142] In one manufacturing process of the aforementioned display panel 100, combined with Figure 19 and Figure 37First, the motherboard 200 needs to be cut into multiple independent display panels 600 to be tested. Then, each display panel 600 is tested to avoid wasting materials by bonding driver chips or printed circuit boards to defective products. During the testing process, a test voltage is applied to the test pads 4 in the display panel 600. The test voltage is transmitted to various signal lines to control the display panel 600 to display the test screen. Based on the displayed test screen, it can be determined whether the display panel 600 can emit light normally. After the test of the display panel 600 is completed, the display panel is further formed using the display panel 600.

[0143] In this embodiment of the invention, by designing the spacing d1 between adjacent first line segments 6 to be smaller, that is, by narrowing the design of this part of the first line segment 6, the total width required by this part of the first line segment 6 in the first direction x can be reduced. Furthermore, when the interval between two adjacent test pads 4 is constant, the distance d3 between the first line segment 6 and the test pad 4 can be increased, thus widening the distance between the first line segment 6 and the test pad 4. In this way, during the testing of the display panel 600 under test, when applying test voltage to the test pad 4 using a probe, the probe can be prevented from touching the first line segment 6, thereby preventing short circuits between the test pad 4 and the first line segment 6, and between two adjacent first line segments 6. Especially when the first electrostatic discharge protection trace 5 is connected to the pin, short circuits between the pins caused by short circuits between the test pad 4 and the first line segment 6, and between two adjacent first line segments 6, can be further avoided, thus preventing false detections during the testing of the display panel 600 under test.

[0144] Furthermore, when there are a large number of test pads 4 set in each panel area 300, after narrowing the first line segment 6, while ensuring that the first line segment 6 and the test pad 4 can be spaced at a sufficient distance, the spacing between two adjacent test pads 4 can also be reduced to a certain extent, thereby reducing the total width required by the test pads 4 in the first direction x and optimizing the arrangement of the test pads 4 on the lower edge.

[0145] In addition, it should be noted that, see Figure 19 In the motherboard 200, the first electrostatic protection traces 5 in each panel area 300 are further extended to the outside of the panel area 300 and short-circuited together, and then led to the outer edge of the motherboard 200 through leads, so that the static electricity generated in the process of the motherboard 200 is released to the outside of the motherboard 200, thus providing electrostatic protection for the motherboard 200.

[0146] Further, see Figure 2The distance between the test pad 4 and the adjacent first line segment 6 in the first direction x is greater than the distance between the adjacent first line segments 6 in the first direction x between two adjacent test pads 4, so as to ensure that there is a sufficient distance between the test pad 4 and the nearest first line segment 6, and to avoid the probe from scratching the first line segment 6 during the test.

[0147] In one feasible implementation, such as Figure 20 and Figure 21 As shown, Figure 20 This is a schematic diagram of a structure of the motherboard 200 provided in an embodiment of the present invention. Figure 21 for Figure 20 A structural schematic diagram of a single display panel 600 to be tested is provided. The panel area 300 also includes a bonding area 8 located between the display area 2 and the test area 3. The bonding area 8 includes a plurality of pins 9. The first end of at least some of the pins 9 is electrically connected to the drive signal line 10, and the second end of at least some of the pins 9 is electrically connected to the test pad 4 through the connecting line 11.

[0148] Based on the above structure, when testing each display panel 600 under test, the test voltage applied to the test pad 4 is transmitted to the drive signal line 10 via the connection line 11 and the pin 9, thereby driving the display panel 600 under test to display the test screen.

[0149] Furthermore, see again Figure 20 and Figure 21 At least some of the pins 9 are also connected to the first electrostatic discharge protection trace 5. In this way, the first electrostatic discharge protection trace 5 and the pins 9 are connected. When the display panel 600 under test is tested, the static electricity in the display panel 600 under test is more easily conducted away through the first electrostatic discharge protection trace 5.

[0150] In one feasible implementation, combined with Figures 22-26 The second line segment 7 includes a first type of second line segment 40, which is located on the side of the first line segment 6 near the first edge 400. The spacing between adjacent first type of second line segments 40 in the first direction x is greater than the spacing between adjacent first line segments 6 in the first direction x between two adjacent test pads 4.

[0151] In conjunction with the foregoing, in this embodiment of the invention, the motherboard 200 can be used to form the display panel 10 in two ways.

[0152] In the first process of manufacturing the display panel 100, combined with Figures 1-5 , Figure 22 , Figure 23 and Figure 37 , Figure 22 and Figure 23 , Figure 22This is a partial structural diagram of the motherboard 200 provided in an embodiment of the present invention. Figure 23 for Figure 22 A partially enlarged schematic diagram shows that after forming the motherboard 200, the motherboard 200 is cut along the cutting line 500 to form multiple display panels 600 to be tested. The cutting line 500 includes a first cutting line 501, which coincides with a first edge 400. Then, the display panels 600 to be tested are tested. After the test, [further details are needed]. Figures 3-5 The laser is used to cut each connecting line 11 in the display panel 600 to be tested, forming a break 14 on each connecting line 11 to form a break. Figure 3 The display panel 100 shown.

[0153] That is, the display panel 100 obtained by the above structure retains the sub-step where the test pad 4 is located. After the test of the display panel 600 to be tested is completed, the display reliability can be improved by disconnecting the connection line 11 between the test pad 4 and the pin 9.

[0154] In the above structure, the first type of second line segment 40 is adjacent to the first edge 400, which is equivalent to being adjacent to the first cutting line 501. In this embodiment of the invention, by designing the spacing between adjacent first type of second line segments 40 to be larger, when the mother plate 200 is cut along the first cutting line 501, even if the cutting metal debris falls between adjacent first type of second line segments 40, the metal debris is unlikely to come into contact with these two first type of second line segments 40 at the same time, thus avoiding short circuits between adjacent first type of second line segments 40 and thus avoiding adverse effects on the test.

[0155] In the second process flow of the display panel 100, combined with Figure 38 ,like Figures 24-26 As shown, Figure 24 This is another structural schematic diagram of the motherboard 200 provided in an embodiment of the present invention. Figure 25 for Figure 24 A corresponding enlarged schematic diagram, Figure 26 This is another schematic diagram of the structure of the display panel 100 provided in an embodiment of the present invention. After the mother board 200 is formed, it is cut along the cutting line 500 to form multiple independent display panels 600 to be tested. The cutting line 500 includes a first cutting line 501, which coincides with the first edge 400. Then, the display panels 600 to be tested are tested. After the test, the display panels 600 to be tested are cut along the second cutting line 502 to form the display panel 100. The second cutting line is located between the pin 9 and the test pad 4.

[0156] That is, the display panel 100 obtained by the above structure does not retain the sub-step where the test pad 4 is located. After the test of the display panel 600 to be tested is completed, the sub-step where the test pad 4 is located is directly cut off along the second cutting line 502.

[0157] In the above structure, the first type of second line segment 40 is adjacent to the first edge 400, which is also equivalent to being adjacent to the first cutting line 501. By designing the spacing between adjacent first type of second line segments 40 to be larger, when cutting the mother plate 200 along the first cutting line 501, the short circuit of the two adjacent first type of second line segments 40 caused by cutting metal debris can also be avoided, thereby avoiding adverse effects on the test.

[0158] In one feasible implementation, combined with Figures 24-26 ,like Figure 27 As shown, Figure 27 for Figure 24 Another corresponding enlarged schematic diagram shows that the second line segment 7 includes a second type of second line segment 41. The second type of second line segment 41 is located on the side of the first line segment 6 away from the first edge 400, and the spacing between adjacent second type of second line segments 41 is greater than the spacing between adjacent first line segments 6.

[0159] Based on the above description of the second process flow for the display panel 100, after the test of the display panel 600 is completed, the display panel 600 can be further cut along the second cutting line 502 on the side of the first line segment 6 away from the first edge 400. By designing a larger spacing between adjacent second-type second line segments 41, short circuits between adjacent first-type second line segments 40 caused by cutting metal debris can be avoided when further cutting the display panel 600 along the second cutting line 502.

[0160] In one feasible implementation, such as Figure 28 As shown, Figure 28 This is another schematic diagram of the motherboard 200 provided in an embodiment of the present invention. Pin 9 includes a first pin 15, drive signal line 10 includes a data line Data located in display area 2, and connection line 11 includes a first connection line 16. The first end of the first pin 15 is electrically connected to the data line Data, and the second end of the first pin 15 is electrically connected to the first connection line 16. Test pad 4 includes at least two first pads 17, each first pad 17 is electrically connected to multiple first connection lines 16, and the data lines Data coupled to different first pads 17 are different.

[0161] Among them, at least some of the first pads 17 are arranged along the first direction x, and multiple first electrostatic protection lines 5 are included between at least two adjacent first pads 17 in the first direction x.

[0162] In this embodiment of the invention, by dividing the data lines Data into at least two groups, each group corresponding to a single first pad 17, when testing the display panel 600 under test, a data test voltage can be applied to these at least two first pads 17 at different times, causing the display panel 600 under test to display multiple test screens at different times. When one of the first pads 17 receives the data test voltage, only the sub-pixels corresponding to the portion of the data lines Data connected to the first pad 17 display the test screen. The number of luminous sub-pixels in this test screen is relatively small, thus greatly reducing the probability of false detection and missed detection during testing.

[0163] Furthermore, in this embodiment of the invention, multiple first electrostatic protection traces 5 are included between at least two adjacent first pads 17 in the first direction x. The width of the required interval between adjacent first pads 17 can be compressed based on the narrowing design of the first line segment 6 in the first electrostatic protection traces 5 in this embodiment of the invention, thereby compressing the overall space required by all the first pads 17 in the first direction x and optimizing the arrangement of the first pads 17 on the lower frame.

[0164] When one first pad 17 corresponds to multiple data lines Data, in a feasible real-time manner, such as Figure 29 As shown, Figure 29 This is a schematic diagram of a panel area 300 provided in an embodiment of the present invention. The panel area 300 further includes a plurality of pixel columns 19 arranged along a first direction x in the display area 2. The data line Data includes a first data line Data1 electrically connected to the (2n-1)th pixel column 19 and a second data line Data2 electrically connected to the 2nth pixel column 19, where n takes values ​​of 1, 2, 3, ... The first connecting line 16 includes a first sub-connecting line 16_1 connected to the first data line Data1 and a second sub-connecting line 16_2 connected to the second data line Data2. The first pad 17 includes at least one first sub-pad 17_1 and at least one second sub-pad 17_2. One first sub-pad 17_1 is electrically connected to a plurality of first sub-connecting lines 16_1, and one second sub-pad 17_2 is electrically connected to a plurality of second sub-connecting lines 16_2.

[0165] Taking the first sub-pad 17_1 as an example, when a data test voltage is applied to the first sub-pad 17_1, only the sub-pixels 18 in a plurality of odd-numbered pixel columns 19 emit light to form a test image. Between any two adjacent emitting odd-numbered pixel columns 19, there will be at least one non-emitting even-numbered pixel column 19. Therefore, in each test image, there will be a certain distance between every two adjacent emitting pixel columns 19. When some of the sub-pixels 18 that should emit light do not emit light, it can be easily identified.

[0166] Furthermore, such as Figure 30 As shown, Figure 30 This is another structural schematic diagram of the panel area 300 provided in an embodiment of the present invention. The display area 2 includes at least two sub-areas 20 arranged along a first direction x. The number of first sub-pads 17_1 is at least two, and the pixel columns 19 coupled to the at least two first sub-pads 17_1 are respectively located in at least two different sub-areas 20; and / or, the number of second sub-pads 17_2 is at least two, and the pixel columns 19 coupled to the at least two second sub-pads 17_2 are respectively located in at least two sub-areas 20.

[0167] Taking the first sub-pad 17_1 as an example, in the above setting, the odd number of pixel columns 19 are further divided into at least two groups, and each group is located in a sub-area 20. In this way, when the display panel 600 to be tested is tested, when a data test voltage is applied to one of the first sub-pads 17_1, only the odd number of pixel columns 19 in that sub-area 20 will display the test screen. This ensures that there is a gap between any two light-emitting pixel columns 19, and also makes the light-emitting pixel columns 19 not too scattered in the entire display area 2, which is easy to identify.

[0168] When one first pad 17 corresponds to multiple data lines Data, in another feasible real-time method, such as Figure 31 As shown, Figure 31 This is another schematic diagram of the panel region 300 provided in an embodiment of the present invention. The panel region 300 further includes a plurality of pixel columns 19 arranged along a first direction x in the display area 2. The display area 2 includes at least two sub-regions 20 arranged along the first direction x, wherein at least two pixel columns 19 coupled to first pads 17 are respectively located in at least two sub-regions 20.

[0169] In the above configuration, the data lines Data in each sub-area 20 are divided into groups corresponding to one first pad 17. When testing the display panel 600 to be tested, data test voltages can be applied to at least two first pads 17 at different times, controlling the sub-pixels 18 in at least two sub-areas 20 to present the test screen at different times. This reduces the number of sub-pixels 18 that need to be tested in the test screen, thus reducing the risk of false detections and missed detections. Moreover, the number of first pads 17 in this configuration is also smaller, which reduces the difficulty of manufacturing the test fixture.

[0170] In one feasible implementation, such as Figure 32 As shown, Figure 32This is another structural schematic diagram of the motherboard 200 provided in an embodiment of the present invention. The pin 9 includes a first pin 15, the drive signal line 10 includes a data line Data located in the display area 2, and the connection line 11 includes a first connection line 16. The first end of the first pin 15 is electrically connected to the data line Data, and the second end of the first pin 15 is electrically connected to the first connection line 16.

[0171] The test pad 4 includes a plurality of first pads 17, which are electrically connected one-to-one with a plurality of first connecting lines 16; wherein, at least some of the first pads 17 are arranged along a first direction x, and a plurality of first electrostatic protection lines 5 are included between at least two adjacent first pads 17 in the first direction x.

[0172] In the above setup, when testing the display panel 600 to be tested, data test voltages can be applied to multiple first pads 17 in a time-division manner, so that only one data line Data corresponding to the pixel column 19 illuminates and presents the test screen at the same time. Alternatively, data test voltages can be applied to several first pads 17 simultaneously, so that several data lines Data corresponding to the pixel columns 19 illuminate and present the test screen at the same time. This makes the number of sub-pixels 18 that need to be tested in the test screen very small. When a sub-pixel 18 fails to illuminate normally, it can be easily identified, greatly reducing the probability of false detection or missed detection.

[0173] Furthermore, in this embodiment of the invention, multiple first electrostatic protection traces 5 are included between at least two adjacent first pads 17 in the first direction x. The width of the required interval between adjacent first pads 17 can be compressed based on the narrowing design of the first line segment 6 in the first electrostatic protection traces 5 in this embodiment of the invention, thereby compressing the overall space required by all the first pads 17 in the first direction x and optimizing the arrangement of the first pads 17 on the lower frame.

[0174] In one feasible implementation, such as Figure 33 As shown, Figure 33 This is another schematic diagram of the motherboard 200 provided in an embodiment of the present invention. Pin 9 includes a second pin 21, drive signal line 10 includes a power signal line 22 located in display area 2, and connecting line 11 includes a second connecting line 23. A first end of one second pin 21 is electrically connected to a power signal line 22, and a second end of one second pin 21 is electrically connected to a second connecting line 23. The pad includes a second pad 24, which is electrically connected to all the second connecting lines 23.

[0175] Unlike the connection method between the data line 22 and the first pad 17, the connection method between the power signal line 22 and the second pad 24 is designed such that the power signal line 22 is not grouped, but all power signal lines 22 are connected to the second pad 24. During testing, when a power test voltage is applied to the second pad 24, regardless of which part of the pixel column 19 is currently driving to display the test screen, the sub-pixels 18 in the pixel column 19 can receive the power test voltage.

[0176] Since there are many types of drive signal lines 10 in the display panel 100, it would be difficult to balance test accuracy and space saving if a consistent grouping and testing method were used for all types of drive signal lines 10. This arrangement can reduce the number of corresponding second pads 24 required for the power signal lines 22, thereby reducing the overall number of test pads 4 required for the lower bezel.

[0177] Furthermore, in one related design, a power bus is provided in the bezel area, and multiple power signal lines 22 in the display area 2 are led to and connected to the power bus, and then the power bus is led to and connected to pin 9. However, to avoid electrostatic discharge damage to the power bus, the power bus is generally quite wide, requiring a large bezel space at the bottom, resulting in a larger width of the bottom bezel in the second direction y. The arrangement in this embodiment allows each power signal line 22 to be directly led to and connected to pin 9, eliminating the need for a separate power bus, and thus reducing the design size of the bottom bezel in the second direction y.

[0178] Furthermore, see again Figure 33 The pad includes at least two second pads 24, so that during testing, a power supply test voltage can be applied to at least two second pads 24 simultaneously, thereby transmitting the power supply test voltage on at least two second pads 24 to the power signal line 22 in the display area 2 at the same time, reducing the voltage drop of the power supply test voltage during transmission.

[0179] Furthermore, such as Figure 34 As shown, Figure 34 This is another schematic diagram of the motherboard 200 provided in an embodiment of the present invention. Pin 9 includes a third pin 25, drive signal line 10 includes a fixed potential signal line 26 surrounding the display area 2, and connection line 11 includes a third connection line 27. The first end of the third pin 25 is electrically connected to the constant voltage signal line 30, and the second end of the third pin 25 is electrically connected to the third connection line 27. Test pad 4 includes a third pad 28, which is electrically connected to the third connection line 27.

[0180] When testing the display panel 600, it is generally necessary to test all types of signal lines in the display panel 600. Based on the above, the data line and power signal line 22 can be directly pulled down to the location of pin 9 and connected to pin 9, and then led to the test pad 4. As for the other fixed potential signal lines 26, this embodiment of the invention does not directly pull down these fixed potential signal lines 26. Instead, these fixed potential signal lines 26 are led from the outside around the display area 2 to the location of the third pin 25 and connected to the third pin 25. This reduces the crossing between the third connecting line 27 corresponding to these fixed potential signal lines 26 and other connecting lines 11. In this way, the third connecting line 27 corresponding to these fixed potential signal lines 26 and other connecting lines 11 can be set on the same layer, without the need for an additional metal trace layer.

[0181] Furthermore, see again Figure 34 The two ends of the fixed potential signal line 26 are electrically connected to two third pins 25, and one third pin 25 is connected to a third pad 28 through a third connecting line 27. When testing the display panel 600 under test, a power supply test voltage can be applied to both third pads 28 simultaneously, so that the fixed test voltage on the two third pads 28 is transmitted from both ends of the fixed potential signal line 26 to the middle at the same time, reducing the voltage drop of the fixed test voltage during transmission.

[0182] Furthermore, see again Figure 34 In the second direction y, the third pin 25 does not overlap with the display area 2. In this way, when the fixed potential signal line 26 is connected to the third pin 25, it does not need to cross the connection trace (fan-out line) between the data line Data and the first pin 15, or the connection trace between the power signal line 22 and the second pin 21. These traces can be set on the same layer.

[0183] In one feasible implementation, see again Figure 34 The panel area 300 also includes a protection circuit 29. The fixed potential signal line 26 includes a constant voltage signal line 30, which surrounds the display area 2 and is electrically connected to the protection circuit 29. In one configuration, the constant voltage signal line 30 includes a first constant voltage signal line VGH and a second constant voltage signal line VGL. The protection circuit 29 can be electrically connected to the data line Data to protect the data line Data from electrostatic discharge.

[0184] And / or, panel area 300 also includes a first reset signal line Vref1 extending in the display area 2 along the second direction y, and fixed potential signal line 26 including a second reset signal line Vref2. The second reset signal line Vref2 surrounds the display area 2 and is connected to the end of the first reset signal line Vref1 away from the third pad 28, that is, the second reset signal line Vref2 and the first reset signal line Vref1 are connected at the upper bezel. When a reset test voltage is transmitted on the second reset signal line Vref2, the reset test voltage is quickly transmitted to each reset signal line, thereby quickly writing into the sub-pixels 18 of each pixel column 19.

[0185] In one feasible implementation, such as Figure 35 As shown, Figure 35 This is another schematic diagram of the motherboard 200 provided in an embodiment of the present invention. The driving signal line 10 may further include a scan signal line Scan extending along the first direction x within the display area 2. The scan signal line Scan is electrically connected to the pixel circuit in the sub-pixel 18 and is used to transmit scan signals to the pixel circuit to control the pixel circuit to perform reset and charging operations. The pin 9 also includes a fourth pin 36, the connecting line 11 also includes a fourth connecting line 38, and the test pad 4 also includes a fourth pad 40. One or both ends of each scan signal line Scan are respectively connected to the first end of the fourth pin 36, and the second end of the fourth pin 36 is connected to the fourth pad 40 through the fourth connecting line 38.

[0186] And / or, the drive signal line 10 may further include an emission control signal line Emit extending along the first direction x within the display area 2. The emission control signal line Emit is electrically connected to the pixel circuit in the sub-pixel 18 and is used to transmit emission control signals to the pixel circuit to control the pixel circuit to perform emission control operations. Pin 9 also includes a fifth pin 37, connecting line 11 also includes a fifth connecting line 39, and test pad 4 also includes a fifth pad 41. One or both ends of each emission control signal line Emit are connected to the first end of the fifth pin 37, and the second end of the fifth pin 37 is connected to the fifth pad 41 via the fifth connecting line 39.

[0187] When testing the display panel 600, the fourth pad 40 applies a scan test voltage to each scan signal line Scan individually, and the fifth pad 41 applies a light emission control test voltage to each light emission control signal line Emit individually.

[0188] As mentioned above, the above design is generally applied in the motherboard 200 used to form a mini LED display panel. Since the number of test pads 4 required to be set in each panel area 300 in this type of motherboard 200 is relatively large, the design of the first electrostatic protection trace 5 provided by the embodiment of the present invention can achieve a better improvement effect.

[0189] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a display panel 100, such as... Figure 36 As shown, Figure 36 This is a flowchart of a method for manufacturing a display panel 100 provided in an embodiment of the present invention. The method includes:

[0190] Step S1: Form the above-mentioned mother plate 200.

[0191] Step S2: Cut the motherboard 200 to form multiple independent display panels 600 to be tested.

[0192] Step S3: Apply a test voltage to the test pads 4 in each display panel 600 to be tested, and test each display panel 600.

[0193] Step S4: Use the display panel 600 to be tested to form the display panel 100.

[0194] Based on the above analysis of the display panel 100 and the motherboard 200, the display panel 100 formed by the above manufacturing method can reduce the risk of the probe hitting the first line segment 6 when applying a test voltage to the test pad 4 using a probe. This avoids short circuits between the test pad 4 and the first line segment 6, as well as between two adjacent first line segments 6, thereby preventing false detections when testing the display panel 600 under test. Furthermore, when the number of test pads 4 provided in each panel area 300 is large, the arrangement of the test pads 4 on the lower bezel can be optimized based on the narrowing design of the first line segment 6.

[0195] It should be noted that when the required display panel is a mini LED display panel, after the motherboard 200 is cut into multiple independent display panels 600 to be tested, a component-making operation is required to place the mini LEDs on the display panels 600 to be tested, and then the display panels 600 to be tested are tested.

[0196] In one feasible implementation, combined with Figure 28 and Figure 29 The panel area 300 also includes a bonding area 8 located between the display area 2 and the test area 3. The bonding area 8 includes a plurality of pins 9, at least some of the first ends of the pins 9 being electrically connected to the drive signal line 10, and at least some of the second ends of the pins 9 being electrically connected to the test pad 4 via the connecting line 11.

[0197] Pin 9 includes a first pin 15, drive signal line 10 includes a data line Data located in display area 2, and connection line 11 includes a first connection line 16. The first end of the first pin 15 is electrically connected to the data line Data, and the second end of the first pin 15 is electrically connected to the first connection line 16. Test pad 4 includes at least two first pads 17, each first pad 17 being electrically connected to multiple first connection lines 16, and different first pads 17 are coupled to different data lines Data. At least some of the first pads 17 are arranged along a first direction x, and multiple first electrostatic discharge (ESD) protection traces 5 are included between at least two adjacent first pads 17 in the first direction x.

[0198] Based on the above structure, the process of applying test voltage to the test pads 4 in each display panel 600 under test includes: applying test voltage to at least two first pads 17 in each display panel 600 under test at different times, so that the display panel 600 under test displays multiple test screens at different times. When one of the first pads 17 receives the data test voltage, only the sub-pixels 18 corresponding to the part of the data line Data connected to the first pad 17 display the test screen. The number of light-emitting sub-pixels 18 in the test screen is small, so the probability of false detection and missed detection can be greatly reduced during testing.

[0199] In one feasible implementation, combined with Figures 3-5 , Figure 22 and Figure 23 The panel area 300 also includes a bonding area 8 located between the display area 2 and the test area 3. The bonding area 8 includes a plurality of pins 9. The first end of the pins 9 is electrically connected to the drive signal line 10, and at least some of the second ends of the pins 9 are electrically connected to the test pad 4 via the connecting line 11.

[0200] Based on this, such as Figure 37 As shown, Figure 37 This is a structural flowchart of a method for manufacturing a display panel provided in an embodiment of the present invention. Step S2 may specifically include: cutting the mother plate 200 along the cutting line 500 to form a plurality of display panels 600 to be tested, wherein the cutting line 500 includes a first cutting line 501, and the first cutting line 501 coincides with the first edge 400.

[0201] Step S4 may specifically include: using a laser to cut the connecting lines 11 in each display panel 600 to be tested, forming a break 14 in each connecting line 11 to form a display panel.

[0202] That is, the display panel 100 obtained by the above manufacturing method retains the sub-step where the test pad 4 is located. After the test of the display panel 600 is completed, the connection between the test pad 4 and the pin 9 can be disconnected by laser cutting the connecting line 11 between the test pad 4 and the pin 9, thereby improving the display reliability after the display panel 100 is put into use. Moreover, using laser cutting of the connecting line 11 reduces the risk of electrostatic discharge and is less likely to generate cutting metal shavings, thus avoiding short circuits between adjacent traces caused by cutting metal shavings.

[0203] Among them, Figure 37 and Figure 38 In step S3, reference numeral 700 indicates the probe.

[0204] In one feasible implementation, combined with Figures 24-26 The panel area 300 also includes a bonding area 8 located between the display area 2 and the test area 3. The bonding area 8 includes a plurality of pins 9. The first end of the pins 9 is electrically connected to the drive signal line 10, and at least some of the second ends of the pins 9 are electrically connected to the test pad 4 via the connecting line 11.

[0205] Based on this, such as Figure 38 As shown, Figure 38 This is another structural flowchart of the method for manufacturing a display panel provided in an embodiment of the present invention. Step S2 may specifically include: cutting the mother plate 200 along the cutting line 500 to form multiple independent display panels 600 to be tested, wherein the cutting line 500 includes a first cutting line 501, and the first cutting line coincides with the first edge 400.

[0206] Step S4 may specifically include: cutting the display panel 600 to be tested along the second cutting line 502 to form the display panel 100, wherein the second cutting line 502 is located between the pin 9 and the test pad 4.

[0207] That is, the display panel 100 obtained by the above manufacturing method does not retain the sub-step where the test pad 4 is located. After the test of the display panel 600 to be tested is completed, the sub-step where the test pad 4 is located is directly cut off along the second cutting line 502. This makes the bottom bezel of the final display panel 100 very narrow, thus optimizing the narrow bezel design of the display panel 100.

[0208] Based on the same inventive concept, embodiments of the present invention also provide a display panel 100, which is formed by the aforementioned manufacturing method of the display panel 100. The display panel 100 formed based on the aforementioned manufacturing method can be used as... Figure 3 The panel structure shown retains test pad 4, and can also be used for... Figure 26 The panel structure shown does not retain test pad 4.

[0209] Based on the same inventive concept, embodiments of the present invention also provide a mini LED display device, such as... Figure 39 As shown, Figure 39 This is a schematic diagram of a mini LED display device provided in an embodiment of the present invention. The display device includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. It should be noted that the display panel 100 can be... Figure 3 The panel structure shown retains test pad 4, and can also be used for... Figure 26 The panel structure shown does not retain test pad 4.

[0210] certainly, Figure 39 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0211] It should be noted that the number of test pads 4 in the display panel of a mini LED display device is generally much greater than that in the display panels of liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs). In the display panels of LCDs and OLEDs, the scan signal line (Scan) and the emission control signal line (Emit) are generally electrically connected to a shift register. Driven by signal lines such as the clock signal line and the start-of-frame signal line, the shift register sequentially outputs scan signals to the scan signal line (Scan) or emission control signals to the emission control signal line (Emit). Based on this structure, only a few test pads 4 are needed to provide test voltages to the clock signal line, the start-of-frame signal line, etc., to drive the shift register output signals normally during testing. However, in the display panel of a mini LED display device, combined with... Figure 18 and Figure 35 Each scan signal line corresponds to one or two fourth pads 40, and each emission control signal line corresponds to one or two fifth pads 41. This results in the need to set a large number of test pads 4 in this type of display panel. For mini LED display devices with a large number of test pads 4, the design of the first electrostatic protection trace 5 provided by the embodiment of the present invention has a more significant improvement effect.

[0212] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0213] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: The edge of the panel extending along the first direction; A display area and a test area are arranged along a second direction, the test area being located between the display area and the edge of the panel, the first direction intersecting the second direction; the test area includes a plurality of test pads, at least a portion of the test pads being arranged along the first direction, and a plurality of first electrostatic discharge (ESD) protection traces are included between at least two adjacent test pads in the first direction, the first ESD protection traces extending from the side of the display area closer to the test area to the edge of the panel; The first electrostatic discharge protection trace includes a first segment and a second segment. The first segment is located between two adjacent test pads, and the second segment is adjacent to the edge of the panel. Furthermore, the spacing between adjacent first segments in the first direction between two adjacent test pads is smaller than the spacing between adjacent second segments in the first direction.

2. The display panel according to claim 1, characterized in that, The distance between the test pad and the adjacent first line segment in the first direction is greater than the distance between adjacent first line segments between two adjacent test pads in the first direction.

3. The display panel according to claim 1, characterized in that, The display panel further includes a bonding area located between the display area and the test area. The bonding area includes a plurality of pins, at least some of the first ends of the pins are connected to a drive signal line, at least some of the second ends of the pins are connected to a first end of a connecting line, and the second end of the connecting line is connected to the test pad. The connecting wires are disconnected at the first and second ends of each of the connecting wires.

4. The display panel according to claim 3, characterized in that, At least some of the second ends of the pins are also connected to the first electrostatic discharge (ESD) protection trace.

5. The display panel according to claim 3, characterized in that, The pin includes a first pin, the drive signal line includes a data line located in the display area, and the connection line includes a first connection line, wherein the first end of the first pin is connected to the data line, and the second end of the first pin is connected to the first end of the first connection line; The test pad includes at least two first pads, one of which is connected to the second end of a plurality of first connecting lines, and the data lines corresponding to the first connecting lines connected to different first pads are different. Wherein, at least a portion of the first pads are arranged along the first direction, and a plurality of first electrostatic protection traces are included between at least two adjacent first pads in the first direction.

6. The display panel according to claim 5, characterized in that, The display panel further includes a plurality of pixel columns arranged along the first direction in the display area, and the data line includes a first data line connected to the (2n-1)th pixel column and a second data line connected to the 2nth pixel column, where n takes values ​​of 1, 2, 3... in sequence; The first connecting line includes a first sub-connecting line and a second sub-connecting line, wherein a first end of the first sub-connecting line is connected to the first data line, and a first end of the second sub-connecting line is connected to the second data line; The first pad includes at least one first sub-pad and at least one second sub-pad, one first sub-pad being connected to a plurality of first sub-connecting lines, and one second sub-pad being connected to a plurality of second sub-connecting lines.

7. The display panel according to claim 6, characterized in that, The display area includes at least two sub-areas arranged along the first direction; The number of the first sub-pads is at least two, and the pixel columns corresponding to the first sub-connecting lines connected by the at least two first sub-pads are respectively located in at least two different sub-regions; And / or, the number of the second sub-pads is at least two, and the pixel columns corresponding to the second sub-connecting lines connected by the at least two second sub-pads are respectively located in at least two sub-regions.

8. The display panel according to claim 5, characterized in that, The display panel further includes a plurality of pixel columns arranged along the first direction in the display area; The display area includes at least two sub-areas arranged along the first direction, wherein the pixel columns corresponding to the first connecting lines connected by at least two first pads are respectively located in at least two of the sub-areas.

9. The display panel according to claim 3, characterized in that, The pin includes a first pin, the drive signal line includes a data line located in the display area, and the connection line includes a first connection line, wherein the first end of the first pin is connected to the data line, and the second end of the first pin is connected to the first end of the first connection line; The test pad includes a plurality of first pads, and the plurality of first pads are connected one-to-one with the second ends of the plurality of first connecting lines; Wherein, at least a portion of the first pads are arranged along the first direction, and a plurality of first electrostatic protection traces are included between at least two adjacent first pads in the first direction.

10. The display panel according to claim 3, characterized in that, The pin includes a second pin, the drive signal line includes a power signal line located in the display area, and the connection line includes a second connection line, wherein the first end of one second pin is connected to one of the power signal lines, and the second end of one second pin is connected to the first end of one of the second connection lines; The pad includes a second pad, which is connected to the second end of all the second connecting lines.

11. The display panel according to claim 10, characterized in that, The liner includes at least two second liner pads.

12. The display panel according to claim 10, characterized in that, The second pin includes a first sub-pin, the power signal line includes a positive power signal line, the second connection line includes a third sub-connection line, the first end of one of the first sub-pins is electrically connected to one of the positive power signal lines, and the second end of one of the first sub-pins is connected to the first end of one of the third sub-connection lines. The second pad includes a third sub-pad, which is connected to the second end of all the third sub-connecting lines; And / or, the second pin includes a second sub-pin, the power signal line includes a negative power signal line, the second connection line includes a fourth sub-connection line, the first end of a second sub-pin is electrically connected to a negative power signal line, and the second end of a second sub-pin is connected to the first end of a fourth sub-connection line; The second pad includes a fourth sub-pad, which is connected to the second end of all the fourth sub-connecting lines.

13. The display panel according to claim 3, characterized in that, The pin includes a third pin, the drive signal line includes a fixed potential signal line that surrounds the display area, and the connection line includes a third connection line, wherein the first end of the third pin is connected to the fixed potential signal line, and the second end of the third pin is connected to the first end of the third connection line. The test pad includes a third pad, which is connected to the second end of the third connecting line.

14. The display panel according to claim 13, characterized in that, The two ends of the fixed potential signal line are electrically connected to the two third pins respectively, and one of the third pins is connected to a third pad through a third connecting line.

15. The display panel according to claim 13, characterized in that, In the second direction, the third pin does not overlap with the display area.

16. The display panel according to claim 13, characterized in that, The display panel also includes a protection circuit, and the fixed potential signal line includes a constant voltage signal line, which surrounds the display area and is connected to the protection circuit. And / or, the display panel further includes a first reset signal line extending in the display area along the second direction, the fixed potential signal line including a second reset signal line, the second reset signal line surrounding the display area and connected to the end of the first reset signal line remote from the third pad.

17. The display panel according to claim 1, characterized in that, The test pad is also connected to a second electrostatic discharge (ESD) protection trace, which extends at least to the edge of the panel.

18. The display panel according to claim 1, characterized in that, The test area includes at least two sets of pads arranged along the second direction, and each set of pads includes a plurality of the test pads arranged along the first direction; For the first line segment between adjacent test pads in each of the pad groups, the spacing between adjacent first line segments is smaller than the spacing between adjacent second line segments.

19. The display panel according to claim 1, characterized in that, The test area includes a pad assembly, the pad assembly including at least two pad units arranged along the first direction, and the pad unit including at least two of the test pads arranged in the first direction; In this configuration, no first electrostatic discharge (ESD) protection trace is provided between two adjacent test pads in the pad unit, but a first ESD protection trace is provided between two adjacent pad units. Furthermore, for any first line segment between any two adjacent pad units, the spacing between adjacent first line segments is less than the spacing between adjacent second line segments.

20. The display panel according to claim 3, characterized in that, The pins include a fourth pin, the drive signal lines include scan signal lines extending along the first direction, the connecting lines include a fourth connecting line, and the pads include a fourth pad; wherein, one end of each scan signal line is connected to the first end of one of the fourth pins, or, both ends of each scan signal line are respectively connected to the first ends of two of the fourth pins, the second end of the fourth pins is connected to the first end of the fourth connecting line, and the second end of the fourth connecting line is connected to the fourth pad; And / or, the pin further includes a fifth pin, the drive signal line includes a light emission control signal line extending along the first direction, the connecting line includes a fifth connecting line, and the pad includes a fifth pad; wherein, one end of each light emission control signal line is connected to a first end of one of the fifth pins, or, both ends of each light emission control signal line are respectively connected to the first ends of two of the fifth pins, the second end of the fifth pin is connected to the first end of the fifth connecting line, and the second end of the fifth connecting line is connected to the fifth pad.

21. A mother plate, characterized in that, It includes multiple panel areas, each panel area corresponding to a display panel to be tested, and each panel area includes: The first edge extending along the first direction; A display area and a test area are arranged along a second direction, the test area being located between the display area and the first edge, the first direction intersecting the second direction; the test area includes a plurality of test pads, at least a portion of the test pads being arranged along the first direction, and a plurality of first electrostatic discharge (ESD) protection traces are included between at least two adjacent test pads in the first direction, the first ESD protection traces extending at least from the side of the display area closer to the test area to the first edge; The first electrostatic discharge protection trace includes a first segment and a second segment. The first segment is located between two adjacent test pads, and the second segment is connected to the first segment. Furthermore, the spacing between adjacent first segments in the first direction between two adjacent test pads is less than the spacing between adjacent second segments in the first direction.

22. The mother plate according to claim 21, characterized in that, The distance between the test pad and the adjacent first line segment in the first direction is greater than the distance between adjacent first line segments between two adjacent test pads in the first direction.

23. The mother plate according to claim 21, characterized in that, The panel area also includes a bonding area located between the display area and the test area. The bonding area includes a plurality of pins, at least some of the first ends of the pins being electrically connected to a drive signal line, and at least some of the second ends of the pins being electrically connected to the test pad via a connecting line.

24. The mother plate according to claim 23, characterized in that, At least some of the second ends of the pins are also connected to the first electrostatic discharge (ESD) protection trace.

25. The mother plate according to claim 21, characterized in that, The second line segment includes a first type of second line segment, which is located on the side of the first line segment near the first edge, and the spacing between adjacent first type second line segments in the first direction is greater than the spacing between adjacent first line segments in the first direction between two adjacent test pads.

26. The mother plate according to claim 21, characterized in that, The second line segment includes a second type of second line segment, which is located on the side of the first line segment away from the first edge, and the spacing between adjacent second type second line segments is greater than the spacing between adjacent first line segments.

27. The mother plate according to claim 23, characterized in that, The pin includes a first pin, the drive signal line includes a data line located in the display area, and the connection line includes a first connection line, wherein the first end of the first pin is electrically connected to the data line, and the second end of the first pin is electrically connected to the first connection line; The test pad includes at least two first pads, one of which is electrically connected to multiple first connection lines, and the data lines coupled to different first pads are different. Wherein, at least a portion of the first pads are arranged along the first direction, and a plurality of first electrostatic protection traces are included between at least two adjacent first pads in the first direction.

28. The mother plate according to claim 27, characterized in that, The panel area further includes a plurality of pixel columns arranged along the first direction in the display area, and the data line includes a first data line electrically connected to the (2n-1)th pixel column and a second data line electrically connected to the 2nth pixel column, where n takes values ​​of 1, 2, 3... in sequence; The first connecting line includes a first sub-connecting line connected to the first data line and a second sub-connecting line connected to the second data line; The first pad includes at least one first sub-pad and at least one second sub-pad, one of the first sub-pads being electrically connected to a plurality of first sub-connecting lines, and one of the second sub-pads being electrically connected to a plurality of second sub-connecting lines.

29. The mother plate according to claim 28, characterized in that, The display area includes at least two sub-areas arranged along the first direction; The number of the first sub-pads is at least two, and the pixel columns coupled to the at least two first sub-pads are respectively located in at least two different sub-regions; And / or, the number of the second sub-pads is at least two, and the pixel columns coupled to the at least two second sub-pads are respectively located in the at least two sub-regions.

30. The mother plate according to claim 28, characterized in that, The panel area also includes a plurality of pixel columns arranged along the first direction in the display area; The display area includes at least two sub-areas arranged along the first direction, wherein at least two of the pixel columns coupled to the first pad are respectively located in at least two of the sub-areas.

31. The mother plate according to claim 23, characterized in that, The pin includes a first pin, the drive signal line includes a data line located in the display area, and the connection line includes a first connection line, wherein the first end of the first pin is electrically connected to the data line, and the second end of the first pin is electrically connected to the first connection line; The test pad includes a plurality of first pads, and the plurality of first pads are electrically connected to a plurality of first connecting lines in a one-to-one correspondence. Wherein, at least a portion of the first pads are arranged along the first direction, and a plurality of first electrostatic protection traces are included between at least two adjacent first pads in the first direction.

32. The mother plate according to claim 23, characterized in that, The pin includes a second pin, the drive signal line includes a power signal line located in the display area, and the connection line includes a second connection line, wherein the first end of one second pin is electrically connected to one of the power signal lines, and the second end of one second pin is electrically connected to one of the second connection lines; The gasket includes a second gasket, which is electrically connected to all of the second connecting wires.

33. The mother plate according to claim 32, characterized in that, The liner includes at least two second liner pads.

34. The mother plate according to claim 23, characterized in that, The pin includes a third pin, the drive signal line includes a fixed potential signal line that surrounds the display area, and the connection line includes a third connection line, wherein the first end of the third pin is electrically connected to the constant voltage signal line, and the second end of the third pin is electrically connected to the third connection line; The test pad includes a third pad, which is electrically connected to the third connecting line.

35. The mother plate according to claim 34, characterized in that, The two ends of the fixed potential signal line are electrically connected to the two third pins respectively, and one of the third pins is connected to a third pad through a third connecting line.

36. The mother plate according to claim 34, characterized in that, In the second direction, the third pin does not overlap with the display area.

37. The mother plate according to claim 34, characterized in that, The panel area also includes a protection circuit, and the fixed potential signal line includes a constant voltage signal line, which surrounds the display area and is electrically connected to the protection circuit. And / or, the panel area further includes a first reset signal line extending in the display area along the second direction, the fixed potential signal line including a second reset signal line, the second reset signal line surrounding the display area and connected to the end of the first reset signal line away from the third pad.

38. The mother plate according to claim 23, characterized in that, The pins include a fourth pin, the drive signal lines include scan signal lines extending along the first direction, the connecting lines include a fourth connecting line, and the pads include a fourth pad. One end of each scan signal line is connected to the first end of one of the fourth pins, or both ends of each scan signal line are respectively connected to the first ends of two of the fourth pins. The second end of the fourth pins is connected to the fourth pads through the fourth connecting line. And / or, the pin further includes a fifth pin, the drive signal line includes a light emission control signal line extending along the first direction, the connecting line includes a fifth connecting line, and the pad includes a fifth pad, wherein one end of each of the light emission control signal lines is connected to a first end of one of the fifth pins, or both ends of each of the light emission control signal lines are respectively connected to the first ends of two of the fifth pins, and the second end of the fifth pin is connected to the fifth pad through the fifth connecting line.

39. A method for manufacturing a display panel, characterized in that, include: Forming a mother plate as described in any one of claims 21 to 38; The motherboard is cut into multiple independent display panels to be tested; A test voltage is applied to the test pads in each of the display panels to be tested, and each of the display panels to be tested is tested. A display panel is formed using the display panel to be tested.

40. The manufacturing method according to claim 39, characterized in that, The panel area also includes a bonding area located between the display area and the test area. The bonding area includes a plurality of pins, at least some of the first ends of the pins are electrically connected to drive signal lines, and at least some of the second ends of the pins are electrically connected to the test pads via connecting lines. The pin includes a first pin, the drive signal line includes a data line located in the display area, and the connection line includes a first connection line, wherein the first end of the first pin is electrically connected to the data line, and the second end of the first pin is electrically connected to the first connection line; The test pad includes at least two first pads, one of which is electrically connected to multiple first connection lines, and the data lines coupled to different first pads are different. Wherein, at least a portion of the first pads are arranged along the first direction, and a plurality of first electrostatic protection traces are included between at least two adjacent first pads in the first direction; The process of applying a test voltage to the test pads in each of the said display panels under test includes: applying a test voltage to at least two of the first pads in each of the said display panels under test in a time-division manner.

41. The manufacturing method according to claim 39, characterized in that, The panel area also includes a bonding area located between the display area and the test area. The bonding area includes a plurality of pins, the first end of which is electrically connected to a drive signal line, and at least a portion of the second end of which is electrically connected to the test pad via a connecting line. The process of cutting the motherboard into multiple independent display panels to be tested includes: cutting the motherboard along a cutting line to form multiple display panels to be tested, wherein the cutting line includes a first cutting line that coincides with the first edge; The process of forming the display panel using the display panel under test includes: using a laser to cut the connecting lines in each of the display panels under test, forming a break in each of the connecting lines to form the display panel.

42. The manufacturing method according to claim 39, characterized in that, The panel area also includes a bonding area located between the display area and the test area. The bonding area includes a plurality of pins, the first end of which is electrically connected to a drive signal line, and at least a portion of the second end of which is electrically connected to the test pad via a connecting line. The process of cutting the motherboard into multiple independent display panels to be tested includes: cutting the motherboard along a cutting line to form multiple independent display panels to be tested, wherein the cutting line includes a first cutting line that coincides with the first edge; The process of forming the display panel using the display panel under test includes: cutting the display panel under test along a second cutting line to form the display panel, wherein the second cutting line is located between the pin and the test pad.

43. A display panel, characterized in that, It is manufactured by the method of manufacturing the display panel according to any one of claims 39 to 42.

44. A mini LED display device, characterized in that, Includes the display panel as described in any one of claims 1 to 20 and 43.

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