A silicon carbide trench gate mosfet device and method of manufacturing the same

Abstract

This invention belongs to the technical field of semiconductor manufacturing, specifically relating to a silicon carbide trench gate MOSFET device and its fabrication method. A silicon carbide trench gate MOSFET device includes: an N-type substrate and an N- epitaxial layer located on the substrate; the epitaxial layer serves as the drift region of the MOSFET; multiple P-well regions exist above the epitaxial layer; an N+ source region is correspondingly located above each P-well region; the multiple P-well regions are separated by silicon carbide trenches; multiple trench mesas are spaced apart along the trench direction in the silicon carbide trenches. This application utilizes the P+ electric field shielding layer at the bottom of the trench and the trench mesas to effectively shield the trench gate oxide electric field, solving the problem of excessive electric field stress within the trench gate oxide layer and improving gate oxide reliability. Furthermore, the source is connected to the trench bottom P+ electric field shielding layer through the trench mesas P+ electric field shielding layer, solving the problem that the trench gate bottom P+ electric field shielding layer cannot be effectively grounded.

Description

Technical Field

[0001] This invention belongs to the technical field of semiconductor manufacturing, specifically relating to a silicon carbide trench gate MOSFET device and its fabrication method. Background Technology

[0002] The rise of the new energy electric vehicle market has provided an opportunity for the development of SiC power devices, but it has also placed higher demands on the performance and reliability of SiC devices. As the technology level of SiC chips steadily improves, the performance improvement of SiC planar gate MOSFETs has gradually encountered a bottleneck, while the trench gate MOSFET structure, which can achieve higher current density, has gradually gained favor and become the mainstream structure for next-generation devices.

[0003] However, the commercial application of SiC trench gate MOSFETs requires solving the reliability problem of trench gate oxide. There are generally two ways to improve the reliability of trench gate oxide. One way is to improve the quality of the trench gate oxide layer itself. This requires high requirements for trench etching and trench gate oxide processes. It is necessary to etch to form a smooth and flat trench surface, and at the same time oxidize to form an oxide layer with few defects. Ideally, the trench gate oxide layer is thick at the bottom and thin at the sidewalls. The other way is to introduce a trench gate oxide electric field shielding structure. In recent years, the structural improvements of SiC trench gate MOSFETs have basically revolved around this point. A common method is to implant Al ions at the bottom of the trench to form a P+ electric field shielding layer. The electric field is shielded by the depletion layer expansion in the blocking state, thereby reducing the electric field strength in the trench gate oxide and improving the long-term reliability of the device.

[0004] The P+ electric field shielding layer at the bottom of the trench can be formed before trench etching, which requires high-energy ion implantation technology. This places high demands on the process technology and equipment, and limits the space for shrinking the overall cell size, making it difficult to improve chip performance. Alternatively, the P+ electric field shielding layer can be formed after trench etching, but due to the scattering effect of ion implantation, a certain thickness of P-type inversion layer will form on the trench sidewall, preventing the chip from being forward-biased. Furthermore, grounding the P+ electric field shielding layer is also a problem that needs to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a silicon carbide trench gate MOSFET device and its fabrication method. This application utilizes P+ electric field shielding layers at the bottom of the trench and the trench mesa to effectively shield the gate oxide electric field, solving the problem of excessive electric field stress within the trench gate oxide layer and improving gate oxide reliability. Furthermore, the source is connected to the bottom P+ electric field shielding layer of the trench via the trench mesa P+ electric field shielding layer, solving the problem of the bottom P+ electric field shielding layer of the trench gate not being effectively grounded.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention includes two aspects.

[0007] In a first aspect, a silicon carbide trench gate MOSFET device is provided, comprising: an N-type substrate and an N- epitaxial layer located on the substrate; the epitaxial layer serving as a drift region of the MOSFET; a plurality of P-well regions existing above the epitaxial layer; an N+ source region correspondingly existing above each P-well region; the plurality of P-well regions being separated by silicon carbide trenches; a plurality of trench mesa existing at intervals along the trench direction in the silicon carbide trenches; a P+ electric field shielding layer simultaneously distributed at the bottom of the silicon carbide trenches and inside the trench mesa; a gate oxide layer existing on the inner surface of the silicon carbide trenches; and a polysilicon gate existing in the silicon carbide trenches.

[0008] In some embodiments, the device further includes: a source metal on the upper surface of the epitaxial layer, the source metal being in ohmic contact with the N+ source region and the P+ electric field shielding layer; a gate metal on the upper surface of the polysilicon gate, the gate metal being isolated from the source metal by an interlayer dielectric; a gate-source electrode above the interlayer dielectric, the gate-source electrode being connected to the source metal through a contact hole; and a drain metal on the lower surface of the substrate.

[0009] In some embodiments, the P+ electric field shielding layer is connected to the P-well region.

[0010] In some embodiments, the outer surface of the gate metal is wrapped by the interlayer dielectric.

[0011] Secondly, this application proposes a method for fabricating a silicon carbide trench gate MOSFET device, comprising: forming a P-well region and an N+ source region on the upper surface of a silicon carbide wafer by high-temperature aluminum ion implantation and high-temperature nitrogen ion implantation, respectively; forming a silicon carbide trench on the upper surface of the wafer by dry etching, wherein the depth of the silicon carbide trench is greater than the depth of the P-well region; tilting aluminum ions into the silicon carbide trench to form a P+ electric field shielding layer in the silicon carbide trench; after the P+ electric field shielding layer is formed, performing sacrificial oxidation on the wafer; removing the oxide layer formed by sacrificial oxidation and performing high-temperature activation annealing on the wafer; growing a gate oxide layer on the surface of the silicon carbide trench to form a trench gate oxide layer; depositing polysilicon on the surface of the trench gate oxide layer and etching back to form a trench polysilicon gate.

[0012] In some embodiments, the method further includes: generating source metal on the upper surface of the wafer and patterning the source metal; performing rapid thermal annealing on the wafer to form an ohmic contact between the source metal and the N+ source region and the P+ electric field shielding layer; depositing a first interlayer dielectric on the upper surface of the wafer and etching a gate contact hole on the first interlayer dielectric above the polysilicon gate; growing gate metal in the gate contact hole; depositing a second interlayer dielectric on the upper surface of the wafer and etching a source contact hole on the second interlayer dielectric; growing a gate-source electrode through the source contact hole, while simultaneously growing drain metal on the lower surface of the wafer.

[0013] In some embodiments, the step of tilting the aluminum ions into the silicon carbide trench includes: tilting the aluminum ions twice in the direction of extension of the silicon carbide trench, each time towards a different end of the silicon carbide trench.

[0014] In some embodiments, the wafer is subjected to sacrificial oxidation using either dry oxidation or wet oxidation.

[0015] In some embodiments, the trench gate oxide layer is formed by high-temperature thermal oxidation or CVD process or a combination of both.

[0016] The beneficial effects of this invention are as follows: This application utilizes the P+ electric field shielding layer at the bottom of the trench and the trench mesa to effectively shield the electric field of the trench gate oxide, solving the problem of excessive electric field stress within the trench gate oxide layer and improving gate oxide reliability. Furthermore, the source electrode is connected to the P+ electric field shielding layer at the bottom of the trench via the P+ electric field shielding layer at the trench mesa, solving the problem that the P+ electric field shielding layer at the bottom of the trench gate cannot be effectively grounded. Attached Figure Description

[0017] The scope of this disclosure can be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The accompanying drawings are:

[0018] Figure 1 A schematic diagram of the main structure of a silicon carbide trench gate MOSFET device provided in this application embodiment;

[0019] Figure 2 A planar top view of the main structure of a silicon carbide trench gate MOSFET device provided in this application embodiment;

[0020] Figure 3 A cross-sectional schematic diagram along the AA' direction of a silicon carbide trench gate MOSFET device provided for an embodiment of this application;

[0021] Figure 4A cross-sectional schematic diagram along the BB' direction of a silicon carbide trench gate MOSFET device provided for an embodiment of this application;

[0022] Figure 5 A cross-sectional schematic diagram along the CC' direction of a silicon carbide trench gate MOSFET device provided for an embodiment of this application;

[0023] Figure 6 A cross-sectional schematic diagram along the DD' direction of a silicon carbide trench gate MOSFET device provided for an embodiment of this application;

[0024] Figure 7 A cross-sectional schematic diagram along the direction of the top view AA' after etching a silicon carbide trench in a method for manufacturing a silicon carbide trench gate MOSFET device provided in this application embodiment;

[0025] Figure 8 A cross-sectional schematic diagram along the CC' direction in a planar top view during the formation of a P+ cell shielding layer in a method for manufacturing a silicon carbide trench gate MOSFET device provided in an embodiment of this application;

[0026] Figure 9 A cross-sectional schematic diagram along the AA' direction in a planar top view after forming a P+ cell shielding layer in a method for manufacturing a silicon carbide trench gate MOSFET device provided in an embodiment of this application.

[0027] Figure 10 A cross-sectional schematic diagram along the direction AA' in a planar top view of a method for manufacturing a silicon carbide trench gate MOSFET device provided in an embodiment of this application;

[0028] Figure 11 This is a cross-sectional view along the AA' direction in a planar top view, showing the process of manufacturing a silicon carbide trench gate MOSFET device according to an embodiment of this application, after the gate metal growth is completed. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] If the application documents contain similar descriptions such as "first, second, third", the following explanation shall be added: In the following description, the terms "first, second, third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0033] Example 1:

[0034] The P+ electric field shielding layer at the bottom of the trench can be formed before trench etching, which requires high-energy ion implantation technology. This places high demands on the process technology and equipment, and limits the space for shrinking the overall cell size, making it difficult to improve chip performance. Alternatively, the P+ electric field shielding layer can be formed after trench etching, but due to the scattering effect of ion implantation, a certain thickness of P-type inversion layer will form on the trench sidewall, preventing the chip from being forward-biased. Furthermore, grounding the P+ electric field shielding layer is also a problem that needs to be solved.

[0035] To address the problems existing in the current technology, such as Figures 1 to 6 As shown, this application provides a silicon carbide trench 14 gate MOSFET device, the device comprising: an N-type substrate 1, an epitaxial layer 2, a P-well region 8, an N+ source region 7, a silicon carbide trench 14, a trench mesa 4, a P+ electric field shielding layer 3, a gate oxide layer 6, and a polysilicon gate 5.

[0036] Epitaxial layer 2 is located on the N-type substrate 1. Epitaxial layer 2 is an N-epitaxial layer 2, mainly serving as the drift region of the MOSFET. Above epitaxial layer 2 are multiple P-well regions 8 and N+ source regions 7, with the N+ source regions 7 located above the P-well regions 8 and corresponding to each other. Silicon carbide trenches 14 exist between the multiple P-well regions 8 and the N+ source regions 7, and the silicon carbide trenches 14 are deeper than the P-well regions 8, meaning the bottom of the silicon carbide trenches 14 is farther from the upper surface of epitaxial layer 2 than the bottom of the P-well regions 8. A trench mesa 4 is provided at intervals within the silicon carbide trenches 14, forming a discontinuous line segment structure. The width of the silicon carbide trenches 14 is 0.4 μm-2 μm, the length of each line segment of the silicon carbide trenches 14 is 1 μm-20 μm, and the length of each trench mesa 4 is 0.4 μm-2 μm. The junction depth of the P+ electric field shielding layer 3 located at the bottom of the silicon carbide trench 14 is 0.5μm-2μm.

[0037] A P+ electric field shielding layer 3 is distributed at the bottom of the silicon carbide trench 14 and in the trench mesa 4, and the P+ electric field shielding layer 3 at the bottom of the silicon carbide trench 14 is interconnected with the P+ electric field shielding layer 3 in the trench mesa 4. A gate oxide layer 6 is formed on the inner surface of the silicon carbide trench 14, which covers both the bottom and sides of the silicon carbide trench 14. A polysilicon gate 5 is also present in the silicon carbide trench 14.

[0038] In some embodiments, the device further includes: source metal 9, gate metal 12, interlayer dielectric 10, contact hole, gate-source electrode 11, and drain metal 13.

[0039] The source metal 9 has an upper surface of the epitaxial layer 2, and the source metal 9 forms an ohmic contact with the N+ source region 7 and the P+ electric field shielding layer 3. At this time, the P+ electric field shielding layer 3 that mainly forms an ohmic contact with the source metal 9 is the P+ electric field shielding layer 3 in the trench mesa 4.

[0040] like Figure 4 and Figure 5 As shown, a gate metal 12 exists on the upper surface of the polysilicon gate 5, and the gate metal 12 is isolated from the source metal 9 by an interlayer dielectric 10. The interlayer dielectric 10 actually has two layers: a first interlayer dielectric 10 and a second interlayer dielectric 10. However, in actual devices, the first and second interlayer dielectrics overlap in some areas, making them indistinguishable, so they are collectively referred to as interlayer dielectric 10. This interlayer dielectric 10 encapsulates both the gate metal 12 and the source metal 9, and an interlayer dielectric 10 also exists between the gate metal 12 and the source metal 9. Contact holes are formed in the interlayer dielectric 10 in the source metal 9 region, allowing the gate-source electrode 11 to connect to the source metal 9 through these contact holes. A drain metal 13 exists on the back side of the substrate 1. The gate metal 12 covers the polysilicon gate 5 and the trench mesa 4 along the trench delay direction, while the source metal 9 covers the N+ source region 7 and the trench mesa 4. However, there is an interlayer dielectric 10 separating the source metal 9 from the gate metal.

[0041] In some embodiments, the P+ electric field shielding layer 3 is connected to the P-well region 8.

[0042] This application utilizes the P+ electric field shielding layer 3 at the bottom of the trench and the trench mesa 4 to effectively shield the electric field of the trench gate oxide, solving the problem of excessive electric field stress within the trench gate oxide layer 6 and improving gate oxide reliability. Furthermore, the source electrode is connected to the P+ electric field shielding layer 3 at the bottom of the trench via the P+ electric field shielding layer 3 at the trench mesa 4, solving the problem that the P+ electric field shielding layer 3 at the bottom of the trench gate cannot be effectively grounded.

[0043] Example 2:

[0044] To address the technical problems existing in the prior art, this application proposes a method for fabricating a silicon carbide trench 14-gate MOSFET device in a second aspect. The method includes:

[0045] Step S01: A P-well region 8 and an N+ source region 7 are formed on the upper surface of a silicon carbide wafer by high-temperature aluminum ion implantation and high-temperature nitrogen ion implantation, respectively.

[0046] This application mainly describes the technical means adopted to address the technical problems existing in the background art, so some conventional steps are omitted or simplified. Therefore, the selection and cleaning of the wafer before step S01 are omitted. The formation of the P-well region 8 and the N+ source region 7 is also simplified, that is, the P-well region 8 and the N+ source region 7 are formed by high-temperature aluminum ion implantation and high-temperature nitrogen ion implantation on the upper surface of the silicon carbide wafer.

[0047] Step S02: A silicon carbide trench 14 is formed on the upper surface of the wafer by dry etching, wherein the depth of the silicon carbide trench 14 is greater than the depth of the P-well region 8.

[0048] The silicon carbide trenches 14 formed here have a segmented structure, with trench mesas 4 existing in discontinuous regions. The wafer at this point is as follows: Figure 7 As shown, the trench platform 4 is not shown in this figure to better illustrate the trench.

[0049] Step S03: Aluminum ions are tilted and injected into the silicon carbide trench 14 to form a P+ electric field shielding layer 3 in the silicon carbide trench 14.

[0050] Since the main problem addressed in this application is that the P+ electric field shielding layer 3 at the bottom of the trench mentioned in the prior art can also be formed after trench etching, but due to the scattering effect of ion implantation, a certain thickness of P-type inversion layer will be formed on the sidewall of the trench, causing the chip to be unable to turn on in the forward direction, it is necessary to tilt aluminum ions into the silicon carbide trench 14 at this point.

[0051] Therefore, in some embodiments, step S03, "tilt-injecting aluminum ions into the silicon carbide trench 14", includes:

[0052] Step S031: Aluminum ions are injected twice at an angle toward the extension direction of the silicon carbide trench 14, each time toward a different end of the silicon carbide trench 14.

[0053] like Figure 8As shown in the figure, the direction indicated by the arrows in the dashed lines represents the angle and direction of the tilted implantation. Since the silicon carbide trench 14 in this application is generally segmented, each segment of the silicon carbide trench 14 inevitably has two ends. Therefore, it is necessary to tilt and implant aluminum ions twice, each time tilting towards one end of the silicon carbide trench 14. The purpose of the tilted implantation is to form a P+ electric field shielding layer 3 on both the trench mesa 4 and the trench bottom, and also to reduce ion scattering on the sidewalls of the silicon carbide trench 14. This solves the problem of excessive electric field stress within the trench gate oxide layer 6, improving gate oxide reliability. The tilt angle is between 40° and 80°.

[0054] Step S04: After the P+ electric field shielding layer 3 is formed, the wafer is subjected to sacrificial oxidation treatment.

[0055] Step S05: Remove the oxide layer formed by sacrificial oxidation and perform high-temperature activation annealing on the wafer.

[0056] Even with aluminum ion implantation tilted towards the end of the silicon carbide trench 14, some ions will inevitably be scattered onto the sidewalls of the trench 14. However, the number of ions scattered onto the sidewalls is relatively small and shallow. Therefore, in this application, after the P+ electric field shielding layer 3 is formed, the entire wafer undergoes sacrificial oxidation treatment, causing a certain thickness of silicon carbide on the wafer surface to be oxidized to form an oxide layer. This oxide layer is then removed, minimizing the impact of scattered ions on the trench sidewalls and enabling the chip formed in this application to be forward-conductive. The oxide layer thickness must be greater than 200 nm. The wafer after the P+ electric field shielding layer 3 is formed is shown below. Figure 9 As shown, the trench platform 4 is not shown in this figure in order to represent the trench.

[0057] In some embodiments, the wafer may be subjected to sacrificial oxidation using either dry oxidation or wet oxidation.

[0058] Step S06: A gate oxide layer 6 is grown on the surface of the silicon carbide trench 14 to form a trench gate oxide layer 6.

[0059] Step S07: Polysilicon is deposited on the surface of the trench gate oxide layer 6 and etched back to form the trench polysilicon gate 5.

[0060] After the P+ electric field shielding layer 3 in the silicon carbide trench 14 is processed, the gate oxide layer 6 can be grown on the surface of the silicon carbide trench 14 to form the trench gate oxide layer 6.

[0061] The trench gate oxide layer 6 can be formed using high-temperature thermal oxidation, CVD processes, or a combination of both, and its thickness is between 30nm and 120nm. The wafer after the polysilicon gate 5 is formed is shown in the image. Figure 10As shown.

[0062] In some embodiments, the method for fabricating a silicon carbide trench 14-gate MOSFET device further includes:

[0063] Step S08: Generate source metal 9 on the upper surface of the wafer and perform patterning processing on the source metal 9.

[0064] Step S09: Perform rapid thermal annealing on the wafer to form an ohmic contact between the source metal 9, the N+ source region 7, and the P+ electric field shielding layer 3.

[0065] Since the P+ electric field shielding layer 3 of the trench mesa 4 and the P+ electric field shielding layer 3 at the bottom of the trench are connected in the same way, the problem that the P+ electric field shielding layer 3 at the bottom of the trench gate cannot be effectively grounded can be solved by making ohmic contact between the P+ electric field shielding layer 3 of the trench mesa 4 and the source metal 9.

[0066] Therefore, in step S09, after the source metal 9 is patterned, it covers the N+ source region 7 and the trench mesa 4. Then, under rapid thermal annealing, an ohmic contact is formed between the source metal 9 and the P+ electric field shielding layer 3 of the N-source region and the trench mesa 4. Since the P+ electric field shielding layer 3 of the trench mesa 4 is connected to the P+ electric field shielding layer 3 at the bottom of the trench, the P+ electric field shielding layer 3 at the bottom of the trench gate can be effectively extracted.

[0067] Step S10: Deposit a first interlayer dielectric 10 on the upper surface of the wafer, and etch gate contact holes on the first interlayer dielectric 10 above the polysilicon gate 5.

[0068] Step S11: Grow gate metal 12 in the gate contact hole.

[0069] The interlayer dielectric 10 serves as an isolation layer, preventing direct contact between the gate metal 12 and the source metal 9. After the first interlayer dielectric 10 is deposited, it covers the entire upper surface of the wafer. Then, an aperture is created in the first interlayer dielectric 10 above the polysilicon gate 5 to form a gate contact hole. The gate metal 12 is grown within the gate contact hole, allowing it to connect to the polysilicon gate 5. After the gate metal 12 is grown, it is etched back to cover the trench 14 along its extension direction and over the trench mesa 4. The wafer after the gate metal 12 growth is shown below. Figure 11 As shown.

[0070] Step 12: Deposit a second interlayer dielectric 10 on the upper surface of the wafer, and etch source contact holes on the second interlayer dielectric 10.

[0071] Step S13: Grow the gate source electrode 11 through the source contact hole, and at the same time grow the drain metal 13 on the lower surface of the wafer.

[0072] After the growth of the gate metal 12 is completed, a second interlayer dielectric 10 is deposited on the wafer surface. The deposited second interlayer dielectric 10 covers the entire upper surface of the wafer. Then, a source contact hole is opened above the N+ source region 7, and the gate-source electrode 11 is grown through the source contact hole, wherein the gate-source electrode 11 is connected to the source metal 9.

[0073] In this application, the P+ electric field shielding layer 3 at the bottom of the trench and the P+ electric field shielding layer 3 on the trench mesa 4 are formed simultaneously, requiring only one ion implantation process. Furthermore, it is interconnected with the P-well region 8, eliminating the need for further ion implantation to form the P+ source region, thus reducing process complexity. The P+ electric field shielding layer 3 is formed using a tilted ion implantation process after trench etching, which requires lower ion implantation energy and allows for self-aligned doping using the trench etching mask, further simplifying the process. The sacrificial oxidation following ion implantation removes the ion implantation scattering layer from the sidewalls of the trench, thereby eliminating the channel pinch-off phenomenon during forward conduction and reducing the device's on-resistance.

[0074] Therefore, the SiC trench gate MOSFET structure in this application utilizes the P+ electric field shielding layer 3 at the bottom of the trench and the trench mesa 4 to effectively shield the trench gate oxide electric field, solving the problem of excessive electric field stress within the trench gate oxide layer 6 and improving gate oxide reliability. Furthermore, the source is connected to the trench bottom P+ electric field shielding layer 3 via the trench mesa 4 P+ electric field shielding layer 3, solving the problem of the trench gate bottom P+ electric field shielding layer 3 not being effectively grounded. Since the P+ electric field shielding layer 3 is located at the bottom of the trench and within the trench mesa 4, and the two parts are interconnected, it can effectively protect the trench gate oxide layer 6, reduce the gate oxide electric field, and improve device reliability. The P+ electric field shielding layer 3 can be directly grounded through the trench mesa 4, eliminating the need for additional structures and providing more space for further reduction of the chip cell area.

[0075] The manufacturing method of this invention utilizes tilted ion implantation to form the P+ electric field shielding layer 3 at the bottom of the trench and on the trench mesa 4, eliminating the need for high-energy ion implantation, thus reducing the requirements for process technology and equipment and simplifying the process implementation. In this application, the P+ electric field shielding layer 3 at the bottom of the trench and the P+ electric field shielding layer 3 on the trench mesa 4 are formed simultaneously, requiring only one ion implantation step. Furthermore, it is interconnected with the P-well region 8, eliminating the need for further ion implantation to form the P+ source region, thereby reducing process complexity. Moreover, the P+ electric field shielding layer 3 is formed using tilted ion implantation after trench etching, which requires low ion implantation energy and allows for self-aligned doping using the trench etching mask, further simplifying the process. The sacrificial oxidation after ion implantation removes the ion implantation scattering layer on the sidewall of the channel, thereby eliminating the channel pinch-off phenomenon during forward conduction and reducing the device's on-resistance.

[0076] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a particular feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment.

[0077] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0078] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0079] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon carbide trench gate MOSFET device, characterized by, include: An N-type substrate and an N-epitaxial layer located on the substrate; The epitaxial layer serves as the drift region of the MOSFET; Multiple P-well regions exist above the epitaxial layer; Above each of the P-well regions, there is a corresponding N+ source region; The multiple P-well regions are separated by silicon carbide trenches; Multiple trench platforms are spaced apart along the trench direction in the silicon carbide trench; The bottom of the silicon carbide trench and the interior of the trench platform are both provided with P+ electric field shielding layers. The inner surface of the silicon carbide trench has a gate oxide layer; The silicon carbide trench contains a polycrystalline silicon gate.

2. The silicon carbide trench gate MOSFET device of claim 1, wherein, The device also includes: The upper surface of the epitaxial layer contains a source metal, which is in ohmic contact with the N+ source region and the P+ electric field shielding layer. The upper surface of the polysilicon gate has a gate metal, and the gate metal is isolated from the source metal by an interlayer dielectric. A gate-source electrode is present above the interlayer dielectric, and the gate-source electrode is connected to the source metal through a contact hole; The lower surface of the substrate contains drain metal.

3. The silicon carbide trench gate MOSFET device of Claim 1, wherein, The P+ electric field shielding layer is connected to the P-well region.

4. The silicon carbide trench gate MOSFET device of Claim 2, wherein, The outer surface of the gate metal is wrapped by the interlayer dielectric.

5. A method for fabricating a silicon carbide trench gate MOSFET device, characterized in that, include: P-well region and N+ source region are formed on the upper surface of silicon carbide wafer by high-temperature aluminum ion implantation and high-temperature nitrogen ion implantation, respectively. A silicon carbide trench is formed on the upper surface of the wafer using dry etching, and the depth of the silicon carbide trench is greater than the depth of the P-well region; Aluminum ions are tilted and injected into the silicon carbide trench to form a P+ electric field shielding layer in the silicon carbide trench; After the P+ electric field shielding layer is formed, the wafer is subjected to sacrificial oxidation. Remove the oxide layer formed by sacrificial oxidation and perform high-temperature activation annealing on the wafer; A gate oxide layer is grown on the surface of the silicon carbide trench to form a trench gate oxide layer. Polysilicon is deposited on the surface of the trench gate oxide layer and etched back to form a trench polysilicon gate.

6. The method for fabricating a silicon carbide trench gate MOSFET device according to claim 5, characterized in that, The method further includes: Source metal is generated on the upper surface of the wafer, and the source metal is patterned. The wafer is subjected to rapid thermal annealing, which enables the source metal to form an ohmic contact with the N+ source region and the P+ electric field shielding layer. A first interlayer dielectric is deposited on the upper surface of the wafer, and a gate contact hole is etched on the first interlayer dielectric above the polysilicon gate; Gate metal is grown in the gate contact hole; A second interlayer dielectric is deposited on the upper surface of the wafer, and source contact holes are etched on the second interlayer dielectric. The gate-source electrode is grown through the source contact hole, while the drain metal is grown on the lower surface of the wafer.

7. The method of manufacturing a silicon carbide trench gate MOSFET device of claim 5, wherein, "Injecting aluminum ions into the silicon carbide trench at an angle" includes: Aluminum ions are injected twice at an angle toward the extension direction of the silicon carbide trench, each time toward a different end of the silicon carbide trench.

8. The method of fabricating a silicon carbide trench gate MOSFET device of claim 5, wherein, The wafer is subjected to sacrificial oxidation using either dry oxidation or wet oxidation methods.

9. The method of producing a silicon carbide trench gate MOSFET device according to claim 5, wherein The trench gate oxide layer is formed by high-temperature thermal oxidation, CVD process, or a combination of both.

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