Single-power-interface level converter and chip

Abstract

This invention discloses a single-power-interface level converter and chip. The single-power-interface level converter includes: a first conversion circuit, a second conversion circuit, and a buffer, all operating on the same power supply and connected sequentially. The first conversion circuit receives an input signal, inverts and levels the input signal to obtain a first converted signal. The second conversion circuit receives the input signal and the first converted signal, levels the input signal and the first converted signal to obtain a second converted signal. The buffer outputs the second converted signal. The input signal has an amplitude of 0 to VIN, and the second converted signal serves as the output signal with an amplitude of 0 to VDD, where VDD is the voltage value of the power supply. This invention can convert an external logic signal within a certain level range into a signal suitable for the internal power domain of the chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a single-power-interface level converter and chip. Background Technology

[0002] In integrated circuits (ICs), multi-power-domain design has long been a good solution for optimizing chip performance and reducing power consumption. Level-shifting circuits in multi-power-domain systems ensure the interchangeability of low-power-domain and high-power-domain signals, meeting the normal operating requirements of the chip. For example, some analog circuits or digital modules in a chip operate in a lower power domain to save power, while some critical timing circuits or interface circuits, which require fast response times, operate in a higher power domain. The design of interface circuits is crucial to meeting the chip's clock requirements or the information exchange needs with external controllers. If the clock or data signal level provided by the external controller is inconsistent with the chip's internal level, the interface circuit must provide sufficient drive while fulfilling the level-shifting function.

[0003] In existing technologies, most interface circuit level conversion methods employ a common level conversion mechanism combined with two different power domains. Besides the internal power supply of the chip, the power supply for the chip's interface level is generally provided by a pin connection or an internal voltage generation circuit. The former requires adding a pin to the chip, undoubtedly increasing the chip's packaging and manufacturing costs, and also requires multiple voltages from external devices, further increasing the cost of external circuitry. The latter requires the chip to generate a suitable interface power supply through analog circuitry, such as a low dropout regulator (LDO) circuit, and also relies on a bandgap reference circuit. This increases the complexity of the chip's circuit design and its power consumption. Furthermore, if the chip operates over a wide voltage range, and the interface level falls within the chip's operating voltage range, the difficulty of generating the interface power supply within the chip increases significantly. Summary of the Invention

[0004] This invention provides a single-power-interface level converter and chip that can convert an external logic signal of a certain level range into a signal suitable for the internal power domain of the chip.

[0005] Therefore, the embodiments of the present invention provide the following technical solutions:

[0006] On one hand, embodiments of the present invention provide a single-power-interface level converter, comprising: a first conversion circuit, a second conversion circuit, and a buffer, all operating on the same power supply and connected in sequence; the first conversion circuit receives an input signal, inverts and levels the input signal to obtain a first converted signal; the second conversion circuit receives the input signal and the first converted signal, levels the input signal and the first converted signal to obtain a second converted signal; the buffer outputs the second converted signal, wherein the amplitude of the input signal is 0 to VIN, the second converted signal is used as the output signal, and the amplitude of the output signal is 0 to VDD, where VDD is the voltage value of the power supply.

[0007] Optionally, the first conversion circuit includes a pull-up unit and a pull-down unit; the pull-up unit is used to pull up the level of the first converted signal to VDD when the level of the input signal is 0; the pull-down unit is used to pull down the level of the first converted signal to 0 when the level of the input signal is VIN.

[0008] Optionally, the pull-up unit includes: an intermediate voltage generating circuit, a first PMOS transistor, and a capacitor. One end of the capacitor is connected to the output terminal of the intermediate voltage generating circuit and the source of the first PMOS transistor, respectively, and the other end of the capacitor is grounded. The pull-down unit includes: a first NMOS transistor, the source of which is grounded; the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor and receives the input signal; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and outputs the first conversion signal; the intermediate voltage generating circuit is used to transfer the voltage of the power supply to the source of the first PMOS transistor when the level of the input signal is 0; the capacitor keeps the source voltage of the first PMOS transistor in a stable state.

[0009] Optionally, the intermediate voltage generation circuit includes one or more current-limiting PMOS transistors, which are connected in series and the gate of each current-limiting PMOS transistor is grounded.

[0010] Optionally, a resistor is also connected between the gate and ground of the current-limiting PMOS transistor.

[0011] Optionally, the second conversion circuit includes: a first input unit and a second input unit; the first input unit includes: a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor is connected to the power supply, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor receives the input signal, and the source of the second NMOS transistor is grounded; the second input unit includes: a third PMOS transistor and a third NMOS transistor, the source of the third PMOS transistor is connected to the power supply, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor receives the first conversion signal, and the source of the third NMOS transistor is grounded; the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third PMOS transistor is connected to the drain of the second PMOS transistor.

[0012] Optionally, the buffer includes a first inverter and a second inverter connected in series.

[0013] Optionally, the first inverter includes: a fourth PMOS transistor and a fourth NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and serves as the input terminal of the buffer; the source of the fourth PMOS transistor is connected to the power supply, and the source of the fourth NMOS transistor is grounded; the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and serves as the output terminal of the first inverter.

[0014] Optionally, the second inverter includes a fifth PMOS transistor and a fifth NMOS transistor; the gate of the fifth PMOS transistor is connected to the gate of the fifth NMOS transistor and serves as the input terminal of the second inverter; the source of the fifth PMOS transistor is connected to the power supply, and the source of the fifth NMOS transistor is grounded; the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor and serves as the output terminal of the buffer.

[0015] On the other hand, embodiments of the present invention also provide a chip, including the single-power-interface level converter described above.

[0016] The single-supply interface level converter provided in this embodiment of the invention requires only one power supply, VDD. A first conversion circuit inverts and levels the input signal to obtain a first converted signal. The input signal and the first converted signal are then input to a second conversion circuit, which performs level conversion on both. The resulting second converted signal is then buffered and output as an output signal with an amplitude of VDD. This converts an external logic signal (i.e., the input signal) within a certain level range into a signal suitable for the chip's internal power domain (i.e., the output signal). The single-supply interface level converter provided in this embodiment of the invention can meet application requirements where the high level of the input or output can be selected within a certain range. The overall circuit can achieve rapid logic level conversion under a single input power amplitude, allowing the output signal with the internal power amplitude to effectively flip in sync with the input signal. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a circuit that uses two different power domains to achieve level conversion in the prior art.

[0018] Figure 2 This is a schematic diagram of the structure of a single-power-interface level converter according to an embodiment of the present invention.

[0019] Figure 3 This is a specific circuit diagram of the first conversion circuit in an embodiment of the present invention.

[0020] Figure 4 This is a specific circuit diagram of the second conversion circuit in an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of a specific circuit of a buffer in an embodiment of the present invention.

[0022] Figure 6 This is a specific circuit diagram of a single-power-interface level converter according to an embodiment of the present invention.

[0023] Figure 7 This is a waveform diagram of each signal in the single-power-interface level converter of this invention. Detailed Implementation

[0024] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] The following is a brief description of the circuits in the prior art that utilize two different power domains to achieve level conversion.

[0026] like Figure 1As shown, the two power domains are VDD and VDDIN. The input signal in and the inverter operate in the VDD power domain, and the four MOS transistors M1 to M4 operate in the VDDIN power domain. Among them, M1 and M2 are NMOS transistors, and M3 and M4 are PMOS transistors.

[0027] When the input signal in changes from "0" to VDD, M1 turns on and pulls its drain terminal down to "0"; correspondingly, M4 turns on and precharges the out terminal to VDDIN; when the input signal in changes from VDD to "0", M1 turns off and M2 turns on and pulls the out terminal low.

[0028] The above process completes the transition from an input signal in swinging between 0 and VDD to an output signal out swinging between 0 and VDDDIN. The input signal in can switch back and forth between 0 and VDD, but if the system cannot provide VDD power, the circuit cannot complete the level conversion.

[0029] Therefore, embodiments of the present invention provide a single-power-interface level converter, such as... Figure 2 The diagram shown is a schematic of the single-power-interface level converter.

[0030] In this embodiment, the single-power-interface level converter includes a first conversion circuit 21, a second conversion circuit 22, and a buffer 23 connected in sequence, and the first conversion circuit 21, the second conversion circuit 22, and the buffer 23 operate on the same power supply, that is, these three are connected to the same power supply.

[0031] like Figure 2 As shown, the first conversion circuit 21 receives the input signal IN, inverts and levels the input signal IN to obtain the first conversion signal INB. The amplitude of the first conversion signal INB can be less than, greater than or equal to the amplitude of the power supply. The second conversion circuit 22 receives the input signal IN and the first conversion signal INB respectively, and levels the input signal IN and the first conversion signal INB to obtain the second conversion signal.

[0032] In this embodiment, the second conversion signal is output through buffer 23. For ease of description, the signal output by the buffer is referred to as the output signal OUT.

[0033] In practical applications, the input signal IN can be a square wave signal or other waveform signals, such as a sine wave signal. This embodiment of the invention does not limit this. Its amplitude is denoted as 0 to VIN, and the amplitude of the output signal is 0 to VDD, where VDD is the voltage value of the aforementioned power supply. Furthermore, the output signal OUT can effectively flip along with the input signal IN. It should be noted that VIN can be less than, greater than, or equal to VDD; this embodiment of the invention does not limit this.

[0034] In one non-limiting embodiment, the first conversion circuit 21 may include a pull-up unit and a pull-down unit, wherein the pull-up unit is used to pull up the level of the first conversion signal INB to VDD when the level of the input signal IN is 0; and the pull-down unit is used to pull down the level of the first conversion signal INB to 0 when the level of the input signal IN is VIN.

[0035] like Figure 3 The diagram shown is a specific circuit diagram of the first conversion circuit in an embodiment of the present invention.

[0036] In this embodiment, the pull-up unit in the first conversion circuit 21 includes: an intermediate voltage generation circuit 210, a first PMOS transistor MP1, and a capacitor C. One end of the capacitor C is connected to the output terminal of the intermediate voltage generation circuit 210 and the source terminal of the first PMOS transistor MP1, respectively. Figure 3 The ND terminal of the capacitor is connected to the ground, and the other end of the capacitor C is grounded. The pull-down unit in the first conversion circuit 21 includes: a first NMOS transistor MN1, the source of which is grounded; the gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1 and receives the input signal IN; the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and outputs the first conversion signal INB.

[0037] The intermediate voltage generation circuit 210 is used to transfer the voltage of the power supply to the source of the first PMOS transistor MP1, i.e., the ND terminal, when the input signal IN is 0; the capacitor C keeps the source voltage of the first PMOS transistor MP1 in a stable state.

[0038] Furthermore, in specific applications, the intermediate voltage generation circuit 210 may include one or more current-limiting PMOS transistors. When there are multiple current-limiting PMOS transistors, the multiple current-limiting PMOS transistors are connected in series sequentially, and the gate of the current-limiting PMOS transistor is grounded. Figure 3 As shown, in this embodiment, four PMOS transistors are connected in series, namely MP11, MP12, MP13, and MP14. It should be noted that the number of PMOS transistors can be determined as needed, and this embodiment of the invention does not limit this.

[0039] Furthermore, a resistor R can be connected between the gate and ground of the current-limiting PMOS transistor to limit the current and prevent ground potential fluctuations from damaging the MOS transistor.

[0040] like Figure 4 The diagram shown is a specific circuit diagram of the second conversion circuit in an embodiment of the present invention.

[0041] In this embodiment, the second conversion circuit 22 includes a first input unit and a second input unit. The first input unit includes a second PMOS transistor MP2 and a second NMOS transistor MN2. The source of the second PMOS transistor MP2 is connected to the power supply VDD, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 receives the input signal IN, and the source of the second NMOS transistor MN2 is grounded. The second input unit includes a third PMOS transistor MP3 and a third NMOS transistor MN3. The source of the third PMOS transistor MP3 is connected to the power supply VDD, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, the gate of the third NMOS transistor MN3 receives the first conversion signal INB, and the source of the third NMOS transistor MN3 is grounded.

[0042] In addition, the gate of the second PMOS transistor MP2 is connected to the drain of the third PMOS transistor MP3, that is... Figure 4 At terminal X, the gate of the third PMOS transistor MP3 is connected to the drain of the second PMOS transistor MP2, i.e. Figure 4 The Y terminal is used as the output terminal of the second conversion circuit 22, and the second conversion signal is output to the buffer.

[0043] like Figure 5 The diagram shown is a specific circuit diagram of a buffer in an embodiment of the present invention.

[0044] In this embodiment, the buffer includes a first inverter and a second inverter connected in series. The first inverter includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4; the gate of the fourth PMOS transistor MP4 is connected to the gate of the fourth NMOS transistor MN4 and serves as the input terminal of the buffer. Figure 5 The first inverter comprises a fifth PMOS transistor MP5 and a fifth NMOS transistor MN5. The gate of the fifth PMOS transistor MP5 is connected to the gate of the fifth NMOS transistor MN5 and serves as the input of the second inverter. The source of the fifth PMOS transistor MP5 is connected to the power supply VDD, and the source of the fifth NMOS transistor MN5 is grounded. The drain of the fifth PMOS transistor MP5 is connected to the drain of the fifth NMOS transistor MN5 and serves as the output of the buffer. Figure 5 The Z-end in the middle.

[0045] Reference Figure 6 The diagram illustrates a specific circuit schematic of a single-power-interface level converter according to an embodiment of the present invention. The following is in conjunction with... Figure 6A detailed description of the working process of the single - power - supply interface level converter according to the embodiments of the present invention is given.

[0046] First, it should be noted that in this single - power - supply interface level converter, all PMOS transistors are of the same type, and all NMOS transistors are of the same type. In the present invention, VDD is the power supply voltage, corresponding to the logical high level of the output signal; GND is the ground, defaulting to 0V, corresponding to the logical low level of the input and output signals. VIN is the high level of the input logic signal IN.

[0047] In the single - power - supply interface level converter according to the embodiments of the present invention, the level amplitude of the input signal is 0 to VIN, and the level amplitude of the output signal is 0 to VDD. Among them, VIN < VDD. The converter has only VDD as the power supply and can achieve the level conversion from input to output.

[0048] When the input terminal IN signal is at a low level, the first PMOS transistor MP1 is turned on, and the first NMOS transistor MN1 is turned off. The power supply VDD is transmitted to the INB terminal through MP11 - MP14. When the high level VIN of the input terminal IN signal is slightly greater than the threshold value of the first NMOS transistor MN1, by designing the width - to - length ratio of the first NPMOS transistor MN1, it can be ensured that the VIN voltage can pull the INB terminal to 0V, that is, the first NMOS transistor MN1 has a strong enough pulling - down ability to ensure that the subsequent level - conversion circuit can distinguish the high and low levels of the INB terminal. The same principle applies to the second NMOS transistor MN2 and the third NMOS transistor MN3, and it is necessary to ensure that the X terminal and the Y terminal can be pulled down to 0V. The width - to - length ratios of MP11 - MP14 can be designed to be relatively small and all operate in the linear region. As current - limiting transistors, they can effectively reduce the power consumption of the circuit. Among them, there is a certain voltage drop between the source and drain terminals of each PMOS transistor, so that the level of the ND point is at a certain potential between 0 and VDD, and the presence of the capacitor C makes the voltage of the ND point maintain a relatively stable state. Even if the first PMOS transistor MP1 has an obvious body effect (that is, the larger the source voltage, the larger the threshold voltage), resulting in an increase in its threshold voltage, when the input signal IN is 0, the first PMOS transistor MP1 is turned on, and the voltage of the ND point is transmitted to the INB terminal, serving as a high - level to control the conduction of the third NMOS transistor MN3, pulling the output terminal down to 0V.

[0049] When the input signal is at the high level VIN, the first NMOS transistor MN1 is turned on, and the pulling - down ability of the first NMOS transistor MN1 pulls the INB terminal down to 0V. At this time, the second NMOS transistor MN2 is turned on, and the third NMOS transistor MN3 is turned off. Correspondingly, the second PMOS transistor MP2 is turned off, and the third PMOS transistor MP3 is turned on, transmitting the voltage VDD to the output terminal OUT through the buffer 23. In this way, the level conversion under the condition of only one power supply is completed.

[0050] It should be noted that, depending on the application requirements, the frequency of the input logic signal IN can be selected within a certain range. The dimensions of MP11 to MP14 impose certain constraints on the frequency of the input logic signal IN. Reducing the aspect ratio can control power consumption, while increasing the aspect ratio can improve response speed. In specific applications, the dimensions of each MOS transistor in the single-supply interface level converter of this embodiment can be adjusted according to actual needs to ensure that the first NMOS transistor MN1 and the second NMOS transistor MN2 can conduct and be strongly pulled down when the input signal is high-level VIN. In addition, the power supply voltage range does not exceed the withstand voltage value of the selected MOS transistor.

[0051] Taking a square wave signal with an input signal IN of 500kHz, an input high level VIN of 1V, and VDD of 5V as an example, the single-supply interface level converter of this invention can be used to obtain... Figure 7 The waveform diagram shown.

[0052] Reference Figure 7 When the input terminal IN is 0V, the first PMOS transistor MP1 is turned on and the first NMOS transistor MN1 is turned off. The capacitor C slowly raises the voltage at the ND terminal. At this time, the average voltage at the ND terminal is about 3V and is transmitted to the INB terminal. When the input terminal level is 1V, the first NMOS transistor MN1 is turned on, and the pull-down capability of the first NMOS transistor MN1 is stronger than the pull-up capability of the first PMOS transistor MP1. The INB terminal is pulled down to 0V.

[0053] Therefore, when the input voltage IN is 0–1V, the voltage range of INB is approximately 0–3V. Correspondingly, when the input voltage IN is 0V, the INB voltage is 3V, the second NMOS transistor MN2 is off, the third NMOS transistor MN3 is on, the Y terminal is pulled down to GND, and the 0V voltage is output as 0V through buffer 23. When the input voltage IN is 1V, the INB voltage is 0V. At this time, the second NMOS transistor MN2 is on and has a strong pull-down capability, the third NMOS transistor MN3 is off, the X terminal is pulled down, causing the third PMOS transistor MP3 to turn on, and the power supply voltage is transmitted to the Y terminal and output as VDD through the buffer. This completes the voltage conversion from 1V to 5V.

[0054] The single-supply interface level converter provided in this invention can convert an input signal of one amplitude to an output signal of another amplitude, requiring only one power supply VDD. This converter allows for selection of input or output level magnitudes within a certain range. The overall circuit enables rapid logic level switching under the input power supply amplitude, allowing the output signal with the internal power supply amplitude to effectively flip along with the input signal. This effectively solves the application scenario where the input signal level differs from the internal power supply and there is no power supply of equal magnitude to the input signal level in the interface circuit, thus improving the input / output voltage range and effectively controlling power consumption.

[0055] The single-power-supply interface level converter provided in this invention enables level conversion even when there is only one internal power supply and the input signal cannot provide power. This solves the problems in the prior art, such as the need for an intermediate level generation circuit to generate interface power, which leads to design costs. Moreover, it can support a certain input level range and a large power supply voltage range, and meets the application requirements for fast level conversion of interface input signals at different frequencies.

[0056] Accordingly, embodiments of the present invention also provide a chip including the above-described single-power-interface level converter, which can convert an external logic signal with a level range into a signal with a level range suitable for the chip's internal power domain.

[0057] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A single-power-source interface level converter, characterized in that, include: A first conversion circuit, a second conversion circuit, and a buffer, all operating on the same power supply and connected in sequence; The first conversion circuit is used to receive the input signal, invert and level-convert the input signal to obtain the first converted signal; The second conversion circuit is used to receive the input signal and the first conversion signal, and to perform level conversion on the input signal and the first conversion signal to obtain the second conversion signal; The buffer is used to output the second conversion signal. The amplitude of the input signal is 0~VIN. The second conversion signal is used as the output signal. The amplitude of the output signal is 0~VDD, where VDD is the voltage value of the power supply. The first conversion circuit includes a pull-up unit and a pull-down unit; The pull-up unit is used to pull up the level of the first conversion signal to VDD when the level of the input signal is 0; The pull-down unit is used to pull down the level of the first conversion signal to 0 when the level of the input signal is VIN; The pull-up unit includes: an intermediate voltage generating circuit, a first PMOS transistor, and a capacitor. One end of the capacitor is connected to the output terminal of the intermediate voltage generating circuit and the source of the first PMOS transistor, and the other end of the capacitor is grounded. The pull-down unit includes: a first NMOS transistor, the source of which is grounded; the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor and receives the input signal; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and outputs the first conversion signal. The intermediate voltage generating circuit is used to transfer the voltage of the power supply to the source of the first PMOS transistor when the level of the input signal is 0; the capacitor keeps the source voltage of the first PMOS transistor in a stable state; the intermediate voltage generating circuit includes one or more current-limiting PMOS transistors, which are connected in series in sequence, and the gate of the current-limiting PMOS transistor is grounded.

2. The single-power-interface level converter according to claim 1, characterized in that, A resistor is also connected between the gate of the current-limiting PMOS transistor and ground.

3. The single-power-interface level converter according to claim 1 or 2, characterized in that, The second conversion circuit includes: a first input unit and a second input unit; The first input unit includes: a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor is connected to the power supply, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor receives the input signal, and the source of the second NMOS transistor is grounded. The second input unit includes a third PMOS transistor and a third NMOS transistor. The source of the third PMOS transistor is connected to the power supply, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor receives the first conversion signal, and the source of the third NMOS transistor is grounded. The gate of the second PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third PMOS transistor is connected to the drain of the second PMOS transistor.

4. The single-power-interface level converter according to claim 3, characterized in that, The buffer includes a first inverter and a second inverter connected in series.

5. The single-power-interface level converter according to claim 4, characterized in that, The first inverter includes a fourth PMOS transistor and a fourth NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and serves as the input terminal of the buffer; the source of the fourth PMOS transistor is connected to the power supply, and the source of the fourth NMOS transistor is grounded; the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and serves as the output terminal of the first inverter.

6. The single-power-interface level converter according to claim 4, characterized in that, The second inverter includes a fifth PMOS transistor and a fifth NMOS transistor; the gate of the fifth PMOS transistor is connected to the gate of the fifth NMOS transistor and serves as the input terminal of the second inverter; the source of the fifth PMOS transistor is connected to the power supply, and the source of the fifth NMOS transistor is grounded; the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor and serves as the output terminal of the buffer.

7. A chip, characterized in that, Includes a single-power-interface level converter as described in any one of claims 1 to 6.

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