A real-time high-precision monitoring method for instrument landing systems

Abstract

This invention discloses a real-time high-precision monitoring method for an instrument landing system (ILS), comprising: a monitor receiving the transmitted signal and spatially synthesized signal of the ILS in real time and sampling them at high speed; performing multidimensional parallel processing on the sampled signal without changing the sampling rate to obtain a reduced-speed multidimensional parallel synchronous high-speed sampled signal; a fully low-speed multidimensional parallel NCO module outputting orthogonal local oscillator signals of different frequencies by adjusting the phase increment in real time; performing multidimensional parallel orthogonal down-conversion processing on the multidimensional parallel high-speed sampled signal and the multidimensional parallel high-speed orthogonal local oscillator signal to generate a multidimensional parallel low-speed orthogonal signal of the high-speed sampled signal; and performing fully reduced-speed multidimensional parallel FIR filtering processing on the multidimensional parallel low-speed orthogonal signal to output the fully low-speed processing result of the high-speed sampled signal. This invention reduces the number of processing stages and the processing delay links, ensuring high sampling rate, high precision, and high real-time performance of the monitor's signal processing.

Description

Technical Field

[0001] This invention relates to the field of monitoring technology, and in particular to a real-time high-precision monitoring method for an instrument landing system. Background Technology

[0002] The Instrument Landing System (ILS) is the most widely used precision approach and landing guidance system for aircraft internationally. It uses radio signals transmitted from the ground to create a localizer and glide path in the air, establishing a virtual path from the runway threshold into the air. This provides all-weather, 24 / 7 approach and landing guidance for the aircraft, guiding it to approach the runway in the correct direction and ultimately achieve a safe landing.

[0003] Instability in the amplitude, modulation, phase, frequency, and frequency difference of the transmitted signals from the Instrument Landing System (ILS) can lead to deviations, deformations, fluctuations, and errors in the flight path and its structure, preventing aircraft from landing safely on the correct heading and severely impacting flight safety. Therefore, two monitors are configured in Category I / II ILS and three in Category III ILS for real-time signal calibration. Poor real-time performance, untimely calibration, and insufficient accuracy of the monitors mean that any false alarms, system shutdowns, or other disruptions can cause deviations, deformations, fluctuations, and errors in the flight path and its structure. Therefore, improving the processing accuracy and real-time performance of ILS monitors has become a key focus and challenge in ILS monitoring technology. Traditional signal processing methods, such as frequency domain transformation and multi-stage processing, reduce real-time performance. Furthermore, low sampling rates, undersampling, and reduced sampling rate all contribute to signal-to-noise ratio (SNR) loss, thereby reducing processing accuracy.

[0004] Traditional instrument landing system monitors often use undersampling or low sampling rate to sample signals at low speed, and then perform decimation and speed-down processing on the signals, which both result in a certain loss of signal-to-noise ratio, thereby reducing processing accuracy. Traditional instrument landing system monitors use a method of quadrature mixing (including NCO module) + CIC filtering + HB half-band filtering + decimation + FIR filtering to process high-speed sampled signals. This method not only complicates signal processing but also increases the number of processing stages, which seriously affects the real-time performance of signal processing. Traditional instrument landing systems often use frequency domain processing to extract the amplitude of carrier / sideband signals. However, the processing accuracy of frequency domain transformation is affected by the number of calculation points, and the processing delay is also affected by the number of points. This not only degrades the real-time performance but also fails to guarantee both high accuracy and real-time performance. Summary of the Invention

[0005] In view of this, the present invention provides a real-time high-precision monitoring method for instrument landing systems. By sampling the signal at high speed and realizing the processing of high-speed sampled signals under low-speed clock conditions, the number of processing stages is reduced and the processing flow is simplified, thereby ensuring high precision and real-time performance of signal processing.

[0006] This invention discloses a real-time high-precision monitoring method for an instrument landing system, which includes the following steps: Step 1: The monitor receives the transmitted signals and space-synthesized signals from the Instrument Landing System in real time and performs high-speed signal sampling on the received transmitted and space-synthesized signals; without changing the signal sampling rate. In the case of M-dimensional parallelization, the sampled signal is processed to obtain a reduced-speed M-dimensional parallel synchronous high-speed sampled signal; where M is a positive integer. Step 2: Using direct digital frequency synthesis technology as a model, perform algorithm calculations and transformations, and design a fully low-speed multidimensional parallel NCO module. The fully low-speed multidimensional parallel NCO module outputs orthogonal local oscillator signals of different frequencies by adjusting the phase increment in real time, and the output orthogonal local oscillator signals are fully synchronized M-dimensional high sampling rate low-speed local oscillator signals. Step 3: Perform multidimensional parallel orthogonal downconversion processing on the M-dimensional parallel high-speed sampling signal generated in Step 1 and the M-dimensional parallel high-speed orthogonal local oscillator signal generated in Step 2 to generate an M-dimensional parallel low-speed orthogonal signal of the high-speed sampling signal. Step 4: Based on the designed M-dimensional parallel FIR filtering architecture and algorithm model, perform full-speed reduction multi-dimensional parallel FIR filtering on the M-dimensional parallel low-speed orthogonal signal output in Step 3, and output the full-speed low-speed processing result of the high-speed sampled signal.

[0007] Further, step 1 includes: Step 11: Sampling Rate Based on the data rate reduction ratio M, the sampled signal After passing through an M-mode switching switch, the output M-dimensional data rate is... The signal will have a sampling rate of The sampled signal is converted into an M-dimensional parallel low-speed high-sampling-rate signal. ; Step 12: Take the M-dimensional parallel low-speed high-sampling-rate signal generated in Step 11, and adjust it according to the first dimension data delay of (M-1) units. The second dimension data is delayed by (M-2) units. ..., the data in the (M-1)th dimension is delayed by 1. Then, it is aligned and synchronized with the Mth dimension data to obtain the synchronized and aligned M-dimensional parallel low-speed high-sampling-rate signal; Step 13: Change the processing clock from the original After M-frequency division, the frequency is reduced to ,and Synchronize with the Mth dimension data to obtain the same data. Synchronous M-dimensional parallel low-speed high-sampling-rate signals Thus far, M-dimensional data Composition The signal maintains the original data sampling rate And with the number of samples remaining unchanged, the original data rate Reduced to .

[0008] Further, step 2 includes: Step 21: Calculate the phase increment using the direct digital frequency synthesis technique formula: The direct digital frequency synthesis technology processing flow, based on the traditional lookup table method, is determined by the output local oscillator frequency. Sampling rate and the number of bits of the phase accumulator Determine a unique phase increment As input to the DDS; Step 22: According to θ, Integrator Output The relationship between orthogonal local oscillator signals is calculated and derived. Step 23: Based on the derivation results in Step 22, transform the traditional NCO module to... For phase increment, with The operating clock performs phase integration to obtain the reference sequence. ; Step 24: Based on the relationship between the outputs of the M-dimensional parallel decomposition in the derivation results of Step 22, convert the benchmark sequence... respectively with i Adding θ together yields the 2nd to Mth dimensions of the θ(n) sequence. ;in ; Step 25: To make Synchronous alignment of the M-dimensional sequences of the sequence, using the reference sequence Perform a processing clock After the delay, we obtain θ0(Mk+0), which serves as the first dimension of the M-dimensional θ(n) sequence. Thus, we obtain... M-dimensional sequence after sequence synchronization ,by Each of the M input addresses for a lookup table is used as an input address, and the output rate from the ROM is... M-dimensional parallel low-speed orthogonal local oscillator signals and .

[0009] Further, step 22 includes: The integrator output sequence is as follows: The corresponding NCO output sequence is: and ,in, ; Output sequence , , All are operating at sampling rate Below, to , , Time index in the series To perform Euclid division, that is: let Deformation yields and corresponding , The M-dimensional output of the sequence is: Sequence: 0th dimension: ,…,No. dimension: ; Sequence: 0th dimension: ,…,No. dimension: ; Sequence: 0th dimension: ,…,No. dimension: ; according to The M-dimensional output formula of the sequence is obtained by decomposition. An M-dimensional sequence is represented as , , ; right After performing M-dimensional parallel decomposition, the output of each dimension is in M-dimensional order. θ is the phase increment that is integrated and accumulated, and the operating frequency of the integrator also becomes Meanwhile, the outputs of the M-dimensional parallel decomposition have the following relationship: First dimension: ={with For phase increment, with The phase integral output of the operating clock; i-th dimension: =First dimension output+ .

[0010] Further, step 3 includes: Step 1 Each with step 2 and Multiplying the data of corresponding dimensions yields the M-dimensional parallel orthogonal down-converted I-channel signal. and Q-channel signal .

[0011] Furthermore, the M-dimensional parallel FIR filtering processing architecture is obtained by performing algorithm calculations and transformations based on the traditional single-rate FIR filtering processing model. The M-dimensional parallel FIR filtering architecture is transformed to obtain a fully de-speeded version. The processor can implement an M-dimensional parallel FIR filtering algorithm model.

[0012] Furthermore, the process of obtaining the M-dimensional parallel FIR filtering algorithm model is as follows: Step 51: The traditional N-tap FIR filtering algorithm is represented in the time domain as:

[0013] in,{ } is an infinitely long signal input sequence, { Let} be the coefficients of an FIR filter of length N, where N is an integer multiple of M. The expression of the above formula in the z-domain is:

[0014] The input sequence { After decomposition into M dimensions, the M-dimensional parallel data in the formula are respectively represented as follows: , … , Finally, X(z) can be expressed as: =

[0015] Step 52: Using the same method, convert the FIR filter coefficients of length N { After decomposition into M dimensions, the M-dimensional parallel data in the formula are respectively represented as follows: , , , , Finally, H(z) can be expressed as: =

[0016] Step 53: Based on the expression of the FIR filtering algorithm in the z-domain: The M-dimensional parallel X(z) expression from step 51 and the M-dimensional parallel H(z) expression from step 52 are calculated and represented in matrix form as follows:

[0017] Step 54: In step 53 That is, M. Latency, each dimension of data operates on the reduced speed Under the clock, so one That is, one The delay, denoted as a delay D, is used to transform and implement the M-dimensional parallel decomposition formula for FIR filtering derived in step 53, thus constructing a fully degraded... The processor can implement an M-dimensional parallel FIR filtering algorithm model.

[0018] Further, step 4 includes: Step 41: According to the orthogonal FIR filtering formula The processing requires dividing the orthogonal FIR filtering into four groups for processing. An M-dimensional parallel FIR filter with real parts of coefficients is designed. and the imaginary part of the filter coefficients ; Step 42: Using the M-dimensional parallel FIR filtering algorithm model designed in Step 4 as the algorithm structure for each group of filtering processes, perform calculations for the four groups of filters respectively: The input to the first group of filters is: M-dimensional parallel I-data. and the real part of the filter coefficients The filter output is obtained as follows: ; The input to the second group of filters is: M-dimensional parallel I-data. and the imaginary part of the filter coefficients The filter output is obtained as follows: ; The input to the third group of filters is: M-dimensional parallel Q-data. and the real part of the filter coefficients The filter output is obtained as follows: ; The input to the fourth group of filters is: M-dimensional parallel Q-data. and the imaginary part of the filter coefficients The filter output is obtained as follows: ; Step 43: Convert the output of the first group of filters and the output of the fourth group of filters Subtracting the data of corresponding dimensions yields the M-dimensional parallel I-channel signal output after high-speed data processing at low speed. The output of the second group of filters and the output of the third group of filters By summing the data of corresponding dimensions, we obtain the M-dimensional parallel Q-channel signal output after high-speed data processing at low speed. .

[0019] Because of the adoption of the above technical solution, the present invention has the following advantages: 1. This invention can achieve true full speed reduction processing without changing the signal sampling rate, thereby avoiding the signal-to-noise ratio loss caused by undersampling or low sampling rate sampling of the signal due to the inability to process high-speed data streams, as well as the signal decimation and speed reduction processing, thereby improving the processing accuracy of the monitor. 2. This invention simplifies the signal processing flow to only require quadrature mixing + FIR filtering to achieve high-speed sampling signal processing, with fewer stages, greatly improving the real-time performance of signal processing; 3. This invention employs a time-domain processing method for high-speed signals, which eliminates the limitations of the number of calculation points on the signal processing speed and real-time performance, thus ensuring both high precision and real-time performance in signal processing. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0021] Figure 1 This is a flowchart illustrating a real-time high-precision monitoring method for an instrument landing system according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating the parallel processing of the sampled signal according to an embodiment of the present invention; Figure 3 This is a direct digital frequency synthesis (DDS) model based on the traditional lookup table method in this embodiment of the invention; Figure 4 A model of an 8-dimensional parallel NCO module signal processing implementation scheme designed for embodiments of the present invention, featuring complete speed reduction, high reuse, and portability. Figure 5 This is a model of the implementation scheme for the 8-dimensional parallel orthogonal downconversion processing method in this invention. Figure 6 The 8-dimensional parallel decomposition formula for FIR filtering, designed for embodiments of the present invention, is transformed and then fully degraded to... The processor can implement an 8-dimensional parallel FIR filtering algorithm model; Figure 7 This is a flowchart illustrating the implementation of 8-dimensional parallel orthogonal FIR filtering operations in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0023] The technical solution proposed in the specific embodiments can at least solve the following technical problems: 1. Traditional instrument landing system (ILS) monitors often employ undersampling or low sampling rates for slow signal sampling, followed by decimation to reduce signal speed. Both methods result in a loss of signal-to-noise ratio (SNR) and reduced processing accuracy. This solution designs a complete method for fully slowing down high-speed data streams. It achieves true full-speed reduction processing without changing the signal sampling rate, thus avoiding the SNR loss caused by undersampling or low sampling rates due to the inability to handle high-speed data streams, and by decimation to reduce signal speed. This improves the monitor's processing accuracy. 2. Traditional instrument landing system (ILS) monitors use a combination of quadrature mixing (including an NCO module), CIC filtering, HB half-band filtering, decimation, and FIR filtering to process high-speed sampled signals. This approach not only complicates signal processing but also increases the number of processing stages, severely impacting real-time performance. This solution employs a completely low-speed processing method for high-speed data streams, simplifying the signal processing flow to just quadrature mixing and FIR filtering. This reduces the number of processing stages and significantly improves real-time performance. 3. Traditional instrument landing systems (ILS) often use frequency domain processing to extract the amplitude of carrier / sideband signals. However, the accuracy and latency of frequency domain transformation are affected by the number of computation points, leading to decreased real-time performance and an inability to simultaneously guarantee high accuracy and real-time performance. This solution employs time domain processing of high-speed signals, freeing signal processing accuracy and real-time performance from the limitations of the number of computation points, thus ensuring both high accuracy and real-time performance.

[0024] See Figure 1 This invention provides an embodiment of a real-time high-precision monitoring method for an instrument landing system, which includes the following steps: Step 101: Without changing the signal sampling rate In this case, the AD sampling signal s(n) is processed in M ​​dimensions to obtain a reduced-speed M-dimensional parallel synchronous high-speed sampling signal. M is a positive integer; Step 102: Using the traditional lookup table method of Direct Digital Frequency Synthesis (DDS) as a model, such as... Figure 3As shown, algorithm calculations and transformations are performed, and a fully low-speed multidimensional parallel NCO module is designed. This module can modify the phase increment in real time. It outputs quadrature local oscillator signals of different frequencies, and the output quadrature local oscillator signals are fully synchronized M-dimensional high sampling rate low-speed local oscillator signals; Step 103: Perform multidimensional parallel orthogonal downconversion processing on the M-dimensional parallel high-speed sampling signal generated in step 101 and the M-dimensional parallel high-speed orthogonal local oscillator signal generated in step 102 to generate an M-dimensional parallel low-speed orthogonal signal of the high-speed sampling signal. Step 104: Using traditional single-rate FIR filtering as a model, perform algorithm calculations and transformations to design an M-dimensional parallel FIR filtering architecture based on high sampling rate signals and full low-speed processing. Then, transform the processing architecture model to obtain the fully degraded... The processor can implement an M-dimensional parallel FIR filtering algorithm model; Step 105: Based on the processing architecture and algorithm model designed in Step 104, the M-dimensional parallel low-speed orthogonal signal output in Step 103 is subjected to multi-dimensional parallel FIR filtering with full speed reduction to obtain the full low-speed processing result output of the high-speed sampled signal. Due to the complete processing flow of Steps 101 to 105, high sampling rate processing of the signal is guaranteed, thereby avoiding the decrease in processing accuracy caused by undersampling or low sampling rate sampling of the signal due to the inability to process high-speed data streams, and the signal-to-noise ratio loss caused by decimation and speed reduction processing of the signal. At the same time, the simplification of the processing flow, the reduction of the number of stages, and the low latency of time-domain processing also effectively improve the high real-time performance of signal processing.

[0025] With M=8, Taking 480MHz as an example, the technical solution of the present invention will be specifically described as follows: See Figure 2 The detailed processing flowchart for step 101 includes: Step 1011: Input AD sampling signal s(n) (sampling rate is...) =480MHz), based on the data rate reduction ratio M=8, s(n) outputs an 8-dimensional data rate after passing through an 8-channel modulo-8 switching switch. The signal will have a sampling rate of The sampled signal is converted into an 8-dimensional parallel low-speed high-sampling-rate signal. Execute step 1012; Step 1012: Since the 8-dimensional parallel low-speed high-sampling-rate signal output after the 8-channel modulo-8 switching is an asynchronous signal, the M-dimensional parallel low-speed high-sampling-rate signal formed in step 1011 needs to be delayed by (M-1) data points according to the first dimension. The second dimension data is delayed by (M-2) units. ..., the data in the (M-1)th dimension is delayed by 1. Then, it is aligned and synchronized with the Mth dimension data to obtain the synchronized and aligned M-dimensional parallel low-speed high-sampling-rate signal, and step 1013 is executed. Step 1013: After the synchronization and alignment process in step 1012, the data rate of each dimension of the 8-dimensional data has been reduced from the original... Reduced to At this point, the processing clock will be changed from the original... After being divided by 8, the frequency was reduced to 8, and Synchronize with the 8th dimension data to obtain the same data. Eight synchronous, 8-dimensional parallel low-speed, high-sampling-rate signals s0(8k+0),…,s7(8k+7) are generated. Thus, the 8-dimensional data… The s(n) signal is composed while maintaining the original data sampling rate. With the number of samples remaining unchanged, the original data rate has been reduced. Reduced to .

[0026] See Figure 3 This invention provides a direct digital frequency synthesis (DDS) model based on a traditional lookup table method. It can be seen that although this method yields an 8-dimensional, low-speed orthogonal local oscillator signal, the NCO module itself and the switching switch still operate at a high sampling rate. At 480MHz, it is impossible to achieve a true full speed reduction in processing.

[0027] See Figure 4 Step 102 presents a schematic diagram of the signal processing implementation scheme for the M-dimensional parallel NCO module, which features complete speed reduction, high multiplexing, and portability. Based on this implementation scheme diagram, a synchronous output rate of [missing information] can be achieved. M-dimensional parallel low-speed orthogonal local oscillator signals and Furthermore, all signal processing is completed on a low-speed clock. This achieves true full speed reduction in processing, and this module can be modified in real time. By outputting quadrature local oscillator signals of different frequencies, the module achieves rapid reusability and portability.

[0028] See Figure 5 The implementation scheme of the 8-dimensional parallel orthogonal down-conversion processing method designed in step 103 provides an achievable method for realizing multi-dimensional parallel orthogonal down-conversion processing under full speed reduction.

[0029] See Figure 6 After transforming the M-dimensional parallel decomposition formula for FIR filtering in step 104, the fully degraded formula is constructed. The processor can implement an M-dimensional parallel FIR filtering algorithm model, which provides an algorithm model for a multi-dimensional parallel FIR filter for this scheme. Based on this implementation scheme, multi-dimensional parallel de-speeding processing of arbitrary FIR filtering can be completed. The implementation models of 4-dimensional parallel and 2-dimensional parallel FIR filtering algorithms can also be derived from this implementation scheme model. See Figure 7 Step 105: Design the flowchart for the M-dimensional parallel orthogonal FIR filtering operation, including: Step 1051: According to the orthogonal FIR filtering operation formula The orthogonal FIR filtering process needs to be divided into four groups for processing. The real part of the coefficients of the 8-dimensional parallel FIR filter is designed using the method in step 101. and the imaginary part of the filter coefficients Execute step 1052; Step 1052: Using the 8-dimensional parallel FIR filtering algorithm model designed in Step 104 as the algorithm structure for each group of filtering processes, perform 4 sets of filter calculations. The inputs to the 4 sets of filters are: 8-dimensional parallel I-channel data. and the real part of the filter coefficients 8-dimensional parallel I-channel data and the imaginary part of the filter coefficients 8-dimensional parallel Q-path data and the real part of the filter coefficients 8-dimensional parallel Q-path data and the imaginary part of the filter coefficients The outputs of the four filter banks are obtained: , , , Execute step 1053; Step 1053: Convert the outputs of the four filter groups... and Subtracting data of corresponding dimensions yields an 8-dimensional parallel I-channel signal output after high-speed data processing at low speed. Output and The corresponding dimensions of data are added together to obtain the 8-dimensional parallel Q-channel signal output after high-speed data processing at low speed. .

[0030] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A real-time high-precision monitoring method for an instrument landing system, characterized in that, Includes the following steps: Step 1: The monitor receives the transmitted signals and space-synthesized signals from the Instrument Landing System in real time and performs high-speed signal sampling on the received transmitted and space-synthesized signals; without changing the signal sampling rate. In the case of M-dimensional parallelization, the sampled signal is processed to obtain a reduced-speed M-dimensional parallel synchronous high-speed sampled signal; where M is a positive integer. Step 2: Using direct digital frequency synthesis technology as a model, perform algorithm calculations and transformations, and design a fully low-speed multidimensional parallel NCO module. The fully low-speed multidimensional parallel NCO module outputs orthogonal local oscillator signals of different frequencies by adjusting the phase increment in real time, and the output orthogonal local oscillator signals are fully synchronized M-dimensional high sampling rate low-speed local oscillator signals. Step 3: Perform multidimensional parallel orthogonal downconversion processing on the M-dimensional parallel high-speed sampling signal generated in Step 1 and the M-dimensional parallel high-speed orthogonal local oscillator signal generated in Step 2 to generate an M-dimensional parallel low-speed orthogonal signal of the high-speed sampling signal. Step 4: Based on the designed M-dimensional parallel FIR filtering architecture and algorithm model, perform full-speed reduction multi-dimensional parallel FIR filtering on the M-dimensional parallel low-speed orthogonal signal output in Step 3, and output the full-speed low-speed processing result of the high-speed sampling signal. Step 1 includes: Step 11: Sampling Rate Based on the data rate reduction ratio M, the sampled signal After passing through an M-mode switching switch, the output M-dimensional data rate is... The signal will have a sampling rate of The sampled signal is converted into an M-dimensional parallel low-speed high-sampling-rate signal. ; Step 12: Take the M-dimensional parallel low-speed high-sampling-rate signal generated in Step 11, and adjust it according to the first dimension data delay of (M-1) units. The second dimension data is delayed by (M-2) units. ..., the data in the (M-1)th dimension is delayed by 1. Then, it is aligned and synchronized with the Mth dimension data to obtain the synchronized and aligned M-dimensional parallel low-speed high-sampling-rate signal; Step 13: Change the processing clock from the original After M-frequency division, the frequency is reduced to ,and Synchronize with the Mth dimension data to obtain the same data. Synchronous M-dimensional parallel low-speed high-sampling-rate signals Thus far, M-dimensional data Composition The signal maintains the original data sampling rate And with the number of samples remaining unchanged, the original data rate Reduced to ; Step 2 includes: Step 21: Calculate the phase increment using the direct digital frequency synthesis technique formula: The direct digital frequency synthesis technology processing flow, based on the traditional lookup table method, is determined by the output local oscillator frequency. Sampling rate and the number of bits of the phase accumulator Determine a unique phase increment As input to the DDS; Step 22: According to θ, Integrator Output The relationship between orthogonal local oscillator signals is calculated and derived. Step 23: Based on the derivation results in Step 22, transform the traditional NCO module to... For phase increment, with The operating clock performs phase integration to obtain the reference sequence. ; Step 24: Based on the relationship between the outputs of the M-dimensional parallel decomposition in the derivation results of Step 22, convert the benchmark sequence... respectively with i Adding θ together yields the 2nd to Mth dimensions of the θ(n) sequence. ;in ; Step 25: To make Synchronous alignment of the M-dimensional sequences of the sequence, using the reference sequence Perform a processing clock After the delay, we obtain θ0(Mk+0), which serves as the first dimension of the M-dimensional θ(n) sequence. Thus, we obtain... M-dimensional sequence after sequence synchronization ,by Each of the M input addresses for a lookup table is used as an input address, and the output rate from the ROM is... M-dimensional parallel low-speed orthogonal local oscillator signals and .

2. The method according to claim 1, characterized in that, Step 22 includes: The integrator output sequence is as follows: The corresponding NCO output sequence is: and ,in, ; Output sequence , , All are operating at sampling rate Below, to , , Time index in the series To perform Euclid division, that is: let Deformation yields and corresponding , The M-dimensional output of the sequence is: Sequence: 0th dimension: ,…,No. dimension: ; Sequence: 0th dimension: ,…,No. dimension: ; Sequence: 0th dimension: ,…,No. dimension: ; according to The M-dimensional output formula of the sequence is obtained by decomposition. An M-dimensional sequence is represented as , , ; right After performing M-dimensional parallel decomposition, the output of each dimension is in M-dimensional order. θ is the phase increment that is integrated and accumulated, and the operating frequency of the integrator also becomes Meanwhile, the outputs of the M-dimensional parallel decomposition have the following relationship: First dimension: ={with For phase increment, with The phase integral output of the operating clock; i-th dimension: =First dimension output+ .

3. The method according to claim 1, characterized in that, Step 3 includes: Step 1 Each with step 2 and Multiplying the data of corresponding dimensions yields the M-dimensional parallel orthogonal down-converted I-channel signal. and Q-channel signal .

4. The method according to claim 1, characterized in that, The M-dimensional parallel FIR filtering processing architecture is obtained by performing algorithm calculations and transformations based on the traditional single-rate FIR filtering processing model. The M-dimensional parallel FIR filtering architecture is transformed to obtain a fully de-speeded version. The processor can implement an M-dimensional parallel FIR filtering algorithm model.

5. The method according to claim 1, characterized in that, The process of obtaining the M-dimensional parallel FIR filtering algorithm model is as follows: Step 51: The traditional N-tap FIR filtering algorithm is represented in the time domain as: in,{ } is an infinitely long signal input sequence, { Let} be the coefficients of an FIR filter of length N, where N is an integer multiple of M. The expression of the above formula in the z-domain is: The input sequence { After decomposition into M dimensions, the M-dimensional parallel data in the formula are respectively represented as follows: , … , Finally, X(z) can be expressed as: ＝ Step 52: Using the same method, convert the FIR filter coefficients of length N { After decomposition into M dimensions, the M-dimensional parallel data in the formula are respectively represented as follows: , , , , Finally, H(z) can be expressed as: Step 53: Based on the expression of the FIR filtering algorithm in the z-domain: The M-dimensional parallel X(z) expression from step 51 and the M-dimensional parallel H(z) expression from step 52 are calculated and represented in matrix form as follows: Step 54: In step 53 That is, M. Latency, each dimension of data operates on the reduced speed Under the clock, so one That is, one The delay, denoted as a delay D, is used to transform and implement the M-dimensional parallel decomposition formula for FIR filtering derived in step 53, thus constructing a fully degraded... The processor can implement an M-dimensional parallel FIR filtering algorithm model.

6. The method according to claim 1, characterized in that, Step 4 includes: Step 41: According to the orthogonal FIR filtering formula The processing requires dividing the orthogonal FIR filtering into four groups for processing. An M-dimensional parallel FIR filter with real parts of coefficients is designed. and the imaginary part of the filter coefficients ; Step 42: Using the M-dimensional parallel FIR filtering algorithm model designed in Step 4 as the algorithm structure for each group of filtering processes, perform calculations for the four groups of filters respectively: The input to the first group of filters is: M-dimensional parallel I-data. and the real part of the filter coefficients The filter output is obtained as follows: ; The input to the second group of filters is: M-dimensional parallel I-data. and the imaginary part of the filter coefficients The filter output is obtained as follows: ; The input to the third group of filters is: M-dimensional parallel Q-data. and the real part of the filter coefficients The filter output is obtained as follows: ; The input to the fourth group of filters is: M-dimensional parallel Q-data. and the imaginary part of the filter coefficients The filter output is obtained as follows: ; Step 43: Convert the output of the first group of filters and the output of the fourth group of filters Subtracting the data of corresponding dimensions yields the M-dimensional parallel I-channel signal output after high-speed data processing at low speed. The output of the second group of filters and the output of the third group of filters By summing the data of corresponding dimensions, we obtain the M-dimensional parallel Q-channel signal output after high-speed data processing at low speed. .

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