Contact hole preparation method, semiconductor structure and electronic device

Abstract

The present invention discloses a contact hole preparation method, a semiconductor structure and an electronic device. The method comprises: generating a mask layer on the upper end face of a first oxide layer of a semiconductor structure, exposing a target contact hole pattern on the mask layer; etching the first oxide layer according to the target contact hole pattern to expose the upper end face of the contact layer corresponding to the position of the target contact hole, and the upper end face of an upper structure corresponding to the position of the target contact hole; depositing a second insulating layer on the etched surface, and depositing a second oxide layer on the second insulating layer; removing the second insulating layer and the second oxide layer above the upper end face of the first oxide layer, etching downward from the exposed upper end face of the contact layer to remove part of the contact layer, and etching downward from the exposed upper end face of the upper structure to expose the upper end face of the zeroth layer contact.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor production, and in particular to a contact hole preparation method, a semiconductor structure and an electronic device. Background Art

[0002] After the Dynamic Random Access Memory (DRAM) process technology entered 20nm, the process integration of semiconductor processes increased, and it became increasingly difficult to reduce the size of devices. With the continuous development of semiconductor integrated circuit device technology, the line width has gradually decreased, and the height of the storage capacitor in DRAM has continued to increase, so some contact holes need to be made deeper. However, the process window of contact holes with high aspect ratios is relatively narrow. If the size of the contact hole is too large, it is easy to cause a short circuit. If the size of the contact hole is too small, it is easy to cause the risk of insufficient etching. Summary of the invention

[0003] In order to solve the problem that the existing contact hole preparation method in the dynamic random access memory is prone to short circuit or insufficient etching, the embodiments of the present invention provide a contact hole preparation method, a dynamic random access memory and an electronic device.

[0004] In a first aspect, an embodiment of the present invention provides a contact hole preparation method, which is applied to a semiconductor structure, wherein the semiconductor structure includes an array region and a peripheral region, wherein a substrate of the array region includes a buried word line, a first insulating layer, and the first insulating layer has a storage capacitor array and a contact layer in a direction away from the buried word line, wherein the contact layer covers the storage capacitor array, and an active region is provided on the substrate of the peripheral region, wherein an isolation layer and a gate structure are provided in a direction away from the active region, wherein the isolation layer covers the gate structure, wherein the isolation layer includes a lower structure, a middle structure, and an upper structure, wherein both sides of the gate structure include a zero-layer contact, wherein the top of the zero-layer contact is lower than the upper end surface of the upper structure, and wherein a first oxide layer is provided in a direction away from the contact layer and the upper structure, wherein the method includes:

[0005] Generating a mask layer on the upper end surface of the first oxide layer, and exposing a target contact hole pattern on the mask layer;

[0006] Etching the first oxide layer according to the target contact hole pattern to expose the upper end surface of the contact layer corresponding to the position of the target contact hole and the upper end surface of the upper structure corresponding to the position of the target contact hole;

[0007] Depositing a second insulating layer on the etched surface, and depositing a second oxide layer on the second insulating layer;

[0008] The second insulating layer and the second oxide layer above the upper end surface of the first oxide layer are removed, and etching is performed downward from the exposed upper end surface of the contact layer to remove part of the contact layer, and etching is performed downward from the exposed upper end surface of the upper structure to expose the upper end surface of the zeroth layer contact.

[0009] The contact hole preparation method provided by the embodiment of the present invention is applied to a semiconductor structure, wherein the semiconductor structure includes an array area and a peripheral area, wherein the substrate of the array area includes a buried word line, a first insulating layer, and the first insulating layer has a storage capacitor array and a contact layer in a direction away from the buried word line, wherein the contact layer covers the storage capacitor array, and the substrate of the peripheral area is provided with an active area, and has an isolation layer and a gate structure in a direction away from the active area, wherein the isolation layer covers the gate structure, wherein the isolation layer includes a lower structure, a middle structure, and an upper structure, wherein both sides of the gate structure include a zeroth layer contact, wherein the top of the zeroth layer contact is lower than the upper end surface of the upper structure, and has a first oxide layer in a direction away from the contact layer and the upper structure, wherein the contact hole preparation method specifically comprises: generating a mask layer on the upper end surface of the first oxide layer, exposing a target contact hole pattern on the mask layer, and etching the first oxide layer according to the target contact hole pattern to expose the contact layer corresponding to the position of the target contact hole The upper end surface, and the upper end surface of the upper structure corresponding to the target contact hole position, deposit a second insulating layer on the surface after etching, and deposit a second oxide layer on the second insulating layer, remove the second insulating layer and the second oxide layer above the upper end surface of the first oxide layer, etch downward from the exposed upper end surface of the contact layer to remove part of the contact layer, and etch downward from the exposed upper end surface of the upper structure to expose the zero-layer contact upper end surface. The above-mentioned contact hole preparation method provided by the embodiment of the present invention can reduce the critical size of the contact hole opening by depositing a layer of insulating layer and a layer of oxide layer without reducing the critical size of the contact hole opening in the array area and the peripheral area of ​​the semiconductor structure. Therefore, the critical size of the contact hole opening can be controlled to be more reasonable, which can not only avoid the short circuit problem caused by the excessive size of the contact hole, but also avoid the risk of insufficient etching caused by the small size of the contact hole, and reduce the difficulty of semiconductor process technology.

[0010] In a possible implementation manner, the mask layer includes a first mask layer and a second mask layer;

[0011] Generating a mask layer on the upper end surface of the first oxide layer specifically includes:

[0012] A first mask layer is formed on the upper end surface of the first oxide layer, and a second mask layer is formed on the upper end surface of the first mask layer.

[0013] In a possible implementation manner, the material of the first mask layer is carbon, and the material of the second mask layer is silicon oxynitride.

[0014] In a possible implementation manner, the first insulating layer, the upper structure, the lower structure and the second insulating layer are made of the same material.

[0015] In a possible implementation manner, the second oxide layer and the first oxide layer are made of the same material.

[0016] In a possible implementation manner, the second oxide layer is made of silicon dioxide.

[0017] In a possible implementation manner, the second insulating layer is made of silicon nitride.

[0018] In a possible implementation manner, a dry etching process is used to remove the second insulating layer and the second oxide layer above the upper end surface of the first insulating layer.

[0019] In a second aspect, an embodiment of the present invention provides a contact hole preparation method, which is applied to a semiconductor structure, wherein a bit line, a word line, an active area, and an isolation structure located between adjacent active areas are prepared on a substrate of the semiconductor structure, and an isolation layer and a gate structure are provided in a direction away from the active area, wherein the isolation layer covers the gate structure, and the isolation layer includes a lower structure, a middle structure, and an upper structure;

[0020] For the contact holes to be prepared, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, wherein the target contact holes include target bit line contact holes, target word line contact holes, target active area contact holes and target gate contact holes, wherein the target bit line contact holes represent contact holes for connecting to the bit lines, the target word line contact holes represent contact holes for connecting to the word lines, the target active area contact holes represent contact holes for connecting to the active areas, and the target gate contact holes represent contact holes for connecting to the gates of the gate structures;

[0021] Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, wherein the target contact surface includes the upper end surface of the target bit line, the upper end surface of the target word line, the upper end surface of the target active area and the upper end surface of the target gate;

[0022] Depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer;

[0023] The first insulating layer and the first oxide layer above the upper end surface of each level after deposition are removed to expose the target contact surface.

[0024] Another contact hole preparation method provided by an embodiment of the present invention is applied to a semiconductor structure, wherein a bit line, a word line, an active area, and an isolation structure located between adjacent active areas are prepared on a substrate of the semiconductor structure, and an isolation layer and a gate structure are provided in a direction away from the active area, wherein the isolation layer covers the gate structure, and the isolation layer includes a lower structure, a middle structure, and an upper structure. The contact hole preparation method is specifically as follows: for a contact hole to be prepared, a mask layer is generated on a corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, wherein the target contact hole includes a target bit line contact hole, a target word line contact hole, a target active area contact hole, and a target gate contact hole, and the target bit line contact hole is characterized by a contact hole for contacting the bit line. The target word line contact hole represents a contact hole connected to the word line, the target active area contact hole represents a contact hole connected to the active area, and the target gate contact hole represents a contact hole connected to the gate of the gate structure; etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the target contact hole position, the target contact surface includes the target bit line upper end surface, the target word line upper end surface, the target active area upper end surface and the target gate upper end surface; a first insulating layer is deposited on the surface after etching, and a first oxide layer is deposited on the first insulating layer; the first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed to expose the target contact surface. The above-mentioned contact hole preparation method provided by the embodiment of the present invention can reduce the critical dimensions of the openings of the bit line contact holes, word line contact holes, active area contact holes and gate contact holes in the semiconductor structure by depositing an insulating layer and an oxide layer without reducing the critical dimensions of the openings of the above-mentioned contact holes. Therefore, the critical dimensions of the openings of the above-mentioned contact holes can be controlled to be more reasonable, which can not only avoid the short circuit problem caused by the excessive size of the contact holes, but also avoid the risk of insufficient etching caused by the excessively small size of the contact holes, and reduce the difficulty of the semiconductor process technology.

[0025] In a possible implementation manner, the semiconductor structure further includes a second insulating layer disposed on the top and side of the bit line, a second oxide layer is disposed on the substrate, the second oxide layer covers the second insulating layer and the bit line, and an upper end surface of the second oxide layer is higher than an upper end surface of the second insulating layer;

[0026] When the target contact hole is a target bit line contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including:

[0027] Generating a mask layer on the upper end surface of the second oxide layer, and exposing the target bit line contact hole pattern on the mask layer;

[0028] Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising:

[0029] Etching the second oxide layer and the second insulating layer according to the target bit line contact hole pattern to expose the upper end surface of the target bit line;

[0030] Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising:

[0031] The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the upper end surface of the target bit line.

[0032] In a possible implementation manner, the word line is buried in the isolation structure, and has a third insulating layer in a direction away from the isolation structure;

[0033] When the target contact hole is a target word line contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including:

[0034] Generating a mask layer on the upper end surface of the third insulating layer, and exposing the target word line contact hole pattern on the mask layer;

[0035] Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising:

[0036] Etching downward from the third insulating layer according to the target word line contact hole pattern to expose the upper end surface of the target word line;

[0037] Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising:

[0038] The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the upper end surface of the target word line.

[0039] In a possible implementation manner, when the target contact hole is a target active area contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including:

[0040] Generating a mask layer on the upper end surface of the upper structure, and exposing the target active area contact hole pattern on the mask layer;

[0041] Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising:

[0042] Etching the upper structure, the middle structure and the lower structure according to the contact hole pattern of the target active area to expose the contact upper end surface of the target active area;

[0043] Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising:

[0044] The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the contact upper end surface of the target active area.

[0045] In a possible implementation manner, the top surface and sidewalls of the gate structure further include an insulating cap layer;

[0046] When the target contact hole is a target gate contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including:

[0047] Generating a mask layer on the upper end surface of the upper structure, and exposing the target gate contact hole pattern on the mask layer;

[0048] Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising:

[0049] Etching the upper structure and the insulating cap layer according to the target gate contact hole pattern to expose the upper end surface of the target gate;

[0050] Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising:

[0051] The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the upper end surface of the target gate.

[0052] In a possible implementation manner, the first oxide layer is made of silicon dioxide.

[0053] In a possible implementation manner, the first insulating layer is made of silicon nitride.

[0054] In a third aspect, an embodiment of the present invention provides a semiconductor structure, which is a semiconductor structure prepared by the contact hole preparation method provided by an embodiment of the present invention.

[0055] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising the semiconductor structure provided by an embodiment of the present invention.

[0056] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0058] Figure 1 is a cross-sectional view of an initial structure of a semiconductor structure in an embodiment of the present invention;

[0059] Figure 2 A schematic diagram of an implementation process of a contact hole preparation method provided by an embodiment of the present invention;

[0060] Figure 3 , Figure 4 , Figure 5 and Figure 6 A cross-sectional view of a semiconductor structure corresponding to each step of the contact hole preparation method provided in an embodiment of the present invention;

[0061] Figure 7 A schematic diagram of an implementation process of another contact hole preparation method provided by an embodiment of the present invention;

[0062] Figure 8 An initial cross-sectional view of a semiconductor structure for preparing a bit line contact hole provided by an embodiment of the present invention;

[0063] Fig. 9 A schematic diagram of an implementation process of preparing a bit line contact hole provided by an embodiment of the present invention;

[0064] Fig.10 , Fig.11 , Fig.12 and Fig.13 A cross-sectional view of a semiconductor structure corresponding to each step of preparing a bit line contact hole provided in an embodiment of the present invention;

[0065] Fig.14 An initial cross-sectional view of a semiconductor structure for preparing a word line contact hole provided by an embodiment of the present invention;

[0066] Fig.15 A schematic diagram of an implementation process of preparing a word line contact hole provided by an embodiment of the present invention;

[0067] Fig.16 , Fig.17 , Fig.18 and Fig.19A cross-sectional view of a semiconductor structure corresponding to each step of preparing a word line contact hole provided in an embodiment of the present invention;

[0068] Fig. 20 An initial cross-sectional view of a semiconductor structure for preparing active area contact holes provided by an embodiment of the present invention;

[0069] Fig.21 A schematic diagram of an implementation process of preparing active area contact holes provided by an embodiment of the present invention;

[0070] Fig. 22 , Fig.23 , Fig.24 and Fig.25 A cross-sectional view of a semiconductor structure corresponding to each step of preparing an active area contact hole provided in an embodiment of the present invention;

[0071] Fig.26 An initial cross-sectional view of a semiconductor structure for preparing a gate contact hole provided by an embodiment of the present invention;

[0072] Fig. 27 A schematic diagram of an implementation process of preparing a gate contact hole provided by an embodiment of the present invention;

[0073] Fig.28 , Fig.29 , Fig.30 and Fig.31 A cross-sectional view of a semiconductor structure corresponding to each step of preparing an active area contact hole provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0074] After the DRAM manufacturing process enters 20nm, the process integration of the semiconductor manufacturing process is increased, and it is increasingly difficult to reduce the size of the device. With the continuous development of semiconductor integrated circuit device technology, the line width is gradually reduced, and the height of the storage capacitor in the DRAM is constantly increasing. In this way, some contact holes need to be made deeper. However, the process window of the contact hole with a high aspect ratio is relatively narrow. If the size of the contact hole is too large, it is easy to cause a short circuit. If the size of the contact hole is too small, it is easy to cause the risk of insufficient etching. Based on this, the embodiment of the present invention provides a contact hole preparation method, a semiconductor structure and an electronic device.

[0075] The preferred embodiments of the present invention are described below in conjunction with the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other if there is no conflict.

[0076] An embodiment of the present invention provides a contact hole preparation method, the contact hole preparation method is applied to a semiconductor structure, the semiconductor structure is a dynamic random access memory, in the embodiment of the present invention, before the contact hole is prepared, the initial structure cross-section of the semiconductor structure is as shown in Figure 1 As shown, the semiconductor structure includes an array area 11 and a peripheral area 12. The substrate of the array area 11 includes a buried word line 111, a first insulating layer 112, and the first insulating layer 112 has a storage capacitor array 113 and a contact layer 114 in a direction away from the buried word line 111. The contact layer 114 covers the storage capacitor array 113. The substrate of the peripheral area 12 is provided with an active area 121, and has an isolation layer 122 and a gate structure 123 in a direction away from the active area 121. The isolation layer 122 covers the gate structure 123. The isolation layer 122 includes a lower structure 122-1, a middle structure 122-2 and an upper structure 122-3. Both sides of the gate structure 123 include a zero-layer contact 124, the top of the zero-layer contact 124 is lower than the upper end surface of the upper structure 122-3, and has a first oxide layer 13 in a direction away from the contact layer 114 and the upper structure 122-3. An isolation structure 14 located between adjacent active areas (AA) 121 is also provided on the substrate of the array area 11 and the substrate of the peripheral area 12. The isolation structure 14 is used to isolate multiple active areas 121 on the substrate of the semiconductor structure, wherein the upper end surface of the first insulating layer 112 in the array area 11 is flush with the upper end surface of the upper structure 122-3 of the isolation layer 122 in the peripheral area 12. The material of the substrate of the array area 11 and the substrate of the peripheral area 12 can be silicon (Si). The first insulating layer 112, the upper structure 122-3 of the isolation layer 122 and the lower structure 122-1 of the isolation layer 122 are made of the same material, all of which are insulating materials and can be silicon nitride (SiN). The material of the middle structure 122-2 of the isolation layer 122 is oxide, which can be silicon dioxide (SiO2). The material of the first oxide layer 13 is the same as that of the middle structure 122-2 of the isolation layer 122, which is also silicon dioxide. The material of the contact layer 114 can be polysilicon (Poly). The zero-layer contact 124 is a metal pad, and its material can be metal tungsten (W).

[0077] like Figure 2 As shown, it is a schematic diagram of an implementation process of a contact hole preparation method provided by an embodiment of the present invention. The contact hole preparation method may include the following steps:

[0078] S21, generating a mask layer on the upper end surface of the first oxide layer, and exposing a target contact hole pattern on the mask layer.

[0079] When implementing it, Figure 3As shown, a mask layer 15 is generated on the upper end surface of the first oxide layer 13, and target contact hole patterns 16-1 and 16-2 are exposed on the mask layer 15, wherein the mask layer 15 may include a first mask layer 15-1 and a second mask layer 15-2, the target contact hole pattern 16-1 is a pattern corresponding to the contact hole to be prepared in the array area 11, and the target contact hole pattern 16-2 is a pattern corresponding to the contact hole to be prepared in the peripheral area 12.

[0080] In the specific implementation process, a first mask layer 15-1 is deposited on the end surface of the first oxide layer 13, and a second mask layer 15-2 is deposited on the end surface of the first mask layer 15-1. The target contact hole patterns 16-1 and 16-2 are exposed on the second mask layer 15-2 using a photoresist 17. When exposing the target contact hole patterns 16-1 and 16-2, the size (i.e., diameter) of the target contact hole patterns 16-1 and 16-2 can be set to be slightly larger than the existing process size, so that the opening size of the corresponding target contact hole (i.e., the diameter of the contact hole) is larger than the existing process size. The size setting can be set according to actual conditions, and the embodiment of the present invention does not limit this. In this way, the process difficulty can be reduced. The material of the first mask layer 15-1 can be carbon, and the material of the second mask layer 15-2 can be silicon oxynitride (SiON).

[0081] S22, etching the first oxide layer according to the target contact hole pattern to expose the upper end surface of the contact layer corresponding to the target contact hole position and the upper end surface of the upper structure corresponding to the target contact hole position.

[0082] When implementing it, Figure 4 As shown, the first oxide layer 13 is etched according to the target contact hole patterns 16-1 and 16-2 to form a target contact hole 17-1 in the array area 11 and a target contact hole 17-2 in the peripheral area 12, so as to expose the upper end surface of the contact layer 114 corresponding to the position of the target contact hole 17-1 and the upper end surface of the upper structure 122-3 of the isolation layer 122 corresponding to the position of the target contact hole 17-2.

[0083] S23, depositing a second insulating layer on the etched surface, and depositing a second oxide layer on the second insulating layer.

[0084] When implementing it, Figure 5 As shown, a second insulating layer 18 is deposited on the surface after etching, and a second oxide layer 19 is deposited on the surface of the second insulating layer 18 to shrink the target contact hole 17-1 in the array area 11 and the target contact hole 17-2 in the peripheral area 12, thereby reducing the parasitic capacitance directly at the target contact hole.

[0085] Specifically, a second insulating layer 18 is deposited on the upper surface and side surfaces of the etched first oxide layer 13 , the exposed upper surface of the contact layer 114 , and the exposed upper surface of the upper structure 122 - 3 of the isolation layer 122 , and a second oxide layer 19 is deposited on the second insulating layer 18 .

[0086] In the specific implementation process, the second insulating layer 18 is made of the same material as the first insulating layer 112, the upper structure 122-3 of the isolation layer 122, and the lower structure 122-1 of the isolation layer 122, both of which can be made of silicon nitride. The second oxide layer 19 is made of the same material as the first oxide layer 13, both of which can be made of silicon dioxide. The embodiment of the present invention is not limited to this.

[0087] S24, remove the second insulating layer and the second oxide layer above the upper end surface of the first oxide layer, and etch downward from the exposed upper end surface of the contact layer to remove part of the contact layer, and etch downward from the exposed upper end surface of the upper structure to expose the zeroth layer contact upper end surface.

[0088] When implementing it, Figure 6 As shown, a dry etching process can be used to remove the second insulating layer 18 and the second oxide layer 19 above the upper end surface of the first oxide layer 13, and the upper end surface of the contact layer 114 exposed in the array area 11 is etched downward to remove part of the contact layer 114, and the upper end surface of the upper structure 122-3 of the isolation layer 122 exposed in the peripheral area 12 is etched downward to expose the upper end surface of the zeroth layer contact 124, thereby generating a contact hole 20-1 in the array area 11 and a contact hole 20-2 in the peripheral area 12, so that the generated contact hole 20-1 can be connected to the contact layer 114, and the generated contact hole 20-2 can be connected to the zeroth layer contact 124.

[0089] The semiconductor structure also includes a bit line (above Figure 2-Figure 6 not shown).

[0090] The above-mentioned contact hole preparation method provided by the embodiment of the present invention first enlarges the size of the target contact hole, and then reduces the size of the target contact hole by depositing an insulating layer (i.e., the second insulating layer 18) and an oxide layer (i.e., the second oxide layer 19). In this way, the risk of insufficient etching caused by the small size of the contact hole and the problem of short circuit of the zero-layer contact 124 caused by the large size of the contact hole are avoided, and the difficulty of semiconductor process technology is reduced.

[0091] In practical applications, as the critical dimensions of the peripheral area continue to decrease, the bombardment effect needs to be strengthened during the process, which will cause more damage to the silicon in the active area. This is extremely unfavorable for process technologies with height differences and high selectivity requirements.

[0092] Based on this, the embodiment of the present invention provides another contact hole preparation method, which is applied to a semiconductor structure, wherein the semiconductor structure is a dynamic random access memory, and a bit line 31, a word line 32, an active area 33 and an isolation structure 33-1 located between adjacent active areas 33 are prepared on the substrate of the semiconductor structure, and an isolation layer 34 and a gate structure 35 are provided in a direction away from the active area 33, wherein the isolation layer 34 covers the gate structure 35, and the isolation layer 34 includes a lower structure 34-1, a middle structure 34-2 and an upper structure 34-3. The material of the substrate can be silicon, and the upper structure 34-3 of the isolation layer 34 and the lower structure 34-1 of the isolation layer 34 are made of the same material, both of which are insulating materials, and both can be made of silicon nitride, and the material of the middle structure 34-2 of the isolation layer 34 is an oxide, which can be silicon dioxide.

[0093] The schematic diagram of the implementation process of the contact hole preparation method is as follows Figure 7 As shown, the following steps may be included:

[0094] S41 . For the contact hole to be prepared, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer.

[0095] In a specific implementation, the target contact holes include target bit line contact holes, target word line contact holes, target active area contact holes and target gate contact holes. The target bit line contact holes represent contact holes used to connect to the bit lines, the target word line contact holes represent contact holes used to connect to the word lines, the target active area contact holes represent contact holes used to connect to the active areas, and the target gate contact holes represent contact holes used to connect to the gate of the gate structure.

[0096] S42, etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the target contact hole position.

[0097] The target contact surface includes: a target bit line upper surface, a target word line upper surface, a target active region upper surface and a target gate upper surface.

[0098] S43, depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer.

[0099] In specific implementation, the first insulating layer and the upper structure 34-3 of the isolation layer 34 and the lower structure 34-1 of the isolation layer 34 are made of the same material, both of which can be silicon nitride. The material of the first oxide layer is oxide, which can be silicon dioxide. The embodiment of the present invention is not limited to this.

[0100] S44, removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface.

[0101] The following describes the implementation process of the contact hole preparation method corresponding to each of the target contact holes to be prepared, namely, the target bit line contact hole, the target word line contact hole, the target active area contact hole and the target gate contact hole.

[0102] The semiconductor structure also includes a second insulating layer 36 arranged on the top and side of the bit line 31, and a second oxide layer 37 is arranged on the substrate of the semiconductor structure. The second oxide layer 37 covers the second insulating layer 36 and the bit line 36, and the upper end surface of the second oxide layer 36 is higher than the upper end surface of the second insulating layer 36.

[0103] When the target contact hole to be prepared is a target bit line contact hole, the initial cross-sectional view of the semiconductor structure for preparing the bit line contact hole is as follows: Figure 8 As shown, according to Fig. 9 The process shown in the figure for preparing the bit line contact hole may include the following steps:

[0104] S51, generating a mask layer on the upper end surface of the second oxide layer, and exposing a target bit line contact hole pattern on the mask layer.

[0105] When implementing it, Fig.10 As shown, a mask layer 38 is generated on the upper surface of the second oxide layer 37, and a target bit line contact hole pattern 39 is exposed on the mask layer 38, wherein the mask layer 38 may include a first mask layer 38-1 and a second mask layer 38-2.

[0106] In the specific implementation process, a first mask layer 38-1 is deposited on the upper end surface of the second oxide layer 37, and a second mask layer 38-2 is deposited on the upper end surface of the first mask layer 38-1. The target bit line contact hole pattern 39 is exposed on the second mask layer 38-2 using a photoresist 310. When exposing the target bit line contact hole pattern 39, the size (i.e., diameter) of the target bit line contact hole pattern 39 can be set to be slightly larger than the existing process size, so that the opening size of the corresponding target bit line contact hole (i.e., the diameter of the bit line contact hole) is larger than the existing process size. The size setting can be set according to actual conditions, so that the process difficulty can be reduced. The material of the first mask layer 38-1 can be carbon, and the material of the second mask layer 38-2 can be silicon oxynitride.

[0107] S52, etching the second oxide layer and the second insulating layer according to the target bit line contact hole pattern to expose the upper end surface of the target bit line.

[0108] When implementing it, Fig.11 As shown, the second oxide layer 37 is etched according to the target bit line contact hole pattern 39 to form a target bit line contact hole 311 to expose the upper end surface of the target bit line.

[0109] S53, depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer.

[0110] When implementing it, Fig.12 As shown, a first insulating layer 312 is deposited on the surface after etching, and a first oxide layer 313 is deposited on the surface of the first insulating layer to reduce the size of the target bit line contact hole 311 and reduce the parasitic capacitance of the target bit line contact hole. The first insulating layer 312 is made of the same material as the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, and both can be made of silicon nitride. The first oxide layer 313 and the second oxide layer 37 are made of the same material, and both can be made of silicon dioxide, which is not limited in the embodiment of the present invention.

[0111] S54, removing the first insulating layer and the first oxide layer above each horizontal upper end surface after deposition, and retaining the first insulating layer and the first oxide layer on each side surface to expose the upper end surface of the target bit line.

[0112] When implementing it, Fig.13 As shown, the first insulating layer 312 and the first oxide layer 313 above each horizontal upper end surface after deposition are removed, and the first insulating layer 312 and the first oxide layer 313 on each side are retained to expose the upper end surface of each target bit line, thereby generating a target bit line contact hole 314. In this way, the target bit line contact hole 314 is connected to the target bit line.

[0113] In the semiconductor structure, the word line 32 is buried in the isolation structure 33 - 1 , and has a third insulating layer 315 in a direction away from the isolation structure 33 - 1 .

[0114] When the target contact hole to be prepared is a target word line contact hole, the initial cross-sectional view of the semiconductor structure for preparing the corresponding word line contact hole is as follows: Fig.14 As shown, according to Fig.15 The process shown in the figure for preparing word line contact holes may include the following steps:

[0115] S61, generating a mask layer on the upper end surface of the third insulating layer, and exposing a target word line contact hole pattern on the mask layer.

[0116] When implementing it, Fig.16 As shown, a mask layer 316 is generated on the upper end surface of the third insulating layer 315, and a target word line contact hole pattern 317 is exposed on the mask layer 316. The mask layer 316 includes a first mask layer 316-1 and a second mask layer 316-2.

[0117] In the specific implementation process, a first mask layer 316-1 is deposited on the upper end surface of the third insulating layer 315, and a second mask layer 316-2 is deposited on the upper end surface of the first mask layer 316-1. The target word line contact hole pattern 317 is exposed on the second mask layer 316-2 using a photoresist 318. When exposing the target word line contact hole pattern 317, the size (i.e., the diameter) of the target word line contact hole pattern 317 can be set to be slightly larger than the existing process size, so that the opening size of the corresponding target word line contact hole (i.e., the diameter of the word line contact hole) is larger than the existing process size. The size setting can be set according to actual conditions, so that the process difficulty can be reduced. The material of the first mask layer 316-1 can be carbon, and the material of the second mask layer 316-2 can be silicon oxynitride.

[0118] S62, etching downward from the third insulating layer according to the target word line contact hole pattern to expose the upper end surface of the target word line.

[0119] When implementing it, Fig.17 As shown, etching is performed downward from the third insulating layer 315 according to the target word line contact hole pattern 317 to form a target word line contact hole 319 to expose the upper end surface of the target word line.

[0120] S63, depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer.

[0121] When implementing it, Fig.18 As shown, after etching, a first insulating layer 320 is deposited on the surface, and a first oxide layer 321 is deposited on the surface of the first insulating layer to reduce the size of the target bit line contact hole 319 and reduce the parasitic capacitance directly of the target bit line contact hole. Among them, the first insulating layer 320 is made of the same material as the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, and both can be made of silicon nitride. The first oxide layer 321 and the second oxide layer 37 are made of the same material, and both can be made of silicon dioxide. This is not limited in the embodiment of the present invention. The third insulating layer 315 is made of the same material as the first insulating layer 320, the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, and both can be made of silicon nitride.

[0122] S64, removing the first insulating layer and the first oxide layer above each horizontal upper end surface after deposition, and retaining the first insulating layer and the first oxide layer on each side surface to expose the target word line upper end surface.

[0123] When implementing it, Fig.19As shown, the first insulating layer 320 and the first oxide layer 321 above each horizontal upper end surface after deposition are removed, and the first insulating layer 320 and the first oxide layer 321 on each side are retained to expose the upper end surface of the target word line, thereby generating a target word line contact hole 322 to connect the target word line contact hole 322 to the target word line.

[0124] When the target contact hole to be prepared is a target active area contact hole, the initial cross-sectional view of the corresponding semiconductor structure for preparing the active area contact hole is as follows: Fig. 20 As shown, according to Fig.21 The process shown in the figure is to prepare the active area contact hole, which may include the following steps:

[0125] S71, generating a mask layer on the upper end surface of the upper structure of the isolation layer, and exposing a target active area contact hole pattern on the mask layer.

[0126] When implementing it, Fig. 22 As shown, a mask layer 323 is generated on the upper end surface of the upper structure 34-3 of the isolation layer 34, and a target active area contact hole pattern 324 is exposed on the mask layer 323. The mask layer 323 includes a first mask layer 323-1 and a second mask layer 323-2.

[0127] In the specific implementation process, a first mask layer 323-1 is deposited on the upper end surface of the upper structure 34-3 of the isolation layer 34, and a second mask layer 323-2 is deposited on the upper end surface of the first mask layer 323-1. The target active area contact hole pattern 324 is exposed on the second mask layer 323-2 using a photoresist 325. When exposing the target active area contact hole pattern 324, the size (i.e., diameter) of the target word line contact hole pattern 324 can be set to be slightly larger than the existing process size, so that the opening size of the corresponding target active area contact hole (i.e., the diameter of the active area contact hole) is larger than the existing process size. The size setting can be set according to actual conditions, so that the process difficulty can be reduced. The material of the first mask layer 323-1 can be carbon, and the material of the second mask layer 323-2 can be silicon oxynitride.

[0128] S72, etching the upper structure of the isolation layer, the middle structure of the isolation layer and the lower structure of the isolation layer according to the contact hole pattern of the target active region to expose the contact upper end surface of the target active region.

[0129] When implementing it, Fig.23 As shown, the upper structure 34-3 of the isolation layer 34, the middle structure 34-2 of the isolation layer 34 and the lower structure 34-1 of the isolation layer 34 are etched according to the target active area contact hole pattern 324 to form a target active area contact hole 326 to expose the upper end surface of the target active area contact.

[0130] S73, depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer.

[0131] When implementing it, Fig.24 As shown, a first insulating layer 327 is deposited on the surface after etching, and a first oxide layer 328 is deposited on the surface of the first insulating layer to reduce the size of the target active area contact hole 326 and reduce the parasitic capacitance directly in the target active area contact hole. The first insulating layer 327 is made of the same material as the upper structure 34-3 of the isolation layer 34 and the upper structure 34-1 of the isolation layer 34, and both can be made of silicon nitride. The first oxide layer 328 and the second oxide layer 37 are made of the same material, and both can be made of silicon dioxide, which is not limited in the embodiment of the present invention.

[0132] S74, removing the first insulating layer and the first oxide layer above each horizontal upper end surface after deposition, and retaining the first insulating layer and the first oxide layer on each side surface to expose the contact upper end surface of the target active area.

[0133] When implementing it, Fig.25 As shown, the first insulating layer 327 and the first oxide layer 328 above each horizontal upper end surface after deposition are removed, and the first insulating layer 327 and the first oxide layer 328 on each side are retained to expose the contact upper end surface of the target active area, thereby generating a target active area contact hole 329 to connect the target active area contact hole 329 to the target active area.

[0134] The top surface and sidewalls of the gate structure 35 of the semiconductor structure further include an insulating capping layer 330 .

[0135] When the target contact hole to be prepared is a target gate contact hole, the initial cross-sectional view of the semiconductor structure for preparing the gate contact hole is as follows: Fig.26 As shown, according to Fig. 27 The process shown in the figure for preparing the gate contact hole may include the following steps:

[0136] S81, generating a mask layer on the upper end surface of the upper structure of the isolation layer, and exposing a target gate contact hole pattern on the mask layer.

[0137] When implementing it, Fig.28 As shown, a mask layer 331 is generated on the upper end surface of the upper structure 34 - 3 of the isolation layer 34 , and a target gate contact hole pattern 332 is exposed on the mask layer 331 . The mask layer 331 includes a first mask layer 331 - 1 and a second mask layer 331 - 2 .

[0138] Specifically, a first mask layer 331-1 is deposited on the upper end surface of the upper structure 34-3 of the isolation layer 34, and a second mask layer 331-2 is deposited on the upper end surface of the first mask layer 331-1. The target gate contact hole pattern 332 is exposed on the second mask layer 331-2 using a photoresist 333. When exposing the target gate contact hole pattern 332, the size (i.e., diameter) of the target gate contact hole pattern 332 can be set to be slightly larger than the existing process size, so that the opening size of the corresponding target gate contact hole (i.e., the diameter of the gate contact hole) is larger than the existing process size. The size setting can be set according to actual conditions, so that the process difficulty can be reduced. The material of the first mask layer 331-1 can be carbon, and the material of the second mask layer 331-2 can be silicon oxynitride.

[0139] S82, etching the upper structure of the isolation layer and the insulating cap layer according to the target gate contact hole pattern to expose the upper end surface of the target gate.

[0140] When implementing it, Fig.29 As shown, the upper structure 34 - 3 of the isolation layer 34 and the insulating cap layer 330 are etched according to the target gate contact hole pattern 332 to form a target gate contact hole 334 to expose the upper end surface of the target gate.

[0141] S83, depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer.

[0142] When implementing it, Fig.30 As shown, a first insulating layer 335 is deposited on the surface after etching, and a first oxide layer 336 is deposited on the surface of the first insulating layer to reduce the size of the target gate contact hole 334 and reduce the parasitic capacitance directly of the target gate contact hole. The first insulating layer 335, the insulating cap layer 330, the upper structure 34-3 of the isolation layer 34, and the upper structure 34-1 of the isolation layer 34 are made of the same material, which can be silicon nitride, and the first oxide layer 336 and the second oxide layer 37 are made of the same material, which can be silicon dioxide, which is not limited in the embodiment of the present invention.

[0143] S84, removing the first insulating layer and the first oxide layer above each horizontal upper end surface after deposition, and retaining the first insulating layer and the first oxide layer on each side surface to expose the target gate upper end surface.

[0144] When implementing it, Fig.31 As shown, the first insulating layer 335 and the first oxide layer 336 above each horizontal upper end surface after deposition are removed, and the first insulating layer 335 and the first oxide layer 336 on each side are retained to expose the upper end surface of the target gate, thereby generating a target gate active area contact hole 337, so that the target gate contact hole 337 is connected to the target gate.

[0145] The above-mentioned bit line contact hole preparation method, word line contact hole preparation method, active area contact hole preparation method and gate contact hole preparation method provided by the embodiments of the present invention first enlarge the size of the target contact hole, and then reduce the size of the target contact hole by depositing a layer of insulating layer and a layer of oxide layer. In this way, the risk of insufficient etching caused by the small size of the contact hole and the short circuit problem caused by the large size of the contact hole are avoided, the difficulty of the semiconductor process is reduced, and the damage to the silicon in the active area during the process is effectively reduced.

[0146] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor structure, which is a semiconductor structure prepared by the contact hole preparation method provided by an embodiment of the present invention.

[0147] Based on the same technical concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned semiconductor structure provided by an embodiment of the present invention.

[0148] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A contact hole preparation method, characterized in that: Applied to a semiconductor structure, the semiconductor structure includes an array area and a peripheral area, the array area includes a buried word line, a first insulating layer on the substrate, the first insulating layer has a storage capacitor array and a contact layer in a direction away from the buried word line, the contact layer covers the storage capacitor array, the peripheral area is provided with an active area on the substrate, and has an isolation layer and a gate structure in a direction away from the active area, the isolation layer covers the gate structure, the isolation layer includes a lower structure, a middle structure and an upper structure, both sides of the gate structure include a zero-layer contact, the top of the zero-layer contact is lower than the upper end surface of the upper structure, and has a first oxide layer in a direction away from the contact layer and the upper structure, the method includes: Generating a mask layer on the upper end surface of the first oxide layer, and exposing a target contact hole pattern on the mask layer; Etching the first oxide layer according to the target contact hole pattern to expose the upper end surface of the contact layer corresponding to the position of the target contact hole and the upper end surface of the upper structure corresponding to the position of the target contact hole; Depositing a second insulating layer on the etched surface, and depositing a second oxide layer on the second insulating layer; The second insulating layer and the second oxide layer above the upper end surface of the first oxide layer are removed, and etching is performed downward from the exposed upper end surface of the contact layer to remove part of the contact layer, and etching is performed downward from the exposed upper end surface of the upper structure to expose the upper end surface of the zeroth layer contact.

2. The method according to claim 1, characterized in that The mask layer includes a first mask layer and a second mask layer; Generating a mask layer on the upper end surface of the first oxide layer specifically includes: A first mask layer is formed on the upper end surface of the first oxide layer, and a second mask layer is formed on the upper end surface of the first mask layer.

3. The method according to claim 2, characterized in that The material of the first mask layer is carbon, and the material of the second mask layer is silicon oxynitride.

4. The method according to claim 1, characterized in that The first insulating layer, the upper structure, the lower structure and the second insulating layer are made of the same material.

5. The method according to claim 1, characterized in that The second oxide layer is made of the same material as the first oxide layer.

6. The method according to claim 1, characterized in that The second oxide layer is made of silicon dioxide.

7. The method according to claim 1, characterized in that The material of the second insulating layer is silicon nitride.

8. The method according to claim 1, characterized in that The second insulating layer and the second oxide layer above the upper end surface of the first insulating layer are removed by a dry etching process.

9. A contact hole preparation method, characterized in that: Applied to a semiconductor structure, wherein a bit line, a word line, an active area and an isolation structure located between adjacent active areas are prepared on a substrate of the semiconductor structure, an isolation layer and a gate structure are provided in a direction away from the active area, the isolation layer covers the gate structure, and the isolation layer includes a lower structure, a middle structure and an upper structure, and the method comprises: For the contact holes to be prepared, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, wherein the target contact holes include target bit line contact holes, target word line contact holes, target active area contact holes and target gate contact holes, wherein the target bit line contact holes represent contact holes for connecting to the bit lines, the target word line contact holes represent contact holes for connecting to the word lines, the target active area contact holes represent contact holes for connecting to the active areas, and the target gate contact holes represent contact holes for connecting to the gates of the gate structures; Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, wherein the target contact surface includes the upper end surface of the target bit line, the upper end surface of the target word line, the upper end surface of the target active area and the upper end surface of the target gate; Depositing a first insulating layer on the etched surface, and depositing a first oxide layer on the first insulating layer; The first insulating layer and the first oxide layer above the upper end surface of each level after deposition are removed to expose the target contact surface.

10. The method according to claim 9, characterized in that The semiconductor structure further comprises a second insulating layer disposed on the top and side of the bit line, a second oxide layer is disposed on the substrate, the second oxide layer covers the second insulating layer and the bit line, and an upper end surface of the second oxide layer is higher than an upper end surface of the second insulating layer; When the target contact hole is a target bit line contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including: Generating a mask layer on the upper end surface of the second oxide layer, and exposing the target bit line contact hole pattern on the mask layer; Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising: Etching the second oxide layer and the second insulating layer according to the target bit line contact hole pattern to expose the upper end surface of the target bit line; Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising: The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the upper end surface of the target bit line.

11. The method according to claim 9, characterized in that The word line is buried in the isolation structure and has a third insulating layer in a direction away from the isolation structure; When the target contact hole is a target word line contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including: Generating a mask layer on the upper end surface of the third insulating layer, and exposing the target word line contact hole pattern on the mask layer; Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising: Etching downward from the third insulating layer according to the target word line contact hole pattern to expose the upper end surface of the target word line; Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising: The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the upper end surface of the target word line.

12. The method according to claim 9, characterized in that When the target contact hole is a target active area contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically comprising: Generating a mask layer on the upper end surface of the upper structure, and exposing the target active area contact hole pattern on the mask layer; Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising: Etching the upper structure, the middle structure and the lower structure according to the contact hole pattern of the target active area to expose the contact upper end surface of the target active area; Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising: The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the contact upper end surface of the target active area.

13. The method according to claim 9, characterized in that The top surface and sidewalls of the gate structure also include an insulating cap layer; When the target contact hole is a target gate contact hole, a mask layer is generated on the corresponding target upper end surface, and a target contact hole pattern is exposed on the mask layer, specifically including: Generating a mask layer on the upper end surface of the upper structure, and exposing the target gate contact hole pattern on the mask layer; Etching is performed according to the target contact hole pattern to expose the target contact surface corresponding to the position of the target contact hole, specifically comprising: Etching the upper structure and the insulating cap layer according to the target gate contact hole pattern to expose the upper end surface of the target gate; Removing the first insulating layer and the first oxide layer above the upper end surface of each level after deposition to expose the target contact surface, specifically comprising: The first insulating layer and the first oxide layer above each horizontal upper end surface after deposition are removed, and the first insulating layer and the first oxide layer on each side surface are retained to expose the upper end surface of the target gate.

14. The method according to any one of claims 9 to 13, characterized in that: The first oxide layer is made of silicon dioxide.

15. The method according to any one of claims 9 to 13, characterized in that: The material of the first insulating layer is silicon nitride.

16. A semiconductor structure, characterized in that: The semiconductor structure is a semiconductor structure prepared by the contact hole preparation method according to any one of claims 1 to 8 or 9 to 15.

17. An electronic device, characterized in that: Comprising the semiconductor structure as claimed in claim 16.

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