Method for manufacturing semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing an initial structure, which includes a substrate and an initial trench, and the initial trench exposes a part of an active region structure; forming a capacitive contact structure, the capacitive contact structure covering the exposed part of the active region structure, and the capacitive contact structure includes a first groove; forming a Schottky contact structure, the Schottky contact structure at least covering the top surface of the capacitive contact structure and filling the first groove; forming a barrier structure, the barrier structure covering the exposed sidewalls of the Schottky contact structure and the initial trench; forming a conductive structure, the conductive structure being connected through the Schottky contact structure and the capacitive contact structure. In the manufacturing method of the semiconductor structure and the semiconductor structure of the present disclosure, the Schottky contact structure serves as an intermediate transition structure for electrical connection between the capacitive contact structure and the conductive structure, reducing the contact resistance between the capacitive contact structure and the conductive structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the field of integrated circuits, according to Moore's law, as the number of semiconductor devices packaged in an integrated circuit doubles, the performance of the integrated circuit also doubles. Therefore, the integration degree of integrated circuits is continuously improved, and the line width of semiconductor devices is continuously reduced.

[0003] However, semiconductor devices often form electrical connections by forming metal-semiconductor contact structures. The work function of the metal affects the affinity of the semiconductor material, and the energy band of the semiconductor material bends at the interface. Metal Induced Gap States (MIGS) are easily generated at the contact interface between the metal and the semiconductor material. The metal induced gap states cause a Schottky barrier to form at the contact interface between the metal and the semiconductor material. The Schottky barrier inhibits the flow of charge carriers, and the existence of the Schottky barrier increases the contact resistance of the metal-semiconductor contact structure, which is not conducive to improving the device performance. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0006] The first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method comprising:

[0007] Providing an initial structure, the initial structure including a substrate and a plurality of bit line structures disposed on the substrate, an initial trench being formed between adjacent bit line structures, the substrate including an active region structure, and the initial trench exposing a part of the active region structure;

[0008] Forming a capacitor contact structure, the capacitor contact structure covering the exposed part of the active region structure, the capacitor contact structure including a first groove;

[0009] Forming a metal-semiconductor contact structure, the metal-semiconductor contact structure at least covering the top surface of the capacitor contact structure and filling the first groove;

[0010] Forming a barrier structure, the barrier structure covering the metal-semiconductor contact structure and the exposed sidewalls of the initial trench;

[0011] Form a conductive structure that covers the barrier structure and fills the unfilled initial trenches, and the conductive structure is connected through the Schottky contact structure and the capacitive contact structure.

[0012] According to some embodiments of the present disclosure, forming the Schottky contact structure includes:

[0013] Form a first contact layer that fills the first groove and part of the initial trench;

[0014] Form a second contact layer that covers the top surface of the first contact layer and the exposed part of the side wall of the initial trench.

[0015] According to some embodiments of the present disclosure, forming the Schottky contact structure includes:

[0016] Form a first contact layer that covers the top surface of the capacitive contact structure;

[0017] Form a second contact layer that fills the first groove and covers the exposed part of the side wall of the initial trench.

[0018] According to some embodiments of the present disclosure, forming the first contact layer includes:

[0019] Deposit a first contact material to form the first contact layer, and the first contact material includes a single-layer semiconductor material.

[0020] According to some embodiments of the present disclosure, forming the second contact layer includes:

[0021] Deposit a second contact material to form the second contact layer, and the second contact material includes a Group VA semimetal element.

[0022] According to some embodiments of the present disclosure, forming the capacitive contact structure includes:

[0023] Form an initial capacitive contact structure that fills the initial trench;

[0024] Etch back the initial capacitive contact structure, and the remaining initial capacitive contact structure forms the capacitive contact structure;

[0025] Etch the capacitive contact structure to form the first groove on the top surface of the capacitive contact structure.

[0026] According to some embodiments of the present disclosure, providing the initial structure includes:

[0027] Provide a substrate;

[0028] Etch the substrate to form a plurality of active region structures arranged in an array;

[0029] Form a shallow trench isolation structure for isolating the active region structures;

[0030] Form bit line contact holes exposing part of the active region structures and part of the shallow trench isolation structure;

[0031] Form bit line contact parts filling the bit line contact holes;

[0032] Form a bit line structure disposed on the top surfaces of the active region structures and the shallow trench isolation structure, the bit line structure being connected to the bit line contact parts, a plurality of the bit line structures being parallel to each other, an initial trench being formed between adjacent bit line structures, the initial trench exposing the top surface of part of the active region structures.

[0033] According to some embodiments of the present disclosure, after forming the bit line structure, further comprising:

[0034] Form a spacer structure in the initial trench, an extending direction of the spacer structure being perpendicular to an extending direction of the bit line structure;

[0035] Using the spacer structure and the bit line structure as masks, remove part of the active region structures and the shallow trench isolation structure exposed by the initial trench to form capacitor contact holes.

[0036] According to some embodiments of the present disclosure, forming the capacitor contact structure includes:

[0037] Form a capacitor contact structure filling the capacitor contact holes and part of the initial trench.

[0038] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0039] A substrate and a plurality of bit line structures disposed on the substrate;

[0040] A capacitor contact structure formed between the bit line structures, the capacitor contact structure including a first groove;

[0041] A Schottky contact structure at least covering the top surface of the capacitor contact structure and filling the first groove;

[0042] A barrier structure covering part of sidewalls of the Schottky contact structure and the bit line structures;

[0043] A conductive structure, the conductive structure covering the barrier structure, and the conductive structure being connected through the Schottky contact structure and the capacitive contact structure.

[0044] According to some embodiments of the present disclosure, the Schottky contact structure includes:

[0045] A first contact layer, the first contact layer filling the first groove and covering part of the sidewalls of the bit line structure;

[0046] A second contact layer, the second contact layer covering the first contact layer and part of the sidewalls of the bit line structure.

[0047] According to some embodiments of the present disclosure, the Schottky contact structure includes:

[0048] A first contact layer, the first contact layer covering the top surface of the capacitive contact structure;

[0049] A second contact layer, the second contact layer filling the first groove and covering part of the sidewalls of the bit line structure.

[0050] According to some embodiments of the present disclosure, the material of the first contact layer includes a single-layer semiconductor material, and the material of the second contact layer includes a Group VA element.

[0051] According to some embodiments of the present disclosure, the substrate includes an active region structure and a shallow trench isolation structure, the top surface of the active region structure is flush with the top surface of the shallow trench isolation structure, and the initial trench exposes part of the active region structure and the shallow trench isolation structure.

[0052] According to some embodiments of the present disclosure, the semiconductor structure further includes:

[0053] Capacitive contact holes, the capacitive contact holes are disposed on the substrate, the capacitive contact holes are located between adjacent bit line structures, and part of the active region structure and the shallow trench isolation structure are exposed between adjacent bit line structures; the capacitive contact structure fills the capacitive contact holes.

[0054] In the manufacturing method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, a Schottky contact structure is added between the capacitive contact structure and the conductive structure, and the Schottky contact structure is used as an intermediate transition structure for electrical connection between the capacitive contact structure and the conductive structure, so as to reduce the contact resistance between the capacitive contact structure and the conductive structure.

[0055] Other aspects will be apparent after reading and understanding the drawings and the detailed description. Description of the Drawings

[0056] The accompanying drawings incorporated herein and constituting a part of the specification illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The drawings in the following description are some embodiments of the present disclosure, rather than all structural embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0057] Figure 1 is a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0058] Figure 2 is a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0059] Figure 3 is a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0060] Figure 4 is a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0061] Figure 5 is a schematic diagram of an initial structure provided in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0062] Figure 6 is a schematic diagram of forming an initial capacitor contact structure in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0063] Figure 7 is a schematic diagram of forming a capacitor contact structure in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0064] Figure 8 is a schematic diagram of forming a first groove on the capacitor contact structure in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0065] Figure 9 is a schematic diagram of depositing a first contact material in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0066] Figure 10 is a schematic diagram of forming a first contact layer in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0067] Figure 11 is a schematic diagram of depositing a second contact material in a method for fabricating a semiconductor structure shown according to an exemplary embodiment.

[0068] Figure 12 Schematic diagram of forming a second contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0069] Figure 13 Schematic diagram of a Schottky contact structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0070] Figure 14 Schematic diagram of forming a barrier structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0071] Figure 15 Schematic diagram of forming a conductive structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0072] Figure 16 Schematic diagram of forming a first contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0073] Figure 17 Schematic diagram of depositing a second contact material in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0074] Figure 18 Schematic diagram of forming a second contact layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0075] Figure 19 Schematic diagram of a Schottky contact structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0076] Figure 20 Schematic diagram of forming a photoresist mask on a substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0077] Figure 21 Schematic diagram of the projection of a photoresist mask on a substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0078] Figure 22 Schematic diagram of etching a substrate to form an active region structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0079] Figure 23 Schematic diagram of forming a shallow trench isolation structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0080] Figure 24 Schematic diagram of a bit line contact hole structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0081] Figure 25 It is a schematic projection diagram of a bit line contact hole formed on a substrate in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment.

[0082] Figure 26 It is a schematic diagram of forming a bit line contact part in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment.

[0083] Figure 27 It is a schematic diagram of forming a bit line structure in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment.

[0084] Figure 28 It is a schematic diagram of forming a spacer structure in an initial trench in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment.

[0085] Figure 29 It is a schematic projection diagram of a spacer structure formed on a substrate in a method for manufacturing a semiconductor structure shown according to an exemplary embodiment.

[0086] Reference numerals:

[0087] 100, initial structure; 101, substrate; 102, photoresist mask; 103, shallow trench; 104, first mask layer; 105, bit line contact hole; 110, substrate 110; 111, active region structure; 112, shallow trench isolation structure; 120, bit line structure; 121, bit line contact part; 130, initial trench; 140, capacitor contact hole; 150, spacer structure;

[0088] 210, capacitor contact structure; 211, initial capacitor contact structure; 215, first groove; 220, Schottky contact structure; 221, first contact layer; 222, second contact layer; 230, barrier structure; 240, conductive structure. Detailed implementation manners

[0089] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, rather than all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other arbitrarily.

[0090] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, as Figure 1As shown, Figure 1 FIG. Figure 1 shows a flowchart of a method for fabricating a semiconductor structure provided according to an exemplary embodiment of the present disclosure, Figures 2 - 10 and FIGS. Figures 2 - 10 are schematic diagrams of various stages of the method for fabricating the semiconductor structure. The method for fabricating the semiconductor structure will be introduced below in conjunction with Figures 2 - 10 the figures.

[0091] In this embodiment, the semiconductor structure is not limited. Below, a dynamic random access memory (DRAM) will be taken as an example for introduction, but this embodiment is not limited thereto. The semiconductor structure in this embodiment can also be other structures.

[0092] As Figure 1 shown, a method for fabricating a semiconductor structure provided according to an exemplary embodiment of the present disclosure includes the following steps:

[0093] Step S110: Provide an initial structure. The initial structure includes a substrate and a plurality of bit line structures disposed on the substrate. An initial trench is formed between adjacent bit line structures. The substrate includes an active region structure, and the initial trench exposes a part of the active region structure.

[0094] As Figure 5 shown, the substrate 110 includes a plurality of active region structures 111. The plurality of active region structures 111 are independently disposed. The active region structure 111 includes a semiconductor material. Among them, the semiconductor material can be one or more of silicon, germanium, silicon-germanium compound, and silicon-carbon compound. A plurality of bit line structures 120 are spaced apart and disposed on the substrate 110. An initial trench 130 is formed between adjacent bit line structures 120. The initial trench 130 exposes the top surface of a part of the active region structure 111.

[0095] Step S120: Form a capacitor contact structure. The capacitor contact structure covers the exposed part of the active region structure. The capacitor contact structure includes a first groove.

[0096] As Figure 8 shown, the material of the capacitor contact structure 210 is a doped semiconductor. Exemplarily, the material of the capacitor contact structure 210 is n-type or p-type conductive doped polysilicon.

[0097] In this embodiment, the step of forming the capacitor contact structure 210 includes: As Figure 6 shown, referring to Figure 5 , form an initial capacitor contact structure 211. The initial capacitor contact structure 211 fills the initial trench 130. In this embodiment, atomic layer deposition (ALD) process can be used to deposit doped polysilicon to form the initial capacitor contact structure 211. Then, as Figure 7 shown, referring to Figure 6, etch the initial capacitor contact structure 211, and the remaining initial capacitor contact structure 211 forms the capacitor contact structure 210. In this embodiment, the initial capacitor contact structure 211 can be etched by a dry or wet etching process, and the initial capacitor contact structure 211 is etched back to be lower than the top surface of the substrate 110. Finally, as Figure 8 shown, referring to Figure 7 , etch the capacitor contact structure 210 to form a first groove 215 on the top surface of the capacitor contact structure 210.

[0098] Step S130: Form a metal-semiconductor contact structure, and the metal-semiconductor contact structure covers at least the top surface of the capacitor contact structure and fills the first groove.

[0099] As Figure 12 shown, form a metal-semiconductor contact structure 220, and use the metal-semiconductor contact structure 220 as an intermediate transition structure between the capacitor contact structure 210 and the subsequent formed conductive structure 240.

[0100] In this embodiment, the formed metal-semiconductor contact structure 220 is formed by a two-dimensional semiconductor material (two-dimensionalsemimetal) and a material with half-metal (half metal) characteristics. The energy band structure of the material with half-metal characteristics includes two different sub-energy band structures, one of which has a metallic spin orientation and the other has semiconductor properties. The Schottky barrier formed by the two-dimensional semiconductor material (two-dimensionalsemimetal) and the material with half-metal (half metal) characteristics in the metal-semiconductor contact structure 220 is smaller than the Schottky barrier formed by the direct contact between the capacitor contact structure 210 and the subsequent formed conductive structure.

[0101] Step S140: Form a barrier structure, and the barrier structure covers the exposed sidewalls of the metal-semiconductor contact structure and the initial trench.

[0102] As Figure 14 shown, referring to Figure 12 , an atomic layer deposition (ALD) process can be used to deposit and form a barrier structure 230, and the barrier structure 230 covers the exposed part of the metal-semiconductor contact structure 220 and the exposed sidewalls of the initial trench 130.

[0103] Among them, the material of the barrier structure 230 includes inorganic metal nitrides. Exemplarily, the material of the barrier structure 230 includes one or more of titanium nitride, aluminum nitride, boron nitride, hafnium nitride, tantalum nitride, titanium nitride or zirconium nitride. In this embodiment, the material of the barrier structure 230 is titanium nitride.

[0104] Step S150: Form a conductive structure that covers the blocking structure and fills the unfilled initial trenches, and the conductive structure is connected through a Schottky contact structure and a capacitive contact structure.

[0105] As Figure 15 shown, referring to Figure 14 , a metal conductive material can be deposited by Chemical Vapor Deposition (CVD) to form the conductive structure 240, and the conductive structure 240 fills the remaining unfilled areas in the initial trench 130. In this embodiment, the material of the conductive structure 240 includes tungsten.

[0106] In this embodiment, the step of forming the conductive structure 240 includes: depositing tungsten to fill the initial trench 130 until it covers the top surface of the bit line structure 120, and etching away the tungsten covering the top surface of the bit line structure 120 through a dry or wet etching process to form the conductive structure 240.

[0107] In the manufacturing method of the semiconductor structure of this embodiment, a Schottky contact structure is formed between the capacitive contact structure and the conductive structure. The Schottky barrier of the Schottky contact structure is smaller than the Schottky barrier formed by the direct contact between the capacitive contact structure and the conductive structure. The Schottky contact structure serves as a transition structure for connecting the capacitive contact structure and the conductive structure, reducing the Schottky barrier generated by the connection between the capacitive contact structure and the conductive structure, reducing the contact resistance generated by the electrical connection between the capacitive contact structure and the conductive structure, and further reducing the size of the semiconductor device.

[0108] In an exemplary embodiment of the present disclosure, a manufacturing method of a semiconductor structure is provided. As Figure 2 shown, Figure 2 shows a flowchart of a manufacturing method of a semiconductor structure provided according to an exemplary embodiment of the present disclosure.

[0109] As Figure 2 shown, a manufacturing method of a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0110] Step S210: Provide an initial structure.

[0111] As Figure 5 shown, the initial structure 100 includes a substrate 110 and a plurality of bit line structures 120 disposed on the substrate 110. Initial trenches 130 are formed between adjacent bit line structures 120. The substrate 110 includes an active region structure 111, and the initial trenches 130 expose a part of the active region structure 111.

[0112] Step S220: Form a capacitive contact structure that covers the exposed part of the active region structure, and the capacitive contact structure includes a first groove.

[0113] Step S230: Form a first contact layer, which fills the first groove and part of the initial trench.

[0114] As Figure 9 , Figure 10 shown, the first contact layer 221 can be formed by depositing a first contact material, and the first contact material 221 includes monolayer semiconductors.

[0115] Exemplarily, a top-down lift-off process or a bottom-up low-pressure metal-organic chemical vapor deposition (MOCVD) process can be used to form the first contact layer 221. In this embodiment, as Figure 9 shown, referring to Figure 8 , a low-pressure metal-organic chemical vapor deposition (MOCVD) process is used to grow monolayer semiconductors on the top surface of the capacitive contact structure. The monolayer semiconductors fill the unfilled areas in the first groove 215 and the initial trench 130, and cover the top surface of the bit line structure 120. As Figure 10 shown, referring to Figure 9 , the monolayer semiconductors covering the top surface of the bit line structure 120 are etched away and the monolayer semiconductors filled in the initial trench 130 are etched back. The remaining monolayer semiconductors form the first contact layer 221. The top surface of the first contact layer 221 is lower than the top surface of the bit line structure 120, and the first contact layer 221 fills the first groove 215 and part of the initial trench 130.

[0116] In this embodiment, the monolayer semiconductors included in the first contact material are two-dimensional transition metal dichalcogenides (TMDs). Exemplarily, the first contact material may include at least one of molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), rhenium disulfide (ReS 2 ), titanium diselenide (TiSe 2 ), niobium diselenide (NbSe 2 ), and rhenium diselenide (ReSe 2 ).

[0117] Step S240: Form a second contact layer, which covers the top surface of the first contact layer and the exposed sidewalls of part of the initial trench. The first contact layer and the second contact layer form a Schottky contact structure.

[0118] As Figure 11 shown, referring to Figure 10 , the second contact layer 222 can be formed by depositing a second contact material, and the second contact material includes a Group VA semimetal element. The material including the Group VA semimetal element can be heated and evaporated by an electron beam evaporation process, or the material including the Group VA semimetal element can be sputtered by a magnetron sputtering process, so that the material including the Group VA semimetal element is deposited on the top surface of the first contact layer 221 and the sidewalls exposed by the initial trench 130.

[0119] As Figure 12 shown, referring to Figure 11 , part of the material covering the sidewalls of the initial trench 130 is etched away to form the second contact layer 222, and the second contact layer 222 covers the top surface of the first contact layer 221 and part of the sidewalls exposed by the initial trench 130. Exemplarily, the second contact material may include at least one of the Group VA semimetal elements in the fourth - sixth periods of the periodic table of chemical elements, such as arsenic (As), antimony (Sb), and bismuth (Bi).

[0120] As Figure 12 、 Figure 13 shown, the first contact layer 221 and the second contact layer 222 form a Schottky contact structure 220. At the contact interface between the first contact layer 221 and the second contact layer 222, the Fermi level of the Group VA semimetal element in the second contact layer 222 is close to the minimum value of the semiconductor conduction band of the two - dimensional transition metal chalcogenide in the first contact layer 221. The valence band of the two - dimensional transition metal chalcogenide is saturated (the gap state is saturated), and the metal - induced gap state generated by the Group VA semimetal element in the two - dimensional transition metal chalcogenide is suppressed. Then, the Schottky barrier generated at the contact interface between the first contact layer 221 and the second contact layer 222 decreases towards a value close to zero. Therefore, the Schottky barrier generated at the contact interface between the first contact layer 221 and the second contact layer 222 can be negligible. There is no barrier for carriers to enter the second contact layer 222 from the first contact layer 221, while there is only a very small or even negligible barrier for carriers to enter the first contact layer 221 from the second contact layer 222. The two - dimensional transition metal chalcogenide in the first contact layer 221 and the Group VA semimetal element in the second contact layer 222 form a good ohmic contact, the resistance at the contact interface between the first contact layer 221 and the second contact layer 222 is small, and the carrier density flowing from the first contact layer 221 to the second contact layer 222 is high.

[0121] Step S250: Form a blocking structure, and the blocking structure covers the top surface of the second contact layer and the exposed sidewalls of the initial trench.

[0122] Step S260: Form a conductive structure that covers the barrier structure and fills the unfilled initial trenches, and the conductive structure is connected through a Schottky contact structure and a capacitive contact structure.

[0123] The implementation manners of steps S210 - S220 in this embodiment are the same as those of steps S110 - S120 in the above - mentioned embodiment, and the implementation manners of steps S250 - S260 are the same as those of steps S140 - S150 in the above - mentioned embodiment. Therefore, they will not be elaborated here.

[0124] In this embodiment, the Schottky contact structure includes a first contact layer and a second contact layer. The first contact layer includes a single - layer semiconductor material, and the second contact layer includes a Group VA semimetal element. The contact between the single - layer semiconductor material and the Group VA semimetal element material reduces the Schottky barrier generated at the contact interface between the first contact layer and the second contact layer. A good ohmic contact is formed at the contact interface between the first contact layer and the second contact layer, thereby reducing the resistance between the first contact layer and the second contact layer. The Schottky contact structure serves as an intermediate transition structure for electrically connecting the capacitive contact structure and the conductive structure, reducing the contact resistance between the capacitive contact structure and the conductive structure. The on - state current density between the capacitive contact structure and the conductive structure is higher, improving the potential for the semiconductor structure to develop towards high performance and high miniaturization, and further reducing the size of semiconductor devices. Moreover, the filling of the first groove by the first contact layer increases the contact area between the first contact layer and the first groove, and the second contact layer covers the top surface of the first contact layer and a part of the side wall exposed by the initial trench, increasing the contact area between the second contact layer and the conductive structure, further improving the mobility of carriers from the capacitive contact structure to the conductive structure, and increasing the on - state current density between the capacitive contact structure and the conductive structure.

[0125] An exemplary embodiment of the present disclosure provides a method for fabricating a semiconductor structure, as Figure 3 shown, Figure 3 which shows a flowchart of the method for fabricating a semiconductor structure provided according to an exemplary embodiment of the present disclosure.

[0126] As Figure 3 shown, an exemplary embodiment of the present disclosure provides a method for fabricating a semiconductor structure, including the following steps:

[0127] Step S310: Provide an initial structure.

[0128] Exemplarily, providing an initial structure in this embodiment includes the following steps:

[0129] S311: Provide a substrate.

[0130] As Figure 20As shown, the substrate 101 can be made of a semiconductor material, where the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0131] S312: Etch the substrate to form a plurality of active region structures arranged in an array.

[0132] As Figure 20 shown, a photoresist mask layer 102 is formed on the top surface of the substrate 101. As Figure 21 shown, the projection of the photoresist mask layer 102 on the substrate 101 exposes a part of the top surface of the substrate 101. As Figure 22 shown, the exposed part of the substrate 101 covered by the photoresist mask layer 102 is removed by dry or wet etching to form a shallow trench 103. The photoresist mask layer 102 is removed, and the substrate covered by the photoresist mask layer 102 forms a plurality of independently arranged active region structures 111, and the plurality of active region structures 111 are separated by the shallow trench 103.

[0133] S313: Form a shallow trench isolation structure for isolating each active region structure.

[0134] As Figure 23 shown, referring to Figure 22 , a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or an atomic layer deposition process (Atomic layer deposition, ALD) is used to deposit a low-k dielectric material to fill the shallow trench 103 to form a shallow trench isolation structure 112, and the shallow trench isolation structure 112 separates the plurality of active region structures 111. The shallow trench isolation structure 112 and the active region structure 111 form a substrate 110. In this embodiment, silicon oxide is deposited into the shallow trench 103 to form a shallow trench isolation structure 112.

[0135] S314: Form bit line contact holes, and the bit line contact holes expose part of the active region structure and part of the shallow trench isolation structure.

[0136] As Figure 23 shown, a first mask layer 104 is formed on the top surfaces of the active region structure 111 and the shallow trench isolation structure 112. The projection of the first mask layer 104 on the substrate 101 exposes part of the active region structure 111 and part of the shallow trench isolation structure 112. As Figure 24 shown, the exposed part of the active region structure 111 and part of the shallow trench isolation structure 112 covered by the first mask layer 104 are etched away by dry or wet etching process to form bit line contact holes 105. As Figure 25 shown, the bit line contact holes 105 expose part of the active region structure 111 and part of the shallow trench isolation structure 112.

[0137] S315: Form bit line contact parts, and fill the bit line contact holes with the bit line contact parts.

[0138] As Figure 26 shown, referring to Figure 24 , a doped semiconductor material is deposited through a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process to form the bit line contact part 121. In this embodiment, the material of the bit line contact part 121 includes conductive type doped polysilicon.

[0139] S316: Form a bit line structure.

[0140] As Figure 27 shown, referring to Figure 26 , the bit line structure 120 is disposed on the top surfaces of the active region structure 111 and the shallow trench isolation structure 112. The bit line structure is connected to the bit line contact part 121. Multiple bit line structures 120 are parallel to each other, and an initial trench 130 is formed between adjacent bit line structures 120. The initial trench 130 exposes a part of the top surface of the active region structure 111.

[0141] In this embodiment, to provide the initial structure, the following steps are further included:

[0142] S317: Form a spacer structure in the initial trench, and the extending direction of the spacer structure is perpendicular to the extending direction of the bit line structure.

[0143] As Figure 28 shown, referring to Figure 27 , a spacer structure 150 is formed. The spacer structure 150 is located in the initial trench 130 and covers a part of the initial trench 130. As Figure 28 , Figure 29 shown, the setting direction of the spacer structure 150 is perpendicular to the extending direction of the bit line structure 120. The spacer structure 150 exposes a part of the top surface of the active region structure 111 and a part of the top surface of the shallow trench isolation structure 112.

[0144] S318: Using the spacer structure and the bit line structure as masks, remove the exposed part of the active region structure and the shallow trench isolation structure in the initial trench to form capacitor contact holes.

[0145] As Figure 5 shown, referring to Figure 28 , Figure 29 , through a dry or wet etching process, etch and remove the exposed part of the active region structure 111 and the exposed part of the shallow trench isolation structure 112 by the spacer structure 150 and the bit line structure 120 to form capacitor contact holes 140. The capacitor contact holes 140 expose a part of the active region structure 111 and a part of the shallow trench isolation structure 112.

[0146] Step S320: Form a capacitive contact structure that covers the exposed part of the active region structure. The capacitive contact structure includes a first groove.

[0147] Exemplarily, in this embodiment, forming the capacitive contact structure 210 includes the following steps: As Figure 6 shown, referring to Figure 5 , an initial capacitive contact structure 211 is deposited by atomic layer deposition (ALD) to form doped polysilicon. The initial capacitive contact structure 211 fills the capacitive contact hole 140 and the initial trench 130. Then, as Figure 7 shown, referring to Figure 6 , the initial capacitive contact structure 211 is etched by a dry or wet etching process, and the initial capacitive contact structure 211 is etched back to be lower than the top surface of the substrate 110. The remaining initial capacitive contact structure 211 forms the capacitive contact structure 210, and the capacitive contact structure 210 fills the capacitive contact hole 140 and part of the initial trench 130. Finally, as Figure 8 shown, referring to Figure 7 , the top surface of the capacitive contact structure 210 is etched to form a first groove 215 that is recessed toward the substrate 110 on the top surface of the capacitive contact structure 210.

[0148] Step S330: Form a first contact layer that covers the top surface of the capacitive contact structure.

[0149] As Figure 16 shown, referring to Figure 8 , a top-down lift-off process or a bottom-up low-pressure metal-organic chemical vapor deposition (MOCVD) process can be used to form the first contact layer 221 by depositing a first contact material. The first contact material includes a single-layer semiconductor material (monolayer semiconductors).

[0150] In this embodiment, the single-layer semiconductor material included in the first contact material is a two-dimensional transition metal dichalcogenide (TMDs). Exemplarily, the first contact material may include at least one of molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), rhenium disulfide (ReS 2 ), titanium diselenide (TiSe2), niobium diselenide (NbSe 2 ), and rhenium diselenide (ReSe 2 ).

[0151] Monolayer two-dimensional transition metal dichalcogenides (TMDs) consist of three atomic layers arranged in the pattern of sulfur atom - transition metal atom - sulfur atom. Monolayer two-dimensional transition metal dichalcogenides have good semiconductor properties and high planar carrier mobility.

[0152] In this embodiment, as Figure 16 shown, a three-dimensional semiconductor material can be formed using a exfoliation process. By removing a single atomic layer or multiple atomic layers from the three-dimensional semiconductor material through the exfoliation process, a monolayer two-dimensional semiconductor material is formed. The monolayer two-dimensional semiconductor material is transferred onto the capacitive contact structure 210, and the monolayer two-dimensional semiconductor material covers the top surface of the capacitive contact structure to form the first contact layer 221.

[0153] Step S340: Form a second contact layer. The second contact layer fills the first groove and covers a part of the sidewalls exposed by the initial trench. The first contact layer and the second contact layer form a Schottky contact structure.

[0154] As Figure 17 shown, referring to Figure 16 , a second contact layer 222 can be formed by heating and evaporating through an electron beam evaporation process or sputter depositing through a magnetron sputtering process. The second contact material includes materials of Group VA semimetal elements. The materials of Group VA semimetal elements cover the top surface of the first contact layer 221, fill the first groove 215, and cover the sidewalls exposed by the initial trench 130. As Figure 18 shown, referring to Figure 17 , a part of the material covering the sidewalls of the initial trench 130 is etched away to form the second contact layer 222. Among them, the second contact material may include at least one of the Group VA semimetal elements arsenic (As), antimony (Sb), and bismuth (Bi) in the fourth to sixth periods of the periodic table of chemical elements.

[0155] Step S350: Form a blocking structure. The blocking structure covers the top surface of the second contact layer and the exposed sidewalls of the initial trench.

[0156] Step S360: Form a conductive structure. The conductive structure covers the blocking structure and fills the unfilled initial trench. The conductive structure is connected through the Schottky contact structure and the capacitive contact structure.

[0157] The implementation manners of steps S350 - S360 in this embodiment are the same as those of steps S140 - S150 in the above embodiment, and will not be elaborated here.

[0158] The metal-semiconductor contact structure in this embodiment includes a first contact layer and a second contact layer. The first contact layer covers the top surface of the capacitive contact structure, that is, the first contact layer has a concave structure with the bottom facing downwards, which increases the contact area between the first contact layer and the second contact layer and reduces the contact resistance of the metal-semiconductor contact structure. At the same time, the second contact layer covers part of the sidewalls of the initial trench, increasing the contact area between the second contact layer and the conductive structure and reducing the contact resistance between the metal-semiconductor contact structure and the conductive structure, which can further reduce the size of the semiconductor device. Moreover, the Schottky barrier generated at the contact interface between the two-dimensional semiconductor material of the first contact layer and the second contact layer including group VA semimetal elements is small, and the contact resistance of the metal-semiconductor contact structure is small, resulting in a higher carrier mobility flowing from the capacitive contact structure to the conductive structure.

[0159] In an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure is provided, as Figure 4 shown, Figure 4 FIG. shows a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0160] As Figure 4 shown, a method for fabricating a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0161] Step S410: Provide an initial structure.

[0162] As Figure 5 shown, the initial structure 100 includes a substrate 110 and a plurality of bit line structures 120 disposed on the substrate 110. An initial trench 130 is formed between adjacent bit line structures 120. The substrate 110 includes an active region structure 111, and the initial trench 130 exposes part of the active region structure 111.

[0163] Step S420: Form a capacitive contact structure. The capacitive contact structure covers the exposed part of the active region structure, and the capacitive contact structure includes a first groove.

[0164] Step S430: Form a first contact layer. The first contact layer covers the top surface of the capacitive contact structure, and the material of the first contact layer includes molybdenum disulfide.

[0165] As Figure 16 shown, the first contact layer 221 can be formed by using a low-pressure metal-organic chemical vapor deposition process (Metal-organic Chemical Vapor Deposition, MOCVD). In this embodiment, molybdenum hexacarbonyl (Mo(CO) 6 ) and diethyl sulfide (C 4 H 10S) can also be used as the precursor of molybdenum (Mo) and sulfur (S) respectively. Molybdenum pentachloride (MoCl 5 ) and hexamethyldisilathiane (HMDST) can be used as the precursor of molybdenum (Mo) and sulfur (S) respectively. Using argon (Ar) as the carrier gas, the precursors of molybdenum (Mo) and sulfur (S) are supplied to the semiconductor structure in the form of vapor respectively. The precursors of molybdenum (Mo) and sulfur (S) react to form molybdenum disulfide (Molybdenum disulfide, MoS 2 ). Molybdenum disulfide is deposited on the top surface of the capacitive contact structure 210 to form the first contact layer 221.

[0166] The planar carrier mobility of molybdenum disulfide (Molybdenum disulfide, MoS 2 ) is between 200 and 500 cm 2 V -1 s -1 . Its band gap is 1.3 eV. It is an indirect bandgap semiconductor material. In this embodiment, the molybdenum disulfide deposited on the capacitive contact structure 210 is monolayer molybdenum disulfide. The band gap of monolayer molybdenum disulfide is 1.8 eV. It is a semiconductor material that changes from an indirect bandgap to a direct bandgap.

[0167] Step S440: Form the second contact layer. The second contact layer fills the first groove and covers the exposed part of the sidewall of the initial trench. The material of the second contact layer includes bismuth element. The first contact layer and the second contact layer form a Schottky contact structure.

[0168] As Figure 17 、 Figure 18 shown, the second contact layer 222 can be formed by heating and evaporating bismuth (Bi) or bismuth compound through an electron beam evaporation process. In this embodiment, the deposition rate is The second contact layer 222 covers the top surface of the first contact layer 221, fills the first groove 215 and the exposed part of the sidewall of the initial trench 130.

[0169] Bismuth (Bi) is the metal with the highest diamagnetism, having a high Hall coefficient and resistivity. When the thickness of bismuth is reduced to the nanometer scale, the band structure of bismuth changes. The spin orientation of one of the sub-band structures of the band structure of bismuth has metallicity, and the other sub-band structure has semiconductivity. That is, bismuth at the nanometer scale has half-metallicity. Similarly, bismuth compounds also have the above characteristics. For example, bismuth selenide (Bi 2 Se 3 ), bismuth telluride (Bismuth(III)telluride, Bi 2 Te3 )。

[0170] As Figure 19 shown, the second contact layer 222 and the first contact layer 221 form a metal-semiconductor contact structure 220. At the contact interface between the second contact layer 222 and the first contact layer 221, the Fermi level of bismuth is higher than the minimum value of the conduction band of molybdenum disulfide. The pz orbital of bismuth resonates with the pz and dz2 orbitals of molybdenum disulfide. The distribution of the induced electric dipole at the contact interface between bismuth and molybdenum disulfide falls into the van der Waals gap. The metal-induced gap states of molybdenum disulfide are saturated with electrons, resulting in the saturation of the gap states of molybdenum disulfide. A zero Schottky barrier is achieved at the contact interface between bismuth and molybdenum disulfide, and an ohmic contact is formed at the contact interface between bismuth and molybdenum disulfide, reducing the contact resistance between the second contact layer 222 and the first contact layer 221.

[0171] Step S450: Form a blocking structure that covers the exposed sidewalls of the metal-semiconductor contact structure and the initial trench.

[0172] Step S460: Form a conductive structure that covers the blocking structure and fills the unfilled initial trench. The conductive structure is connected through the metal-semiconductor contact structure and the capacitive contact structure.

[0173] The implementation manners of steps S410 - S420 in this embodiment are the same as those of steps S310 - S320 in the above embodiment, and the implementation manners of steps S450 - S460 are the same as those of steps S350 - S360 in the above embodiment, and will not be elaborated here.

[0174] In this embodiment, a metal-semiconductor contact structure formed by a semimetal bismuth and a semiconductor molybdenum disulfide is used as an intermediate transition structure for the contact between the capacitive contact structure and the conductive structure, avoiding direct contact between the semiconductor material of the capacitive contact structure and the metal material of the conductive structure. A zero Schottky barrier is achieved at the contact interface between bismuth and molybdenum disulfide, and carriers do not need to cross a barrier when migrating between the first contact layer and the second contact layer. Thus, a good ohmic contact is formed at the contact interface between bismuth and molybdenum disulfide, and the contact resistance of the metal-semiconductor contact structure reaches the minimum.

[0175] A semiconductor structure provided by an exemplary embodiment of the present disclosure, as Figure 15 shown, referring to Figure 5, including a substrate 110 and a plurality of bit line structures 120 disposed on the substrate 110. The semiconductor structure further includes a capacitive contact structure 210, the capacitive contact structure 210 includes a first groove 215, and the capacitive contact structure 210 is formed between adjacent bit line structures 120. The semiconductor structure further includes a Schottky contact structure 220, the Schottky contact structure 220 at least covers the top surface of the capacitive contact structure 210 and fills the first groove 215 of the Schottky contact structure 220. The semiconductor structure further includes a barrier structure 230 and a conductive structure 240, the barrier structure 230 covers a part of the side walls of the Schottky contact structure 220 and the bit line structure 120, the conductive structure 240 covers the barrier structure 230, and the conductive structure 240 is connected through the Schottky contact structure 220 and the capacitive contact structure 210. In this embodiment, the material of the conductive structure 240 includes tungsten metal.

[0176] Among them, the material of the capacitive contact structure 210 is a doped semiconductor. Exemplarily, the material of the capacitive contact structure is n-type or p-type conductive doped polysilicon.

[0177] The material of the barrier structure 230 includes one or more of titanium nitride, aluminum nitride, boron nitride, hafnium nitride, tantalum nitride, titanium nitride or zirconium nitride. In this embodiment, the material of the barrier structure is titanium nitride. The function of the barrier structure 230 is to prevent the material of the conductive structure 240 from penetrating into the substrate 110 and causing contamination of the substrate 110, so as to ensure the yield and service life of the semiconductor structure.

[0178] The Schottky contact structure 220 formed in this embodiment includes a two-dimensional semiconductor material (two-dimensional semimetal) and a material with half-metal (half metal) characteristics. The energy band structure of the material with half-metal characteristics includes two different sub-energy band structures, one of which has a metallic spin orientation and the other has semiconductor properties. The Schottky barrier generated by the contact between the two-dimensional semiconductor material (two-dimensional semimetal) and the material with half-metal (half metal) characteristics in the Schottky contact structure 220 is smaller than the Schottky barrier generated by the direct contact between the capacitive contact structure 210 and the subsequent formed conductive structure 240.

[0179] The semiconductor structure of this embodiment, as Figure 15 shown, a Schottky contact structure 220 is disposed between the capacitive contact structure 210 and the conductive structure 240. The Schottky contact structure 220 serves as an intermediate transition structure for connecting the capacitive contact structure 210 and the conductive structure 240, reducing the Schottky barrier generated by the contact between the capacitive contact structure 210 and the conductive structure 240, and can further reduce the size of the semiconductor structure, improving the potential for further miniaturization development of the semiconductor structure.

[0180] According to an exemplary embodiment, most of the content of the semiconductor structure in this embodiment is the same as that in the above embodiment. The difference between this embodiment and the above embodiment is that, as Figure 13 shown, the metal-semiconductor contact structure 220 includes: a first contact layer 221 that fills the first groove 215 and covers a partial sidewall of the bit line structure 120, and a second contact layer 222 that covers the first contact layer 221 and a partial sidewall of the bit line structure 120.

[0181] In this embodiment, the first contact layer 221 fills the first groove 215, increasing the contact area between the first contact layer 221 and the first groove 215. The second contact layer 222 covers the top surface of the first contact layer 221 and a partial sidewall of the bit line structure 120, increasing the contact area between the second contact layer 222 and the conductive structure 240, further improving the mobility of carriers from the capacitive contact structure 210 to the conductive structure 240, and increasing the on-state current density between the capacitive contact structure 210 and the conductive structure 240.

[0182] According to an exemplary embodiment, most of the content of the semiconductor structure in this embodiment is the same as that in the above embodiment. The difference between this embodiment and the above embodiment is that, as Figure 19 shown, the metal-semiconductor contact structure 220 includes: a first contact layer 221 that covers the top surface of the capacitive contact structure 210, and a second contact layer 222 that fills the first groove 215 and covers a partial sidewall of the bit line structure 120.

[0183] In this embodiment, the first contact layer 221 covers the top surface of the capacitive contact structure 210, that is, the first contact layer 221 has a concave structure with the bottom facing downwards, increasing the contact area between the first contact layer 221 and the second contact layer 222, and reducing the contact resistance of the metal-semiconductor contact structure 220. At the same time, the second contact layer 222 covers a partial sidewall of the bit line structure 120, increasing the contact area between the second contact layer 222 and the conductive structure 240, and reducing the contact resistance between the metal-semiconductor contact structure 220 and the conductive structure 240, which can further reduce the size of the semiconductor structure.

[0184] According to an exemplary embodiment, most of the content of the semiconductor structure in this embodiment is the same as that in the above embodiment. The difference between this embodiment and the above embodiment is that the material of the first contact layer 221 includes a single-layer semiconductor material, and the material of the second contact layer 222 includes a Group VA element.

[0185] In this embodiment, the monolayer semiconductor material included in the first contact material is a two-dimensional transition metal dichalcogenide (TMDs). Exemplarily, the first contact material may include at least one of molybdenum disulfide (MoS 2 ), tungsten disulfide (WS 2 ), rhenium disulfide (ReS 2 ), titanium diselenide (TiSe 2 ), niobium diselenide (NbSe 2 ), rhenium diselenide (ReSe 2 ).

[0186] The second contact material may include at least one of the Group VA semimetal elements arsenic (As), antimony (Sb), and bismuth (Bi) in the fourth to sixth periods of the periodic table of chemical elements.

[0187] In this embodiment, the first contact layer 221 and the second contact layer 222 of the metal-semiconductor contact structure 220 form a metal-semiconductor contact interface. The Fermi level of the Group VA semimetal element in the second contact layer 222 is close to the minimum value of the semiconductor conduction band of the two-dimensional transition metal dichalcogenide in the first contact layer 221. The valence band of the two-dimensional transition metal dichalcogenide is saturated (the gap state is saturated), and the metal-induced gap state generated by the Group VA semimetal element in the two-dimensional transition metal dichalcogenide is suppressed. Then, the Schottky barrier generated at the contact interface between the first contact layer 221 and the second contact layer 222 is close to zero, and the influence of the Schottky barrier on the contact resistance of the metal-semiconductor contact structure 220 can be ignored. The first contact layer 221 and the second contact layer 222 form a good ohmic contact. The metal-semiconductor contact structure 220 in this embodiment reduces the contact resistance between the capacitive contact structure 210 and the conductive structure 240. The carrier mobility between the capacitive contact structure 210 and the conductive structure 240 is greater, and the on-state current density is higher, which can further reduce the size of the semiconductor structure and improve the potential of the semiconductor structure to develop towards high performance and high miniaturization.

[0188] According to an exemplary embodiment, most of the content of the semiconductor structure in this embodiment is the same as that in the above embodiment. The difference between this embodiment and the above embodiment is that, as Figure 15 shown, referring to Figure 5 , the substrate 110 includes an active region structure 111 and a shallow trench isolation structure 112. The top surface of the active region structure 111 is flush with the top surface of the shallow trench isolation structure 112, and a part of the active region structure 111 and the shallow trench isolation structure 112 are exposed between adjacent bit line structures 120.

[0189] According to an exemplary embodiment, most of the content of the semiconductor structure in this embodiment is the same as that in the above embodiment. The difference between this embodiment and the above embodiment is that, as Figure 15 shown, referring to Figure 5 , the semiconductor structure further includes: a capacitor contact hole 140, the capacitor contact hole 140 is disposed on the substrate 110, the capacitor contact hole 140 is located between adjacent bit line structures 120, and the capacitor contact hole 140 exposes a part of the active region structure 111 and a part of the shallow trench isolation structure 112; a capacitor contact structure 210 fills the capacitor contact hole 140.

[0190] In this embodiment, a capacitor contact 111 is disposed on the substrate 110 to increase the contact area between the capacitor contact structure 210 and the active region structure 111, and further reduce the contact resistance of the semiconductor structure.

[0191] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0192] In the description of this specification, the description with reference to terms such as "embodiment", "exemplary embodiment", "some implementation manners", "schematic implementation manners", "example", etc. means that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure.

[0193] In this specification, the schematic expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0194] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present disclosure.

[0195] It can be understood that the terms "first", "second", etc. used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

[0196] In one or more of the accompanying drawings, like elements are represented by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structures obtained after several steps may be described in one drawing. Many specific details of the present disclosure are described below, such as the structure, materials, dimensions, processing techniques and technologies of the device, in order to understand the present disclosure more clearly. However, as those skilled in the art can understand, the present disclosure may be implemented without these specific details.

[0197] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the structural technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, the method for fabricating the semiconductor structure includes: providing an initial structure, the initial structure including a substrate and a plurality of bit line structures disposed on the substrate, an initial trench being formed between adjacent bit line structures, the substrate including an active region structure, and the initial trench exposing a part of the active region structure; forming a capacitive contact structure, the capacitive contact structure covering the exposed part of the active region structure, the capacitive contact structure including a first groove; forming a Schottky contact structure, the Schottky contact structure at least covering the top surface of the capacitive contact structure and filling the first groove; forming a barrier structure, the barrier structure covering the Schottky contact structure and the exposed sidewalls of the initial trench; forming a conductive structure, the conductive structure covering the barrier structure and filling the unfilled initial trench, the conductive structure being connected through the Schottky contact structure and the capacitive contact structure.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming of the Schottky contact structure includes: forming a first contact layer, the first contact layer filling the first groove and a part of the initial trench; forming a second contact layer, the second contact layer covering the top surface of the first contact layer and the exposed part of the sidewall of the initial trench.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming of the Schottky contact structure includes: forming a first contact layer, the first contact layer covering the top surface of the capacitive contact structure; forming a second contact layer, the second contact layer filling the first groove and covering the exposed part of the sidewall of the initial trench.

4. The method for fabricating a semiconductor structure according to claim 2 or 3, characterized in that, the forming of the first contact layer includes: depositing a first contact material to form the first contact layer, the first contact material including a single-layer semiconductor material.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, the forming of the second contact layer includes: depositing a second contact material to form the second contact layer, the second contact material including a Group VA semimetal element.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming of the capacitive contact structure includes: forming an initial capacitive contact structure, the initial capacitive contact structure filling the initial trench; etching back the initial capacitive contact structure, and the remaining initial capacitive contact structure forms the capacitive contact structure; etching the capacitive contact structure to form the first groove on the top surface of the capacitive contact structure.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the providing of the initial structure includes: providing a substrate; etching the substrate to form a plurality of active region structures arranged in an array; forming a shallow trench isolation structure for isolating each of the active region structures; forming a bit line contact hole, the bit line contact hole exposing a part of the active region structure and a part of the shallow trench isolation structure; Form a bit line contact portion to fill the bit line contact hole; Form a bit line structure disposed on the top surfaces of the active region structure and the shallow trench isolation structure. The bit line structure is connected to the bit line contact portion. A plurality of the bit line structures are parallel to each other, and an initial trench is formed between adjacent bit line structures, and the initial trench exposes a part of the top surface of the active region structure.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, after forming the bit line structure, further comprising: forming a spacer structure in the initial trench, the extending direction of the spacer structure being perpendicular to the extending direction of the bit line structure; using the spacer structure and the bit line structure as masks to remove the part of the active region structure and the shallow trench isolation structure exposed by the initial trench to form a capacitor contact hole.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, forming the capacitor contact structure includes: forming a capacitor contact structure to fill the capacitor contact hole and a part of the initial trench.

10. A semiconductor structure, wherein, comprising: a substrate and a plurality of bit line structures disposed on the substrate; a capacitor contact structure formed between the bit line structures, the capacitor contact structure including a first groove; a metal-semiconductor contact structure covering at least the top surface of the capacitor contact structure and filling the first groove; a barrier structure covering the metal-semiconductor contact structure and a part of the sidewalls of the bit line structures; a conductive structure covering the barrier structure, and the conductive structure is connected through the metal-semiconductor contact structure and the capacitor contact structure.

11. The semiconductor structure according to claim 10, wherein, the metal-semiconductor contact structure includes: a first contact layer filling the first groove and covering a part of the sidewalls of the bit line structures; a second contact layer covering the first contact layer and a part of the sidewalls of the bit line structures.

12. The semiconductor structure according to claim 10, wherein, the metal-semiconductor contact structure includes: a first contact layer covering the top surface of the capacitor contact structure; a second contact layer filling the first groove and covering a part of the sidewalls of the bit line structures.

13. The semiconductor structure according to claim 11 or 12, wherein, the material of the first contact layer includes a single-layer semiconductor material, and the material of the second contact layer includes a Group VA element.

14. The semiconductor structure according to claim 10, wherein, the substrate includes an active region structure and a shallow trench isolation structure, the top surfaces of the active region structure and the shallow trench isolation structure are flush, and a part of the active region structure and the shallow trench isolation structure are exposed between adjacent bit line structures.

15. The semiconductor structure according to claim 14, wherein, the semiconductor structure further includes: A capacitor contact hole is provided on the substrate. The capacitor contact hole is located between adjacent bit line structures, and the capacitor contact hole exposes part of the active region structure and the shallow trench isolation structure. The capacitor contact structure fills the capacitor contact hole.

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