Semiconductor structure and manufacturing method

Abstract

This application relates to the semiconductor field, providing a semiconductor structure and its manufacturing method. The semiconductor structure includes: a substrate; a storage capacitor cell located in an array region comprising: N insulating pillars distributed in a direction parallel to the substrate surface; a lower electrode layer covering the top and side surfaces of the insulating pillars; an upper electrode layer directly opposite the lower electrode layer; and a capacitor dielectric layer located between the upper and lower electrode layers; wherein either the lower electrode layer corresponding to the N insulating pillars or the upper electrode layer corresponding to the N insulating pillars is a continuous film layer, and the other is a discrete film layer, where N is a natural number greater than or equal to 2; a transistor located in a circuit region, and the transistor includes a capacitor control terminal located within the substrate in the circuit region; and an electrical connection structure electrically connected to the capacitor control terminal and extending from the circuit region to the array region to contact the corresponding discrete film layer. This application embodiment can at least reduce the process difficulty of fabricating the semiconductor structure and improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] Memory is a storage component used to store programs and various data. Based on its usage type, memory can be divided into read-only memory (ROM) and random access memory (RAM). Memory typically includes storage capacitor cells and transistors connected to these cells. Storage capacitor cells store electrical charges representing the stored information, while transistors act as switches controlling the inflow and release of charge within the cells. Currently, storage capacitor cells are typically in cup-shaped or columnar stacked structures.

[0003] However, as memory process nodes continue to shrink, the aspect ratio of the capacitor holes used to form memory capacitor cells gradually increases, raising the difficulty of fabricating semiconductor structures containing memory capacitor cells. Furthermore, controlling the dimensional accuracy of the capacitor holes during etching is challenging, and incomplete filling can easily occur when filling the capacitor holes in the memory to form memory capacitor cells, affecting the electrical performance of the semiconductor structure.

[0004] Therefore, a new storage capacitor cell structure is needed to reduce the difficulty of fabricating semiconductor structures and improve their electrical performance. Summary of the Invention

[0005] This application provides a semiconductor structure and its manufacturing method, which at least helps to reduce the difficulty of preparing the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0006] According to some embodiments of this application, one aspect of this application provides a semiconductor structure having an array region and a circuit region, comprising: a substrate; at least one storage capacitor cell located in the array region, the storage capacitor cell comprising: N insulating pillars distributed in a direction parallel to the surface of the substrate; a lower electrode layer covering the top and side surfaces of the insulating pillars; an upper electrode layer facing the lower electrode layer; a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer; wherein, one of the lower electrode layer corresponding to the N insulating pillars or the upper electrode layer corresponding to the N insulating pillars is a continuous film layer, and the other is a discrete film layer, N is a natural number greater than or equal to 2, transistors are located in the circuit region, and the transistors include a capacitor control terminal located within the substrate in the circuit region; an electrical connection structure electrically connected to the capacitor control terminal, and the electrical connection structure extending from the circuit region to the array region to contact the corresponding discrete film layer.

[0007] In addition, the semiconductor structure further includes: a dielectric layer located on the substrate of the circuit region; the electrical connection structure includes: a conductive pillar penetrating the dielectric layer and electrically connected to the capacitor control terminal; and an electrical connection layer located on the top surface of the dielectric layer and in contact with the top surface of the conductive pillar, and the electrical connection layer extending from the circuit region to the array region to contact the corresponding discrete film layer.

[0008] In addition, the material of the electrical connection layer is the same as the material of the discrete film layer.

[0009] In addition, the capacitor dielectric layer corresponding to the N insulating pillars is a continuous film layer, and the capacitor dielectric layer is also located on the top surface of the dielectric layer and the top surface of the electrical connection layer.

[0010] In addition, the number of transistors is N, and the number of electrical connection structures is m times N, where m is a natural number greater than or equal to 1.

[0011] In addition, the material of the lower electrode layer includes at least one of TiN, Ti, W or Mo; the material of the upper electrode layer includes at least one of TiN, Ti, W or Mo.

[0012] In addition, the material of the capacitor dielectric layer includes at least one of ZrO, AlO, HfO, or NbO.

[0013] In addition, the thickness of the insulating pillar is 1 nm to 100 nm in the direction perpendicular to the surface of the substrate.

[0014] In addition, the width of the insulating pillar is 1 nm to 100 nm in the direction parallel to the surface of the substrate.

[0015] In addition, the lower electrode layer corresponding to the N insulating pillars is a discrete film layer, and the upper electrode layer corresponding to the N insulating pillars is a continuous film layer.

[0016] Additionally, the semiconductor structure includes M storage capacitor cells stacked in a direction perpendicular to the surface of the substrate, where M is a natural number greater than or equal to 2; it also includes: an insulating layer located between storage capacitor cells in adjacent layers; and conductive vias penetrating the insulating layer and the continuous film layer of each storage capacitor cell, such that the conductive vias are in contact with the continuous film layer of each storage capacitor cell.

[0017] In addition, the semiconductor structure includes M electrical connection structures stacked in a direction perpendicular to the surface of the substrate, and the electrical connection structures in adjacent layers are in contact with each other.

[0018] In addition, the semiconductor structure also includes: a word line, which is located in the substrate of the array region, and the substrate on both sides of the word line has a first doped region and a second doped region, respectively, and the first doped region is electrically connected to the lower electrode layer; and a bit line, which is located in the array region and is electrically connected to the second doped region.

[0019] According to some embodiments of this application, another aspect of this application provides a method for manufacturing a semiconductor structure, the semiconductor structure having an array region and a circuit region. The manufacturing method includes: providing a substrate; forming at least one storage capacitor cell on the substrate, the storage capacitor cell being located in the array region, the storage capacitor cell comprising: N insulating pillars distributed in a direction parallel to the surface of the substrate; a lower electrode layer covering the top and side surfaces of the insulating pillars; an upper electrode layer facing the lower electrode layer; and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer; wherein, one of the lower electrode layer corresponding to the N insulating pillars or the upper electrode layer corresponding to the N insulating pillars is a continuous film layer, and the other is a discrete film layer, N being a natural number greater than or equal to 2; forming a transistor in the circuit region, the transistor including a capacitor control terminal located within the substrate in the circuit region; forming an electrical connection structure electrically connected to the capacitor control terminal, the electrical connection structure extending from the circuit region to the array region to contact the corresponding discrete film layer.

[0020] Additionally, the substrate of the circuit region has a dielectric layer; the steps of forming the lower electrode layer and the electrical connection structure include: forming a conductive pillar that penetrates the dielectric layer and is electrically connected to the capacitor control terminal; forming a continuous first conductive layer located on the top and side surfaces of the insulating pillar, and also located on the top surface of the dielectric layer in the circuit region and in contact with the top surface of the conductive pillar; patterning the first conductive layer to form an electrical connection layer and a plurality of mutually discrete lower electrode layers, the electrical connection layer being located on the top surface of the dielectric layer and in contact with the top surface of the conductive pillar, and the electrical connection layer extending from the circuit region to the array region to be electrically connected to the corresponding lower electrode layer.

[0021] In addition, the process steps for forming the capacitor dielectric layer and the upper electrode layer include: forming a continuous capacitor dielectric layer on the surface of the lower electrode layer, the capacitor dielectric layer being located between adjacent insulating pillars and also located on the top surface of the electrical connection layer and the top surface of the dielectric layer; forming a second conductive layer on the top surface of the capacitor dielectric layer; removing the second conductive layer located in the circuit area, and leaving the second conductive layer as the upper electrode layer.

[0022] In addition, the manufacturing method further includes: forming M storage capacitor cells stacked in a direction perpendicular to the surface of the substrate, where M is a natural number greater than or equal to 2, and the storage capacitor cells in adjacent layers have an insulating layer; forming a conductive via that penetrates the insulating layer and the continuous film layer of each storage capacitor cell, so that the conductive via is in contact with the continuous film layer of each storage capacitor cell.

[0023] The technical solution provided in this application has at least the following advantages:

[0024] In the above technical solution, the lower electrode layer at least covers the top and side surfaces of the insulating pillars, and one of the lower electrode layers corresponding to the N insulating pillars or the upper electrode layers corresponding to the N insulating pillars is a continuous film layer, while the other is a discrete film layer. This makes the upper and lower electrode layers in the storage capacitor cell appear as a wave or mountain peak shape. On the one hand, from the perspective of fabrication process, forming a storage capacitor cell with such a shape avoids the need to create capacitor holes for forming the storage capacitor cell, thus reducing the process difficulty of fabricating the storage capacitor cell and the process difficulty of fabricating the semiconductor structure. On the other hand, as the aspect ratio of the capacitor hole increases with the shrinking of the memory process node, the quality of the formed storage capacitor cell is not high, which will adversely affect the electrical performance of the semiconductor structure. Using the storage capacitor cell of this application, there is no need to create capacitor holes, which helps to ensure that the formed storage capacitor cell has a high quality. Moreover, the fact that the upper and lower electrode layers appear as a wave or mountain peak shape helps to increase the facing area between the upper and lower electrode layers, thereby increasing the capacitance of the storage capacitor cell and thus improving the electrical performance of the semiconductor structure. Attached Figure Description

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0026] Figures 1 to 10 This is a cross-sectional structural diagram of each step in the manufacturing method of the semiconductor structure provided in the embodiments of this application. Detailed Implementation

[0027] As can be seen from the background technology, the fabrication process of semiconductor structures needs to be simplified, and the electrical properties of semiconductor structures need to be improved.

[0028] This application provides a semiconductor structure and its manufacturing method. In the semiconductor structure, the upper and lower electrode layers of the storage capacitor cell are generally wavy or mountain-shaped. On the one hand, from the perspective of fabrication process, forming a storage capacitor cell with such a shape avoids the need to create capacitor holes for forming the storage capacitor cell, thus reducing the process difficulty of fabricating the storage capacitor cell. On the other hand, as the aspect ratio of the capacitor hole increases with the shrinking of memory process nodes, the dimensional accuracy of the formed capacitor hole and the quality of the storage capacitor cell formed based on the capacitor hole are not high, which will adversely affect the electrical performance of the semiconductor structure. Using the storage capacitor cell of this application, there is no need to create capacitor holes, which helps to improve the quality of the formed storage capacitor cell. Moreover, the fact that the upper and lower electrode layers are generally wavy or mountain-shaped helps to increase the facing area between the upper and lower electrode layers, thereby increasing the capacitance of the storage capacitor cell and thus improving the electrical performance of the semiconductor structure.

[0029] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0030] Figure 1 and Figure 2 This is a cross-sectional view of a semiconductor structure provided in an embodiment of this application. It should be noted that... Figure 2 The ellipsis with three dots indicates that the semiconductor structure includes multiple layers of stacked storage capacitors and multiple layers of stacked transistors and electrical connection structures.

[0031] refer to Figure 1 or Figure 2The semiconductor structure has an array region a and a circuit region b. The semiconductor structure includes: a substrate 100; at least one storage capacitor cell 101 located in the array region a, the storage capacitor cell 101 including: N insulating pillars 111 distributed in a direction parallel to the surface of the substrate 100; a lower electrode layer 121 covering the top and side surfaces of the insulating pillars 111; an upper electrode layer 131 facing the lower electrode layer 121; and a capacitor dielectric layer 141 located between the upper electrode layer 131 and the lower electrode layer 121. Between; wherein, one of the lower electrode layer 121 corresponding to N insulating pillars 111 or the upper electrode layer 131 corresponding to N insulating pillars 111 is a continuous film layer and the other is a discrete film layer, where N is a natural number greater than or equal to 2; transistor 102, transistor 102 is located in circuit region b, and transistor 102 includes a capacitor control terminal 112 located in substrate 100 in circuit region b; electrical connection structure 103, electrical connection structure 103 is electrically connected to capacitor control terminal 112, and electrical connection structure 103 extends from circuit region b to array region a to contact the corresponding discrete film layer.

[0032] Compared to the columnar vertical stacked storage capacitor cell where the area between the lower electrode layer and the upper electrode layer is planar, in this application, the lower electrode layer 121 at least covers the top and side surfaces of the insulating pillar 111, and the upper electrode layer 131 is directly opposite the lower electrode layer 121. Therefore, the area between the lower electrode layer 121 and the upper electrode layer 131 at least includes the area corresponding to the top and side surfaces of the insulating pillar 111. This is beneficial for increasing the area between the lower electrode layer 121 and the upper electrode layer 131, thereby increasing the capacitance of the storage capacitor cell and thus improving the electrical performance of the semiconductor structure.

[0033] Compared to cup-shaped storage capacitor cells, which require the formation of capacitor holes with a large aspect ratio, and the formation of lower and upper electrode layers based on the capacitor holes, the present application reduces the process difficulty of forming the insulating pillar 111 and the lower electrode layer 121 and upper electrode layer 131 based on the insulating pillar 111. It is also easier to control the dimensional accuracy of the formed lower electrode layer 121 and upper electrode layer 131, thereby helping to reduce the process difficulty of preparing semiconductor structures and improve the electrical performance of semiconductor structures.

[0034] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0035] In this circuit region b, the outer periphery of the array region a is located. The capacitor control terminal 112 in the transistor 102 is electrically connected to the discrete film layer in the storage capacitor unit 101 through the electrical connection structure 103, and is used to control the potential of the discrete film layer.

[0036] In some embodiments, the thickness of the insulating pillar 111 in the direction perpendicular to the surface of the substrate 100 can be 1 nm to 100 nm, and the width of the insulating pillar 111 in the direction parallel to the surface of the substrate 100 can be 1 nm to 100 nm. When the thickness and width of the insulating pillar 111 are within this range, it is beneficial to promote the refinement of the semiconductor structure. That is, while ensuring a large facing area between the lower electrode layer 121 and the upper electrode layer 131, it ensures that the space occupied by a single storage capacitor cell 101 in the semiconductor structure is of an appropriate size, avoiding an excessively large overall size of the semiconductor structure due to the storage capacitor cell 101. For example, the thickness of the insulating pillar 111 can be 50 nm, and the width of the insulating pillar 111 can be 50 nm.

[0037] In some embodiments, the lower electrode layer 121 corresponding to the N insulating pillars 111 is a discrete film layer, and the upper electrode layer 131 corresponding to the N insulating pillars 111 is a continuous film layer.

[0038] It should be noted that, Figure 1 and Figure 2 In this example, only the lower electrode layer 121 is a discrete film layer, and the upper electrode layer 131 is a continuous film layer. In other embodiments, the lower electrode layer corresponding to the N insulating pillars can also be a continuous film layer, and the upper electrode layer corresponding to the N insulating pillars can also be a discrete film layer. Furthermore, Figure 1 and Figure 2 The example uses N=3, but in practical applications, N can be any natural number greater than or equal to 1.

[0039] The lower electrode layer 121 is made of at least one of TiN, Ti, W, or Mo; the upper electrode layer 131 is made of at least one of TiN, Ti, W, or Mo. In some embodiments, the materials of the lower electrode layer 121 and the upper electrode layer 131 can be the same, which simplifies the fabrication process of the storage capacitor cell 101 and reduces its fabrication cost. In other embodiments, the materials of the lower electrode layer and the upper electrode layer can be different.

[0040] In addition, the material of the capacitor dielectric layer 141 includes at least one of ZrO, AlO, HfO or NbO, which is used to ensure that the capacitor dielectric layer 141 has a high dielectric constant, so as to improve the capacitance of the storage capacitor cell 101.

[0041] Continue to refer Figure 1 or Figure 2The semiconductor structure may further include: a dielectric layer 104 located on a substrate 100 of circuit region b; an electrical connection structure 103 including: a conductive pillar 113 penetrating the dielectric layer 104 and electrically connected to a capacitor control terminal 112; and an electrical connection layer 123 located on the top surface of the dielectric layer 104 and in contact with the top surface of the conductive pillar 113, and the electrical connection layer 123 extending from circuit region b to array region a to contact the corresponding discrete film layers.

[0042] In addition, transistor 102 also includes gate 122, which in some embodiments is located on the surface of substrate 100 and in dielectric layer 104, spaced apart from conductive pillar 113.

[0043] It should be noted that, Figure 1 and Figure 2 The example only shows the approximate range of the capacitor control terminal 112 in the substrate 100 with a dashed box. In actual applications, there are no restrictions on the shape of the range of the capacitor control terminal 112 in the substrate 100, as long as the capacitor control terminal 112 is located on one side of the substrate 100 directly below the gate 122.

[0044] In some embodiments, when the lower electrode layer 121 is a discrete film layer, the electrical connection layer 123 is in contact with and electrically connected to the lower electrode layer 121, and the material of the electrical connection layer 123 may be the same as the material of the lower electrode layer 121. In other embodiments, when the upper electrode layer is a discrete film layer, the electrical connection layer is in contact with and electrically connected to the upper electrode layer, and the material of the electrical connection layer may be the same as the material of the upper electrode layer; or, when the lower electrode layer is a discrete film layer, the electrical connection layer is in contact with and electrically connected to the lower electrode layer, and the material of the electrical connection layer may be different from the material of the lower electrode layer; or, when the upper electrode layer is a discrete film layer, the electrical connection layer is in contact with and electrically connected to the upper electrode layer, and the material of the electrical connection layer may be different from the material of the upper electrode layer.

[0045] In the above embodiments, the material of the electrical connection layer 123 is the same as the material of the discrete film layers. Therefore, the material of the electrical connection layer 123 and the discrete film layers can be integrally formed, which helps to simplify the semiconductor structure fabrication process and reduce the semiconductor structure fabrication cost. In other embodiments, the material of the electrical connection layer and the material of the discrete film layers may also be different.

[0046] In some embodiments, the capacitor dielectric layer 141 corresponding to the N insulating pillars 111 is a continuous film layer, and the capacitor dielectric layer 141 is also located on the top surface of the dielectric layer 104 and the top surface of the electrical connection layer 123. That is, the capacitor dielectric layer 141 is located not only in the array region a, but also in the circuit region b. The capacitor dielectric layer 141 located in the circuit region b is used to achieve insulation between the electrical connection layer and other unrelated conductive structures.

[0047] Regarding the number of storage capacitor cells 101, the following will refer to... Figures 1 to 2 A detailed explanation will be provided.

[0048] In some embodiments, reference Figure 1 The number of storage capacitor cells 101 is one. The semiconductor structure also includes an insulating layer 151 located on the top surface of the upper electrode layer 131 and the capacitor dielectric layer 141, and a conductive via 105 that penetrates at least through the insulating layer 151 and is in contact with and electrically connected to the upper electrode layer 131, which is a continuous film layer. The insulating layer 151 can be a continuous film layer, used to make the top surface of the semiconductor structure of the array region a flush with the top surface of the semiconductor structure of the circuit region b, and to prevent the upper electrode layer 131 from being exposed. The conductive via 105 is used to control the potential of the upper electrode layer 131, which is a continuous film layer.

[0049] in, Figure 1 Taking the example of a conductive via 105 passing through a portion of the thickness of the upper electrode layer 131 to make contact and electrical connection with the upper electrode layer 131, in practical applications, the conductive via can penetrate the upper electrode layer to make contact and electrical connection with the upper electrode layer, or the conductive via can only penetrate the insulating layer to make contact and electrical connection with the top surface of the upper electrode layer.

[0050] In other embodiments, reference is made to... Figure 2 The semiconductor structure includes M storage capacitor cells 101 stacked in a direction perpendicular to the surface of the substrate 100, where M is a natural number greater than or equal to 2. The semiconductor structure also includes: an insulating layer 151 located between adjacent storage capacitor cells 101; and conductive vias 105 penetrating the insulating layer 151 and a continuous film layer of each storage capacitor cell 101, such that the conductive vias 105 are in contact with the continuous film layer of each storage capacitor cell 101.

[0051] Furthermore, the conductive via 105 also penetrates the capacitor dielectric layer 141 in other storage capacitor cells 101 besides the storage capacitor cell 101 that contacts the substrate 100, thereby controlling the potential of the upper electrode layer 131, which is a continuous film layer.

[0052] The insulating layer 151 is used to achieve electrical insulation between the discrete film layers in the adjacent storage capacitor units 101; the M storage capacitor units 101 are stacked in a direction perpendicular to the surface of the substrate 100, which is beneficial to further improve the overall capacitance of the semiconductor structure.

[0053] The semiconductor structure includes M electrical connection structures 103 stacked in a direction perpendicular to the surface of the substrate 100, and the electrical connection structures 103 in adjacent layers are in contact with each other.

[0054] Specifically, for the storage capacitor cells 101 other than those in contact with the substrate 100, the conductive pillars 113 in the storage capacitor cells 101 not only penetrate the dielectric layer 104 in the storage capacitor cells 101, but also penetrate the insulating layer 151 and the capacitor dielectric layer 141 located below the storage capacitor cells 101. This allows the bottom surface of the conductive pillars 113 in the storage capacitor cells 101 to make contact and electrical connection with the top surface of the electrical connection layer in the storage capacitor cells 101 located below the storage capacitor cells 101. This enables the corresponding discrete film layers in the multilayer storage capacitor cells 101 to be controlled by the same transistor 102 through the sequentially contacting electrical connection structure 103.

[0055] It should be noted that, Figure 2 Taking the example that the orthographic projections of the insulating pillars 111 in the adjacent storage capacitor cells 101 on the substrate 100 coincide, in practical applications, the orthographic projections of the insulating pillars in the adjacent storage capacitor cells on the substrate can partially overlap or not overlap at all. That is, the arrangement of the insulating pillars in the storage capacitor cells is not limited by the arrangement of the insulating pillars in the storage capacitor cells adjacent to the storage capacitor cell. It is only necessary to ensure that when the conductive via is electrically connected to the continuous film layer in each storage capacitor cell, it does not contact the discrete film layer in each storage capacitor cell.

[0056] also, Figure 2 Only the three-layer storage capacitor unit 101 in the semiconductor structure is shown in the diagram, and Figure 2 Taking the conductive via 105 penetrating the upper electrode layer 131, which is a continuous film layer in the storage capacitor cell 101 that is in contact with the substrate 100, as an example, in practical applications, the conductive via can penetrate a portion of the thickness of the upper electrode layer in the storage capacitor cell that is in contact with the substrate to make contact and make electrical connection with the upper electrode layer. Alternatively, the conductive via can only penetrate the insulating layer in the storage capacitor cell that is in contact with the substrate to make contact and make electrical connection with the top surface of the upper electrode layer in the storage capacitor cell that is in contact with the substrate.

[0057] In the two embodiments described above, Figure 1 and Figure 2 Taking a continuous film layer as the upper electrode layer 131 and a discrete film layer as the lower electrode layer 121 as an example, a conductive via 105 penetrates the upper electrode layer 131 so that the conductive via 105 contacts the upper electrode layer 131 of each storage capacitor cell 101. A transistor 102 controls the potential of the lower electrode layer 121 through a capacitor control terminal 112 and an electrical connection structure 103. The conductive via 105 is used to control the potential of the upper electrode layer 131. In practical applications, the continuous film layer can be the lower electrode layer, and the discrete film layer can be the upper electrode layer. In this case, a conductive via penetrates the lower electrode layer so that the conductive via contacts the lower electrode layer of each storage capacitor cell. The transistor is used to control the potential of the upper electrode layer, and the conductive via is used to control the potential of the lower electrode layer.

[0058] In both embodiments described above, the number of transistors 102 can be equal to the number of insulating posts 111 in a single storage capacitor cell 101, i.e., the number of transistors 102 is N, and there is a one-to-one correspondence between transistors 102 and insulating posts 111 in a single storage capacitor cell 101. The number of electrical connection structures 103 is m times N, where m is a natural number greater than or equal to 1.

[0059] It should be noted that the number of insulating pillars 111 is equal to the number of discrete film layers, that is, there is a one-to-one correspondence between the insulating pillars 111 and the discrete film layers. The multiple electrical connection structures 103 in the same transistor 102 correspond to at least one discrete film layer in each storage capacitor cell 101.

[0060] In some embodiments, the conductive pillars 113 and the electrical connection structures 103 are in a one-to-one correspondence, and the discrete film layers between the multilayer storage capacitor units 101 are also in a one-to-one correspondence. Furthermore, the discrete film layers with corresponding relationships are in contact with and electrically connected to multiple electrical connection structures 103 in the same transistor 102. Thus, the number of transistors is equal to the number of discrete film layers in a single-layer storage capacitor unit 101.

[0061] In other embodiments, the same conductive post 113 can be electrically connected to at least two electrical connection layers 123, meaning that the same transistor 102 can control at least two discrete film layers in the same storage capacitor cell. Therefore, in practical applications, the specific connection relationship between the electrical connection structure and the discrete film layers in the storage capacitor cell is not limited and can be reasonably set according to the circuit connection requirements.

[0062] In addition, the semiconductor structure also includes: word lines (not shown), which are located in the substrate 100 of the array region a, and the substrate 100 on both sides of the word lines has a first doped region (not shown) and a second doped region (not shown), respectively, and the first doped region is electrically connected to the lower electrode layer 121; and bit lines (not shown), which are located in the array region a and are electrically connected to the second doped region.

[0063] In summary, the upper electrode layer 131 and lower electrode layer 121 in the storage capacitor cell 101 are generally wavy or mountain-shaped. On the one hand, this helps to increase the facing area between the upper electrode layer 131 and the lower electrode layer 121, thereby increasing the capacitance of the storage capacitor cell 101. Furthermore, by stacking multiple layers of storage capacitor cells 101, the overall capacitance of the semiconductor structure can be further increased, thus improving the electrical performance of the semiconductor structure. On the other hand, from a fabrication process perspective, forming such a shape of storage capacitor cell helps to reduce the difficulty of fabricating the storage capacitor cell while improving the overall dimensional accuracy of the formed storage capacitor cell 101.

[0064] Another embodiment of this application provides a method for manufacturing a semiconductor structure, used to form the aforementioned semiconductor structure. The method for manufacturing a semiconductor structure according to another embodiment of this application will be described in detail below with reference to the accompanying drawings. Details that are the same as or corresponding to those in the above embodiment will not be repeated here.

[0065] refer to Figure 3 A substrate 100 is provided, which has an array region a and a circuit region b, with the circuit region b located around the array region a.

[0066] Reference Figures 3 to 10 At least one storage capacitor cell 101 is formed on a substrate 100, located in array region a. The storage capacitor cell 101 includes: N insulating pillars 111 distributed in a direction parallel to the surface of the substrate 100; a lower electrode layer 121 covering the top and side surfaces of the insulating pillars 111; an upper electrode layer 131 facing the lower electrode layer 121; and a capacitor dielectric layer 141 located between the upper electrode layer 131 and the lower electrode layer 121. The N insulating pillars 101 are distributed in an array region a. One of the lower electrode layer 121 corresponding to pillar 111 or the upper electrode layer 131 corresponding to N insulating pillars 111 is a continuous film layer, and the other is a discrete film layer, where N is a natural number greater than or equal to 2; a transistor 102 is formed in circuit region b, and the transistor 102 includes a capacitor control terminal 112 located in the substrate 100 of circuit region b; an electrical connection structure 103 is formed, which is electrically connected to the capacitor control terminal 112, and the electrical connection structure 103 extends from circuit region b to array region a to contact the corresponding discrete film layer.

[0067] In some embodiments, forming the insulating pillar 111 includes the following process steps:

[0068] Continue to refer Figures 3 to 4 Along a direction perpendicular to the surface of the substrate 100, a first dielectric layer 116, a second dielectric layer 126, a third dielectric layer 136, and a mask 107 with openings are formed on the substrate 100.

[0069] Using mask 107 as a mask, the first dielectric layer 116, the second dielectric layer 126, and the third dielectric layer 136 are etched sequentially. Mask 107 and the remaining first and second dielectric layers 116 are removed, while the remaining third dielectric layer 136 is retained as the insulating pillar 111. In some examples, the material of mask 107 can be photoresist, the first dielectric layer 116 can be a silicon nitride layer, the second dielectric layer 126 can be a spin-coated hard mask layer, and the third dielectric layer 136 can be a silicon oxynitride layer. Thus, by using mask 107 as a mask to etch the first dielectric layer 116, the second dielectric layer 126, and the third dielectric layer 136, the opening pattern in mask 107 is sequentially passed downwards, which helps to improve the dimensional accuracy of the finally formed insulating pillar 111.

[0070] In some embodiments, the thickness of the insulating pillar 111 in the direction perpendicular to the surface of the substrate 100 can be 1 nm to 100 nm, and the width of the insulating pillar 111 in the direction parallel to the surface of the substrate 100 can be 1 nm to 100 nm. In practical applications, the thickness and width of the insulating pillar 111 can be reasonably set according to the needs of circuit connection, thereby adjusting the facing area of ​​the lower electrode layer 121 and the upper electrode layer 131.

[0071] Compared to forming capacitor holes with a large aspect ratio, the process steps for forming the insulating pillar 111 in this embodiment are simple and the dimensional accuracy of the final insulating pillar 111 can be easily controlled. When forming the lower electrode layer and the upper electrode layer based on the insulating pillar 111, it is also easier to control the quality and dimensional accuracy of the formed lower electrode layer and the upper electrode layer, thereby helping to reduce the process difficulty of preparing semiconductor structures and improve the electrical performance of semiconductor structures.

[0072] In some embodiments, before forming the insulating pillar 111, a transistor 102 is formed in the substrate 100 of the circuit region b, consisting of a capacitor control terminal 112 and a gate 122 located on the surface of the substrate 100, to form the transistor 102 in the circuit region b, and a dielectric layer 104 is formed enclosing the transistor 102. In other embodiments, the transistor located in the circuit region may be formed after forming the insulating pillar and before forming the lower electrode layer.

[0073] refer to Figures 5 to 6 The formation of the lower electrode layer 121 and the electrical connection structure 103 may include the following process steps:

[0074] refer to Figure 5 Conductive pillars 113 are formed, which penetrate the dielectric layer 104 and are electrically connected to the capacitor control terminal 112.

[0075] Continue to refer Figure 5A continuous first conductive layer 133 is formed, which is located on the top and side surfaces of the insulating pillar 111, and is also located on the top surface of the dielectric layer 104 in the circuit region b and is in contact with the top surface of the conductive pillar 113.

[0076] The small depth-to-width ratio of the spacing between adjacent insulating pillars 111 helps to ensure the continuity of the first conductive layer 133, as well as the continuity of the subsequently formed capacitor dielectric layer and the second conductive layer, thereby improving the quality of the formed upper and lower electrode layers.

[0077] Reference Figure 5 and Figure 6 A first conductive layer 133 is patterned to form an electrical connection layer 123 and a plurality of discrete lower electrode layers 121. The electrical connection layer 123 is located on the top surface of the dielectric layer 104 and is in contact with the top surface of the conductive pillars 113. The electrical connection layer 123 extends from the circuit region b to the array region a to be electrically connected to the corresponding lower electrode layers 121. The electrical connection layer 123 and the conductive pillars 113 together constitute the electrical connection structure 103.

[0078] In other embodiments, only the first conductive layer of the circuit region may be patterned to form an electrical connection layer, with the continuous first conductive layer in the array region serving as the lower electrode layer.

[0079] refer to Figures 7 to 8 Forming the capacitor dielectric layer 141 and the upper electrode layer 131 may include the following process steps:

[0080] refer to Figure 7 A continuous capacitor dielectric layer 141 is formed on the surface of the lower electrode layer 121. The capacitor dielectric layer 141 is located between adjacent insulating pillars 111, and is also located on the top surface of the electrical connection layer 123 and the top surface of the dielectric layer 104. A second conductive layer (not shown) is formed on the top surface of the capacitor dielectric layer 141.

[0081] refer to Figure 8 Remove the second conductive layer located in circuit region b, and the remaining second conductive layer serves as the upper electrode layer 131.

[0082] Continue to refer Figure 8 An initial insulating layer 152 is formed on the top surface of the upper electrode layer 131 and the top surface of the capacitor dielectric layer 141 in the circuit region b. The initial insulating layer 152 fills the gap between adjacent insulating pillars 111.

[0083] Reference Figure 8 and Figure 1 The initial insulating layer 152 is planarized to form an insulating layer 151, so that the top surface of the insulating layer 151 in the array region a is flush with the top surface of the insulating layer 151 in the circuit region b.

[0084] In some embodiments, reference Figure 1 Based on the actual circuit requirements, a single layer of storage capacitor unit 101 can be formed.

[0085] In other embodiments, Figure 1 Based on, refer to Figure 9 , Figure 10 and Figure 2 The manufacturing method may further include: forming M storage capacitor cells 101 stacked in a direction perpendicular to the surface of the substrate 100, where M is a natural number greater than or equal to 2, and an insulating layer 151 is provided between adjacent storage capacitor cells 101; forming a conductive via 105, the conductive via 105 penetrating the insulating layer 151 and a continuous film layer of each storage capacitor cell 101, so that the conductive via 105 is in contact with the continuous film layer of each storage capacitor cell 101.

[0086] Figure 1 Taking the upper electrode layer 131 as an example, which is a continuous film layer, the formed conductive via 105 is electrically connected to the upper electrode layer 131 of each storage capacitor unit 101. In practical applications, the lower electrode layer can also be a continuous film layer, in which case the formed conductive via is electrically connected to the lower electrode layer of each storage capacitor unit.

[0087] Reference Figure 1 and Figure 9 Based on the formed insulating layer 151, a first dielectric layer 116, a second dielectric layer 126, a third dielectric layer 136, and a mask 107 with openings are formed in sequence to form the insulating pillars 111 in the second storage capacitor unit 101. The specific method for forming the insulating pillars is the same as in the above embodiment and will not be described in detail here.

[0088] refer to Figure 10 Based on the formation of insulating pillar 111, a lower electrode layer 121, an upper electrode layer 131, a capacitor dielectric layer 141, an insulating layer 151, and an electrical connection structure 103 corresponding to the lower electrode layer 121 are formed. The formation steps of the lower electrode layer 121, upper electrode layer 131, capacitor dielectric layer 141, insulating layer 151, and electrical connection structure 103 are the same as in the above embodiment, and will not be described again here.

[0089] Reference Figure 10 and Figure 2 Similarly, the steps of forming the insulating pillar 111, the lower electrode layer 121, the upper electrode layer 131, the capacitor dielectric layer 141, the insulating layer 151, and the electrical connection structure 103 can be repeated according to the circuit requirements in the actual circuit to form M storage capacitor units 101 stacked in a direction perpendicular to the surface of the substrate 100.

[0090] In summary, on the one hand, compared to forming capacitor vias with large aspect ratios, the process steps for forming the insulating pillar 111 in this embodiment are simpler, and the dimensional accuracy of the final insulating pillar 111 can be easily controlled. Furthermore, when forming the lower electrode layer 121 and the upper electrode layer 131 based on the insulating pillar 111, it is also easier to control the quality and dimensional accuracy of the formed upper electrode layer 131 and lower electrode layer 121, thereby reducing the process difficulty of fabricating the semiconductor structure and improving the electrical performance of the semiconductor structure. On the other hand, the upper electrode layer 131 and the lower electrode layer 121 are generally wavy or mountain-shaped, which helps to increase the facing area between the upper electrode layer 131 and the lower electrode layer 121, thereby increasing the capacitance of the storage capacitor cell and thus improving the electrical performance of the semiconductor structure.

[0091] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure has an array region and a circuit region, including: Base; At least one storage capacitor cell is located in the array region. The storage capacitor cell includes: N insulating pillars distributed in a direction parallel to the surface of the substrate; a lower electrode layer covering the top and side surfaces of the insulating pillars; an upper electrode layer opposite to the lower electrode layer; and a capacitor dielectric layer located between the upper and lower electrode layers. Wherein, either the lower electrode layer corresponding to the N insulating pillars or the upper electrode layer corresponding to the N insulating pillars is a continuous film layer, and the other is a discrete film layer, where N is a natural number greater than or equal to 2. A transistor located in the circuit region, the transistor including a capacitor control terminal located within the substrate of the circuit region; An electrical connection structure is electrically connected to the capacitor control terminal, and the electrical connection structure extends from the circuit region to the array region to contact the corresponding discrete film layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a dielectric layer located on the substrate of the circuit region; the electrical connection structure includes: A conductive post, which penetrates the dielectric layer and is electrically connected to the capacitor control terminal; An electrical connection layer is located on the top surface of the dielectric layer and in contact with the top surface of the conductive pillar, and the electrical connection layer extends from the circuit region to the array region to contact the corresponding discrete film layer.

3. The semiconductor structure as described in claim 2, characterized in that, The material of the electrical connection layer is the same as the material of the discrete film layer.

4. The semiconductor structure as described in claim 2, characterized in that, The capacitor dielectric layer corresponding to the N insulating pillars is a continuous film layer, and the capacitor dielectric layer is also located on the top surface of the dielectric layer and the top surface of the electrical connection layer.

5. The semiconductor structure as described in claim 1, characterized in that, The number of transistors is N, and the number of electrical connection structures is m times N, where m is a natural number greater than or equal to 1.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the lower electrode layer includes at least one of TiN, Ti, W, or Mo; the material of the upper electrode layer includes at least one of TiN, Ti, W, or Mo.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the capacitor dielectric layer includes at least one of ZrO, AlO, HfO, or NbO.

8. The semiconductor structure as described in claim 1, characterized in that, The thickness of the insulating pillar is 1 nm to 100 nm in the direction perpendicular to the surface of the substrate.

9. The semiconductor structure as described in claim 1, characterized in that, The width of the insulating pillar is 1 nm to 100 nm in the direction parallel to the surface of the substrate.

10. The semiconductor structure as claimed in claim 1, characterized in that, The lower electrode layer corresponding to the N insulating pillars is a discrete film layer, and the upper electrode layer corresponding to the N insulating pillars is a continuous film layer.

11. The semiconductor structure as claimed in claim 1, characterized in that, The semiconductor structure includes M storage capacitor cells stacked in a direction perpendicular to the surface of the substrate, where M is a natural number greater than or equal to 2; it also includes: An insulating layer is located between the storage capacitor cells of adjacent layers; A conductive via penetrates the insulating layer and the continuous film layer of each of the storage capacitor cells, such that the conductive via contacts the continuous film layer of each of the storage capacitor cells.

12. The semiconductor structure as claimed in claim 11, characterized in that, The semiconductor structure includes M electrical connection structures stacked in a direction perpendicular to the surface of the substrate, and the electrical connection structures in adjacent layers are in contact with each other.

13. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: The word line is located within the substrate of the array region, and the substrate on both sides of the word line has a first doped region and a second doped region, respectively, and the first doped region is electrically connected to the lower electrode layer. The bit line is located in the array region and is electrically connected to the second doped region.

14. A method for manufacturing a semiconductor structure, characterized in that, The semiconductor structure has an array region and a circuit region, including: Provide a base; At least one storage capacitor cell is formed on the substrate, the storage capacitor cell being located in the array region, the storage capacitor cell comprising: N insulating pillars distributed in a direction parallel to the surface of the substrate; a lower electrode layer covering the top and side surfaces of the insulating pillars; an upper electrode layer opposite to the lower electrode layer; and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer; wherein, either the lower electrode layer corresponding to the N insulating pillars or the upper electrode layer corresponding to the N insulating pillars is a continuous film layer, and the other is a discrete film layer, and N is a natural number greater than or equal to 2; A transistor is formed in the circuit region, and the transistor includes a capacitor control terminal located within the substrate of the circuit region; An electrical connection structure is formed, which is electrically connected to the capacitor control terminal, and the electrical connection structure extends from the circuit region to the array region to contact the corresponding discrete film layer.

15. The manufacturing method as described in claim 14, characterized in that, The substrate of the circuit region has a dielectric layer; The steps of forming the lower electrode layer and the electrical connection structure include: A conductive pillar is formed, which penetrates the dielectric layer and is electrically connected to the capacitor control terminal; A continuous first conductive layer is formed, which is located on the top and side surfaces of the insulating pillar, and is also located on the top surface of the dielectric layer in the circuit area and in contact with the top surface of the conductive pillar. The first conductive layer is patterned to form an electrical connection layer and a plurality of mutually discrete lower electrode layers. The electrical connection layer is located on the top surface of the dielectric layer and is in contact with the top surface of the conductive pillar. The electrical connection layer extends from the circuit region to the array region to be electrically connected to the corresponding lower electrode layer.

16. The manufacturing method as described in claim 15, characterized in that, The process steps for forming the capacitor dielectric layer and the upper electrode layer include: A continuous capacitor dielectric layer is formed on the surface of the lower electrode layer. The capacitor dielectric layer is located between adjacent insulating pillars and is also located on the top surface of the electrical connection layer and the top surface of the dielectric layer. A second conductive layer is formed on the top surface of the capacitor dielectric layer; Remove the second conductive layer located in the circuit area, and the remaining second conductive layer serves as the upper electrode layer.

17. The manufacturing method as described in claim 16, characterized in that, Also includes: M storage capacitor cells are stacked in a direction perpendicular to the surface of the substrate, where M is a natural number greater than or equal to 2, and there is an insulating layer between the storage capacitor cells of adjacent layers. A conductive via is formed, the conductive via penetrating the insulating layer and the continuous film layer of each of the storage capacitor cells, so that the conductive via is in contact with the continuous film layer of each of the storage capacitor cells.

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