Semiconductor structure and method of forming the same
By forming barrier structures and protective rings in the semiconductor structure, the problem of non-uniformity in the active region caused by the proximity effect is solved, achieving uniformity of the active region and cost savings.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2021-11-11
- Publication Date
- 2026-06-19
AI Technical Summary
In dynamic random access memory, the proximity effect causes the size and spacing of the active region array at the edge and the center of the array to differ, requiring optical proximity effect correction, which increases cost and time.
A barrier structure is formed around the array region, and the patterned photoresist layer of the active region array is extended directly above the barrier structure. The barrier structure blocks the proximity effect and forms a protective ring to uniformly measure the active region size.
It reduces the cost and time of optical proximity effect correction, while achieving a uniform size of the active region in the array area, saving process steps and forming a guard ring.
Smart Images
Figure CN116133401B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] As integrated circuit dimensions shrink and the density of Dynamic Random Access Memory (DRAM) increases, an iso-dense effect occurs at the edges of the active region array. This results in differences in the size and spacing of the active region array at the edges and center of the array region. The proximity effect problem needs to be solved through optical proximity correction (OPC), which incurs higher costs and time. Summary of the Invention
[0003] Some embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a substrate including an array region and a surrounding region; forming a bottom layer on the substrate; forming a barrier structure on the bottom layer, the barrier structure being located in the surrounding region; covering an intermediate layer on the bottom layer and the barrier structure; forming a patterned photoresist layer on the intermediate layer, a first portion of the patterned photoresist layer being located in the array region and directly above the barrier structure in the surrounding region; sequentially transferring the pattern of the patterned photoresist layer to the bottom layer, wherein the pattern of the patterned photoresist layer directly above the barrier layer is not formed on the bottom layer; removing the barrier structure; and patterning a substrate, the substrate including a first portion, a second portion, and a third portion, the first portion of the substrate being located in the array region and being an active region array, the second portion of the substrate being located in the surrounding region and being a protective ring, and the third portion of the substrate being located in the surrounding region and being a surrounding structure.
[0004] Another embodiment of the present invention provides a semiconductor structure, including a substrate, including an array region and a surrounding region; a guard ring located in the surrounding region, abutting against and surrounding the array region; an active region array, including active regions located in the array region; and a surrounding structure located in the surrounding region, wherein the guard ring and the surrounding structure are spaced apart from each other.
[0005] In this embodiment of the invention, a barrier structure is formed in the area surrounding the abutting array region, and the patterned photoresist layer forming the active region array extends directly above the barrier structure. The edge portions of the photoresist pattern of the active region array that generate a proximity effect can be located directly above the barrier structure. Therefore, during substrate patterning, the barrier structure can block the proximity effect of the active region array pattern edges, ensuring that each active region in the array region is approximately the same size. This saves cost and time in correcting for optical proximity effects. Furthermore, a protective ring can be simultaneously formed on the substrate below the barrier structure. Attached Figure Description
[0006] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the devices may be enlarged or reduced to clearly demonstrate the technical features of the embodiments of the present invention.
[0007] Figure 1 This is a top view illustrating a semiconductor structure according to some embodiments of the present invention;
[0008] Figures 2A-2H The present invention provides cross-sectional views illustrating the various stages of forming a semiconductor structure.
[0009] Explanation of icon numbers:
[0010] 10a: Array area
[0011] 10b: Surrounding area
[0012] 10aS, 10bS: Sidewall
[0013] 10i: Interface
[0014] 100: Semiconductor Structure
[0015] 102: Active Zone
[0016] 104: Protective Ring
[0017] 106: Surrounding Structure
[0018] 108:Substrate
[0019] 110: Oxide layer
[0020] 112: Bottom layer
[0021] 114, 114': Barrier structure; 114S: Sidewall
[0022] 116: Photoresist layer
[0023] 118: Intermediate Layer
[0024] 120: Top Floor
[0025] 121: Three-layer photomask structure
[0026] 122: Patterned photomask layer
[0027] 122aS, 122bS: Spacing
[0028] 124: Three-layer photoresist structure
[0029] 126: Bottom layer
[0030] 128: Intermediate Layer
[0031] 130: Patterned photoresist layer
[0032] 130a: Part 1
[0033] 130b: Part Two
[0034] 130aaS, 130abS: Spacing
[0035] 132: Shallow trench isolation structure
[0036] 134: Word Line
[0037] 136: Insulation materials
[0038] 102H, 104H: Altitude
[0039] 102W, 104W, 106W, 10bW: Width
[0040] 2-2: Line Detailed Implementation
[0041] This invention provides a semiconductor structure and a method for forming the same. By forming a barrier structure in the area surrounding the array region and forming an active region array pattern extending into a patterned photoresist layer on the barrier structure, the proximity effect occurs in the patterned photoresist layer on the barrier structure. By setting the barrier structure, the proximity effect at the edge of the active region array pattern can be eliminated simultaneously, and a protective ring is formed around the array region.
[0042] Figure 1 This is a top view illustrating a semiconductor structure 100 according to some embodiments of the present invention. Figures 2A-2H The present invention provides cross-sectional views illustrating various stages of forming the semiconductor structure 100 according to some embodiments thereof. Figures 2A-2H draw Figure 1 A cross-sectional view of the semiconductor structure 100 obtained along line 2-2.
[0043] like Figure 1 As shown, the semiconductor structure 100 includes an array region 10a and a surrounding region 10b. The array region 10a includes an active region array 102. The surrounding region 10b includes a guard ring 104 and a surrounding structure 106. The guard ring 104 and the surrounding structure 106 are spaced apart from each other. In some embodiments, the guard ring 104 surrounds and abuts against the array region 10a.
[0044] like Figure 2AAs shown, the semiconductor structure 100 includes a substrate 108, including an array region 10a and a surrounding region 10b. The substrate 108 can be a semiconductor substrate, which may include elemental semiconductors such as silicon (Si) and germanium (Ge); compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb); alloy semiconductors such as silicon-germanium alloy (SiGe), gallium arsenide-gallium phosphide alloy (GaAsP), aluminum-indium arsenide alloy (AlInAs), aluminum-gallium arsenide alloy (AlGaAs), indium-gallium arsenide alloy (GaInAs), indium-gallium phosphide alloy (GaInP), indium-gallium arsenide-gallium phosphide alloy (GaInAsP), or combinations thereof. Furthermore, the substrate 108 may also be a semiconductor on-insulator (SOI). The substrate 108 may be of N-type or P-type conductivity. N-type dopants may include phosphorus, arsenic, nitrogen, antimony ions, or combinations thereof. P-type dopants may include boron, gallium, aluminum, indium, boron trifluoride ions (BF3+), or combinations thereof.
[0045] Next, an oxide layer 110 is formed on the substrate 108 in a blanket manner. In some embodiments, the oxide layer 110 includes an oxide such as silicon oxide. The oxide layer 110 may be formed by deposition processes such as chemical vapor deposition, spin coating, sputtering, thermal oxidation, or a combination thereof.
[0046] Next, a substrate 112 is formed on top of the oxide layer 110 in a blanket manner. The substrate 112 can serve as an etch stop layer for subsequent etching processes. The substrate 112 can be made of a different material than the oxide layer 110 and has an etch selectivity. In some embodiments, the substrate 112 comprises polysilicon. The substrate 112 can be formed using deposition processes such as chemical vapor deposition, spin coating, sputtering, or a combination thereof.
[0047] Subsequently, a barrier layer 114 is formed blanket-coated over the substrate 112. The barrier layer 114 and the substrate 112 may be made of different materials and have an etching selectivity. In some embodiments, the barrier layer 114 is in direct contact with the substrate 112. In some embodiments, the barrier layer 114 comprises a nitride, such as silicon nitride. The barrier layer 114 may be formed using deposition processes such as chemical vapor deposition, spin coating, sputtering, or combinations thereof.
[0048] Next, a photoresist layer 116 is formed on the barrier layer 114, and a pattern of the photoresist layer 116 is formed using a photolithography process. In some embodiments, the pattern of the photoresist layer 116 surrounds the array region 10a and exposes the barrier layer 114 surrounding the array region 10a and the surrounding region 10b. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure patterning, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable techniques, or combinations thereof.
[0049] Next, as Figure 2B As shown, a photoresist layer 116 is used as a photomask to pattern a blocking layer 114 to form a blocking structure 114'. In some embodiments, the blocking structure 114 is located within the surrounding region 10b. In some embodiments, the sidewalls 114S of the blocking structure 114' are aligned with the interface 10i of the array region 10a and the surrounding region 10b. In some embodiments, the sidewalls 114S of the blocking structure 114' are vertically aligned with the sidewalls 10bS of the surrounding region 10b and the sidewalls 10aS of the array region 10a.
[0050] Next, as Figure 2C As shown, an intermediate layer 118 is formed covering the bottom layer 112 and the barrier structure 114'. In some embodiments, the top surface of the intermediate layer 118 is higher than the top surface of the barrier structure 114'. In some embodiments, the intermediate layer 118, the barrier structure 114', and the bottom layer 112 are made of different materials and have different etching selectivity. In some embodiments, the intermediate layer 118 comprises carbon, such as spin-on carbon (SOC). The intermediate layer 118 can be formed by spin coating, deposition, sputtering, or a combination thereof.
[0051] Next, a top layer 120 is formed on top of the intermediate layer 118 in a blanket manner. The top layer 120 can serve as an etch stop layer for subsequent etching processes. The material of the top layer 120 can be the same as the material of the bottom layer 112. In some embodiments, the top layer 120 comprises polysilicon. The top layer 120 can be formed using deposition processes such as chemical vapor deposition, spin coating, sputtering, or a combination thereof.
[0052] A three-layer photomask structure 121 is formed on the oxide layer 110. The three-layer photomask structure 121 may include a bottom layer 112, an intermediate layer 118, and a top layer 120. In some embodiments, a barrier structure 114' is formed in the intermediate layer 118, and the intermediate layer 118 covers the barrier structure 114'.
[0053] Next, a patterned photomask layer 122 is formed on the top layer 120 of the three-layer photomask structure 121. The patterned photomask layer 122 can define the position of the active region array 102 in the array region 10a, for example, the position of the lines forming the active regions 102. In some embodiments, the patterned photomask layer 122 comprises an oxide, such as silicon oxide. In some embodiments, the pattern of the patterned photomask layer 122 is located in the array region 10a and extends directly above the blocking structure 114' in the surrounding region 10b. In some embodiments, the pattern of the patterned photomask layer 122 overlaps perpendicularly with the blocking structure 114'. The spacing of the pattern of the patterned photomask layer 122 in the array region 10a is 122aS, and the spacing of the pattern of the patterned photomask layer 122 in the surrounding region 10b is 122bS. In some embodiments, the spacing 122aS and the spacing 122bS are approximately equal.
[0054] Next, as Figure 2D As shown, a three-layer photoresist structure 124 is formed on a patterned photomask layer 122. The three-layer photoresist structure 124 may include a bottom layer 126, an intermediate layer 128, and a top layer 130. The bottom layer 126 may include carbon, such as spin-coated carbon material; the intermediate layer 128 may include SOSA; and the top layer 130 may include photoresist. The top layer 130 may also be referred to as the patterned photoresist layer 130. The bottom layer 126 can be formed on the top layer 120 and the patterned photomask layer 122 of the three-layer photomask structure 121 by spin coating, deposition, sputtering, or a combination thereof. The bottom layer 126 may cover the sidewalls and top surface of the patterned photomask layer 122. The intermediate layer 128 can be formed on the bottom layer 126 by deposition or spin coating. The top layer 130 can be formed on the intermediate layer 128 and patterned by spraying, spin coating, or deposition.
[0055] The patterned photoresist layer 130 includes a first portion 130a and a second portion 130b. The first portion 130a can define the position of the active region array 102, for example, by truncating the lines of the active region 102. Therefore, the first portion 130a of the patterned photoresist layer 130 has a different pattern from that of the photomask layer 122 and partially overlaps with the pattern of the patterned photomask layer 122 to form the active region array 102. The second portion 130b of the patterned photoresist layer 130 can define the pattern in the surrounding region 10b to form... Figure 1 The surrounding structure 106. In some embodiments, the active region array 102 and the surrounding structure 106 are formed with the same patterned photoresist layer 130 defined.
[0056] A first portion 130a of the patterned photoresist layer 130 is located in the array region 10a and directly above the blocking structure 114' in the surrounding region 10b. The spacing of the first portion 130a of the patterned photoresist layer 130 in the array region 10a is 130aaS, and the spacing of the first portion 130a of the patterned photoresist layer 130 in the surrounding region 10b is 130abS. In some embodiments, due to the proximity effect at the array edges, the spacing 130abS is not equal to the spacing 130aaS, and the spacing 130abS is greater than the spacing 130aaS.
[0057] Next, as Figure 2E As shown, a patterned photoresist layer 130 and a patterned photomask layer 122 are used as photomasks to pattern the bottom layer 112. Through photolithography and etching processes, the patterns of the patterned photoresist layer 130 and the patterned photomask layer 122 can be sequentially transferred to the bottom layer 112. For example, the patterned photoresist layer 130 can be used as an etching photomask to pattern an intermediate layer 128 to transfer the pattern of the patterned photoresist layer 130 to the intermediate layer 128, and the patterned photoresist layer 130 can be removed while patterning the intermediate layer 128. Next, using the intermediate layer 128 as an etching photomask, the bottom layer 126 and the patterned photomask layer 122 are patterned and etched to transfer the pattern of the patterned photoresist layer 130 to the bottom layer 126 and the patterned photomask layer 122. At this time, a pattern of active region array 102 is formed in patterned photomask layer 122, and a pattern of surrounding structure 106 is formed in bottom layer 126.
[0058] Next, using the patterned photomask layer 122 as an etching photomask, the top layer 120 is patterned and etched, and the patterned photomask layer 122 is removed while patterning the top layer 120. Then, using the pattern of the top layer 120 as an etching photomask, the intermediate layer 118 is patterned and etched, and the top layer 120 is removed while patterning the intermediate layer 118. Because the barrier layer 114 and the intermediate layer 118 have an etching selectivity ratio, the patterned photoresist layer 130 and the patterned photomask layer 122 directly above the barrier layer 114 are not formed on the intermediate layer 118.
[0059] Next, using the intermediate layer 118 and the barrier layer 114 as etching photomasks, the bottom layer 112 is patterned and etched, and the intermediate layer 118 is removed during the patterning of the bottom layer 112. Because the barrier layer 114 has an etching selectivity ratio with the bottom layer 112 and the intermediate layer 118, the barrier layer 114 remains above the bottom layer 112. In some embodiments, since the barrier layer 114 is formed within the three-layer photomask structure 121, the patterns of the patterned photoresist layer 130 and patterned photomask layer 122 directly above the barrier layer 114 are not transferred to the bottom layer 112, but a pattern of a protective ring 104 is formed on the bottom layer 112 directly below the barrier layer 114.
[0060] Next, as Figure 2F As shown, the barrier structure 114' is removed, exposing the underlying layer 112. The barrier structure 114' can be removed using either a wet etching process or a dry etching process. In some embodiments, the barrier structure 114' is removed using a wet etching process, including the use of a phosphoric acid (H3PO4) etching solution.
[0061] Next, as Figure 2G As shown, substrate 108 is patterned using bottom layer 112 as a photomask. The bottom layer 112 can be used as an etching photomask to pattern oxide layer 110. After removing the bottom layer 112, the oxide layer pattern 110 is used as an etching photomask to pattern substrate 108. Substrate 108 includes a first portion 102, a second portion 104, and a third portion 106. The first portion 102 of substrate 108 is located in array region 10a and can be an active region array 102. The width 102W of each active region 102 in the active region array 102 is approximately equal. Furthermore, each portion in each active region 102 has a height 102H that is approximately equal. The second portion 104 of substrate 108 is located in surrounding region 10b and can be a guard ring 104. The guard ring 104 surrounds the active region array 102 and abuts the interface between array region 10a and surrounding region 10b. In some embodiments, the width 104W of the guard ring 104 is greater than the width 102W of each active region 102. In some embodiments, the width 104W of the guard ring 104 is in the range of about 150 nm to about 400 nm. The ratio of the width 104W of the guard ring 104 to the width 102W of each active region 102 is in the range of about 3 to about 8. In some embodiments, the guard ring 104 has a flat upper surface, and each portion of the guard ring 104 has a substantially equal height 104H.
[0062] The third portion 106 of the substrate 108 is located in the surrounding region 10b and may be the surrounding structure 106. In some embodiments, the width 104W of the protective ring 104 is greater than the width 106W of the surrounding structure 106.
[0063] Next, as Figure 2H As shown, a shallow trench isolation structure 132 is formed in the trench between each active region 102, and a liner may be formed on the sidewalls and bottom of the shallow trench isolation structure 132. Next, word lines 134 are formed on and between the shallow trench isolation structures 132. The word lines 134 may include a gate dielectric layer, a barrier layer, and a conductive layer. Then, the trench above the word lines 134 is filled with an isolation material 136.
[0064] As described above, by forming a barrier structure in the area surrounding the abutting array region, and extending the patterned photoresist layer forming the active region array directly above the barrier structure, the edge portion of the photoresist pattern of the active region array that generates a proximity effect can be located directly above the barrier structure. Therefore, during substrate patterning, the barrier structure can block the proximity effect of the active region array pattern edge, making the size of each active region in the array region approximately the same. This saves cost and time in optical proximity effect correction. Furthermore, a protective ring can be simultaneously formed on the substrate below the barrier structure.
Claims
1. A method of forming a semiconductor structure, characterized by, include: A substrate is formed, including an array region and a surrounding region; A bottom layer is formed on the substrate; A barrier structure is formed on the bottom layer, wherein the barrier structure is located in the surrounding area that abuts the array region; An intermediate layer is placed over the bottom layer and the barrier structure; A patterned photoresist layer is formed on the intermediate layer, and a first portion of the patterned photoresist layer is located in the array region and directly above the barrier structure in the surrounding region; A pattern of the patterned photoresist layer is sequentially transferred to the bottom layer, wherein the pattern of the patterned photoresist layer directly above the barrier structure is not formed on the bottom layer; Remove the blocking structure; as well as The substrate is patterned, wherein the substrate includes a first portion, a second portion, and a third portion. The first portion of the substrate is located in the array region and is an active region array. The second portion of the substrate is located in the surrounding region and is a protective ring. The third portion of the substrate is located in the surrounding region and is a surrounding structure. The bottom layer located directly below the barrier structure forms the pattern of the protective ring. The protective ring surrounds the active region array and abuts the interface between the array region and the surrounding region.
2. The method of forming a semiconductor structure of claim 1, wherein, One sidewall of the barrier structure is aligned with an interface of the array region and the surrounding region.
3. The method of forming a semiconductor structure of claim 1, wherein Also includes: A patterned photomask layer is formed on the intermediate layer, and a pattern of the patterned photomask layer is located in the array region and extends directly above the blocking structure in the surrounding region; The pattern of the patterned photomask layer has a spacing in the surrounding area that is equal to a spacing in the array area.
4. The method of forming a semiconductor structure of claim 1, wherein, The spacing of the patterned photoresist layer in the surrounding area is greater than the spacing in the array area.
5. The method of forming a semiconductor structure of claim 1, wherein The barrier structure has an etching selectivity ratio with the bottom layer and the intermediate layer.
6. The method of forming a semiconductor structure of claim 1, wherein, The intermediate layer comprises carbon, the barrier structure comprises nitrides, and the bottom layer comprises polycrystalline silicon.
7. The method of forming a semiconductor structure of claim 3, wherein, The patterns of the patterned photomask layer and the patterned photoresist layer are different, and the patterns of the patterned photomask layer and the patterned photoresist layer partially overlap.
8. The method of forming a semiconductor structure of claim 3, wherein, The patterned photomask layer defines the position of a line forming the active region array in the array region, and the first portion of the patterned photoresist layer defines the position where the line of the active region array is truncated.
9. A semiconductor structure, characterized by include: A substrate, comprising an array region and a surrounding region; A protective ring is located within the surrounding area; An active region array, comprising multiple active regions located within the array region, wherein the guard ring abuts against the active region array; and A surrounding structure, located within that surrounding area; The protective ring is separated from the surrounding structure.
10. The semiconductor structure as described in claim 9, characterized in that, In a cross-sectional view parallel to one edge of the array region, the width of the guard ring is greater than the width of each of the active regions, and the width of the guard ring is greater than the width of the surrounding structure.
11. The semiconductor structure of claim 9, wherein, In a cross-sectional view parallel to one edge of the array region, the width of each active region is equal.
12. The semiconductor structure of claim 9, wherein, In a cross-sectional view parallel to one edge of the array region, the ratio of the width of the guard ring to that of each active region is in the range of 3 to 8.