Semiconductor device and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method of manufacturing such a semiconductor device. The semiconductor device comprises an active layer comprising a channel spaced apart from a substrate and extending in a direction parallel to a surface of the substrate, a gate dielectric layer formed over the active layer, a word line oriented laterally over the gate dielectric layer to face the active layer, and comprising a low work function electrode and a high work function electrode parallel to the low work function electrode, and a dielectric capping layer provided between the high work function electrode and the low work function electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0106512, filed on August 12, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device, and more specifically, to a semiconductor device comprising a memory cell with a three-dimensional structure and a method for manufacturing the semiconductor device. Background Technology

[0004] Since the integration density of two-dimensional (2D) memory devices is primarily determined by the area occupied by a single memory cell, it is subject to the limitations of fine patterning techniques. Fine patterning requires extremely expensive equipment, but it still has limitations in increasing the integration density of 2D memory devices. To address this issue, three-dimensional memory devices comprising memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] Embodiments of the present invention relate to a semiconductor device including highly integrated memory cells, and a method for manufacturing the semiconductor device.

[0006] According to one embodiment of the present invention, a semiconductor device includes: an active layer including channels spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed on the active layer; a word line laterally oriented on the gate dielectric layer to face the active layer, and the word line including a low work function electrode and a high work function electrode, the high work function electrode being parallel to the low work function electrode; and a dielectric capping layer disposed between the high work function electrode and the low work function electrode.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an active layer vertically spaced from the substrate on an upper portion of a substrate; forming a gate dielectric layer on the active layer; forming a low work function electrode on the gate dielectric layer; forming a dielectric capping layer on one side of the low work function electrode; and forming a high work function electrode parallel to the low work function electrode on the dielectric capping layer.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack in which a first interlayer dielectric layer, a first sacrificial layer, an active layer, a second sacrificial layer, and a second interlayer dielectric layer are stacked in the order mentioned above; forming a first opening through the stack; forming a recess by recessing the first sacrificial layer and the second sacrificial layer through the first opening; thinning an active layer exposed by the recess; forming a first gate dielectric layer on the thinned active layer; forming a low work function electrode that partially fills the recess on the first gate dielectric layer; forming a second gate dielectric layer by thinning a portion of the first gate dielectric layer exposed on one side of the low work function electrode; forming a dielectric capping layer on one side of the second gate dielectric layer and the low work function electrode; and forming a high work function electrode that fills the remaining portion of the recess on the dielectric capping layer.

[0009] According to another embodiment of the present invention, a semiconductor device includes: an active layer including channels spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a word line laterally oriented over the active layer to face the active layer, and the word line including a low work function electrode and a high work function electrode, the high work function electrode being parallel to the low work function electrode; a dielectric capping layer disposed between the high work function electrode and the low work function electrode; a first gate dielectric layer disposed between the active layer and the low work function electrode; and a second gate dielectric layer disposed between the active layer and the high work function electrode and being thinner than the first gate dielectric layer, wherein the dielectric capping layer extends to be located between the second gate dielectric layer and the high work function electrode.

[0010] According to another embodiment of the present invention, a semiconductor device includes: an active layer including channels spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a word line laterally oriented over the active layer to face the active layer, and the word line including a low work function electrode and a high work function electrode, the high work function electrode being parallel to the low work function electrode; a single-gate dielectric layer between the active layer and the low work function electrode; and a dual-gate dielectric layer located between the active layer and the high work function electrode, wherein a portion of the dual-gate dielectric layer extends to be located between the high work function electrode and the active layer. According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack including an active layer; forming a first opening vertically through the stack; forming a lateral recess in the stack above and below the active layer to expose a portion of the active layer; thinning the active layer exposed by the recess; forming a low work function electrode that partially fills the recess; forming a high work function electrode that fills the remaining portion of the recess; and forming a capping layer disposed between the low work function electrode and the high work function electrode. Attached Figure Description

[0011] Figure 1 This is a schematic perspective view illustrating a storage unit according to an embodiment of the present invention.

[0012] Figure 2 yes Figure 1 A cross-sectional view of the storage unit.

[0013] Figure 3 This is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention.

[0014] Figure 4 yes Figure 3 A cross-sectional view of the vertical memory cell array (MCA_C).

[0015] Figure 5 This is a cross-sectional view of the edge portion of the double-line character.

[0016] Figure 6 This is a cross-sectional view of a semiconductor memory device according to another embodiment of the present invention.

[0017] Figure 7 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0018] Figures 8A to 8I This is a cross-sectional view illustrating a method for forming double-line characters according to an embodiment of the present invention.

[0019] Figures 9A to 9I This is a cross-sectional view illustrating a method for forming bit lines and capacitors according to an embodiment of the present invention.

[0020] Figure 10 and Figure 11 This is a schematic perspective view illustrating a storage unit according to another embodiment of the present invention. Detailed Implementation

[0021] Embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, similar reference numerals refer to similar parts in the various figures and embodiments of the invention.

[0022] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to illustrate the various elements of the embodiment more clearly. When the first layer is referred to as being "on" the second layer or "on" the substrate, it can refer not only to the case where the first layer is formed directly on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0023] According to the embodiments of the present invention described below, by vertically stacking the memory cells, the memory cell density can be increased and the parasitic capacitance can be reduced.

[0024] The embodiments of the invention described below relate to a three-dimensional (3D) dynamic random access memory (DRAM) in which word lines may include low work function electrodes and high work function electrodes. The low work function electrodes may be adjacent to capacitors, while the high work function electrodes may be adjacent to bit lines. The low work function electrodes may include polysilicon, while the high work function electrodes may include a metal-based material.

[0025] Because of the low work function of the low work function electrode, a low electric field can be formed between the word line and the capacitor, thereby improving the leakage current problem.

[0026] The high work function of the high work function electrode can not only generate a high threshold voltage, but also reduce the height of the memory cell by generating a low electric field, which is advantageous in terms of integration.

[0027] Figure 1 This is a schematic perspective view illustrating a storage unit according to an embodiment of the present invention. Figure 2 yes Figure 1 The diagram shows a cross-sectional view of the storage cell.

[0028] refer to Figure 1 and Figure 2A memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, gate dielectric layers GD1 and GD2, and a double word line DWL. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a plate node PN.

[0029] The bit line BL can have a cylindrical shape extending in a first direction D1 perpendicular to the surface of the substrate SUB. The active layer ACT can have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL can have a linear shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP can be coupled to the plate line PL.

[0030] Bit lines BL can be vertically oriented in a first direction D1. Bit lines BL can be referred to as vertically oriented bit lines or cylindrical bit lines. Bit lines BL can include conductive materials. Bit lines BL can include silicon-based materials, metal-based materials, or combinations thereof. Bit lines BL can include polysilicon, metals, metal nitrides, metal silicides, or combinations thereof. Bit lines BL can include polysilicon, titanium nitride, tungsten, or combinations thereof. For example, bit lines BL can include polysilicon or titanium nitride (TiN) doped with N-type impurities. Bit lines BL can include a stack of titanium nitride and tungsten (TiN / W).

[0031] The dual word line (DWL) can extend in the third direction (D3), and the active layer (ACT) can extend in the second direction (D2). The active layer (ACT) can be arranged laterally starting from the bit line (BL). The dual word line (DWL) can include a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) can face each other using the active layer (ACT) between them. Gate dielectric layers (GD1 and GD2) can be formed on the upper and lower surfaces of the active layer (ACT).

[0032] The active layer ACT may be spaced apart from the substrate SUB and extend in a second direction D2 parallel to the surface of the substrate SUB. The active layer ACT may include a semiconductor material. For example, the active layer ACT may include polycrystalline silicon, monocrystalline silicon, germanium, or silicon-germanium. The active layer ACT may include a channel CH, a first source / drain region SR between the channel CH and the bit line BL, and a second source / drain region DR between the channel CH and the capacitor CAP. According to another embodiment of the invention, the active layer ACT may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). When the active layer ACT is formed of an oxide semiconductor material, the channel CH may also be formed of an oxide semiconductor material, and the first source / drain region SR and the second source / drain region DR may be omitted.

[0033] The first source / drain region SR and the second source / drain region DR may be doped with impurities of the same conductivity type. The first source / drain region SR and the second source / drain region DR may be doped with N-type or P-type impurities. The first source / drain region SR and the second source / drain region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. A first side of the first source / drain region SR may contact the bit line BL, and a second side of the first source / drain region SR may contact the channel CH. A first side of the second source / drain region DR may contact the storage node SN, and a second side of the second source / drain region DR may contact the channel CH. The second sides of the first source / drain region SR and the second source / drain region DR may partially overlap with the sides of the first word line WL1 and the second word line WL2, respectively.

[0034] The transistor TR can be a single-cell transistor and can have a dual-word line (DWL). In the dual-word line DWL, the first word line WL1 and the second word line WL2 can have the same potential. For example, the first word line WL1 and the second word line WL2 can form a pair to be coupled to a memory cell MC. The same word line drive voltage can be applied to the first word line WL1 and the second word line WL2. As described above, the memory cell MC according to an embodiment of the present invention can have a dual-word line DWL, wherein two first word lines WL1 and two second word lines WL2 are arranged adjacent to a channel CH.

[0035] The active layer ACT can have a thickness smaller than that of the first word line WL1 and the second word line WL2. Specifically, the vertical thickness of the active layer ACT in the first direction D1 can be smaller than the vertical thickness of each of the first word line WL1 and the second word line WL2 in the first direction D1.

[0036] As described above, the thin active layer ACT can be referred to as a thin body active layer. The thin active layer ACT may include a thin channel CH. The thin channel CH can be referred to as a "thin body channel (CH)". The thickness of the channel CH in the first direction D1 can be approximately 10 nm or less. According to another embodiment of the present invention, the channel CH can have the same thickness as the first word line WL1 and the second word line WL2.

[0037] The upper and lower surfaces of the active layer ACT can be flat. In other words, the upper and lower surfaces of the active layer ACT can be parallel to each other in the second direction D2.

[0038] Gate dielectric layers GD1 and GD2 may include a first gate dielectric layer GD1 and a second gate dielectric layer GD2. The first gate dielectric layer GD1 may be thicker than the second gate dielectric layer GD2. The first gate dielectric layer GD1 and the second gate dielectric layer GD2 may be formed of the same material and may be formed integrally. The first gate dielectric layer GD1 and the second gate dielectric layer GD2 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or combinations thereof. The first gate dielectric layer GD1 and the second gate dielectric layer GD2 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof.

[0039] The first gate dielectric layer GD1 and the second gate dielectric layer GD2 can be located between the first word line WL1 and the active layer ACT. The first gate dielectric layer GD1 and the second gate dielectric layer GD2 can be located between the second word line WL2 and the active layer ACT. The first gate dielectric layer GD1 can be located between the second source / drain region DR and the first word line WL1 and the second word line WL2. The second gate dielectric layer GD2 can be located between the channel CH and the first word line WL1 and the second word line WL2. The second gate dielectric layer GD2 can extend to be located between the first source / drain region SR and the first word line WL1 and the second word line WL2.

[0040] Double word line (DWL) materials can include metals, metal mixtures, metal alloys, or semiconductor materials. Double word line DWL materials can include titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, a double word line DWL can include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. Double word line DWL materials can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of approximately 4.5 eV or lower, while P-type work function materials can have a high work function of approximately 4.5 eV or higher.

[0041] According to an embodiment of the present invention, a dual word line (DWL) can be formed by a pair of two first word lines (WL1) and two second word lines (WL2), with an active layer (ACT) located between the first word lines (WL1) and the second word lines (WL2). The dual word line (DWL) can be coupled to a memory cell (MC).

[0042] Each of the first word line WL1 and the second word line WL2 may include a dual-function electrode. The dual-function electrode may be laterally oriented in the second direction D2 to face the active layer ACT above the first gate dielectric layer GD1 and the second gate dielectric layer GD2. The dual-function electrode may include a high-function electrode HWG and a low-function electrode LWG. The high-function electrode HWG and the low-function electrode LWG may be laterally adjacent to each other in the second direction D2. The low-function electrode LWG may be adjacent to the second source / drain region DR, while the high-function electrode HWG may be adjacent to the first source / drain region SR.

[0043] The low work function electrode (LWG) and the high work function electrode (HWG) can be formed from different work function materials. The high work function electrode (HWG) can have a higher work function than the low work function electrode (LWG). The high work function electrode (HWG) can include a high work function material. The high work function electrode (HWG) can have a work function higher than the mid-gap work function of silicon. The low work function electrode (LWG) can include a low work function material. The low work function electrode (LWG) can have a work function lower than the mid-gap work function of silicon. For example, the high work function electrode (HWG) can have a work function of approximately 4.5 eV or higher, while the low work function electrode (LWG) can have a work function of approximately 4.5 eV or lower. The low work function electrode (LWG) can include doped polycrystalline silicon doped with N-type impurities. The high work function electrode (HWG) can include a metal-based material. The high work function electrode (HWG) can include tungsten, titanium nitride, or combinations thereof. A conductive barrier layer can be further formed between the low work function electrode (LWG) and the high work function electrode (HWG). In this paper, the high work function electrode HWG may include tungsten, and the conductive barrier layer may include titanium nitride.

[0044] The width of the high work function electrode HWG in the second direction D2 can be longer than the width of the low work function electrode LWG in the second direction D2. The thickness of the low work function electrode LWG in the first direction D1 can be greater than the thickness of the high work function electrode HWG in the first direction D1. The high work function electrode HWG can have a larger volume than the low work function electrode LWG, and correspondingly, the first word line WL1 and the second word line WL2 can have low resistance.

[0045] Each of the high work function electrode HWG and the low work function electrode LWG can vertically overlap with the active layer ACT in the first direction D1. The overlap area between the high work function electrode HWG and the active layer ACT can be greater than the overlap area between the low work function electrode LWG and the active layer ACT. For example, the high work function electrode HWG and the active layer ACT can vertically overlap each other in the first direction D1. The high work function electrode HWG and the first source / drain region SR can vertically overlap each other in the first direction D1. The high work function electrode HWG and the channel CH can vertically overlap each other in the first direction D1. The low work function electrode LWG and the active layer ACT can vertically overlap each other in the first direction D1. The low work function electrode LWG and the second source / drain region DR can vertically overlap each other in the first direction D1. The low work function electrode LWG and the channel CH can not vertically overlap each other in the first direction D1. The overlap area between the high work function electrode HWG and the channel CH can be greater than the overlap area between the low work function electrode LWG and the second source / drain region DR. The low work function electrode LWG and the high work function electrode HWG can extend parallel to the third direction D3, and they do not need to be in direct contact with each other.

[0046] A capping layer DB may be located between a low work function electrode LWG and a high work function electrode HWG. The capping layer DB may include a dielectric material. For example, the capping layer DB may include silicon oxide. The capping layer DB may cover the upper and lower surfaces of the high work function electrode HWG and may extend between the low work function electrode LWG and the high work function electrode HWG. The low work function electrode LWG may contact a first gate dielectric layer GD1, and the capping layer DB may be located between the high work function electrode HWG and a second gate dielectric layer GD2. The capping layer DB can be used to prevent impurities from diffusing from the low work function electrode LWG. In other words, the capping layer DB can suppress impurity loss in the low work function electrode LWG.

[0047] The capping layer DB can be conformally formed to include a first portion P1 and a second portion P2. The first portion P1 of the capping layer DB can cover the upper and lower surfaces of the high work function electrode HWG, and the second portion P2 of the capping layer DB can be located between the low work function electrode LWG and the high work function electrode HWG. The first portion P1 and the second portion P2 can have the same thickness.

[0048] According to another embodiment of the invention, the cover layer DB can be formed nonconformally. In other words, the first portion P1 and the second portion P2 can have different thicknesses. For example, the second portion P2 can be thinner than the first portion P1.

[0049] The first portion P1 of the capping layer DB can be used as a gate dielectric layer. In other words, a thick third gate dielectric layer GD3 can be formed, including a second gate dielectric layer GD2 and the first portion P1 of the capping layer DB. The thick third gate dielectric layer GD3 can be formed between the high work function electrode HWG and the channel CH. The third gate dielectric layer GD3 can be thicker than the first gate dielectric layer GD1. The third gate dielectric layer GD3 can be referred to as the "channel-side gate dielectric layer" that contacts the channel CH. The third gate dielectric layer GD3 can reduce the cell threshold voltage drop (CVT drop) and electric field degradation. The second portion P2 of the capping layer DB can prevent impurities from diffusing from the low work function electrode LWG.

[0050] Even with the formation of the dielectric overlay DB, the high work function electrode (HWG) and the low work function electrode (LWG) can be interconnected. From a top-down view, one end of the high work function electrode (HWG) and one end of the low work function electrode (LWG) can be interconnected.

[0051] As described above, each of the first word line WL1 and the second word line WL2 can have a dual power function electrode structure including a low power function electrode LWG and a high power function electrode HWG. Specifically, the dual word line DWL including the first word line WL1 and the second word line WL2 can have a pair of dual power function electrodes that extend in a third direction D3 intersecting with the channel CH and with the channel CH interposed therebetween.

[0052] Bit line contact nodes (BLCs) can be formed between the first source / drain region SR and the bit line BL. The bit line contact node BLC can have a height that completely covers the sides of the first source / drain region SR. The bit line contact node BLC can comprise polysilicon. For example, the bit line contact node BLC can comprise polysilicon doped with impurities. Herein, the impurities can have the same conductivity type as the impurities in the first source / drain region SR.

[0053] A protective layer LC can be located between the bit line contact node BLC and the high work function electrode HWG. The protective layer LC can include a dielectric material such as silicon nitride. The upper and lower surfaces of the protective layer LC can be covered by a capping layer DB. The combination of the capping layer DB and the protective layer LC can surround the upper surface, lower surface, and both sides of the high work function electrode HWG.

[0054] The capacitor CAP can be laterally positioned along the second direction D2, starting from the transistor TR. The capacitor CAP may include a storage node SN extending laterally along the second direction D2, starting from the active layer ACT. The capacitor CAP may also include a dielectric layer DE and a plate node PN above the storage node SN. The storage node SN, dielectric layer DE, and plate node PN can be laterally arranged along the second direction D2. The storage node SN may have a laterally oriented cylindrical shape. The dielectric layer DE may conformally cover the inner and outer walls of the storage node SN. The plate node PN may have a shape extending above the dielectric layer DE toward the inner and outer walls of the storage node SN. The plate node PN may be coupled to a plate line PL. The storage node SN may be electrically connected to a second source / drain region DR.

[0055] The storage node SN can have a three-dimensional structure, and this three-dimensional storage node SN can have a transverse three-dimensional structure oriented in the second direction D2. As an example of a three-dimensional structure, the storage node SN can have a cylindrical shape. According to another embodiment of the invention, the storage node SN can have a cylindrical shape or a pylinder shape. A pylinder shape can refer to a structure that combines a cylindrical shape and a pylinder shape. The uppermost surface of the storage node SN can be located at the same level as the upper surface of the first word line WL1. The lowermost surface of the storage node SN can be located at the same level as the bottom surface of the second word line WL2.

[0056] Storage nodes (SN) and plate nodes (PN) can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and plate nodes (PN) can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten nitride (TiN / W) stacks, or tungsten nitride / tungsten nitride (WN / W) stacks. Plate nodes (PN) can include combinations of metal-based materials and silicon-based materials. For example, a plate node (PN) can be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the gap filler material inside the cylinder that fills the storage node SN, and titanium nitride (TiN) can be used as the plate node PN of the capacitor CAP. Tungsten nitride can be a low-resistance material.

[0057] The dielectric layer DE may comprise silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer DE may comprise a high-k material having a dielectric constant of approximately 4 or greater. The high-k material may have a dielectric constant of approximately 20 or greater. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the invention, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0058] The dielectric layer DE can be formed of zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure in which zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. The ZA and ZAZ stacks can be referred to as a zirconium oxide (ZrO2) base layer. According to another embodiment of the invention, the dielectric layer DE can be formed of hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnium oxide (HfO2). Stacked structures including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure in which alumina (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a structure in which hafnium oxide (HfO2), alumina (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. HA stacks and HAH stacks can be referred to as hafnium oxide (HfO2) substrates. In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, the band gap energy of alumina (Al2O3) can be greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can include a stack of high-k material and high-bandgap material, wherein the high-bandgap material has a larger bandgap than the high-k material. The dielectric layer DE can include silicon oxide (SiO2) instead of aluminum oxide (Al2O3) as the high-bandgap material. Because the dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the invention, the dielectric layer DE can include a stacked structure in which high-k material and high-bandgap material are alternately stacked. For example, the dielectric layer DE can include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above-mentioned layered structure, aluminum oxide (Al2O3) can be thinner than zirconium oxide and hafnium oxide.

[0059] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a layered structure, or a hybrid structure including zirconium oxide, hafnium oxide and aluminum oxide.

[0060] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material or an antiferroelectric material.

[0061] According to another embodiment of the present invention, an interface control layer for improving leakage current can be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0062] The capacitor CAP can include a MIM (metal-insulator-metal) capacitor, wherein the storage node SN and the plate node PN can include metal-based materials.

[0063] Capacitors (CAPs) can be formed from other data storage materials. For example, data storage materials can be phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0064] A storage contact node (SNC) may be formed between the second source / drain region (DR) and the storage node (SN). The storage contact node (SNC) may have a height that completely covers a first side of the second source / drain region (DR). The storage contact node (SNC) may comprise polysilicon. For example, the storage contact node (SNC) may comprise polysilicon doped with impurities. Here, the impurities may have the same conductivity type as the impurities in the second source / drain region (DR).

[0065] As described above, the memory cell MC may include a dual word line DWL with a pair of dual work function electrodes. Each first word line WL1 and each second word line WL2 of the dual word line DWL may include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG may be adjacent to a capacitor CAP, while the high work function electrode HWG may be adjacent to a bit line BL. Due to the low work function of the low work function electrode LWG, a low electric field can be formed between the dual word line DWL and the capacitor CAP, thereby improving leakage current. Due to the high work function of the high work function electrode HWG, a high threshold voltage of the transistor TR can be formed, and the height of the memory cell MC can be reduced by forming a low electric field, which is advantageous in terms of integration density.

[0066] In Comparative Example 1, where the first word line WL1 and the second word line WL2 are formed solely of a metal-based material, a high electric field can be generated between the first word line WL1 and the second word line WL2 and the capacitor CAP due to the high work function of the metal-based material. This degrades the leakage current of the memory cell. When the channel CH is thinner, the degradation of the leakage current due to the high electric field becomes even worse.

[0067] In Comparative Example 2, where the first word line WL1 and the second word line WL2 are formed solely of low work function materials, the threshold voltage of the transistor may decrease due to the low work function, thereby generating leakage current.

[0068] In Comparative Example 3, where the capping layer DB is omitted between the low work function electrode LWG and the high work function electrode HWG, impurity loss occurs in the low work function electrode LWG, reducing the bifunctional electrode effect.

[0069] In Comparative Example 4, where the conductive capping layer is located between the low work function electrode LWG and the high work function electrode HWG, the cell threshold voltage may decrease and the electric field may deteriorate because the thickness of the gate dielectric layer in contact with the channel CH cannot be increased.

[0070] According to an embodiment of the present invention, since each of the first word line WL1 and the second word line WL2 of the dual word line DWL has a double function electrode, leakage current can be improved, thereby ensuring the refresh characteristics of the memory cell MC. This allows for reduced power consumption.

[0071] According to embodiments of the present invention, since each of the first word line WL1 and the second word line WL2 of the dual word line DWL has a double function electrode, the electric field can be increased relatively advantageously for high integration density, even if the thickness of the channel CH is reduced. Therefore, a large number of stacking levels can be realized.

[0072] According to an embodiment of the present invention, since the thickness of the third gate dielectric layer GD3 in contact with the channel CH is greater than the thickness of the first gate dielectric layer GD1, the cell threshold voltage drop and electric field degradation can be reduced.

[0073] According to an embodiment of the present invention, when forming the capping layer DB, the effect of using a flat-band shifted double-function electrode can be amplified to reduce gate-induced drain leakage (GIDL) that may be caused by the improvement of the electric field, and the operating current (IOP) may be increased.

[0074] As a result, the dielectric capping layer DB can increase the thickness of the gate dielectric layer in contact with the channel CH, and at the same time increase the double function electrode effect.

[0075] Figure 3 This is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention. Figure 4 yes Figure 3 A cross-sectional view of the vertical memory cell array (MCA_C). Figure 5 This is a cross-sectional view of the edge portion of the double-line character.

[0076] refer to Figures 3 to 5The semiconductor memory device 100 may include a memory cell array (MCA). Multiple Figure 1 The storage cells MC shown can be arranged in the first direction to the third direction D1, D2, and D3 to form a multi-layer storage cell array MCA. The storage cell array MCA can include a three-dimensional array of storage cells MC, and the three-dimensional storage cell array can include a vertical storage cell array MCA_C and a horizontal storage cell array MCA_R. The vertical storage cell array MCA_C can refer to an array of storage cells MC arranged vertically in the first direction D1. The horizontal storage cell array MCA_R can refer to an array of storage cells MC arranged horizontally in the third direction D3. The vertical storage cell array MCA_C can be referred to as a column array of storage cells MC, while the horizontal storage cell array MCA_R can be referred to as a row array of storage cells MC. The bit line BL can be vertically oriented to couple to the vertical storage cell array MCA_C, while the double word line DWL can be horizontally oriented to couple to the horizontal storage cell array MCA_R. The bit line BL coupled to the vertical memory cell array MCA_C can be called the common bit line, and vertical memory cell arrays MCA_C adjacent to each other in the third direction D3 can be coupled to different common bit lines. The double word line DWL coupled to the horizontal memory cell array MCA_R can be called the common double word line (Common DWL), and horizontal memory cell arrays MCA_R adjacent to each other in the first direction D1 can be coupled to different common double word lines.

[0077] The memory cell array MCA may include multiple memory cells MC, and each memory cell MC may include a vertically oriented bit line BL, a horizontally oriented active layer ACT, a double word line DWL, and a horizontally oriented capacitor CAP. Figure 3 The diagram illustrates a three-dimensional memory cell array comprising four memory cells (MCs).

[0078] A bit line BL can contact adjacent active layers ACT on the first direction D1. Adjacent active layers ACT on the third direction D3 can share a double word line DWL. The number of capacitors CAP can correspond to the number of active layers ACT, and each capacitor can be coupled to a corresponding one of the active layers ACT. Capacitors CAP can share a plate line PL. Each active layer ACT can be thinner than the first word line WL1 and the second word line WL2 of the double word line DWL.

[0079] In a memory cell array (MCA), two double word lines (DWLs) can be vertically stacked in a first direction D1. Each DWL can include a pair of first word lines WL1 and second word lines WL2. Multiple active layers (ACTs) can be arranged laterally, spaced apart from each other in a third direction D3. Each active layer (ACT) can extend in a second direction D2 and can pass between the first word lines WL1 and the second word lines WL2.

[0080] Each active layer ACT may include a channel CH, a first source / drain region SR, and a second source / drain region DR. The channel CH may be located between a first word line WL1 and a second word line WL2. Each first source / drain region SR may be coupled to each bit line contact node BLC, and the bit line contact node BLC may be coupled to a bit line BL. Each second source / drain region DR may be coupled to each memory contact node SNC, and the memory contact node SNC may be coupled to a memory node SN.

[0081] Each of the first word line WL1 and the second word line WL2 in a dual word line (DWL) can include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG can be adjacent to the capacitor CAP, while the high work function electrode HWG can be adjacent to the bit line BL.

[0082] Return to reference Figure 5 The edge portions on both sides of each double letter line DWL can have a stepped shape, and the stepped shape can define the contact portion CA. Each of the first letter line WL1 and the second letter line WL2 can be included in the edge portions on both sides, i.e., the contact portions CA. Each contact portion CA can have a stepped shape.

[0083] Multiple word line pads WLP1 and WLP2 can be coupled to contact portions CA, respectively. The first word line pad WLP1 can be coupled to an upper-layer dual-word line (DWL), such as the contact portion CA of the upper-layer first word line WL1 and second word line WL2. The second word line pad WLP2 can be coupled to a lower-layer dual-word line (DWL), such as the contact portion CA of the lower-layer first word line WL1 and second word line WL2. The upper-layer first word line WL1 and upper-layer second word line WL2 can be interconnected via the first word line pad WLP1. The lower-layer first word line WL1 and lower-layer second word line WL2 can be interconnected via the second word line pad WLP2. Each of the first word line WL1 and the second word line WL2 can include a high power function electrode HWG and a low power function electrode LWG, and one end of the high power function electrode HWG in the contact portion CA can be interconnected to one end of the low power function electrode LWG.

[0084] The semiconductor memory device 100 may further include a substrate PERI, and the substrate PERI may include a peripheral circuit portion. Hereinafter, the substrate PERI will be simply referred to as the peripheral circuit portion PERI. The bit lines BL of the memory cell array MCA may be oriented in a first direction D1 perpendicular to the upper surface of the peripheral circuit portion PERI, and the double word lines DWL may be oriented in a third direction D3 parallel to the upper surface of the peripheral circuit portion PERI.

[0085] The Peripheral Circuit I (PERI) can be located at a lower level than the Memory Cell Array (MCA). This can be referred to as a COP (Cell Above PERI) structure. The PERI may include at least one control circuit for driving the MCA. The at least one control circuit of the PERI may include N-channel transistors, P-channel transistors, CMOS circuits, or combinations thereof. The at least one control circuit of the PERI may include address decoder circuitry, read circuitry, write circuitry, etc. The at least one control circuit of the PERI may include planar channel transistors, recessed channel transistors, buried gate transistors, fin-channel transistors (FinFETs), etc.

[0086] For example, the peripheral circuitry PERI may include sub-word line drivers SWD1 and SWD2 and a sense amplifier SA. The upper-layer dual-word line DWL can be coupled to the first sub-word line driver SWD1 via a first word line pad WLP1 and a first metal interconnect MI1. The lower-layer dual-word line DWL can be coupled to the second sub-word line driver SWD2 via a second word line pad WLP2 and a second metal interconnect MI2. The bit line BL can be coupled to the sense amplifier SA via a third metal interconnect MI3. The third metal interconnect MI3 may have a multilayer metal structure including multiple vias and multiple metal lines.

[0087] Figure 6 This is a cross-sectional view showing a semiconductor memory device according to another embodiment of the present invention. Figure 6 A semiconductor memory device 110 with a POC (PERI on top of cell) structure is shown. Also appearing... Figure 5 In Figure 6 Detailed descriptions of the constituent elements shown will be omitted.

[0088] refer to Figure 6 The semiconductor memory device 110 may include a memory cell array MCA and a peripheral circuit section PERI′. The peripheral circuit section PERI′ may be located at a higher level than the memory cell array MCA. This may be referred to as a POC (PERI above the cell) structure.

[0089] The peripheral circuitry PERI′ may include sub-word line drivers SWD1 and SWD2, and a sense amplifier SA. The upper-layer dual-word line DWL is coupled to the first sub-word line driver SWD1 via a first word line pad WLP1 and a first metal interconnect MI1. The lower-layer dual-word line DWL is coupled to the second sub-word line driver SWD2 via a second word line pad WLP2 and a second metal interconnect MI2. The bit line BL is coupled to the sense amplifier SA via a third metal interconnect MI3. The third metal interconnect MI3 may have a multilayer metal structure including multiple vias and multiple metal lines.

[0090] Figure 7 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention. Figure 7 It also appears in the middle. Figures 1 to 6 Detailed descriptions of the constituent elements will be omitted.

[0091] refer to Figure 7 The semiconductor memory device 200 may include a peripheral circuit section (PERI) and a memory cell array (MCA) disposed on the PERI. The memory cell array (MCA) may include multiple memory cells. (Reference) Figure 3 The memory cell array (MCA) may include a column array and a row array of memory cells. Each memory cell may include a transistor (TR) and a capacitor (CAP), and each transistor (TR) may include an active layer (ACT) and a double word line (DWL). The double word line (DWL) may include a low work function electrode (LWG) and a high work function electrode (HWG) that are laterally adjacent to each other in a second direction (D2). Each capacitor (CAP) may be coupled to a corresponding active layer in the active layer (ACT) via a corresponding memory contact node (SNC). Each of bit lines (BL1) and (BL2) may be coupled to a corresponding active layer in the active layer (ACT) via a corresponding bit line contact node (BLC).

[0092] The column array of memory cells may include a mirrored structure with shared bit lines BL1 and BL2.

[0093] For example, a column array comprising memory cells arranged laterally in the second direction D2 (where the first bit line BL1 is between the memory cells) can be arranged in a mirror structure in which the first bit line BL1 is shared, while being coupled to different board lines PL1 and PL2. A column array comprising memory cells arranged laterally in the second direction D2 (where the second bit line BL2 is between the memory cells) can be arranged in a mirror structure in which the second bit line BL2 is shared, while being coupled to different board lines PL1 and PL2.

[0094] According to another embodiment of the present invention, the semiconductor memory device 200 may include a mirror structure with shared board lines.

[0095] Figures 8A to 8I This is a cross-sectional view illustrating a method for forming double-line characters according to an embodiment of the present invention.

[0096] refer to Figure 8A A stack SB can be formed. The stack SB may include interlayer dielectric layers 11 and 15, sacrificial layers 12 and 14, and an active layer 13. The active layer 13 may be located between the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15. The first sacrificial layer 12 may be located between the first interlayer dielectric layer 11 and the active layer 13, and the second sacrificial layer 14 may be located between the second interlayer dielectric layer 15 and the active layer 13. The first interlayer dielectric layer 11 and the second interlayer dielectric layer 15 may include silicon oxide, and the first sacrificial layer 12 and the second sacrificial layer 14 may include silicon nitride. The active layer 13 may include a semiconductor material or an oxide semiconductor material. The active layer 13 may include monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, or IGZO.

[0097] refer to Figure 8B The first opening 16 can be formed by etching a first portion of the stack SB. The first opening 16 can extend vertically. The first opening 16 can pass through the stack SB. Multiple active layers 13 can be formed between the first sacrificial layer 12 and the second sacrificial layer 14. For example, similar to Figure 3 The active layer ACT shown can have multiple active layers 13 arranged laterally on the same plane. For example, forming the active layer 13 may include: forming a stack SB such that a first sacrificial layer 12 and a second sacrificial layer 14 are located between a first interlayer dielectric layer 11 and a second interlayer dielectric layer 15, and a planar semiconductor layer is located between the first sacrificial layer 12 and the second sacrificial layer 14; forming multiple isolation vias (not shown) by etching the stack SB; and forming multiple linear semiconductor layers arranged laterally between the first sacrificial layer 12 and the second sacrificial layer 14 by recess etching the planar semiconductor layer through the isolation vias.

[0098] Subsequently, the first sacrificial layer 12 and the second sacrificial layer 14 can be selectively etched through the first opening 16 to form the recess 17. A portion of the active layer 13 can be exposed by the recess 17.

[0099] refer to Figure 8C This process can cause the exposed portion of the active layer 13 to be recessed. Therefore, the exposed upper and lower surfaces of the active layer 13 can be thinned to form a thin body 18. For example, the remaining active layer 13 can have a first thickness V1, and the thin body 18 can have a second thickness V2. The second thickness V2 of the thin body 18 can be thinner than the first thickness V1 of the remaining active layer 13. The process of causing the exposed portion of the active layer 13 to be recessed can be called a thinning process.

[0100] refer to Figure 8D A gate dielectric layer 19 may be formed over the exposed portions of the thin body 18. The gate dielectric layer 19 may also be formed over the exposed portions of the remaining active layer 13, over the exposed portions of the first sacrificial layer 12 and the second sacrificial layer 14, and over the exposed portions of the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15. The exposed portions of the thin body 18, the exposed portions of the remaining active layer 13, the exposed portions of the first sacrificial layer 12 and the second sacrificial layer 14, and the exposed portions of the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15 are those portions exposed to the opening 16 or the recess 17. The gate dielectric layer 19 may be formed of silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or combinations thereof. The gate dielectric layer 19 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof.

[0101] refer to Figure 8E A low work function material 20 can be formed on the gate dielectric layer 19. The low work function material 20 can fill the first opening 16 and the recess 17 on the gate dielectric layer 19. For example, the low work function material 20 may include doped polysilicon doped with N-type impurities.

[0102] refer to Figure 8F A low work function electrode (LWG) can be formed in the recess 17. To form the LWG, a selective etching process of the low work function material 20 can be performed. The selective etching of the low work function material 20 can include dry etching or wet etching. The selective etching of the low work function material 20 can be performed using maskless blanket etching. The selective etching process of the low work function material 20 can include an etch-back process.

[0103] For example, when the low work function material 20 includes doped polysilicon, an etch-back process of the doped polysilicon can be performed to form a low work function electrode LWG.

[0104] When the low work function electrode LWG is formed as described above, a portion of the gate dielectric layer 19 may be lost. Therefore, the exposed portion of the gate dielectric layer 19 can be thinned to form a second gate dielectric layer 19S. For example, the gate dielectric layer 19 can be retained as a first gate dielectric layer 19T that is thicker than the second gate dielectric layer 19S. A thick first gate dielectric layer 19T can be formed between the thin body 18 and the low work function electrode LWG.

[0105] refer to Figure 8GA capping layer 21 can be formed over the second gate dielectric layer 19S and the low work function electrode LWG. The capping layer 21 may include a dielectric material. The capping layer 21 may include silicon oxide. The capping layer 21 may cover the surface of the recess 17. The capping layer 21 may cover the exposed surface of the low work function electrode LWG. The capping layer 21 may prevent impurities from diffusing from the low work function electrode LWG. For example, when the low work function electrode LWG is doped polysilicon, the capping layer 21 may prevent impurities from diffusing from the doped polysilicon.

[0106] Furthermore, the capping layer 21 can enhance the thickness of the second gate dielectric layer 19S lost during the etching process of forming the low work function electrode LWG. The capping layer 21 can be thicker than the second gate dielectric layer 19S. Although in Figure 8G In the illustrated embodiment, the capping layer 21 may be thicker than the first gate dielectric layer 19S, but the invention is not limited to this, and in variations of the embodiment, the capping layer 21 may be thinner than the first gate dielectric layer 19T. According to another embodiment of the invention, the capping layer 21 and the second gate dielectric layer 19S may have the same thickness, and the capping layer 21 may be thinner than the first gate dielectric layer 19T. According to another embodiment of the invention, the total thickness of the capping layer 21 and the second gate dielectric layer 19S may be the same as the thickness of the first gate dielectric layer 19T.

[0107] The capping layer 21 can be formed by depositing silicon oxide followed by rapid thermal annealing (RTA). The deposition of silicon oxide can be performed through the first opening 16.

[0108] According to another embodiment of the present invention, the capping layer 21 can be formed by an oxidation process such as RTO (rapid thermal oxidation). For example, the capping layer 21 can be formed by selectively oxidizing the exposed surface of the low work function electrode LWG, and the oxidation process can also re-oxidize the exposed portion of the second gate dielectric layer 19S.

[0109] The capping layer 21 may have a conformal thickness. The capping layer 21 may have a non-conformal thickness. The conformal thickness may be the same as the thickness formed on the surface of the low work function electrode LWG and the thickness formed on the surface of the second gate dielectric layer 19S. The non-conformal thickness may be thicker than the thickness formed on the surface of the low work function electrode LWG and the thickness formed on the surface of the second gate dielectric layer 19S.

[0110] The first gate dielectric layer 19T, the second gate dielectric layer 19S, and the capping layer 21 can be formed of the same material. For example, the first gate dielectric layer 19T, the second gate dielectric layer 19S, and the capping layer 21 can be formed of silicon oxide. In another embodiment, the first gate dielectric layer 19T, the second gate dielectric layer 19S, and the capping layer 21 can be formed of different materials. For example, the first gate dielectric layer 19T and the second gate dielectric layer 19S can be formed of a high-k material, a ferroelectric material, or an antiferroelectric material, and the capping layer 21 can be formed of silicon oxide.

[0111] refer to Figure 8H A high work function material 22 can be formed on the capping layer 21 to fill the recess 17 and the first opening 16. The high work function material 22 can have a higher work function than the low work function electrode LWG and a lower resistance than the low work function electrode LWG. The high work function material 22 can include a metal-based material. For example, the high work function material 22 can include titanium nitride, tungsten, or a combination thereof. According to embodiments of the present invention, the high work function material 22 can be formed by sequentially stacking titanium nitride and tungsten.

[0112] refer to Figure 8I A high work function electrode (HWG) can be formed in each recess 17. To form the high work function electrode (HWG), the high work function material 22 can be selectively etched.

[0113] A high work function electrode (HWG) may be adjacent to a low work function electrode (LWG) on one side, with a capping layer 21 positioned between the HWG and the LWG. The HWG may have a higher work function than the LWG. The HWG may comprise a metal-based material. For example, the HWG may comprise titanium nitride, tungsten, or a combination thereof, while the LWG may comprise doped polycrystalline silicon with N-type impurities.

[0114] A thick first gate dielectric layer 19T can be formed between the thin body 18 and the low work function electrode LWG, and a thin second gate dielectric layer 19S can be formed between the thin body 18 and the high work function electrode HWG. A capping layer 21 can be located between the second gate dielectric layer 19S and the high work function electrode HWG. The capping layer 21 can also be located between the high work function electrode HWG and the low work function electrode LWG. The capping layer 21 can prevent impurities from diffusing from the low work function electrode LWG to the high work function electrode HWG.

[0115] A first character line WL1 and a second character line WL2 can be formed, wherein the thin body 18 is located between the first character line WL1 and the second character line WL2. The first character line WL1 and the second character line WL2 can correspond to the characters appearing in... Figures 1 to 7The double word line DWL. Each of the first word line WL1 and the second word line WL2 can be a double work function electrode including a low work function electrode LWG and a high work function electrode HWG.

[0116] According to the above embodiment, by forming the dielectric capping layer 21, impurity losses in the low work function electrode LWG can be suppressed, thereby increasing the dual-gate effect using a flat-band shift. Therefore, gate-induced drain leakage (GIDL) that may be caused by the improvement of the electric field (e-field) can be reduced, and the operating current can be increased. Furthermore, by forming the dielectric capping layer 21, the thickness of the second gate dielectric layer 19S, which is lost during the formation of the low work function electrode LWG, can be enhanced. In other words, the capping layer 21 and the second gate dielectric layer 19S can be used as gate dielectric layers with increased thickness.

[0117] Figures 9A to 9I This is a cross-sectional view illustrating a method for forming bit lines and capacitors according to an embodiment of the present invention.

[0118] In passing Figures 8A to 8I After the series of processes shown form the first character line WL1 and the second character line WL2, as follows: Figure 9A As shown, a protective layer 23 can be formed on one side of the high work function electrode HWG. The protective layer 23 may include silicon oxide or silicon nitride. The protective layer 23 may be recessed to fill the remaining space of the recess 17 but not completely fill the recess 17.

[0119] refer to Figure 9B The exposed portion of the second gate dielectric layer 19S and the protective layer 23 of the capping layer 21 can be etched to expose the first end E1 of the thin body 18.

[0120] refer to Figure 9C A bit line contact node (BLC) can be formed, coupled to the first end E1 of the thin body 18. The bit line contact node (BLC) may include polysilicon doped with impurities. The bit line contact node (BLC) may be coupled only to the first end E1 of the thin body 18. Before forming the bit line contact node (BLC), the first end E1 of the thin body 18, the capping layer 21, and the second gate dielectric layer 19S may be recessed. Therefore, the first end E1 of the thin body 18, the capping layer 21, and the second gate dielectric layer 19S may be self-aligned to the side of the protective layer 23.

[0121] When forming the bit line contact node (BLC) or before forming the bit line contact node (BLC), a first source / drain region (SR) can be formed at the first end E1 of the thin body 18. The first source / drain region (SR) can be formed by forming impurity-containing polysilicon over the first opening 16 and then performing a subsequent heat treatment to allow the impurities to diffuse from the polysilicon to the first end E1 of the first thin body 18. Here, the impurity-doped polysilicon can become the bit line contact node (BLC). According to another embodiment of the invention, the first source / drain region (SR) can be formed by doping with impurities and performing a heat treatment. Subsequently, the bit line contact node (BLC) can be formed.

[0122] refer to Figure 9D A bit line BL can be formed to contact the bit line contact node BLC. The bit line BL can fill the first opening 16. The bit line BL can include titanium nitride, tungsten, or a combination thereof. A bit line-side ohmic contact can be further formed between the bit line BL and the bit line contact node BLC. The bit line-side ohmic contact can include a metal silicide. For example, the metal silicide can be formed by sequentially performing metal layer deposition and annealing on the bit line contact node BLC, and unreacted metal layers can be removed. The metal silicide can be formed by a reaction between silicon and metal layers in the bit line contact node BLC.

[0123] refer to Figure 9E The second opening 24 can be formed by etching the second portion of the stack SB. The second opening 24 can extend vertically. The second opening 24 can pass through the stack SB.

[0124] Subsequently, the first sacrificial layer 12, the second sacrificial layer 14, and the remaining active layer 13 can be selectively recessed through the second opening 24. Thus, a capacitor opening 25 can be formed between the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15. After forming the capacitor opening 25, the thin body 18 and the active layer 13 can be retained, as indicated by the reference numeral "ACT". Hereinafter, the thin body 18 and the active layer 13 will be simply referred to as the active layer ACT. One side of the active layer ACT may include the thin body 18. The second end E2 of the active layer ACT can be exposed by the capacitor opening 25. According to another embodiment of the invention, the thickness of the second end E2 of the active layer ACT can be the same as the thickness of the thin body 18.

[0125] refer to Figure 9F A storage contact node SNC can be formed and coupled to the second end E2 of the active layer ACT. The storage contact node SNC may include doped polysilicon. The storage contact node SNC may be coupled only to the second end E2 of the active layer ACT.

[0126] A second source / drain region DR can be formed at the second end E2 of the active layer ACT during or before the formation of the storage contact node SNC. The second source / drain region DR can be formed by forming impurity-doped polysilicon over the second opening 24 and the capacitor opening 25, followed by a subsequent thermal treatment to allow the impurities to diffuse from the polysilicon toward the second end E2 of the active layer ACT. Here, the impurity-doped polysilicon can serve as the storage contact node SNC. According to another embodiment of the invention, the second source / drain region DR can be formed through an impurity doping process and thermal treatment. Subsequently, the storage contact node SNC can be formed.

[0127] The residual sacrificial layers 12 and 14 may be located between the storage contact node SNC and the first gate dielectric layer 19T.

[0128] The channel CH can be defined between the first source / drain region SR and the second source / drain region DR. The dual-gate dielectric layer of the second gate dielectric layer 19S and the capping layer 21 can be located between the channel CH and the high work function electrode HWG. The single-gate dielectric layer of the first gate dielectric layer 19T can be located between the second source / drain region DR and the low work function electrode LWG, and can contact both the second source / drain region DR and the low work function electrode LWG.

[0129] refer to Figure 9G A storage node (SN) can be formed that contacts the storage contact node (SNC). The storage node (SN) can be formed by performing a conductive material deposition and etch-back process. The storage node (SN) may include titanium nitride. The storage node (SN) may have a laterally oriented cylindrical shape.

[0130] refer to Figure 9H The outer wall of the storage node SN can be exposed by recessing the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15 (refer to reference numeral 26 in the figure).

[0131] refer to Figure 9I A dielectric layer DE and a plate node PN can be sequentially formed on top of the storage node SN.

[0132] Figure 10 This is a schematic perspective view illustrating a storage cell MC11 according to another embodiment of the present invention. In addition to the single-word line SWL, Figure 10 The constituent elements of the storage cell MC11 shown can be similar to those of other storage cells. Figure 1 and Figure 2 The components of the storage unit MC shown.

[0133] refer to Figure 10 The memory cell MC11 of the 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT and a word line SWL. The word line SWL may be formed on the upper or lower surface of the active layer ACT. The word line SWL may include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG may be adjacent to the capacitor CAP, while the high work function electrode HWG may be adjacent to the bit line BL. The low work function electrode LWG and the high work function electrode HWG may not be in direct contact with each other.

[0134] The memory cell MC11 may also include a gate dielectric layer and a capping layer. For details regarding the gate dielectric layer and capping layer of the memory cell MC11, please refer to... Figure 2 Return to reference. Figure 2 and Figure 10 The memory cell MC11 may include a capping layer DB between the low work function electrode LWG and the high work function electrode HWG, a first gate dielectric layer GD1 between the active layer ACT and the low work function electrode LWG, and a second gate dielectric layer GD2 located between the active layer ACT and the high work function electrode HWG and thinner than the first gate dielectric layer GD1. The capping layer DB may extend between the dielectric layer GD2 and the high work function electrode HWG.

[0135] According to another embodiment of the present invention, a plurality of storage cells MC11 can be formed as follows: Figure 3 The storage cell array shown.

[0136] Figure 11 This is a schematic perspective view illustrating a memory cell MC12 according to another embodiment of the present invention. Except for the full-ring gate word lines GAA-WL, Figure 11 The components of the storage cell MC12 shown can be similar to those of the memory cell MC12 shown. Figure 1 and Figure 2 The storage unit MC shown is shown.

[0137] refer to Figure 11The memory cell MC12 of the 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT and a full-ring gate word line GAA-WL. The full-ring gate word line GAA-WL may extend in the third direction D3 while surrounding a portion of the active layer ACT (i.e., the channel). The active layer ACT may have a shape that extends through the full-ring gate word line GAA-WL. The full-ring gate word line GAA-WL may include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG may be adjacent to the capacitor CAP, while the high work function electrode HWG may be adjacent to the bit line BL. The low work function electrode LWG and the high work function electrode HWG may not be in direct contact with each other.

[0138] Although not shown, the memory cell MC12 may also include a gate dielectric layer and a capping layer. For the gate dielectric layer of the memory cell MC12, please refer to... Figure 2 Return to reference. Figure 2 and Figure 11 The memory cell MC12 may include a capping layer DB between the low work function electrode LWG and the high work function electrode HWG, a first gate dielectric layer GD1 between the active layer ACT and the low work function electrode LWG, and a second gate dielectric layer GD2 located between the active layer ACT and the high work function electrode HWG and thinner than the first gate dielectric layer GD1. The capping layer DB may extend between the dielectric layer GD2 and the high work function electrode HWG.

[0139] According to another embodiment of the present invention, a plurality of storage cells MC12 can be formed as follows: Figure 3 The storage cell array shown.

[0140] According to embodiments of the present invention, dopant loss can be suppressed by forming a capping layer between the low work function electrode and the high work function electrode, and the effect of using a flat-band shifted double work function electrode can be increased.

[0141] According to embodiments of the present invention, cell threshold voltage drop and electric field degradation can be reduced by forming a thick gate dielectric layer between the channel and the high work function electrode.

[0142] According to embodiments of the present invention, with the formation of a capping layer and a thick gate insulating layer, gate-induced drain leakage (GIDL) caused by electric field improvement can be reduced and the operating current (IOP) can be increased.

[0143] According to embodiments of the present invention, since the word line has dual power function electrodes with low power function electrodes and high power function electrodes, low power consumption can be achieved while ensuring the refresh characteristics of the memory cell.

[0144] The effects expected in the embodiments of the present invention are not limited to those described above, and other effects not mentioned above can be clearly understood by those skilled in the art from the above description.

[0145] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Bit lines, the bit lines extending in a first direction perpendicular to the surface of the substrate; An active layer, the active layer including channels spaced apart from the substrate and extending in a second direction parallel to the surface of the substrate; A gate dielectric layer is formed on the active layer; A word line, the word line being laterally oriented over the gate dielectric layer to face the active layer, and the word line including a low work function electrode and a high work function electrode, the high work function electrode being parallel to the low work function electrode; A dielectric capping layer is disposed between the high work function electrode and the low work function electrode; as well as A capacitor, which includes a storage node, The bit line is adjacent to the high work function electrode, and the storage node of the capacitor is adjacent to the low work function electrode.

2. The semiconductor device as claimed in claim 1, wherein, The dielectric capping layer extends to cover the upper and lower surfaces of the high work function electrode.

3. The semiconductor device as claimed in claim 1, wherein, The dielectric capping layer comprises silicon oxide.

4. The semiconductor device as claimed in claim 1, wherein, The low work function electrode has a lower work function than the intermediate bandgap work function of silicon, while the high work function electrode has a higher work function than the intermediate bandgap work function of silicon.

5. The semiconductor device as claimed in claim 1, wherein, The low work function electrode comprises doped polycrystalline silicon doped with N-type impurities.

6. The semiconductor device of claim 1, wherein, The high work function electrode comprises a metal-based material.

7. The semiconductor device of claim 1, wherein, The high work function electrode includes titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

8. The semiconductor device of claim 1, wherein, The active layer includes semiconductor materials or oxide semiconductor materials.

9. The semiconductor device of claim 1, wherein, The active layer includes polycrystalline silicon, monocrystalline silicon, germanium, silicon-germanium, or indium gallium zinc oxide.

10. The semiconductor device of claim 1, wherein, The gate dielectric layer includes: A first gate dielectric layer is disposed between the low work function electrode and the active layer; and A second gate dielectric layer is disposed between the high work function electrode and the active layer and is thinner than the first gate dielectric layer. The dielectric overlay extends to be disposed between the second gate dielectric layer and the high work function electrode.

11. The semiconductor device of claim 10, wherein, The dielectric overlay layer, the first gate dielectric layer, and the second gate dielectric layer comprise the same material.

12. The semiconductor device of claim 11, wherein, Each of the first gate dielectric layer and the second gate dielectric layer comprises silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof.

13. The semiconductor device of claim 1, wherein, The active layer further includes: A first source / drain region is disposed on one side of the channel and coupled to the bit line; and A second source / drain region is located on the other side of the channel and coupled to the storage node of the capacitor. The first source / drain region is adjacent to the high work function electrode, while the second source / drain region is adjacent to the low work function electrode.

14. The semiconductor device of claim 13, further comprising: Bit line contact node, the bit line contact node being formed between the bit line and the first source / drain region; as well as A storage contact node is formed between the capacitor and the second source / drain region.

15. The semiconductor device of claim 1, wherein, The word lines include double word lines, single word lines, or full-ring grid word lines.

16. A method for manufacturing a semiconductor device, comprising: A bit line is formed, the bit line extending in a first direction perpendicular to the upper surface of the substrate; An active layer is formed on the upper portion of the substrate, which is vertically spaced from the substrate and extends in a second direction parallel to the upper surface of the substrate; A gate dielectric layer is formed on the active layer; A low work function electrode is formed on the gate dielectric layer; A dielectric overlay layer is formed on one side of the low work function electrode; as well as A high work function electrode is formed on the dielectric overlay layer, parallel to the low work function electrode; as well as Forming a capacitor that includes storage nodes, The bit line is adjacent to the high work function electrode, and the storage node of the capacitor is adjacent to the low work function electrode.

17. The method of claim 16, wherein, Forming the dielectric capping layer includes: Silicon oxide is deposited on one side of the low work function electrode; and Heat treatment is performed after silicon oxide deposition.

18. The method of claim 16, wherein, Forming the dielectric capping layer includes: Oxidize the low work function electrode. During the oxidation of the low work function electrode, a portion of the gate dielectric layer is re-oxidized.

19. The method of claim 16, wherein, The dielectric capping layer comprises silicon oxide.

20. The method of claim 16, wherein, The low work function electrode comprises polycrystalline silicon doped with N-type impurities, and The high work function electrode comprises a metal-based material.

21. The method of claim 16, wherein, The high work function electrode includes titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

22. The method of claim 16, further comprising: A first source / drain region is formed at the first end of the active layer adjacent to the high work function electrode, and the first source / drain region is coupled to the bit line; A second source / drain region is formed at the second end of the active layer adjacent to the low work function electrode, and the second source / drain region is coupled to the storage node of the capacitor.

23. The method of claim 22, further comprising: A bit line contact node is formed between the first source / drain region and the bit line; as well as A storage contact node is formed between the second source / drain region and the storage node.

24. A method for manufacturing a semiconductor device, comprising: A stack is formed in which a first interlayer dielectric layer, a first sacrificial layer, an active layer, a second sacrificial layer, and a second interlayer dielectric layer are stacked in the order mentioned above. Forming a first opening through the stack; A recess is formed by recessing the first sacrificial layer and the second sacrificial layer through the first opening; The active layer exposed by the recess is thinned; A first gate dielectric layer is formed on top of the thinned active layer; A low work function electrode is formed on top of the first gate dielectric layer to partially fill the recess; The second gate dielectric layer is formed by thinning the portion of the first gate dielectric layer exposed on one side of the low work function electrode. A dielectric overlay layer is formed on one side of the second gate dielectric layer and the low work function electrode; as well as A high work function electrode is formed on the dielectric overlay layer to fill the remaining portion of the recess; A first source / drain region is formed at the first end of the active layer adjacent to the high work function electrode; A bit line is formed, which is coupled to the first source / drain region and extends in a direction perpendicular to the upper surface of the substrate; A second source / drain region is formed at the second end of the active layer adjacent to the low work function electrode; as well as A capacitor is formed including a storage node, which is coupled to the second source / drain region.

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