Memory structure and method of operating the same

Abstract

A memory structure and its operating method, wherein the structure comprises: a substrate; a plurality of mutually discrete memory gate structures on the substrate, the memory gate structures comprising a memory layer and a control gate layer on the memory layer; a plurality of select gate structures on the substrate, the select gate structures being located between adjacent memory gate structures; a string select line and a ground select line on the substrate, the plurality of memory gate structures and the plurality of select gate structures being located between the string select line and the ground select line, and the string select line and the ground select line being electrically isolated from the memory gate structures; a source layer in the substrate, the source layer being adjacent to the ground select line; and a drain layer in the substrate, the drain layer being adjacent to the string select line. By controlling the select gate structures between adjacent memory gate structures, a channel is formed in the substrate in series with each memory gate structure in a read operation, and the memory gate structures on both sides are isolated, avoiding crosstalk between adjacent memory gate structures, and effectively improving the performance of the device structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and its operation method. Background Technology

[0002] In recent years, the development of flash memory has been particularly rapid. The main feature of flash memory is that it can retain the stored information for a long time without power.

[0003] NAND flash memory is a better storage solution than hard disk drives. Because NAND flash memory reads and writes data in units of pages, it is suitable for storing continuous data, such as pictures, audio or other file data. At the same time, due to its advantages of low cost, large capacity, fast write speed and short erase time, it is widely used in the storage field of mobile communication devices and portable multimedia devices.

[0004] However, the performance of existing NAND memory structures still needs improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a memory structure and its operation method to improve the performance of the device structure.

[0006] To address the aforementioned problems, the present invention provides a memory structure comprising: a substrate including a first region, a second region, and a third region arranged along a first direction, the second region being located between the first region and the third region; a plurality of mutually discrete memory gate structures located on the second region, each memory gate structure including a memory layer and a control gate layer located on the memory layer; a plurality of select gate structures located on the second region, the select gate structures being located between adjacent memory gate structures and electrically isolated from adjacent memory gate structures; a serial select line and a ground select line located on the second region, the plurality of memory gate structures and the plurality of select gate structures being located between the serial select line and the ground select line, and the serial select line and the ground select line being electrically isolated from the memory gate structures respectively; a source layer located in the first region, the source layer being adjacent to the ground select line; and a drain layer located in the third region, the drain layer being adjacent to the serial select line.

[0007] Optionally, the storage layer includes a floating gate layer or an ONO dielectric layer.

[0008] Optionally, when the memory layer is the floating gate layer, the memory gate structure further includes: a tunneling oxide layer located between the floating gate layer and the substrate; and a coupling dielectric layer located between the floating gate layer and the control gate layer.

[0009] Optionally, the ONO dielectric layer includes: a tunneling oxide layer, a storage nitride layer located on the tunneling oxide layer, and a barrier oxide layer located on the storage nitride layer.

[0010] Optionally, it further includes: a well region located within the substrate, the well region spanning the first region, the second region, and the third region, the source layer and the drain layer located within the well region; the dopant ions in the source layer have different electrical types than the dopant ions in the well region, and the dopant ions in the drain layer have different electrical types than the dopant ions in the well region.

[0011] Accordingly, the present invention also provides an operation method based on the memory structure described above, including: erasing, writing, and reading data from the memory structure.

[0012] Optionally, when the storage layer is a floating gate layer or an ONO dielectric layer, the data erasure operation method for the memory structure includes: grounding the selected storage gate structure to Vgnd; applying a first positive voltage V1 to the selected selection gate structure, as well as the currently unselected storage gate structure and the selection gate structure; and setting the serial select line, the ground select line, the source layer, and the drain layer to a floating state.

[0013] Optionally, the method for writing data to the memory structure includes: applying a second positive voltage V2 to the selected memory gate structure, wherein the first positive voltage V1 is less than the second positive voltage V2; applying the first positive voltage V1 to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the source layer; and grounding the ground selection line and the drain layer to Vgnd.

[0014] Optionally, the method for reading data from the memory structure includes: grounding the source layer and the selected memory gate structure (Vgnd); applying a third positive voltage V3 to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the ground selection line, wherein the third positive voltage V3 is less than the first positive voltage V1; applying a fourth positive voltage V4 to the drain layer, wherein the fourth positive voltage V4 is less than the third positive voltage V3; when the read data is "1", the fourth positive voltage V4 remains unchanged; when the read data is "0", the fourth positive voltage V4 decreases.

[0015] Optionally, when the storage layer is a floating gate layer, the method for erasing data from the memory structure further includes: applying a first negative voltage V1 to the selected storage gate structure and the currently unselected storage gate structure; applying a first positive voltage V2 to the selected selection gate structure and the currently unselected selection gate structure; and setting the serial select line, the ground select line, the source layer, and the drain layer to a floating state.

[0016] Optionally, the method for writing data to the memory structure further includes: applying a second positive voltage V3 to the selected memory gate structure, wherein the first positive voltage V2 is less than the second positive voltage V3; applying a third positive voltage V4 to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the source layer, wherein the third positive voltage V4 is less than the first positive voltage V2; and grounding the ground selection line and the drain layer to ground Vgnd.

[0017] Optionally, the method for reading data from the memory structure includes: grounding the source layer and the selected memory gate structure (Vgnd); applying a fourth positive voltage (V5) to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the ground selection line, wherein the third positive voltage (V5) is less than the first positive voltage (V4); applying a fifth positive voltage (V6) to the drain layer, wherein the fifth positive voltage (V6) is less than the fourth positive voltage (V5); when the read data is "1", the fifth positive voltage (V6) remains unchanged; when the read data is "0", the fifth positive voltage (V6) decreases.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] The memory structure of this invention includes a plurality of select gate structures located on the second region. These select gate structures are situated between adjacent memory gate structures and are electrically isolated from each other. By applying a voltage to the select gate structures between adjacent memory gate structures, a channel can be formed within the substrate during read operations, connecting the various memory gate structures in series. Simultaneously, the memory gate structures on both sides can be isolated, preventing crosstalk between adjacent memory gate structures and effectively improving the performance of the device structure. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a memory structure.

[0021] Figure 2 This is a schematic diagram of the memory structure in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the memory structure in another embodiment of the present invention. Detailed Implementation

[0023] As described in the background section, the performance of existing NAND memory structures still needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of a memory structure.

[0025] Please refer to Figure 1 The system includes: a substrate 100, comprising a first region I, a second region II, and a third region III arranged along a first direction X, wherein the second region II is located between the first region I and the third region III; a plurality of mutually discrete memory gate structures 101 located on the second region II, wherein each memory gate structure 101 includes a memory layer 1011 and a control gate layer 1012 located on the memory layer 1011; a plurality of doped layers 102 located within the second region II, wherein the doped layers 102 are located between adjacent memory gate structures 101; a string select line 103 and a ground select line 104 located on the second region II, wherein the string select line 103 and the ground select line 104 are electrically isolated from the memory gate structures 101; a source layer 105 located within the first region I, wherein the source layer 105 is adjacent to the ground select line 104; and a drain layer 106 located within the third region III, wherein the drain layer 106 is adjacent to the string select line 103.

[0026] In this embodiment, the dopant ions in the doped layer 102 have a different electrical type than the dopant ions in the well region of the substrate 100, causing a PN junction to be formed between adjacent memory gate structures 101. During a read operation, a channel is formed in the substrate 100 below the memory layer 1011, and the PN junction connects the channels formed below each memory layer 1011.

[0027] However, in this embodiment, since there is no selection gate between the various memory gate structures 101, the voltage on the control gate layer 1012 can be coupled to the adjacent memory layers 1011, resulting in crosstalk and affecting device performance.

[0028] Based on this, the present invention provides a memory structure and its operation method, comprising: a plurality of select gate structures located on a second region, wherein the select gate structures are located between adjacent memory gate structures and are electrically isolated from the adjacent memory gate structures. By applying a voltage to the select gate structures between adjacent memory gate structures, a channel can be formed in the substrate during read operations, connecting the various memory gate structures in series, while simultaneously isolating the memory gate structures on both sides, avoiding crosstalk between adjacent memory gate structures, and effectively improving the performance of the device structure.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figure 2 This is a schematic diagram of the memory structure in an embodiment of the present invention.

[0031] Please refer to Figure 2 A memory structure includes: a substrate 200, the substrate 200 including a first region I, a second region II, and a third region III arranged along a first direction X, the second region II being located between the first region I and the third region III; a plurality of mutually discrete memory gate structures 201 located on the second region II, the memory gate structure 201 including a memory layer and a control gate layer 2012 located on the memory layer 2011; and a plurality of select gate structures 202 located on the second region II, the select gate structures 202 being located between adjacent memory gate structures 201, and the select gate structures 202 being adjacent to the memory gate structures 201. The memory gate structure 201 is electrically isolated; a serial select line 203 and a ground select line 204 are located on the second region II, a plurality of memory gate structures 201 and a plurality of select gate structures 202 are located between the serial select line 203 and the ground select line 204, and the serial select line 203 and the ground select line 204 are electrically isolated from the memory gate structure 201 respectively; a source layer 205 is located in the first region I, the source layer 205 is adjacent to the ground select line 204; and a drain layer 206 is located in the third region III, the drain layer 206 is adjacent to the serial select line 203.

[0032] In this embodiment, by applying a voltage to the select gate structure 202 between adjacent memory gate structures 201, a channel can be formed in the substrate 200 during the read operation, connecting each memory gate structure 201 in series. At the same time, the memory gate structures 201 on both sides can be isolated, avoiding crosstalk between adjacent memory gate structures 201, and effectively improving the performance of the device structure.

[0033] In this embodiment, the storage layer 2011 is a floating gate layer, and the corresponding storage gate structure 201 further includes: a tunneling oxide layer 2013 located between the floating gate layer and the substrate 200; and a coupling dielectric layer 2014 located between the floating gate layer and the control gate layer 2012.

[0034] In this embodiment, the Fowler-Nordheim tunneling mechanism is used for erase and write operations. The bias voltages for erase and write are shown in Table 1.

[0035] In this embodiment, the select gate structure 202 includes: a select gate layer 2021, and a select gate dielectric layer 2022 located between the select gate layer 2021 and the substrate 200.

[0036] In this embodiment, the storage layer 2011, the control gate layer 2012, the select gate layer 2021, the serial select line 203, and the ground select line 204 are made of polysilicon.

[0037] In this embodiment, the adjacent storage gate structure 201 and the select gate structure 202 are electrically isolated by a dielectric layer.

[0038] In this embodiment, it further includes: a well region 207 located within the substrate 200, the well region 207 spanning the first region I, the second region II, and the third region III, the source layer 205 and the drain layer 206 located within the well region 207; the doped ions in the source layer 205 have different electrical types than the doped ions in the well region 207, and the doped ions in the drain layer 206 have different electrical types than the doped ions in the well region 207.

[0039] Figure 3 This is a schematic diagram of the memory structure in another embodiment of the present invention.

[0040] This embodiment continues the description of the memory structure based on the above embodiments. All other aspects are the same as the memory structure described in the above embodiments, except that the memory layer 2011 can also be an ONO dielectric layer. The following will provide a detailed description in conjunction with the accompanying drawings.

[0041] Please refer to Figure 3 The storage layer 2011 is an ONO medium layer.

[0042] In this embodiment, the ONO dielectric layer includes: a tunneling oxide layer 2011a, a storage nitride layer 2011b located on the tunneling oxide layer 2011a, and a barrier oxide layer 2011c located on the storage nitride layer 2011b.

[0043] In this embodiment, the tunneling oxide layer 2011a and the barrier oxide layer 2011c are made of silicon oxide, and the storage nitride layer 2011b is made of silicon nitride.

[0044] The memory structure employing the ONO dielectric layer is a memory cell based on discrete traps in an insulating medium to store charge. The charge is stored in discrete traps in the insulating storage nitride layer 2011b. The advantage of this storage mechanism is that the presence of local leakage paths in the tunneling oxide layer 2011a will not cause the leakage of all the charge in the storage nitride layer 2011b.

[0045] Accordingly, this embodiment of the invention also provides an operation method based on the memory structure described above, including: erasing, writing, and reading data from the memory structure.

[0046] When the storage layer 2011 is a floating gate layer or an ONO dielectric layer, in a specific embodiment, the table of the voltages applied for reading, erasing and writing data for the memory structure provided in this embodiment of the invention is shown in Table 1.

[0047]

[0048]

[0049] Table 1

[0050] As shown in Table 1, "Erase" represents the data erasure operation of the memory structure, "Program" represents the data writing operation of the memory structure, and "Read" represents the data reading operation of the memory structure; "Sel CG" represents the voltage value applied to the selected memory gate structure 201; "Sel SG" represents the voltage value applied to the selected select gate structure 202; "Pass CG" represents the voltage value applied to the unselected memory gate structure 201; "Pass SG" represents the voltage value applied to the unselected select gate structure 202; "SSL" represents the voltage value applied to the serial select line 203; "GSL" represents the voltage value applied to the ground select line 204; "Sel BL" represents the voltage value applied to the drain layer 206; "Unsel BL" represents the voltage value applied to the source layer 205; and "Array well" represents the voltage value applied to the well region 207.

[0051] Referring to Table 1, in a specific embodiment, the method for erasing data from the memory structure includes: grounding the selected memory gate structure 201 to Vgnd (0V); applying a first positive voltage V1 (3V~6V) to the selected selection gate structure 202, as well as the currently unselected memory gate structure 201 and the selection gate structure 202; setting the string selection line 203, the ground selection line 204, the source layer 205, and the drain layer 206 to a floating state; and applying a second positive voltage V2 (7V~12V) to the well region 207, wherein the first positive voltage V1 is less than the second positive voltage V2.

[0052] Referring to Table 1, in a specific embodiment, the method for writing data to the memory structure includes: applying a second positive voltage V2 (7V~12V) to the selected memory gate structure 201; applying a first positive voltage V1 (3V~6V) to the selected selection gate structure 202, as well as the currently unselected memory gate structure 201, the selection gate structure 202, the serial selection line 203, and the source layer 205; grounding the ground selection line 204 and the drain layer 206 to ground Vgnd (0V); and grounding the well region 207 to ground Vgnd (0V).

[0053] Referring to Table 1, in a specific embodiment, the method for reading data from the memory structure includes: grounding the source layer 205 and the selected memory gate structure 201 to Vgnd (0V); applying a third positive voltage V3 (2V~4V) to the selected selection gate structure 202, the currently unselected memory gate structure 201, the selection gate structure 201, the serial selection line 203, and the ground selection line 204, wherein the third positive voltage V3 is less than the first positive voltage V4. A positive voltage V1 is applied; a fourth positive voltage V4 (1.5V~1.8V) is applied to the drain layer 206, the fourth positive voltage V4 being less than the third positive voltage V3; when the read data is "1", the fourth positive voltage V4 remains unchanged (the voltage of the drain layer 206 is basically maintained at 1.5V); when the read data is "0", the fourth positive voltage V4 decreases (the voltage of the drain layer 206 drops to about 0.5V); the well region 207 is grounded to Vgnd (0V).

[0054] It should be noted that, in this embodiment, when erasing and writing the memory structure as shown in Table 1, the tunneling oxide layer 2013 between the floating gate layer and the substrate 200 is used as the electron tunneling channel (e.g., Figure 3 (As shown in Part A).

[0055] When the storage layer is a floating gate layer, in a specific embodiment, the table of applied voltages for reading, erasing and writing data for the memory structure provided in the embodiment of the present invention is shown in Table 2.

[0056]

[0057]

[0058] Table 2

[0059] Referring to Table 2, in one specific embodiment, the method for erasing data from the memory structure further includes: applying a first negative voltage V1 (-7V to -9V) to the selected memory gate structure 201 and the currently unselected memory gate structure 201; applying a first positive voltage (7V to 9V) to the selected selection gate structure 202 and the currently unselected selection gate structure 202; setting the serial selection line 203, the ground selection line 204, the source layer 205, and the drain layer 206 to a floating state; and grounding the well region 207 to Vgnd (0V).

[0060] Referring to Table 2, in one specific embodiment, the method for writing data to the memory structure further includes: applying a second positive voltage V3 (10V~12V) to the selected memory gate structure 201, wherein the first positive voltage V2 is less than the second positive voltage V3; applying a third positive voltage V4 (5V~6V) to the selected selection gate structure 202, as well as the currently unselected memory gate structure 201, the selection gate structure 202, the serial selection line 203, and the source layer 205, wherein the third positive voltage V4 is less than the first positive voltage V2; grounding the ground selection line 204 and the drain layer 206 to Vgnd (0V); and grounding the well region 207 to Vgnd (0V).

[0061] Referring to Table 2, in a specific embodiment, the method for reading data from the memory structure includes: grounding the source layer 205 and the selected memory gate structure 201 to Vgnd (0V); applying a fourth positive voltage V5 (3V) to the selected selection gate structure 202, the currently unselected memory gate structure 201, the selection gate structure 202, the serial selection line 203, and the ground selection line 204, wherein the third positive voltage V5 is less than the first positive voltage V4; applying a fifth positive voltage V6 (1.5V~1.8V) to the drain layer 206, wherein the fifth positive voltage V6 is less than the fourth positive voltage V5; when the read data is "1", the fifth positive voltage V6 remains unchanged (the voltage of the drain layer 206 is basically maintained at 1.5V); when the read data is "0", the fifth positive voltage V6 decreases (the voltage of the drain layer 206 drops to about 0.5V).

[0062] It should be noted that, in this embodiment, when erasing and writing the memory structure as described in Table 2, the dielectric layer between the memory gate structure 201 and the select gate structure 202 is used as the electron tunneling channel (e.g., ...). Figure 2 (As shown in Part A).

[0063] It should be noted that, in this embodiment, during the erase operation, applying a positive voltage (or a negative voltage) to half (e.g., an even number) of the selection gate structures 202 will erase all the data stored in the storage gate structures 201. This is because each selection gate structure 202 is adjacent to two storage gate structures 201. At this time, the other half (e.g., an odd number) of the selection gate structures 202 have the same function as the storage gate structures 201. Applying a negative voltage (or a positive voltage) to the other half of the selection gate structures 202 helps with the erase operation.

[0064] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory structure, characterized in that, include: A substrate, the substrate comprising a first region, a second region, and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A plurality of mutually independent memory gate structures are located on the second region, the memory gate structure including a memory layer and a control gate layer located on the memory layer; A plurality of selection gate structures are located on the second region, the selection gate structures are located between adjacent memory gate structures, and the selection gate structures are electrically isolated from the adjacent memory gate structures; The serial select line and the ground select line are located on the second region, and a plurality of the memory gate structures and a plurality of the select gate structures are located between the serial select line and the ground select line, and the serial select line and the ground select line are electrically isolated from the memory gate structure respectively; A source layer located within the first region, the source layer being adjacent to the ground selection line; as well as The drain layer is located within the third region and is adjacent to the string select line.

2. The memory structure as described in claim 1, characterized in that, The storage layer includes a floating gate layer or an ONO dielectric layer.

3. The memory structure as described in claim 2, characterized in that, When the memory layer is the floating gate layer, the memory gate structure further includes: a tunneling oxide layer located between the floating gate layer and the substrate; and a coupling dielectric layer located between the floating gate layer and the control gate layer.

4. The memory structure as described in claim 2, characterized in that, The ONO dielectric layer includes: a tunneling oxide layer, a storage nitride layer located on the tunneling oxide layer, and a barrier oxide layer located on the storage nitride layer.

5. The memory structure as described in claim 1, characterized in that, Also includes: A well region is located within the substrate, spanning the first region, the second region, and the third region, and the source layer and the drain layer are located within the well region; the dopants in the source layer have different electrical types than the dopants in the well region, and the dopants in the drain layer have different electrical types than the dopants in the well region.

6. An operation method based on the memory structure according to any one of claims 1 to 5, characterized in that, include: The memory structure is used to erase, write, and read data.

7. The method of operating the memory structure as described in claim 6, characterized in that, When the memory layer is a floating gate layer or an ONO dielectric layer, the data erasure operation method for the memory structure includes: grounding the selected memory gate structure to Vgnd; applying a first positive voltage V1 to the selected selection gate structure, as well as the currently unselected memory gate structure and the selection gate structure; and setting the serial selection line, the ground selection line, the source layer, and the drain layer to a floating state.

8. The method of operating the memory structure as described in claim 7, characterized in that, The method for writing data to the memory structure includes: applying a second positive voltage V2 to the selected memory gate structure, wherein the first positive voltage V1 is less than the second positive voltage V2; applying the first positive voltage V1 to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the source layer; and grounding the ground selection line and the drain layer to Vgnd.

9. The method of operating the memory structure as described in claim 8, characterized in that, The method for reading data from the memory structure includes: grounding the source layer and the selected memory gate structure (Vgnd); applying a third positive voltage V3 to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the ground selection line, wherein the third positive voltage V3 is less than the first positive voltage V1; applying a fourth positive voltage V4 to the drain layer, wherein the fourth positive voltage V4 is less than the third positive voltage V3; when the read data is "1", the fourth positive voltage V4 remains unchanged; when the read data is "0", the fourth positive voltage V4 decreases.

10. The method of operating the memory structure as described in claim 6, characterized in that, When the memory layer is a floating gate layer, the method for erasing data from the memory structure further includes: applying a first negative voltage V1 to the selected memory gate structure and the memory gate structure that is not currently selected; applying a first positive voltage V2 to the selected selection gate structure and the selection gate structure that is not currently selected; and setting the serial select line, the ground select line, the source layer, and the drain layer to a floating state.

11. The method of operating the memory structure as described in claim 10, characterized in that, The method for writing data to the memory structure further includes: applying a second positive voltage V3 to the selected memory gate structure, wherein the first positive voltage V2 is less than the second positive voltage V3; applying a third positive voltage V4 to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the source layer, wherein the third positive voltage V4 is less than the first positive voltage V2; and grounding the ground selection line and the drain layer to ground Vgnd.

12. The method of operating the memory structure as described in claim 11, characterized in that, The method for reading data from the memory structure includes: grounding the source layer and the selected memory gate structure (Vgnd); applying a fourth positive voltage (V5) to the selected selection gate structure, the currently unselected memory gate structure, the selection gate structure, the serial selection line, and the ground selection line, wherein the third positive voltage (V5) is less than the first positive voltage (V4); applying a fifth positive voltage (V6) to the drain layer, wherein the fifth positive voltage (V6) is less than the fourth positive voltage (V5); when the read data is "1", the fifth positive voltage (V6) remains unchanged; when the read data is "0", the fifth positive voltage (V6) decreases.

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