Chip testing auxiliary device and chip testing system

Abstract

The application discloses a kind of chip test auxiliary equipment, which is applied to chip test system, the chip test system also includes ESD machine platform, ESD machine platform includes the latch up test board of bearing chip to be tested, auxiliary equipment includes microprocessor, pulse level generating circuit, power input interface, sampling circuit and operational amplifier circuit;Microprocessor is detected after the trigger signal of ESD machine platform, control pulse level generating circuit releases pulse level to the pin of chip to be tested;Current on the pin of chip to be tested is acquired and transmitted by operational amplifier circuit current data that sampling circuit is collected;Current data and the current of pulse level that pulse level generating circuit releases are compared and analyzed, to complete test.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a chip testing auxiliary device and a chip testing system. Background Technology

[0002] Latch-up testing of integrated circuit chips and chip modules is a crucial aspect of ESD testing. This test is widely applicable, suitable for NMOS, CMOS, bipolar processes, and all variations and combinations thereof. During latch-up testing, the chip needs to be placed in a steady state, i.e., power is supplied to the chip's power pins, and I / O signal pins are set to high or low levels. I-tests are then performed on each I / O signal pin, and V-tests are performed on the power pins. After each pulse, the change in the chip's steady-state current must be measured and analyzed.

[0003] As the scale and complexity of integrated circuits continue to increase, the testing channel capabilities of current mainstream electrostatic discharge (ESD) equipment are insufficient to meet testing requirements. Summary of the Invention

[0004] This application provides a chip testing auxiliary device and a chip testing system, which helps to solve the above-mentioned technical problems.

[0005] In a first aspect, embodiments of this application provide a chip testing auxiliary device, which is applied to a chip testing system. The chip testing system further includes an ESD test bench, which includes a latch-up test board carrying the chip to be tested. The chip testing auxiliary device includes a microprocessor, a pulse level generation circuit, a power input interface, a sampling circuit, and an operational amplifier circuit. The output of the operational amplifier circuit, the first terminal of the pulse level generation circuit, and the output of the trigger signal of the ESD machine are all connected to the microprocessor. The second terminal of the pulse level generation circuit is connected to the latchup test board through the sampling terminal of the sampling circuit to connect to the pin of the chip under test. The sampling circuit is connected to the input terminal of the operational amplifier circuit. The power input interface supplies power to all circuits and chips used on the board through an external power supply. The microprocessor is used to control the pulse level generation circuit to release pulse levels to the pins of the chip under test within a preset time after detecting the trigger signal of the ESD instrument. The sampling circuit is used to collect the current on the pins of the chip under test and transmit it to the microprocessor via the operational amplifier circuit; The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit with the pulse level current released by the pulse level generation circuit in order to complete the test of the chip under test. This method can solve the problem of insufficient test channel capacity, which cannot meet testing requirements. For example, it overcomes the problem that the combined power supply pins with similar voltages in the chip under test due to insufficient power supply path makes current detection of low-current pins difficult; it also solves the problem that the chip under test has more signal pins than the ESD testing equipment can support, making it impossible to complete chip testing.

[0006] In one feasible embodiment, the chip under test includes power supply pins, the pulse level generation circuit includes a programmable DC-DC converter circuit, the first terminal of the pulse level generation circuit includes a controlled terminal of the programmable DC-DC converter circuit, the second terminal of the pulse level generation circuit includes an output terminal of the programmable DC-DC converter circuit, the sampling circuit includes a first sampling circuit, and the chip testing auxiliary equipment also includes the power output interface. The first sampling circuit is connected to the latch-up test board through the power output interface. The first sampling circuit is connected to the input terminal of the operational amplifier circuit. The output terminal of the programmable DC-DC circuit is connected to the first sampling circuit. The controlled terminal of the programmable DC-DC circuit is connected to the microprocessor. The power input interface is connected to the input terminal of the programmable DC-DC circuit so that the external power supply can power the programmable DC-DC circuit through the power input interface. The microprocessor is used to control the programmable DC-DC circuit to release a pulse level to the power supply pin of the chip under test through the first sampling circuit within a preset time after detecting the trigger signal of the ESD instrument. The first sampling circuit is used to collect the current on the power supply pin of the chip under test and transmit it to the microprocessor via the operational amplifier circuit. The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit with the pulse level current released by the programmable DC-DC circuit to complete the test of the chip under test.

[0007] In one feasible embodiment, the pulse-level current is higher than the current that the ESD device can provide.

[0008] In the prior art, high-current latch-up testing cannot be performed. However, the chip testing auxiliary equipment of this application can be used to provide additional power to emit a high-current pulse level and record the current data on the pins of the chip under test. The microprocessor compares and analyzes the current data and the emitted high-current pulse level to complete the high-current latch-up test of the chip under test.

[0009] In one feasible embodiment, the power supply pins of the chip under test include additional power supply pins that the chip under test has relative to the ESD instrument.

[0010] With the circuit described above, when the ESD testing equipment cannot meet the testing requirements of the power supply pins of the chip under test, the chip testing auxiliary equipment of this application can be used to complete the testing of the power supply pins of the chip under test.

[0011] In one feasible embodiment, the pins of the chip under test include signal pins that are additional to the ESD testing equipment, the sampling circuit includes a second sampling circuit, the pulse level generation circuit includes at least one buffer circuit, and the chip testing auxiliary equipment also includes a connector; the microprocessor is connected to at least one buffer circuit, the at least one buffer circuit is connected to the second sampling circuit, and the second sampling circuit is connected to the latch-up test board through the connector; A microprocessor is used to control at least one buffer circuit to release pulse levels to the signal pins of the chip under test through a second sampling circuit within a preset time after detecting a trigger signal from the ESD instrument. The second sampling circuit is used to collect the current on the signal pins of the chip under test and transmit it to the microprocessor via the operational amplifier circuit. The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit with the pulse level current released by at least one buffer circuit to complete the test of the chip under test.

[0012] With the circuit described above, when the number of signal pins of the chip under test exceeds the testing capability of the ESD testing equipment, the chip testing auxiliary equipment of this application can be used to complete the testing of the signal pins of the chip under test.

[0013] In one feasible embodiment, the chip testing auxiliary equipment also includes a level conversion circuit, through which the trigger signal output terminal of the ESD tester is connected to the microprocessor.

[0014] In one feasible embodiment, the chip testing auxiliary equipment further includes a connector, through which the level conversion circuit is connected to the trigger signal output terminal of the ESD tester.

[0015] In one feasible embodiment, the chip test auxiliary equipment includes a low-dropout regulator, and the power input interface is connected to the microprocessor through the low-dropout regulator.

[0016] In one feasible embodiment, the ESD device is either a high-order ESD device or a low-order ESD device.

[0017] For low-end ESD testing equipment, such as the MK2, which can support up to 768 pins, when the number of pins of the chip to be tested exceeds 768 during latch-up testing, even if the excess is not large, only a high-end MK4 equipment can be used, which increases the testing cost exponentially. However, by introducing the chip testing auxiliary equipment disclosed in this application on the basis of low-end ESD testing equipment, latch-up testing of the chip can be completed on the low-end ESD testing equipment even when the number of pins of the chip exceeds the number of pins of the ESD testing equipment.

[0018] For high-end ESD testing equipment, such as the MK4, which can support up to 2304 pin groups, when the number of pins of the chip under test exceeds 2304 during latch-up testing, even if the excess is not significant, latch-up testing cannot be performed unless a higher-end ESD testing equipment is introduced. However, introducing a higher-end ESD testing equipment would greatly increase the testing cost. By introducing the chip testing auxiliary equipment disclosed in this application, latch-up testing of the chip can be completed even when the number of pins of the chip exceeds the number of pins of the ESD testing equipment.

[0019] Secondly, embodiments of this application provide a chip testing system, which includes an ESD testing machine and chip testing auxiliary equipment as described in the first aspect.

[0020] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the architecture of a chip testing auxiliary device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application; Figure 6This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the architecture of another chip testing auxiliary device provided in an embodiment of this application. Detailed Implementation

[0023] The following sections will provide detailed explanations.

[0024] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] "Multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0027] The embodiments of this application will now be described with reference to the accompanying drawings.

[0028] See Figure 1 , Figure 1 This is a schematic diagram of the architecture of a chip testing auxiliary device provided in an embodiment of this application. Figure 1As shown, the chip testing auxiliary equipment 100 is applied to a chip testing system, which also includes an ESD test bench 120. The ESD test bench 120 includes a latch-up test board 130 that carries the chip under test. The chip testing auxiliary equipment 100 includes a microprocessor 101, a pulse level generation circuit 103, a sampling circuit 104, a power input interface 105, and an operational amplifier circuit 102. The output terminal of the operational amplifier circuit 102 is connected to the microprocessor 101. The first terminal of the pulse level generation circuit 103 is connected to the microprocessor 101, and the second terminal of the pulse level generation circuit 103 is connected to the latch-up test board via the sampling terminal of the sampling circuit 104 to connect to the pins of the chip under test. The input terminal of the operational amplifier circuit 102 is connected to the sampling circuit 103. The power input interface is connected to the microprocessor 101 so that an external power supply can power the microprocessor 101 through the power input interface 105. The trigger signal output terminal of the ESD test bench 120 is connected to the microprocessor 101.

[0029] Optionally, an external power supply can also power all the circuits and chips used on the latch-up test board 130 via the power input interface 105.

[0030] It should be noted that the trigger signal output terminal of the ESD instrument 120 can be connected to the first general purpose input / output (GPIO) interface of the microprocessor 101, and the output terminal of the operational amplifier circuit 102 can be connected to the analog-to-digital converter (ADC) interface of the microprocessor 101.

[0031] The microprocessor 101 is used to control the pulse level generation circuit 103 to release pulse levels to the pins of the chip under test within a preset time after detecting the trigger signal output terminal of the trigger signal output terminal of the ESD instrument 120. The sampling circuit 104 is used to collect the current on the pin of the chip under test and transmit it to the microprocessor 101 via the operational amplifier circuit 102; The microprocessor 101 is also used to compare and analyze the current data transmitted by the operational amplifier circuit 102 with the pulse level current released by the pulse level generation circuit 103, so as to complete the test of the chip under test.

[0032] In one feasible embodiment, such as Figure 1 As shown, the chip testing auxiliary equipment 100 also includes a low-dropout regulator 106, and the power input interface 105 is connected to the power interface of the microprocessor 101 through the low-dropout regulator 106. The low-dropout regulator 106 provides a stable voltage to the microprocessor 101.

[0033] In one feasible embodiment, such as Figure 2 As shown, the pins of the chip under test include power supply pins. The pulse level generation circuit 103 includes a programmable DC-DC circuit 107. The first terminal of the pulse level generation circuit 103 includes the controlled terminal of the programmable DC-DC circuit 107, and the second terminal of the pulse level generation circuit 103 includes the output terminal of the programmable DC-DC circuit 107. The sampling circuit 104 includes a first sampling circuit 108. The chip testing auxiliary device 100 also includes a power output interface 109. The first sampling circuit 108 is connected to the latch-up test board through the power output interface 109. The first sampling circuit 108 is connected to the input terminal of the operational amplifier circuit 102. The output terminal of the programmable DC-DC circuit 107 is connected to the first sampling circuit 108. The controlled terminal of the programmable DC-DC circuit 107 is connected to the microprocessor 101. The power input interface is connected to the input terminal of the programmable DC-DC circuit so that the external power supply can power the programmable DC-DC circuit 107 through the power input interface 105. The microprocessor 101 is used to control the programmable DC-DC circuit 107 to release a pulse level to the power supply pin of the chip under test through the first sampling circuit 108 within a preset time after detecting the trigger signal of the ESD instrument 120. The first sampling circuit 108 is used to collect the current on the power supply pin of the chip under test and transmit it to the microprocessor via the operational amplifier circuit 102. The microprocessor 101 is also used to compare and analyze the current data transmitted by the operational amplifier circuit 102 with the pulse level current released by the programmable DC-DC circuit 107 in order to complete the test of the chip under test.

[0034] When the current of the ESD tester 120 is insufficient to output the current required for testing the power pin of the chip under test, the power pin of the chip under test can be connected to the power output interface 109. The programmable DC-DC circuit 107 releases the required current to the power pin of the chip under test through the first sampling circuit 108 and the power output interface 109.

[0035] In an optional embodiment, the power supply pins of the chip under test include the additional power supply pins of the chip under test relative to the ESD test equipment 120. For example, if the chip under test has 20 power supply pins and 40 signal pins, and the ESD test equipment 120 can test 50 pins, but the ESD test equipment 120 can test 40 signal pins and 10 power supply pins, then 10 power supply pins of the chip under test remain untested. These 10 power supply pins include the additional power supply pins of the chip under test relative to the ESD test equipment 120. Through the above circuitry, when the ESD test equipment 120 cannot meet the testing requirements of the power supply pins of the chip under test, the chip testing auxiliary equipment of this application can be used to complete the testing of the power supply pins of the chip under test.

[0036] The controlled terminal of the programmable DC-DC circuit 107 can be connected to the integrated flash controller (IFC) interface of the microprocessor 101.

[0037] Specifically, when it is necessary to test the chip under test mounted on the latch-up test board 130, the trigger signal output terminal of the ESD instrument 120 sends a trigger signal to the microprocessor 101; after detecting the trigger signal from the ESD instrument 120, the microprocessor 101 controls the programmable DC-DC circuit 107 to send a trigger signal to the chip under test mounted on the latch-up test board 130 through the first sampling circuit 108 and the power output interface 109 at a preset time according to the preset program. The pins of the chip under test on the UP test board 130 release pulse levels. After the pulse level fades, the first sampling circuit 108 collects the current on the power supply pin of the chip under test and transmits the current to the operational amplifier circuit 102. The operational amplifier circuit 102 adjusts the gain of the current, for example, by increasing the gain. Then, the gain-adjusted current is transmitted to the microprocessor 101. Optionally, the operational amplifier circuit 102 is also used to convert the gain-adjusted current from an analog signal to a data signal and then transmit the data signal to the microprocessor 101. The microprocessor 101 compares and analyzes the current data transmitted from the operational amplifier circuit 102 and the pulse level current released by the programmable DC-DC circuit 107 to complete the test of the chip under test. During this process, an external power supply powers the microprocessor 101 and the programmable DC-DC circuit 107 through the power input interface 105. The external power supply powers the programmable DC-DC circuit 107 through the power input interface 105, which is essentially the external power supply powering the power supply pins of the chip under test through the programmable DC-DC circuit 107 via the power input interface 105.

[0038] A programmable DC-DC circuit is a DC-DC current controlled by a preset program, which can generate a preset current according to the preset program; for example, it can generate a pulse current at a preset time.

[0039] It should be noted that the programmable DC-DC circuit 107 releases pulse levels to the power pins of the chip under test carried on the latch-up test board 130 through the first sampling circuit 108 and the power output interface 109. Specifically, it releases pulse levels to each power pin of the chip under test carried on the latch-up test board 130 connected to the chip test auxiliary device 100. The current or current of the pulse level released to each power pin connected to the chip test auxiliary device 100 may be different. The microprocessor 101 can control the programmable DC-DC circuit 107 to release pulse levels to the pins of the chip under test as needed.

[0040] This method increases the power supply path and overcomes the problem that insufficient power supply path makes it difficult to detect the current of low-current pins by merging power supply pins with similar voltages in the chip under test.

[0041] In one feasible embodiment, the current at the aforementioned pulse level is higher than a preset current.

[0042] Optionally, the preset current can be 2A, 5A, 8A, 10A, 15A, 18A or other values.

[0043] In the prior art, high-current latch-up testing cannot be performed. However, the chip testing auxiliary equipment of this application can be used to provide additional power, emit a high-current pulse level, and record the current data on the power supply pin of the chip under test. The microprocessor compares and analyzes the current data and the emitted high-current pulse level to complete the high-current latch-up test of the chip under test.

[0044] In one feasible embodiment, such as Figure 3 As shown, the pins of the chip under test include signal pins that are additional to the chip under test relative to the ESD tester 120. The sampling circuit 104 includes a second sampling circuit 111. The pulse level generation circuit 103 includes at least one buffer circuit 110. The chip test auxiliary equipment also includes a connector 112. The microprocessor is connected to at least one buffer circuit 110, the at least one buffer circuit 110 is connected to a second sampling circuit 111, and the second sampling circuit 111 is connected to a latch-up test board 130 via a connector 112. The microprocessor 101 is used to control at least one buffer circuit 110 to release a pulse level to the signal pin of the chip under test through the second sampling circuit 111 within a preset time after detecting the trigger signal of the ESD instrument 120. The second sampling circuit 111 is used to collect the current on the signal pin of the chip under test and transmit it to the microprocessor 101 via the operational amplifier circuit 102. The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit 102 with the pulse level current released by the at least one buffer circuit 110 to complete the test of the chip under test.

[0045] Specifically, the additional signal pins of the chip under test relative to the ESD instrument are connected to connector 112. After detecting the trigger signal output from the output terminal of the ESD instrument 120, the microprocessor 101 controls at least one buffer circuit 110 to release a pulse level to the signal pins of the chip under test via the second sampling circuit 111 within a preset time. After the pulse level fades, the second sampling circuit 111 collects the current on the signal pins of the chip under test and transmits it to the operational amplifier circuit 102. The operational amplifier circuit 102 adjusts the gain of the current, for example, by increasing the gain of the current. Then, the current with the adjusted gain is transmitted to the microprocessor 101. Optionally, the operational amplifier circuit 102 is also used to convert the current with the adjusted gain from an analog signal to a data signal, and then transmits the data signal to the microprocessor 101. The microprocessor 101 compares and analyzes the current data transmitted from the operational amplifier circuit 102 with the pulse level current released by at least one buffer circuit 110 to complete the signal test of the chip under test, thus solving the problem that latching is not possible because the number of signal pins of the chip is higher than the number of pins that the latch-up test board can test. Issues with up-testing.

[0046] It should be pointed out here that Figure 3 Only one buffer circuit is shown in the diagram, but in reality, there can be multiple buffer circuits. At least one of the aforementioned buffer circuits can be connected to the microprocessor's second GPIO interface.

[0047] Whether to use one buffer circuit 110 or multiple buffer circuits 110 depends on the specifications of the buffer circuit 110 itself and the number of signal pins of the chip under test. The function of the buffer circuit 110 is to buffer; the microprocessor 101 and the latch-up test board 130 cannot be directly connected, but need to be connected through the buffer circuit 110. This is equivalent to the microprocessor 101 connecting to the latch-up test board 130 through a buffer.

[0048] In one feasible embodiment, the chip testing auxiliary device further includes a level conversion circuit 113, through which the microprocessor 101 is connected to the output terminal of the trigger signal of the ESD tester 120.

[0049] In one feasible embodiment, the chip testing auxiliary equipment further includes a connector, and the level conversion circuit 113 can be connected to the trigger signal output terminal of the ESD test bench 120 through the connector 112.

[0050] The level conversion circuit 113 can be used to convert a high level to a low level, such as converting a 5V level to a 3.3V level; it can also be used to convert a low level to a high level, such as converting a 3.3V level to a 5V level. In this application, the level conversion circuit with the corresponding function can be selected based on the requirements.

[0051] In one feasible embodiment, the chip test auxiliary device 100 includes a low-dropout regulator 106, and the power input interface 105 is connected to the microprocessor 101 through the low-dropout regulator 106.

[0052] It should be noted that when the number of signal pins of the chip under test is greater than the number of signal pins of the latch-up test board, the connector mentioned above can be regarded as an external signal pin of the latch-up test board 130. During testing, the extra signal pins of the chip under test can be connected to the connector 110, thereby solving the problem that latch-up testing cannot be performed when the number of signal pins of the chip is greater than the number of signal pins of the latch-up test board.

[0053] In one feasible embodiment, the ESD device is a high-order ESD device, a low-order ESD device, or other ESD devices.

[0054] In one example, for a low-end ESD testing machine, such as the MK2, it can support a maximum of 768 pins. When the number of pins of the chip to be tested exceeds 768 during latch-up testing, even if the excess is not large, only a high-end MK4 testing machine can be used, which increases the testing cost exponentially. However, by introducing the chip testing auxiliary device disclosed in this application on the basis of a low-end ESD testing machine, latch-up testing of the chip can be completed on the low-end ESD testing machine even when the number of pins of the chip exceeds the number of pins of the ESD testing machine.

[0055] For high-end ESD testing equipment, such as the MK4, which can support up to 2304 pin groups, when the number of pins of the chip under test exceeds 2304 during latch-up testing, even if the excess is not significant, latch-up testing cannot be performed unless a higher-end ESD testing equipment is introduced. However, introducing a higher-end ESD testing equipment would greatly increase the testing cost. By introducing the chip testing auxiliary equipment disclosed in this application, latch-up testing of the chip can be completed even when the number of pins of the chip exceeds the number of pins of the ESD testing equipment.

[0056] In one feasible embodiment Figure 2 and Figure 3 The circuits shown can be integrated together, and identical circuits can be shared, such as... Figure 4As shown. When the additional pins of the chip under test relative to the ESD instrument include power pins, the additional power pins are connected to the power output interface 109. After detecting the trigger signal output from the trigger signal output terminal of the ESD instrument 120, the microprocessor 101 controls the programmable DC-DC circuit 107 to release a pulse level to the power pin of the chip under test through the first sampling circuit 108 within a preset time. After the pulse level fades, the first sampling circuit 108 collects the current on the power pin of the chip under test and transmits it to the operational amplifier circuit 102. The operational amplifier circuit 102 adjusts the gain of the current, for example, by increasing the gain of the current. Then, the current with the adjusted gain is transmitted to the microprocessor 101. Optionally, the operational amplifier circuit 102 is also used to convert the current with the adjusted gain from an analog signal to a data signal and then transmit the data signal to the microprocessor 101. When the additional pins of the chip under test relative to the ESD instrument include signal pins, the additional signal pins are connected to connector 111. After detecting the trigger signal output from the trigger signal output terminal of the ESD instrument 120, the microprocessor 101 controls at least one buffer circuit 110 to release a pulse level to the signal pin of the chip under test through the second sampling circuit 111 for a preset time. After the pulse level fades, the second sampling circuit 111 collects the current on the signal pin of the chip under test and transmits it to the operational amplifier circuit 102. The operational amplifier circuit 102 adjusts the gain of the current, for example, by increasing the gain of the current. Then, the current with the adjusted gain is transmitted to the microprocessor 101. Optionally, the operational amplifier circuit 102 is also used to convert the current with the adjusted gain from an analog signal to a data signal and then transmit the data signal to the microprocessor 101. The microprocessor 101 compares and analyzes the current data transmitted from the operational amplifier circuit 102 with the pulse-level current released by the programmable DC-DC circuit 107 and the pulse-level current released by at least one buffer circuit 110 to complete the test of the chip under test.

[0057] In one feasible embodiment, such as Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, the chip testing auxiliary device 100 of this application also includes a USB interface 114, an SDIO interface 115, a display screen 116, and a control button 117. These designs help improve the operability of the chip testing auxiliary device. The display screen 116 can be connected to the serial peripheral interface (SPI) of the microprocessor 101, and the control button 117 can be connected to the third GPIO interface of the microprocessor 101.

[0058] The PC can communicate with the microprocessor 101 via USB interface 114, and the PC can write programs and debug programs to the microprocessor 101 via USB interface 114. An SD card can be connected to the microprocessor 101 via the SDIO interface to store configuration files, preset programs, and current data transmitted by the operational amplifier circuit 102. In one example, dual SD cards can be used: one SD card is used to load the configuration file (which has a fixed format), written by the PC, and the MCU reads the SD card and transfers it to Flash for use; it can also be used to store the aforementioned preset programs. The other SD card acts as a data receiving card, mainly storing the current data received by the ADC interface of the microprocessor 101 for review and analysis. To ensure ease of use, the SPI interface of the microprocessor 101 is connected to a display screen 116, such as an LCD, to display current information, such as: 1. Configuration Load, 2. Current Configuration Information, 3. Trigger Mode Information, 4. Data Storage Status, 5. Pulse Status Information, and 6. Current Comparison Results. Control buttons 115 include up, down, confirm, and return buttons, and the trigger mode and display items are selected via the third GPIO.

[0059] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip testing auxiliary device, characterized in that, The chip testing auxiliary equipment is applied to the chip testing system, which also includes an electrostatic discharge (ESD) machine. The ESD machine includes a latch-up test board that carries the chip to be tested. The chip testing auxiliary equipment includes a microprocessor, a pulse level generation circuit, a power input interface, a sampling circuit, and an operational amplifier circuit. The output terminal of the operational amplifier circuit, the first terminal of the pulse level generation circuit, and the output terminal of the trigger signal of the ESD instrument are all connected to the microprocessor. The second terminal of the pulse level generation circuit is connected to the latch-up test board through the sampling terminal of the sampling circuit to connect to the pins of the chip under test. The sampling circuit is connected to the input terminal of the operational amplifier circuit. The power input interface is connected to the microprocessor so that an external power supply can power the microprocessor through the power input interface. The microprocessor is used to control the pulse level generation circuit to release a pulse level to the pin of the chip under test within a preset time after detecting the trigger signal of the ESD instrument. The sampling circuit is used to collect the current on the pin of the chip under test and transmit it to the microprocessor via the operational amplifier circuit. The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit with the pulse level current released by the pulse level generation circuit, so as to complete the test of the chip under test.

2. The device according to claim 1, characterized in that, The chip under test has power pins, the pulse level generation circuit includes a programmable DC-DC converter, the first terminal of the pulse level generation circuit includes the controlled terminal of the programmable DC-DC converter, the second terminal of the pulse level generation circuit includes the output terminal of the programmable DC-DC converter, the sampling circuit includes a first sampling circuit, and the chip testing auxiliary equipment also includes a power output interface. The first sampling circuit is connected to the latch-up test board through the power output interface. The first sampling circuit is connected to the input terminal of the operational amplifier circuit. The output terminal of the programmable DC-DC circuit is connected to the first sampling circuit. The controlled terminal of the programmable DC-DC circuit is connected to the microprocessor. The power input interface is connected to the programmable DC-DC circuit so that the external power supply can supply power to the programmable DC-DC circuit through the power input interface. The microprocessor is used to control the programmable DC-DC circuit to release a pulse level to the power supply pin of the chip under test through the first sampling circuit within the preset time after detecting the trigger signal of the ESD instrument. The first sampling circuit is used to collect the current on the power supply pin of the chip under test and transmit it to the microprocessor via the operational amplifier circuit; The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit with the pulse level current released by the programmable DC-DC circuit, so as to complete the test of the chip under test.

3. The device according to claim 2, characterized in that, The power supply pins of the chip under test include the additional power supply pins that the chip under test has relative to the ESD instrument.

4. The device according to claim 2, characterized in that, The pulse level current is higher than the current that the ESD machine can provide.

5. The device according to claim 1, characterized in that, The pins of the chip under test include signal pins that are additional to the chip under test relative to the ESD instrument; the sampling circuit includes a second sampling circuit; the pulse level generation circuit includes at least one buffer circuit; and the chip testing auxiliary equipment also includes a connector. The microprocessor is connected to the at least one buffer circuit, the at least one buffer circuit is connected to the second sampling circuit, and the second sampling circuit is connected to the latch-up test board through the connector. The microprocessor is configured to, upon detecting a trigger signal from the ESD instrument, control at least one buffer circuit to release a pulse level to the signal pin of the chip under test through the second sampling circuit within a preset time. The second sampling circuit is used to collect the current on the signal pin of the chip under test and transmit it to the microprocessor via the operational amplifier circuit; The microprocessor is also used to compare and analyze the current data transmitted by the operational amplifier circuit with the pulse level current released by the at least one buffer circuit, so as to complete the test of the chip under test.

6. The device according to any one of claims 1-5, characterized in that, The chip testing auxiliary equipment also includes a level conversion circuit, and the trigger signal output terminal of the ESD tester is connected to the microprocessor through the level conversion circuit.

7. The device according to claim 6, characterized in that, The chip testing auxiliary equipment also includes a connector, and the level conversion circuit is connected to the trigger signal output terminal of the ESD tester through the connector.

8. The device according to any one of claims 1-5, characterized in that, The chip testing auxiliary equipment includes a low-dropout regulator, and the power input interface is connected to the microprocessor through the low-dropout regulator.

9. The device according to any one of claims 1-5, characterized in that, The ESD device can be a high-end ESD device or a low-end ESD device.

10. A chip testing system, characterized in that, The chip testing system includes an electrostatic discharge (ESD) machine and chip testing auxiliary equipment as described in any one of claims 1-9.

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