A method, device, processor and computer readable storage medium thereof for realizing chip testing of integrated circuits with few package openings

Abstract

The application relates to a method for realizing chip testing on an integrated circuit with few package ports, which comprises the following steps: (1) performing a command operation through a preset communication port of a chip to enter a test mode; (2) in the test mode, configuring a register under normal function through the preset communication port, and switching the preset communication port to a common IO port to output a corresponding test signal; (3) when the test signal output is completed, switching the common IO port to the preset communication port to perform a next command operation of the test signal; and (4) repeating the steps (2) to (3) until all test signals are tested. The application also relates to a corresponding device, a processor and a storage medium thereof. The method, the device, the processor and the storage medium thereof adopt the application, the switching between the communication port and the common IO port is realized through hardware, and the CPU occupies few resources.

Description

Technical Field

[0001] This invention relates to the field of packaging and testing technology, and more particularly to the field of chip testing technology with few package ports. Specifically, it relates to a method, apparatus, processor, and computer-readable storage medium for chip testing of integrated circuits with few package ports. Background Technology

[0002] Existing chip testing technologies mostly configure fixed registers in the test mode after entering the test mode, and then determine whether the chip can work properly by observing the output signals of different pins. When the number of packaged pins is very small, the existing technologies cannot be used for chip testing due to the lack of observation ports. Furthermore, the fixed register settings in existing technologies result in relatively fixed test items, leading to incomplete functional testing.

[0003] Before a chip is delivered to a customer, it must be tested. The current testing method involves using an I2C or SPI communication port, or other communication ports, to enter test mode by executing the command TEST_EN according to the corresponding communication protocol. In test mode, commands are then executed to enable various test items. The chip's functionality is tested by configuring the corresponding registers set in test mode, and the results are output from the corresponding fixed pins. The output results are used to determine whether the chip is functioning correctly.

[0004] For a chip to maintain performance, its area should be as small as possible. This not only saves on its own cost but also reduces the cost associated with its application. Therefore, the number of pins in the chip package must be minimized. In fact, some customer-customized application-specific integrated circuits (ASICs) require only power and ground pins and an I2C communication port. Furthermore, shorter testing time leads to lower costs, and more comprehensive testing results in higher reliability. Therefore, the ability to quickly and comprehensively test the functionality of chips with fewer pins is crucial. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, apparatus, processor and computer-readable storage medium for chip testing of integrated circuits with few package openings that are comprehensive and fast in testing functions.

[0006] To achieve the above objectives, the present invention provides a method, apparatus, processor, and computer-readable storage medium for chip testing of integrated circuits with few package ports, as follows:

[0007] This method for chip testing of integrated circuits with few package openings is characterized by the following steps:

[0008] (1) Enter the test mode by inputting commands through the chip's preset communication port;

[0009] (2) In the test mode, the registers under normal function are accessed through the preset communication port configuration, and the current preset communication port is switched to a normal IO port to output the corresponding test signals.

[0010] (3) When the test signal is output, the ordinary IO port is switched to the preset communication port to perform the input command operation of the next test signal.

[0011] (4) Repeat steps (2) to (3) above until all signals to be tested have been tested.

[0012] Preferably, step (1) specifically includes the following steps:

[0013] (1.1) The zeroth PAD port PA0 of the chip is used as the clock input port of the preset communication port, and the first PAD port PA1 of the chip is used as the data input / output port of the preset communication port.

[0014] (1.2) The zeroth PAD port PA0 and the first PAD port PA1 enter the test mode by inputting the first instruction enable command TEST_EN according to the preset communication protocol.

[0015] Preferably, step (2) specifically includes the following steps:

[0016] (2.1) Enable the command according to the currently input instruction to enter the corresponding test item for testing;

[0017] (2.2) In the current test mode, access the registers under normal function through the preset communication port configuration;

[0018] (2.3) Switch the zeroth PAD port PA0 and the first PAD port PA1 to ordinary IO ports to output the corresponding test signals.

[0019] Preferably, step (3) specifically includes the following steps:

[0020] (3.1) When the test signal output of the zeroth PAD port PA0 and the first PAD port PA1 is completed, the zeroth PAD port PA0 and the first PAD port PA1 are switched back to the preset communication port.

[0021] (3.2) The chip described above will perform the next register configuration or issue an instruction to enter the next test item.

[0022] Preferably, the preset communication port specifically includes the following state transition process:

[0023] IDLE state: After entering the test mode by entering the command through the preset communication port, continue to enter the second command to enable the xram_test_en, and configure all registers in this test mode;

[0024] In this state, if the preset communication port sends a write command, it enters the address 1 ADDR1 state and configures the high eight bits of the register address; if the preset communication port is in the preset communication port switching mode i2c_mode, the preset communication port sends a stop signal in this state, and the zeroth PAD port PA0 and the first PAD port PA1 switch from the preset communication port to the test signal output port, and the state machine enters the CMD state; otherwise, it continues to remain in the IDLE state.

[0025] Preferably, the preset communication port also includes the following state transition process:

[0026] CMD state: When the preset communication port is in the preset communication port exit mode i2c_mode_exit, the zeroth PAD port PA0 and the first PAD port PA1 are switched to the preset communication port; otherwise, the CMD state is maintained, and the zeroth PAD port PA0 and the first PAD port PA1 are used as ordinary IO ports to output test results.

[0027] Preferably, the preset communication port also includes the following state transition process:

[0028] ADDR1 state: When the second instruction enable command xram_test_en is in the triggered state, if the preset communication port continues to send write instructions, it enters the ADDR2 state and configures the lower eight bits of the register address; otherwise, it continues to maintain the ADDR1 state.

[0029] Preferably, the ADDR2 state undergoes the following state transition process:

[0030] When the second instruction enable command xram_test_en is in the triggered state, if the preset communication port continues to send write commands, it enters the WDAT state; if the preset communication port sends read commands, it enters the RDAT state; otherwise, it continues to maintain the ADDR2 state.

[0031] Preferably, the WDAT state undergoes the following state transition process:

[0032] Based on the received write instruction, data is written to the corresponding address register through the preset communication port, and the IDLE state is returned.

[0033] Preferably, the RDAT state undergoes the following state transition process:

[0034] Based on the received read instruction, data is read from the corresponding address register through the preset communication port, and the IDLE state is returned.

[0035] The main feature of this device for chip testing of integrated circuits with few package openings is that the device includes:

[0036] A processor is configured to execute computer-executable instructions;

[0037] The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the various steps of the method for chip testing of integrated circuits with few package ports described above.

[0038] The processor for chip testing of integrated circuits with few package ports is characterized in that the processor is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by the processor, the various steps of the aforementioned method for chip testing of integrated circuits with few package ports are implemented.

[0039] The main feature of this computer-readable storage medium is that it stores a computer program thereon, which can be executed by a processor to implement the various steps of the method for chip testing of integrated circuits with few package ports described above.

[0040] The present invention provides a method, apparatus, processor, and computer-readable storage medium for testing integrated circuits with few ports. These features allow access to all registers under normal function, eliminating the need for dedicated registers in the test module and reducing its size. Furthermore, the flexible configuration of all registers enables comprehensive functional testing, improving chip reliability. Because registers are configurable, items requiring programming normal functions due to incomplete test module design in existing technologies are eliminated, reducing testing time, increasing efficiency, and saving costs. Simultaneously, the present invention outputs test signals entirely through a preset communication port (in practical applications, the I2C communication port is selected as the preset communication port), minimizing the dependence of chip testing on the number of pins. Testing the entire chip can be achieved solely through the I2C communication port. Compared to existing technologies, this invention requires fewer pins and a smaller chip area; switching between the communication port and ordinary I / O ports is entirely implemented in hardware, eliminating the need for complex software programs, reducing CPU resource consumption, and lowering the requirements for software and chip testing personnel; it also offers shorter testing time, comprehensive testing functions, and high flexibility. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the chip packaging of the present invention.

[0042] Figure 2 This is a schematic diagram illustrating the function and state switching of the preset communication port and the test output port of the present invention.

[0043] Figure Labels

[0044] VDD chip operating voltage

[0045] VSS grounding

[0046] PA0 / SCL Zeroth PAD port

[0047] PA1 / SDA First PAD Port

[0048] IDLE (Idle State)

[0049] ADDR1 Address 1

[0050] ADDR2 Address 2

[0051] RDAT read data

[0052] WDAT write data

[0053] CMD command

[0054] reg_wr write

[0055] reg_rd read

[0056] i2c_mode: Switching mode for I2C communication port.

[0057] i2c_mode_exit Exit mode for I2C communication port Detailed Implementation

[0058] To more clearly describe the technical content of the present invention, the following description is provided in conjunction with specific embodiments.

[0059] Before describing the embodiments of the present invention in detail, it should be noted that, in the following, the terms “comprising,” “including,” or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0060] This method for testing integrated circuits with few package ports includes the following steps:

[0061] (1) Enter the test mode by inputting commands through the chip's preset communication port;

[0062] (2) In the test mode, the registers under normal function are accessed through the preset communication port configuration, and the current preset communication port is switched to a normal IO port to output the corresponding test signals.

[0063] (3) When the test signal is output, the ordinary IO port is switched to the preset communication port to perform the input command operation of the next test signal.

[0064] (4) Repeat steps (2) to (3) above until all signals to be tested have been tested.

[0065] Please see Figure 1 As shown, in a preferred embodiment of the present invention, step (1) specifically includes the following steps:

[0066] (1.1) The zeroth PAD port PA0 of the chip is used as the clock input port of the preset communication port, and the first PAD port PA1 of the chip is used as the data input / output port of the preset communication port.

[0067] (1.2) The zeroth PAD port PA0 and the first PAD port PA1 enter the test mode by inputting the first instruction enable command TEST_EN according to the preset communication protocol.

[0068] In practical applications, the present invention preferably selects the I2C communication port as the preset communication port for chip testing. However, the actual selection of the preset communication port is not limited. It can be arbitrarily selected according to the actual settings of the current chip interface, and the subsequent chip testing work can be completed according to the inventive concept of the present invention.

[0069] Similarly, the preset communication protocol selection of the present invention is not limited. In practical applications, the present invention uses the I2C communication protocol to input the instruction enable command. Users can select the corresponding communication protocol for subsequent chip testing according to the actual selection of the preset communication port.

[0070] like Figure 1 The chip packaging structure shown first uses the I2C communication port, i.e. Figure 1 The PA0 and PA1 ports shown are enabled by the command TEST_EN according to the I2C communication protocol to enter the test mode, and then the command continues to enter the specific item to be tested.

[0071] In a preferred embodiment of the present invention, step (2) specifically includes the following steps:

[0072] (2.1) Enable the command according to the currently input instruction to enter the corresponding test item for testing;

[0073] (2.2) In the current test mode, access the registers under normal function is configured through the I2C communication port;

[0074] (2.3) Switch the zeroth PAD port PA0 and the first PAD port PA1 to ordinary IO ports to output the corresponding test signals.

[0075] In a preferred embodiment of the present invention, step (3) specifically includes the following steps:

[0076] (3.1) When the test signal output of the zeroth PAD port PA0 and the first PAD port PA1 is completed, the zeroth PAD port PA0 and the first PAD port PA1 are switched back to the I2C communication port.

[0077] (3.2) The chip described above will perform the next register configuration or issue an instruction to enter the next test item.

[0078] In test mode, access the registers under normal function via I2C configuration, then switch PA0 and PA1 ports to ordinary I / O ports and output the corresponding test signals; when the test signals are output, switch PA0 and PA1 ports back to I2C communication ports to perform the next register configuration or enter another test item by issuing an instruction.

[0079] Please see Figure 2 As shown, in a preferred embodiment of the present invention, the I2C communication port specifically includes the following state transition process:

[0080] IDLE state: After entering the test mode by entering the command through the I2C communication port, continue to enter the second command to enable the xram_test_en, and configure all registers in this test mode;

[0081] In this state, if the I2C communication port sends a write command, it enters the address-1 ADDR1 state and configures the high eight bits of the register address; if the I2C communication port is in the I2C communication port switching mode i2c_mode, then the I2C communication port sends a stop signal in this state, and the zeroth PAD port PA0 and the first PAD port PA1 switch from the I2C communication port to the test signal output port, and the state machine enters the CMD state; otherwise, it continues to remain in the IDLE state.

[0082] In a preferred embodiment of the present invention, the I2C communication port further includes the following state transition processing:

[0083] CMD state: When the I2C communication port is in I2C communication port exit mode i2c_mode_exit, the zeroth PAD port PA0 and the first PAD port PA1 are switched to the I2C communication port; otherwise, the CMD state is maintained, and the zeroth PAD port PA0 and the first PAD port PA1 are used as ordinary IO ports to output test results.

[0084] In a preferred embodiment of the present invention, the I2C communication port further includes the following state transition processing:

[0085] ADDR1 state: When the second instruction enable command xram_test_en is in the triggered state, if the I2C communication port continues to send write instructions, it enters the ADDR2 state and configures the lower eight bits of the register address; otherwise, it continues to maintain the ADDR1 state.

[0086] In a preferred embodiment of the present invention, the ADDR2 state specifically undergoes the following state transition processing:

[0087] When the second instruction enable command xram_test_en is in the triggered state, if the I2C communication port continues to send write commands, it enters the WDAT state; if the I2C communication port sends read commands, it enters the RDAT state; otherwise, it continues to maintain the ADDR2 state.

[0088] In practical applications, the aforementioned instruction enable command is in the triggered state, i.e., in a high-level active state, so the second instruction enable command xram_test_en is 1.

[0089] In a preferred embodiment of the present invention, the WDAT state specifically undergoes the following state transition processing:

[0090] Based on the received write instruction, data is written to the corresponding address register through the I2C communication port, and the IDLE state is returned.

[0091] In a preferred embodiment of the present invention, the RDAT state specifically undergoes the following state transition processing:

[0092] Based on the received read instruction, the system performs a data read operation on the corresponding address register through the I2C communication port and returns the IDLE state.

[0093] In practical applications, the state transitions for register reading and writing, as well as the switching between the I2C communication port and the test output port, are explained as follows:

[0094] 1. IDLE State: After entering test mode via the I2C communication port, continue to enter commands to enable xram_test_en. In this mode, all registers can be configured. In this state, if an I2C write command is issued, the system enters ADDR1 state to configure the high eight bits of the register address; if i2c_mode goes high, indicating a stop signal from the I2C port, PA0 and PA1 switch from communication ports to test signal output ports, and the state machine enters CMD state; otherwise, it remains in IDLE state.

[0095] 2. CMD state: When i2c_mode_exit is high, PA0 and PA1 ports switch back to I2C communication ports; otherwise, they remain in CMD state, and PA0 and PA1 output test results as ordinary I / O ports.

[0096] 3. ADDR1 state: If I2C continues to send write instructions when xram_test_en is 1, it will enter the ADDR2 state and configure the lower eight bits of the register address; otherwise, it will remain in the ADDR1 state.

[0097] 4. ADDR2 state: When xram_test_en is 1, if I2C continues to send write commands, it enters WDAT state; if I2C sends read commands, it enters RDAT state; otherwise, it remains in ADDR2 state.

[0098] 5. WDAT state: In this state, data is written to the corresponding address register via I2C, and then the system returns to the IDLE state.

[0099] 6. RDAT state: In this state, data is read from the corresponding address register via I2C, and then the system returns to the IDLE state.

[0100] This apparatus for chip testing of integrated circuits with few package openings includes:

[0101] A processor is configured to execute computer-executable instructions;

[0102] The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the various steps of the method for chip testing of integrated circuits with few package ports described above.

[0103] The processor for chip testing of integrated circuits with few package ports is configured to execute computer-executable instructions, which, when executed by the processor, implement the various steps of the aforementioned method for chip testing of integrated circuits with few package ports.

[0104] The computer-readable storage medium contains a computer program that can be executed by a processor to implement the steps of the method for chip testing of integrated circuits with few package ports described above.

[0105] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0106] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution device.

[0107] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0108] The storage media mentioned above can be read-only memory, disk, or optical disk, etc.

[0109] In the description of this specification, references to terms such as "an embodiment," "some embodiments," "example," "specific example," or "embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0111] The present invention provides a method, apparatus, processor, and computer-readable storage medium for testing integrated circuits with few ports. These features allow access to all registers under normal function, eliminating the need for dedicated registers in the test module and reducing its size. Furthermore, the flexible configuration of all registers enables comprehensive functional testing, improving chip reliability. Because registers are configurable, items requiring programming normal functions due to incomplete test module design in existing technologies are eliminated, reducing testing time, increasing efficiency, and saving costs. Simultaneously, the present invention outputs test signals entirely through the I2C communication port, minimizing the dependence of chip testing on the number of pins; testing the entire chip can be achieved solely through the I2C communication port. Compared to existing technologies, this invention requires fewer pins and a smaller chip area; switching between the communication port and ordinary I / O ports is entirely hardware-based, eliminating the need for complex software programs, minimizing CPU resource consumption, and reducing the demands on software and chip testing personnel; it also offers shorter testing time, comprehensive testing functions, and high flexibility.

[0112] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A method for testing integrated circuits with few package ports, characterized in that, The method includes the following steps: (1) Enter the test mode by inputting commands through the chip's preset communication port; (2) In the test mode, the register under normal function is accessed through the preset communication port configuration, and the current preset communication port is switched to a normal IO port to output the corresponding test signal; (3) When the test signal output is completed, the ordinary IO port is switched to the preset communication port to perform the input command operation of the next test signal. (4) Repeat steps (2) to (3) above until all signals to be tested have been tested; Step (1) specifically includes the following steps: (1.1) The zeroth PAD port PA0 of the chip is used as the clock input port of the preset communication port, and the first PAD port PA1 of the chip is used as the data input / output port of the preset communication port. (1.2) The zeroth PAD port PA0 and the first PAD port PA1 enter the test mode by inputting the first instruction enable command TEST_EN according to the preset communication protocol.

2. The method for chip testing of integrated circuits with few package ports according to claim 1, characterized in that, Step (2) specifically includes the following steps: (2.1) Enable the command according to the currently input instruction to enter the corresponding test item for testing; (2.2) In the current test mode, access the registers under normal function through the preset communication port configuration; (2.3) Switch the zeroth PAD port PA0 and the first PAD port PA1 to ordinary IO ports to output the corresponding test signals.

3. The method for chip testing of integrated circuits with few package ports according to claim 2, characterized in that, Step (3) specifically includes the following steps: (3.1) When the test signal output of the zeroth PAD port PA0 and the first PAD port PA1 is completed, the zeroth PAD port PA0 and the first PAD port PA1 are switched back to the preset communication port. (3.2) The chip described above will perform the next register configuration or issue an instruction to enter the next test item.

4. The method for testing integrated circuits with few package ports according to any one of claims 1 to 3, characterized in that, The preset communication port specifically includes the following state transition process: IDLE state: After entering the test mode by entering the command through the preset communication port, continue to enter the second command to enable the xram_test_en, and configure all registers in this test mode; In this state, if the preset communication port sends a write command, it enters the address 1 ADDR1 state and configures the high eight bits of the register address; if the preset communication port is in the preset communication port switching mode i2c_mode, the preset communication port sends a stop signal in this state, and the zeroth PAD port PA0 and the first PAD port PA1 switch from the preset communication port to the test signal output port, and the state machine enters the CMD state; otherwise, it continues to remain in the IDLE state.

5. The method for chip testing of integrated circuits with few package ports according to claim 4, characterized in that, The preset communication port also includes the following state transition process: CMD state: When the preset communication port is in the preset communication port exit mode i2c_mode_exit, the zeroth PAD port PA0 and the first PAD port PA1 are switched to the preset communication port; otherwise, the CMD state is maintained, and the zeroth PAD port PA0 and the first PAD port PA1 are used as ordinary IO ports to output test results.

6. The method for testing integrated circuits with few package ports according to claim 5, characterized in that, The preset communication port also includes the following state transition process: ADDR1 state: When the second instruction enable command xram_test_en is in the triggered state, if the preset communication port continues to send write instructions, it enters the ADDR2 state and configures the lower eight bits of the register address; otherwise, it continues to maintain the ADDR1 state.

7. The method for chip testing of integrated circuits with few package ports according to claim 6, characterized in that, The ADDR2 state undergoes the following state transition process: When the second instruction enable command xram_test_en is in the triggered state, if the preset communication port continues to send write commands, it enters the WDAT state; if the preset communication port sends read commands, it enters the RDAT state; otherwise, it continues to maintain the ADDR2 state.

8. The method for chip testing of integrated circuits with few package ports according to claim 7, characterized in that, The WDAT state specifically undergoes the following state transition processing: Based on the received write instruction, data is written to the corresponding address register through the preset communication port, and the IDLE state is returned.

9. The method for testing integrated circuits with few package ports according to claim 7, characterized in that, The RDAT state specifically undergoes the following state transitions: Based on the received read instruction, data is read from the corresponding address register through the preset communication port, and the IDLE state is returned.

10. An apparatus for chip testing of integrated circuits with few package ports, characterized in that, The device includes: A processor is configured to execute computer-executable instructions; The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the steps of the method for chip testing of integrated circuits with few package ports as described in claim 9.

11. A processor for chip testing of integrated circuits with few package ports, characterized in that, The processor is configured to execute computer-executable instructions, which, when executed by the processor, implement the steps of the method for testing integrated circuits with few package ports as described in claim 9.

12. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the various steps of the method for chip testing of integrated circuits with few package ports as described in claim 9.

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