Semiconductor package substrate and method of manufacturing the same

Abstract

This invention discloses a semiconductor packaging substrate, including a layered circuit structure, at least one optical alignment structure, and an insulating protective layer. The optical alignment structure includes an optical alignment target and a second insulating layer covering the optical alignment target. The second insulating layer is a transparent insulating material, which can be seen through a CCD lens or a tool microscope to align the internal optical alignment target. This allows for the creation of a smaller transparent area and easier control of process parameters. Furthermore, this invention also discloses a method for manufacturing the semiconductor packaging substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging substrate, and more particularly to a semiconductor packaging substrate comprising an optical alignment target and a method thereof for manufacturing the same. Background Technology

[0002] Semiconductor packaging substrates are used in a wide range of applications, including microprocessors, automotive electronics, image processors, and radio frequency identification (RFID) products. The optical alignment points on the semiconductor packaging substrate are used for alignment during subsequent semiconductor packaging processes. The inner layer optical alignment points of the semiconductor packaging substrate must be exposed for the packaging equipment to complete the alignment.

[0003] An existing optical alignment point structure for the opening of the solder resist protective film, such as Figure 1 As shown, one of the IC packaging substrates 10 has an add-on circuit board 12, an optical alignment point 14, and a solder resist film 16. The add-on circuit board 12 has a conductive line 20 and a dielectric layer 22. The solder resist film 16 is a photosensitive solder resist film. To expose the optical alignment point 14, the solder resist film 16 needs to be developed to create an opening 18, thus exposing the optical alignment point 14.

[0004] Using the optical alignment point structure of the aforementioned solder resist protective film, the thickness of the solder resist protective film must be very thin; excessive thickness would affect the opening design. Furthermore, the packaging machine will be affected by height differences and unevenness of the notch, potentially causing the packaging substrate to crack.

[0005] Another existing mechanically opened optical alignment point structure, such as Figure 2 As shown, one of the IC packaging substrates 30 has an add-on circuit board 32 and an optical alignment point 34. The add-on circuit board 32 has a conductive line 40, an upper dielectric layer 42 and a lower dielectric layer 44. To expose the optical alignment point 34, an opening 38 must be mechanically made in the upper dielectric layer 42 to expose the optical alignment point 34.

[0006] The optical alignment point structure using the above-mentioned mechanical opening requires an open substrate, which is then fixed to the substrate with adhesive or film. An opening is then formed in the dielectric layer using a punch, milling cutter, or laser. However, the depth and range of the opening are limited, making it impossible to create designs that are too deep, too large, or too small. Furthermore, the forming factors of punches or mechanical milling cutters can result in a large radius angle, so the opening size must be increased to avoid the radius angle, thus limiting its application. The heat from the laser will harden the film. Therefore, both mechanical and laser openings are prone to problems such as misalignment, deformation, glue run-out, contamination, deterioration, or chipping during lamination.

[0007] Another existing optical alignment point structure, such as Figure 3As shown, one of the IC packaging substrates 60 has an add-on circuit board 62 and an optical alignment point copper pillar 64. The add-on circuit board 62 has a conductive line 70, an upper dielectric layer 72, and a lower dielectric layer 74. To fabricate the optical alignment point copper pillar 64, multiple additional processes are required, including: photolithography to define the required optical alignment point positions, electroplating the optical alignment point copper pillar 64, removing the dry film photoresist, fabricating the upper dielectric layer 72, polishing the upper dielectric layer 72 to expose the optical alignment point copper pillar 64, etc. Furthermore, because the end face of the optical alignment point copper pillar 64 is an exposed structure, it is prone to oxidation or contamination, which can affect the recognition performance of the CCD lens / tool ​​microscope and lead to misjudgment. Summary of the Invention

[0008] The purpose of this invention is to provide a semiconductor packaging substrate and its manufacturing method, enabling the optical alignment structure therein to be visualized and aligned using, for example, a CCD lens or a tool microscope. Furthermore, this invention facilitates the fabrication of a smaller visible area and allows for easy control of process parameters.

[0009] To achieve the above objectives, the present invention provides a semiconductor packaging substrate in one embodiment, comprising an augmentation circuit structure composed of a first insulating layer and augmentation circuitry, an optical alignment structure bonded to the augmentation circuit structure and composed of an optical alignment target and a transparent second insulating layer, a surface that can cover the augmentation circuit structure, and an insulating protective layer for the optical alignment structure; wherein the top of the transparent second insulating layer of the optical alignment structure is exposed outside the insulating protective layer, so that the optical alignment target inside can be viewed and aligned, for example, by a CCD lens or a tool microscope.

[0010] In another embodiment of the present invention, a semiconductor packaging substrate is provided, wherein the insulating protective layer further includes a plurality of openings to expose portions of the added-layer circuitry as external electrical connection pads.

[0011] This invention provides a method for manufacturing a semiconductor packaging substrate, comprising the following steps: providing a substrate; forming an add-on circuit structure including an add-on circuit and a first insulating layer on the substrate using a build-up process, and simultaneously forming at least one metal optical alignment target during the formation of the add-on circuit; forming a transparent second insulating layer on the optical alignment target using photolithography to completely cover the optical alignment target, wherein the transparent second insulating layer and the optical alignment target form an optical alignment structure; forming an insulating protective layer on the add-on circuit structure to cover the optical alignment structure and a surface of the add-on circuit structure; removing a portion of the insulating protective layer to expose the top surface of the transparent second insulating layer; and removing the substrate to expose a portion of the surface of the add-on circuit.

[0012] In another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided. Before removing the substrate in the above-described process steps, the method further includes the following steps: firstly, a plurality of openings are formed on the insulating protective layer using processes such as laser or machine drilling, so that the exposed portion of the added-layer circuitry serves as an external electrical connection pad. Attached Figure Description

[0013] Figure 1 Optical alignment point structure for openings in existing solder resist protective films.

[0014] Figure 2 The optical alignment point structure is an existing mechanically opened type.

[0015] Figure 3 The existing optical alignment point is a copper pillar structure.

[0016] Figure 4 This is a schematic diagram of a semiconductor packaging substrate according to an embodiment of the present invention.

[0017] Figure 5 This is a schematic flowchart of a semiconductor packaging substrate manufacturing method according to an embodiment of the present invention.

[0018] Figures 6A to 6D This is a schematic diagram of a semiconductor packaging substrate manufacturing method according to an embodiment of the present invention.

[0019] Figure 7 This is a schematic diagram illustrating the application of a semiconductor packaging substrate to package a chip according to an embodiment of the present invention.

[0020] Explanation of reference numerals in the attached figures: 100 - Semiconductor packaging substrate; 120 - Add-on circuit structure; 121 - First insulating layer; 1211 - First surface; 1212 - Second surface; 122 - Add-on circuit; 130 - Optical alignment structure; 131 - Optical alignment target; 132 - Second insulating layer; 140 - Insulating protective layer; 110 - Carrier plate; 10, 30, 60 - Packaging substrate; 12, 32, 62 - Add-on circuit substrate; 14, 34 - Optical alignment point; 16 - Solder resist film; 20, 40, 70 - Conductive lines; 22 - Dielectric layer; 18, 38 - Opening; 42, 72 - Upper dielectric layer; 44, 74 - Lower dielectric layer; C - Chip; F1 - Solder bump; F2 - Solder ball; H - Mold layer; S10-S60 - Process steps. Detailed Implementation

[0021] Please refer to Figure 4 This is a schematic diagram of a semiconductor packaging substrate according to an embodiment of the present invention. It can be seen that the semiconductor packaging substrate 100 of the present invention includes a layered circuit structure 120, at least one optical alignment structure 130, and an insulating protective layer 140.

[0022] The added-layer circuit structure 120 includes a first insulating layer 121 and an added-layer circuit 122; wherein the first insulating layer 121 has a first surface 1211 and a second surface 1212 opposite to each other, and a portion of the added-layer circuit 122 protrudes from the first surface 1211 of the first insulating layer 121, a portion of the added-layer circuit 122 is embedded in the first insulating layer 121, and a portion of the added-layer circuit 122 is exposed on the second surface 1212 of the first insulating layer 121.

[0023] The optical alignment structure 130 is disposed on the first surface 1211 of the first insulating layer 121, and the optical alignment structure 130 includes an optical alignment target 131 and a second insulating layer 132 covering the optical alignment target 131; wherein the optical alignment target 131 is composed of a metal material, and a portion of the added-layer circuit 122 may also be defined as the optical alignment target 131, and the second insulating layer 132 is composed of a photosensitive transparent insulating material.

[0024] The insulating protective layer 140 is disposed on the first surface 1211 of the first insulating layer 121 to cover the optical alignment structure 130, part of the added-layer circuit 122 and the first surface 1211 of the first insulating layer 121; wherein the top of the second insulating layer 132 of the optical alignment structure 130 is exposed on the insulating protective layer 140.

[0025] Furthermore, the first insulating layer 121 is composed of a dielectric material with a high content of film-like filling material or a dielectric material of molding compound, and the augmented layer circuit 122 is disposed inside and on the surface of the first insulating layer 121. The augmented layer circuit 122 may include conductive pillars for connecting the augmented layer circuits 122 to each other, for example, connecting the augmented layer circuits 122 located inside the first insulating layer 121 and protruding from the first surface of the first insulating layer 121. The conductive pillars may be made into metal pillars, such as copper pillars.

[0026] Furthermore, the second insulating layer 132 is formed on the optical alignment target 131 using a photolithography process to completely cover the optical alignment target 131 without covering the other added-layer circuitry 122. The second insulating layer 132 is composed of a photosensitive transparent dry film photoresist, a photosensitive transparent dielectric material, or other photosensitive transparent insulating material. The shape of the optical alignment target 131 can be any geometric shape, including circular, polygonal, or cross-shaped, as long as it can be viewed and aligned by a CCD (Charge Coupled Device) lens or a tool maker microscope (a type of microscope used for two-dimensional coordinate measurement).

[0027] Furthermore, the insulating protective layer 140 is composed of a film-like dielectric material with a high filler content or a molding compound dielectric material, and is disposed on the first insulating layer 121.

[0028] In another embodiment, the insulating protective layer 140 may also have a plurality of openings to expose portions of the added-layer circuitry 122 as external electrical connection pads (see reference). Figure 7 (As shown) for use.

[0029] Please see Figure 5 The diagram shown is a schematic flow chart of a semiconductor packaging substrate manufacturing method according to an embodiment of the present invention, including the following process steps:

[0030] Step 1 S10 (Please refer to the following for further information) Figure 6A As shown, a carrier plate 110 is provided, which is a metal substrate structure to provide support and electroplating electrode functions for subsequent processing operations.

[0031] Step 2 S20 (Please refer to the following for further information) Figure 6A As shown, a build-up circuit structure 120 is formed on the carrier plate 110 using a build-up process. The build-up circuit structure 120 includes a first insulating layer 121 and a build-up circuit 122. The first insulating layer 121 has a first surface 1211 and a second surface 1212 facing each other, and the second surface 1212 is coplanar with the surface of the carrier plate 110. A portion of the build-up circuit 122 is embedded in the first insulating layer 121, and another portion of the build-up circuit 122 protrudes from the first surface 1211 of the first insulating layer 121. At least one metal optical alignment target 131 is also simultaneously formed on the first surface 1211 of the first insulating layer 121 (this portion of the build-up circuit 122 can also be defined as the optical alignment target 131).

[0032] Step 3, S30 (please refer to the following) Figure 6B As shown, a photosensitive and transparent second insulating layer 132 is formed on the optical alignment target 131 using photolithography to completely cover the optical alignment target 131.

[0033] Step 4, S40 (Please refer to the relevant documentation) Figure 6C As shown, an insulating protective layer 140 is formed on the first surface 1211 of the first insulating layer 121 to cover the second insulating layer 132, part of the added circuit 122 and the first surface 1211 of the first insulating layer 121.

[0034] Step 5, S50 (Please refer to the relevant documentation) Figure 6DAs shown, a portion of the insulating protective layer 140 is removed to expose the top surface of the second insulating layer 132, thereby allowing the optical alignment target 131 to be visualized through the exposed surface of the second insulating layer 132 by means of, for example, a CCD lens or a tool microscope.

[0035] Finally, in the sixth step S60, the carrier plate 110 is removed to expose the second surface 1212 of the first insulating layer 121 and part of the surface of the added-layer circuit 122.

[0036] Secondly, the first insulating layer 121 is composed of a dielectric material with a high filler content in a film or a dielectric material of a molding compound; the second insulating layer 132 is composed of a photosensitive transparent insulating material, a photosensitive transparent dry film photoresist, or a photosensitive transparent dielectric material; and the insulating protective layer 140 is composed of a dielectric material with a high filler content in a film or a dielectric material of a molding compound. The first insulating layer 121 and the insulating protective layer 140 can be manufactured using molding techniques for encapsulating colloids, such as compression molding. Different amounts or weight percentages of fillers, such as silicon dioxide (SiO2) or aluminum oxide (Al2O3), are added to the molding compound. Taking the most commonly used epoxy molding compound (EMC) as an example, its main components and their weight percentages are: epoxy resin 12-15wt%, curing agent (Novolac Resin) 8-10wt%, and filler (Silica filler) 70-90wt%. The added inorganic powder filler is used to reduce the dielectric constant and dielectric loss coefficient of the encapsulation material.

[0037] Furthermore, the process of removing part of the insulating protective layer 140 to expose the top surface of the second insulating layer 132 can be completed by processes such as grinding, sandblasting, or plasma, and any process that can remove the material to form a flat surface is acceptable, so it is not limited to the above.

[0038] In another embodiment (please refer to the following) Figure 7 As shown), the semiconductor packaging substrate manufacturing method may further include the following steps before removing the substrate (i.e. before step S60): first forming a plurality of openings on the insulating protective layer 140 using processes such as laser or machine drilling, so that the exposed portion of the added layer circuit 122 serves as an external electrical connection pad for connecting and bonding solder balls F2.

[0039] Please refer to Figure 7This is a schematic diagram illustrating an embodiment of the semiconductor packaging substrate of the present invention applied to a packaged chip. As can be seen, the present invention can obtain alignment information by viewing the optical alignment target 131 and move it to the correct position, allowing for smooth subsequent packaging operations. The chip C can be connected to a portion of the augmented layer circuitry 122 via a plurality of solder bumps F1, and a portion of the augmented layer circuitry 122 can also be provided with a plurality of solder balls F2 for connection to a circuit board (not shown in the figure). The encapsulation layer H is used to encapsulate the chip C and isolate it from environmental influences, thereby protecting the chip C and ensuring packaging quality.

[0040] In summary, the present invention has the following advantages:

[0041] 1. The semiconductor packaging substrate of the present invention has a unique optical alignment structure 130 design, the appearance of which is flat and has no adverse effect on packaging equipment or fixtures.

[0042] 2. The semiconductor packaging substrate of the present invention features an optical alignment structure 130 design in which a metal optical alignment target 131 is covered by a transparent second insulating layer 132. This design avoids the problem of oxidation or contamination of the optical alignment target 131, thereby ensuring the recognition alignment performance and accuracy of CCD lenses or tool microscopes.

[0043] 3. The semiconductor packaging substrate of the present invention, wherein the unique optical alignment structure 130 makes it easy to create a small transparent area and also makes it easy to control the process parameters.

[0044] 4. The present invention is based on a semiconductor packaging substrate, wherein the unique optical alignment structure 130 has a simplified process and does not require electroplating to fabricate the copper pillars 64 for the optical alignment points, thus resulting in lower cost performance.

[0045] The above description is merely illustrative and not restrictive. Any equivalent modifications or alterations made without departing from the spirit and scope of this invention should be included within the scope of the claims.

Claims

1. A semiconductor package substrate, characterized by, include: An add-in circuit structure includes a first insulating layer and an add-in circuit, wherein the first insulating layer has a first surface and a second surface opposite to each other, and a portion of the add-in circuit protrudes from the first surface of the first insulating layer, a portion of the add-in circuit is embedded in the first insulating layer, and a portion of the add-in circuit is exposed on the second surface of the first insulating layer. At least one optical alignment structure is disposed on the first surface of the first insulating layer. The optical alignment structure includes an optical alignment target and a second insulating layer covering the optical alignment target. The optical alignment target is exposed from the first surface of the first insulating layer. The optical alignment target is composed of a metallic material, and the second insulating layer is composed of a transparent insulating material. An insulating protective layer is disposed on the first surface of the first insulating layer to cover the optical alignment structure, a portion of the added circuitry, and the first surface of the first insulating layer, wherein the top of the second insulating layer of the optical alignment structure is exposed outside the insulating protective layer.

2. The semiconductor packaging substrate as described in claim 1, characterized in that, The second insulating layer is composed of a photosensitive transparent dry film photoresist, a photosensitive transparent dielectric material, or a photosensitive transparent insulating material.

3. The semiconductor packaging substrate as described in claim 1, characterized in that, The first insulating layer is composed of a dielectric material with a high filler content or a dielectric material of a molding compound.

4. The semiconductor packaging substrate as described in claim 1, characterized in that, The insulating protective layer is composed of dielectric materials with high filler content, dielectric materials of molding compounds, or insulating solder resist materials.

5. The semiconductor packaging substrate as described in claim 1, characterized in that, The insulating protective layer has multiple openings to expose the additional layer circuitry as electrical connection pads.

6. A method for manufacturing a semiconductor packaging substrate, characterized in that, Includes the following steps: Provide a support plate; An additive circuit structure is formed on the carrier plate by an additive method. The additive circuit structure includes an additive circuit and a first insulating layer. The first insulating layer has a first surface and a second surface facing each other. The second surface is coplanar with the surface of the carrier plate. Part of the additive circuit is embedded in the first insulating layer, and part of the additive circuit protrudes from the first surface of the first insulating layer. At least one optical alignment target of metal material is formed simultaneously when the additive circuit is formed on the first surface of the first insulating layer. A transparent second insulating layer is formed on the optical alignment target using photolithography to completely cover the optical alignment target; An insulating protective layer is formed on the first surface of the first insulating layer to cover the second insulating layer, a portion of the added circuitry, and the first surface of the first insulating layer; Remove part of the insulating protective layer to expose the top surface of the second insulating layer; as well as Remove the carrier plate to expose the second surface of the first insulation layer and a portion of the surface of the added-layer circuitry.

7. The method for manufacturing a semiconductor packaging substrate as described in claim 6, characterized in that, It also includes the second insulating layer being composed of a photosensitive transparent dry film photoresist, a photosensitive transparent dielectric material, or a photosensitive transparent insulating material.

8. The method for manufacturing a semiconductor packaging substrate as described in claim 6, characterized in that, It also includes the first insulating layer being composed of a film-like dielectric material with a high filler content or a molding compound dielectric material.

9. The method for manufacturing a semiconductor packaging substrate as described in claim 6, characterized in that, It also includes the composition of the insulating protective layer as a film-like dielectric material with a high filler content, a molding compound dielectric material, or an insulating solder resist material.

10. The method for manufacturing a semiconductor packaging substrate as described in claim 6, characterized in that, It also includes creating multiple openings in the insulating protective layer using a laser or machine drilling before removing the carrier plate, so that the exposed portion of the added-layer circuitry can serve as an electrical connection pad.

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